1 // SPDX-License-Identifier: GPL-2.0
2 /* pci_sun4v.c: SUN4V specific PCI controller support.
3 *
4 * Copyright (C) 2006, 2007, 2008 David S. Miller (davem@davemloft.net)
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/types.h>
9 #include <linux/pci.h>
10 #include <linux/init.h>
11 #include <linux/slab.h>
12 #include <linux/interrupt.h>
13 #include <linux/percpu.h>
14 #include <linux/irq.h>
15 #include <linux/msi.h>
16 #include <linux/export.h>
17 #include <linux/log2.h>
18 #include <linux/of_device.h>
19 #include <linux/dma-map-ops.h>
20 #include <asm/iommu-common.h>
21
22 #include <asm/iommu.h>
23 #include <asm/irq.h>
24 #include <asm/hypervisor.h>
25 #include <asm/prom.h>
26
27 #include "pci_impl.h"
28 #include "iommu_common.h"
29 #include "kernel.h"
30
31 #include "pci_sun4v.h"
32
33 #define DRIVER_NAME "pci_sun4v"
34 #define PFX DRIVER_NAME ": "
35
36 static unsigned long vpci_major;
37 static unsigned long vpci_minor;
38
39 struct vpci_version {
40 unsigned long major;
41 unsigned long minor;
42 };
43
44 /* Ordered from largest major to lowest */
45 static struct vpci_version vpci_versions[] = {
46 { .major = 2, .minor = 0 },
47 { .major = 1, .minor = 1 },
48 };
49
50 static unsigned long vatu_major = 1;
51 static unsigned long vatu_minor = 1;
52
53 #define PGLIST_NENTS (PAGE_SIZE / sizeof(u64))
54
55 struct iommu_batch {
56 struct device *dev; /* Device mapping is for. */
57 unsigned long prot; /* IOMMU page protections */
58 unsigned long entry; /* Index into IOTSB. */
59 u64 *pglist; /* List of physical pages */
60 unsigned long npages; /* Number of pages in list. */
61 };
62
63 static DEFINE_PER_CPU(struct iommu_batch, iommu_batch);
64 static int iommu_batch_initialized;
65
66 /* Interrupts must be disabled. */
iommu_batch_start(struct device * dev,unsigned long prot,unsigned long entry)67 static inline void iommu_batch_start(struct device *dev, unsigned long prot, unsigned long entry)
68 {
69 struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
70
71 p->dev = dev;
72 p->prot = prot;
73 p->entry = entry;
74 p->npages = 0;
75 }
76
iommu_use_atu(struct iommu * iommu,u64 mask)77 static inline bool iommu_use_atu(struct iommu *iommu, u64 mask)
78 {
79 return iommu->atu && mask > DMA_BIT_MASK(32);
80 }
81
82 /* Interrupts must be disabled. */
iommu_batch_flush(struct iommu_batch * p,u64 mask)83 static long iommu_batch_flush(struct iommu_batch *p, u64 mask)
84 {
85 struct pci_pbm_info *pbm = p->dev->archdata.host_controller;
86 u64 *pglist = p->pglist;
87 u64 index_count;
88 unsigned long devhandle = pbm->devhandle;
89 unsigned long prot = p->prot;
90 unsigned long entry = p->entry;
91 unsigned long npages = p->npages;
92 unsigned long iotsb_num;
93 unsigned long ret;
94 long num;
95
96 /* VPCI maj=1, min=[0,1] only supports read and write */
97 if (vpci_major < 2)
98 prot &= (HV_PCI_MAP_ATTR_READ | HV_PCI_MAP_ATTR_WRITE);
99
100 while (npages != 0) {
101 if (!iommu_use_atu(pbm->iommu, mask)) {
102 num = pci_sun4v_iommu_map(devhandle,
103 HV_PCI_TSBID(0, entry),
104 npages,
105 prot,
106 __pa(pglist));
107 if (unlikely(num < 0)) {
108 pr_err_ratelimited("%s: IOMMU map of [%08lx:%08llx:%lx:%lx:%lx] failed with status %ld\n",
109 __func__,
110 devhandle,
111 HV_PCI_TSBID(0, entry),
112 npages, prot, __pa(pglist),
113 num);
114 return -1;
115 }
116 } else {
117 index_count = HV_PCI_IOTSB_INDEX_COUNT(npages, entry),
118 iotsb_num = pbm->iommu->atu->iotsb->iotsb_num;
119 ret = pci_sun4v_iotsb_map(devhandle,
120 iotsb_num,
121 index_count,
122 prot,
123 __pa(pglist),
124 &num);
125 if (unlikely(ret != HV_EOK)) {
126 pr_err_ratelimited("%s: ATU map of [%08lx:%lx:%llx:%lx:%lx] failed with status %ld\n",
127 __func__,
128 devhandle, iotsb_num,
129 index_count, prot,
130 __pa(pglist), ret);
131 return -1;
132 }
133 }
134 entry += num;
135 npages -= num;
136 pglist += num;
137 }
138
139 p->entry = entry;
140 p->npages = 0;
141
142 return 0;
143 }
144
iommu_batch_new_entry(unsigned long entry,u64 mask)145 static inline void iommu_batch_new_entry(unsigned long entry, u64 mask)
146 {
147 struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
148
149 if (p->entry + p->npages == entry)
150 return;
151 if (p->entry != ~0UL)
152 iommu_batch_flush(p, mask);
153 p->entry = entry;
154 }
155
156 /* Interrupts must be disabled. */
iommu_batch_add(u64 phys_page,u64 mask)157 static inline long iommu_batch_add(u64 phys_page, u64 mask)
158 {
159 struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
160
161 BUG_ON(p->npages >= PGLIST_NENTS);
162
163 p->pglist[p->npages++] = phys_page;
164 if (p->npages == PGLIST_NENTS)
165 return iommu_batch_flush(p, mask);
166
167 return 0;
168 }
169
170 /* Interrupts must be disabled. */
iommu_batch_end(u64 mask)171 static inline long iommu_batch_end(u64 mask)
172 {
173 struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
174
175 BUG_ON(p->npages >= PGLIST_NENTS);
176
177 return iommu_batch_flush(p, mask);
178 }
179
dma_4v_alloc_coherent(struct device * dev,size_t size,dma_addr_t * dma_addrp,gfp_t gfp,unsigned long attrs)180 static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
181 dma_addr_t *dma_addrp, gfp_t gfp,
182 unsigned long attrs)
183 {
184 u64 mask;
185 unsigned long flags, order, first_page, npages, n;
186 unsigned long prot = 0;
187 struct iommu *iommu;
188 struct iommu_map_table *tbl;
189 struct page *page;
190 void *ret;
191 long entry;
192 int nid;
193
194 size = IO_PAGE_ALIGN(size);
195 order = get_order(size);
196 if (unlikely(order >= MAX_ORDER))
197 return NULL;
198
199 npages = size >> IO_PAGE_SHIFT;
200
201 if (attrs & DMA_ATTR_WEAK_ORDERING)
202 prot = HV_PCI_MAP_ATTR_RELAXED_ORDER;
203
204 nid = dev->archdata.numa_node;
205 page = alloc_pages_node(nid, gfp, order);
206 if (unlikely(!page))
207 return NULL;
208
209 first_page = (unsigned long) page_address(page);
210 memset((char *)first_page, 0, PAGE_SIZE << order);
211
212 iommu = dev->archdata.iommu;
213 mask = dev->coherent_dma_mask;
214 if (!iommu_use_atu(iommu, mask))
215 tbl = &iommu->tbl;
216 else
217 tbl = &iommu->atu->tbl;
218
219 entry = iommu_tbl_range_alloc(dev, tbl, npages, NULL,
220 (unsigned long)(-1), 0);
221
222 if (unlikely(entry == IOMMU_ERROR_CODE))
223 goto range_alloc_fail;
224
225 *dma_addrp = (tbl->table_map_base + (entry << IO_PAGE_SHIFT));
226 ret = (void *) first_page;
227 first_page = __pa(first_page);
228
229 local_irq_save(flags);
230
231 iommu_batch_start(dev,
232 (HV_PCI_MAP_ATTR_READ | prot |
233 HV_PCI_MAP_ATTR_WRITE),
234 entry);
235
236 for (n = 0; n < npages; n++) {
237 long err = iommu_batch_add(first_page + (n * PAGE_SIZE), mask);
238 if (unlikely(err < 0L))
239 goto iommu_map_fail;
240 }
241
242 if (unlikely(iommu_batch_end(mask) < 0L))
243 goto iommu_map_fail;
244
245 local_irq_restore(flags);
246
247 return ret;
248
249 iommu_map_fail:
250 local_irq_restore(flags);
251 iommu_tbl_range_free(tbl, *dma_addrp, npages, IOMMU_ERROR_CODE);
252
253 range_alloc_fail:
254 free_pages(first_page, order);
255 return NULL;
256 }
257
dma_4v_iotsb_bind(unsigned long devhandle,unsigned long iotsb_num,struct pci_bus * bus_dev)258 unsigned long dma_4v_iotsb_bind(unsigned long devhandle,
259 unsigned long iotsb_num,
260 struct pci_bus *bus_dev)
261 {
262 struct pci_dev *pdev;
263 unsigned long err;
264 unsigned int bus;
265 unsigned int device;
266 unsigned int fun;
267
268 list_for_each_entry(pdev, &bus_dev->devices, bus_list) {
269 if (pdev->subordinate) {
270 /* No need to bind pci bridge */
271 dma_4v_iotsb_bind(devhandle, iotsb_num,
272 pdev->subordinate);
273 } else {
274 bus = bus_dev->number;
275 device = PCI_SLOT(pdev->devfn);
276 fun = PCI_FUNC(pdev->devfn);
277 err = pci_sun4v_iotsb_bind(devhandle, iotsb_num,
278 HV_PCI_DEVICE_BUILD(bus,
279 device,
280 fun));
281
282 /* If bind fails for one device it is going to fail
283 * for rest of the devices because we are sharing
284 * IOTSB. So in case of failure simply return with
285 * error.
286 */
287 if (err)
288 return err;
289 }
290 }
291
292 return 0;
293 }
294
dma_4v_iommu_demap(struct device * dev,unsigned long devhandle,dma_addr_t dvma,unsigned long iotsb_num,unsigned long entry,unsigned long npages)295 static void dma_4v_iommu_demap(struct device *dev, unsigned long devhandle,
296 dma_addr_t dvma, unsigned long iotsb_num,
297 unsigned long entry, unsigned long npages)
298 {
299 unsigned long num, flags;
300 unsigned long ret;
301
302 local_irq_save(flags);
303 do {
304 if (dvma <= DMA_BIT_MASK(32)) {
305 num = pci_sun4v_iommu_demap(devhandle,
306 HV_PCI_TSBID(0, entry),
307 npages);
308 } else {
309 ret = pci_sun4v_iotsb_demap(devhandle, iotsb_num,
310 entry, npages, &num);
311 if (unlikely(ret != HV_EOK)) {
312 pr_err_ratelimited("pci_iotsb_demap() failed with error: %ld\n",
313 ret);
314 }
315 }
316 entry += num;
317 npages -= num;
318 } while (npages != 0);
319 local_irq_restore(flags);
320 }
321
dma_4v_free_coherent(struct device * dev,size_t size,void * cpu,dma_addr_t dvma,unsigned long attrs)322 static void dma_4v_free_coherent(struct device *dev, size_t size, void *cpu,
323 dma_addr_t dvma, unsigned long attrs)
324 {
325 struct pci_pbm_info *pbm;
326 struct iommu *iommu;
327 struct atu *atu;
328 struct iommu_map_table *tbl;
329 unsigned long order, npages, entry;
330 unsigned long iotsb_num;
331 u32 devhandle;
332
333 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
334 iommu = dev->archdata.iommu;
335 pbm = dev->archdata.host_controller;
336 atu = iommu->atu;
337 devhandle = pbm->devhandle;
338
339 if (!iommu_use_atu(iommu, dvma)) {
340 tbl = &iommu->tbl;
341 iotsb_num = 0; /* we don't care for legacy iommu */
342 } else {
343 tbl = &atu->tbl;
344 iotsb_num = atu->iotsb->iotsb_num;
345 }
346 entry = ((dvma - tbl->table_map_base) >> IO_PAGE_SHIFT);
347 dma_4v_iommu_demap(dev, devhandle, dvma, iotsb_num, entry, npages);
348 iommu_tbl_range_free(tbl, dvma, npages, IOMMU_ERROR_CODE);
349 order = get_order(size);
350 if (order < 10)
351 free_pages((unsigned long)cpu, order);
352 }
353
dma_4v_map_page(struct device * dev,struct page * page,unsigned long offset,size_t sz,enum dma_data_direction direction,unsigned long attrs)354 static dma_addr_t dma_4v_map_page(struct device *dev, struct page *page,
355 unsigned long offset, size_t sz,
356 enum dma_data_direction direction,
357 unsigned long attrs)
358 {
359 struct iommu *iommu;
360 struct atu *atu;
361 struct iommu_map_table *tbl;
362 u64 mask;
363 unsigned long flags, npages, oaddr;
364 unsigned long i, base_paddr;
365 unsigned long prot;
366 dma_addr_t bus_addr, ret;
367 long entry;
368
369 iommu = dev->archdata.iommu;
370 atu = iommu->atu;
371
372 if (unlikely(direction == DMA_NONE))
373 goto bad;
374
375 oaddr = (unsigned long)(page_address(page) + offset);
376 npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
377 npages >>= IO_PAGE_SHIFT;
378
379 mask = *dev->dma_mask;
380 if (!iommu_use_atu(iommu, mask))
381 tbl = &iommu->tbl;
382 else
383 tbl = &atu->tbl;
384
385 entry = iommu_tbl_range_alloc(dev, tbl, npages, NULL,
386 (unsigned long)(-1), 0);
387
388 if (unlikely(entry == IOMMU_ERROR_CODE))
389 goto bad;
390
391 bus_addr = (tbl->table_map_base + (entry << IO_PAGE_SHIFT));
392 ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
393 base_paddr = __pa(oaddr & IO_PAGE_MASK);
394 prot = HV_PCI_MAP_ATTR_READ;
395 if (direction != DMA_TO_DEVICE)
396 prot |= HV_PCI_MAP_ATTR_WRITE;
397
398 if (attrs & DMA_ATTR_WEAK_ORDERING)
399 prot |= HV_PCI_MAP_ATTR_RELAXED_ORDER;
400
401 local_irq_save(flags);
402
403 iommu_batch_start(dev, prot, entry);
404
405 for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) {
406 long err = iommu_batch_add(base_paddr, mask);
407 if (unlikely(err < 0L))
408 goto iommu_map_fail;
409 }
410 if (unlikely(iommu_batch_end(mask) < 0L))
411 goto iommu_map_fail;
412
413 local_irq_restore(flags);
414
415 return ret;
416
417 bad:
418 if (printk_ratelimit())
419 WARN_ON(1);
420 return DMA_MAPPING_ERROR;
421
422 iommu_map_fail:
423 local_irq_restore(flags);
424 iommu_tbl_range_free(tbl, bus_addr, npages, IOMMU_ERROR_CODE);
425 return DMA_MAPPING_ERROR;
426 }
427
dma_4v_unmap_page(struct device * dev,dma_addr_t bus_addr,size_t sz,enum dma_data_direction direction,unsigned long attrs)428 static void dma_4v_unmap_page(struct device *dev, dma_addr_t bus_addr,
429 size_t sz, enum dma_data_direction direction,
430 unsigned long attrs)
431 {
432 struct pci_pbm_info *pbm;
433 struct iommu *iommu;
434 struct atu *atu;
435 struct iommu_map_table *tbl;
436 unsigned long npages;
437 unsigned long iotsb_num;
438 long entry;
439 u32 devhandle;
440
441 if (unlikely(direction == DMA_NONE)) {
442 if (printk_ratelimit())
443 WARN_ON(1);
444 return;
445 }
446
447 iommu = dev->archdata.iommu;
448 pbm = dev->archdata.host_controller;
449 atu = iommu->atu;
450 devhandle = pbm->devhandle;
451
452 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
453 npages >>= IO_PAGE_SHIFT;
454 bus_addr &= IO_PAGE_MASK;
455
456 if (bus_addr <= DMA_BIT_MASK(32)) {
457 iotsb_num = 0; /* we don't care for legacy iommu */
458 tbl = &iommu->tbl;
459 } else {
460 iotsb_num = atu->iotsb->iotsb_num;
461 tbl = &atu->tbl;
462 }
463 entry = (bus_addr - tbl->table_map_base) >> IO_PAGE_SHIFT;
464 dma_4v_iommu_demap(dev, devhandle, bus_addr, iotsb_num, entry, npages);
465 iommu_tbl_range_free(tbl, bus_addr, npages, IOMMU_ERROR_CODE);
466 }
467
dma_4v_map_sg(struct device * dev,struct scatterlist * sglist,int nelems,enum dma_data_direction direction,unsigned long attrs)468 static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
469 int nelems, enum dma_data_direction direction,
470 unsigned long attrs)
471 {
472 struct scatterlist *s, *outs, *segstart;
473 unsigned long flags, handle, prot;
474 dma_addr_t dma_next = 0, dma_addr;
475 unsigned int max_seg_size;
476 unsigned long seg_boundary_size;
477 int outcount, incount, i;
478 struct iommu *iommu;
479 struct atu *atu;
480 struct iommu_map_table *tbl;
481 u64 mask;
482 unsigned long base_shift;
483 long err;
484
485 BUG_ON(direction == DMA_NONE);
486
487 iommu = dev->archdata.iommu;
488 if (nelems == 0 || !iommu)
489 return 0;
490 atu = iommu->atu;
491
492 prot = HV_PCI_MAP_ATTR_READ;
493 if (direction != DMA_TO_DEVICE)
494 prot |= HV_PCI_MAP_ATTR_WRITE;
495
496 if (attrs & DMA_ATTR_WEAK_ORDERING)
497 prot |= HV_PCI_MAP_ATTR_RELAXED_ORDER;
498
499 outs = s = segstart = &sglist[0];
500 outcount = 1;
501 incount = nelems;
502 handle = 0;
503
504 /* Init first segment length for backout at failure */
505 outs->dma_length = 0;
506
507 local_irq_save(flags);
508
509 iommu_batch_start(dev, prot, ~0UL);
510
511 max_seg_size = dma_get_max_seg_size(dev);
512 seg_boundary_size = dma_get_seg_boundary_nr_pages(dev, IO_PAGE_SHIFT);
513
514 mask = *dev->dma_mask;
515 if (!iommu_use_atu(iommu, mask))
516 tbl = &iommu->tbl;
517 else
518 tbl = &atu->tbl;
519
520 base_shift = tbl->table_map_base >> IO_PAGE_SHIFT;
521
522 for_each_sg(sglist, s, nelems, i) {
523 unsigned long paddr, npages, entry, out_entry = 0, slen;
524
525 slen = s->length;
526 /* Sanity check */
527 if (slen == 0) {
528 dma_next = 0;
529 continue;
530 }
531 /* Allocate iommu entries for that segment */
532 paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s);
533 npages = iommu_num_pages(paddr, slen, IO_PAGE_SIZE);
534 entry = iommu_tbl_range_alloc(dev, tbl, npages,
535 &handle, (unsigned long)(-1), 0);
536
537 /* Handle failure */
538 if (unlikely(entry == IOMMU_ERROR_CODE)) {
539 pr_err_ratelimited("iommu_alloc failed, iommu %p paddr %lx npages %lx\n",
540 tbl, paddr, npages);
541 goto iommu_map_failed;
542 }
543
544 iommu_batch_new_entry(entry, mask);
545
546 /* Convert entry to a dma_addr_t */
547 dma_addr = tbl->table_map_base + (entry << IO_PAGE_SHIFT);
548 dma_addr |= (s->offset & ~IO_PAGE_MASK);
549
550 /* Insert into HW table */
551 paddr &= IO_PAGE_MASK;
552 while (npages--) {
553 err = iommu_batch_add(paddr, mask);
554 if (unlikely(err < 0L))
555 goto iommu_map_failed;
556 paddr += IO_PAGE_SIZE;
557 }
558
559 /* If we are in an open segment, try merging */
560 if (segstart != s) {
561 /* We cannot merge if:
562 * - allocated dma_addr isn't contiguous to previous allocation
563 */
564 if ((dma_addr != dma_next) ||
565 (outs->dma_length + s->length > max_seg_size) ||
566 (is_span_boundary(out_entry, base_shift,
567 seg_boundary_size, outs, s))) {
568 /* Can't merge: create a new segment */
569 segstart = s;
570 outcount++;
571 outs = sg_next(outs);
572 } else {
573 outs->dma_length += s->length;
574 }
575 }
576
577 if (segstart == s) {
578 /* This is a new segment, fill entries */
579 outs->dma_address = dma_addr;
580 outs->dma_length = slen;
581 out_entry = entry;
582 }
583
584 /* Calculate next page pointer for contiguous check */
585 dma_next = dma_addr + slen;
586 }
587
588 err = iommu_batch_end(mask);
589
590 if (unlikely(err < 0L))
591 goto iommu_map_failed;
592
593 local_irq_restore(flags);
594
595 if (outcount < incount) {
596 outs = sg_next(outs);
597 outs->dma_address = DMA_MAPPING_ERROR;
598 outs->dma_length = 0;
599 }
600
601 return outcount;
602
603 iommu_map_failed:
604 for_each_sg(sglist, s, nelems, i) {
605 if (s->dma_length != 0) {
606 unsigned long vaddr, npages;
607
608 vaddr = s->dma_address & IO_PAGE_MASK;
609 npages = iommu_num_pages(s->dma_address, s->dma_length,
610 IO_PAGE_SIZE);
611 iommu_tbl_range_free(tbl, vaddr, npages,
612 IOMMU_ERROR_CODE);
613 /* XXX demap? XXX */
614 s->dma_address = DMA_MAPPING_ERROR;
615 s->dma_length = 0;
616 }
617 if (s == outs)
618 break;
619 }
620 local_irq_restore(flags);
621
622 return 0;
623 }
624
dma_4v_unmap_sg(struct device * dev,struct scatterlist * sglist,int nelems,enum dma_data_direction direction,unsigned long attrs)625 static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist,
626 int nelems, enum dma_data_direction direction,
627 unsigned long attrs)
628 {
629 struct pci_pbm_info *pbm;
630 struct scatterlist *sg;
631 struct iommu *iommu;
632 struct atu *atu;
633 unsigned long flags, entry;
634 unsigned long iotsb_num;
635 u32 devhandle;
636
637 BUG_ON(direction == DMA_NONE);
638
639 iommu = dev->archdata.iommu;
640 pbm = dev->archdata.host_controller;
641 atu = iommu->atu;
642 devhandle = pbm->devhandle;
643
644 local_irq_save(flags);
645
646 sg = sglist;
647 while (nelems--) {
648 dma_addr_t dma_handle = sg->dma_address;
649 unsigned int len = sg->dma_length;
650 unsigned long npages;
651 struct iommu_map_table *tbl;
652 unsigned long shift = IO_PAGE_SHIFT;
653
654 if (!len)
655 break;
656 npages = iommu_num_pages(dma_handle, len, IO_PAGE_SIZE);
657
658 if (dma_handle <= DMA_BIT_MASK(32)) {
659 iotsb_num = 0; /* we don't care for legacy iommu */
660 tbl = &iommu->tbl;
661 } else {
662 iotsb_num = atu->iotsb->iotsb_num;
663 tbl = &atu->tbl;
664 }
665 entry = ((dma_handle - tbl->table_map_base) >> shift);
666 dma_4v_iommu_demap(dev, devhandle, dma_handle, iotsb_num,
667 entry, npages);
668 iommu_tbl_range_free(tbl, dma_handle, npages,
669 IOMMU_ERROR_CODE);
670 sg = sg_next(sg);
671 }
672
673 local_irq_restore(flags);
674 }
675
dma_4v_supported(struct device * dev,u64 device_mask)676 static int dma_4v_supported(struct device *dev, u64 device_mask)
677 {
678 struct iommu *iommu = dev->archdata.iommu;
679
680 if (ali_sound_dma_hack(dev, device_mask))
681 return 1;
682 if (device_mask < iommu->dma_addr_mask)
683 return 0;
684 return 1;
685 }
686
687 static const struct dma_map_ops sun4v_dma_ops = {
688 .alloc = dma_4v_alloc_coherent,
689 .free = dma_4v_free_coherent,
690 .map_page = dma_4v_map_page,
691 .unmap_page = dma_4v_unmap_page,
692 .map_sg = dma_4v_map_sg,
693 .unmap_sg = dma_4v_unmap_sg,
694 .dma_supported = dma_4v_supported,
695 };
696
pci_sun4v_scan_bus(struct pci_pbm_info * pbm,struct device * parent)697 static void pci_sun4v_scan_bus(struct pci_pbm_info *pbm, struct device *parent)
698 {
699 struct property *prop;
700 struct device_node *dp;
701
702 dp = pbm->op->dev.of_node;
703 prop = of_find_property(dp, "66mhz-capable", NULL);
704 pbm->is_66mhz_capable = (prop != NULL);
705 pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
706
707 /* XXX register error interrupt handlers XXX */
708 }
709
probe_existing_entries(struct pci_pbm_info * pbm,struct iommu_map_table * iommu)710 static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
711 struct iommu_map_table *iommu)
712 {
713 struct iommu_pool *pool;
714 unsigned long i, pool_nr, cnt = 0;
715 u32 devhandle;
716
717 devhandle = pbm->devhandle;
718 for (pool_nr = 0; pool_nr < iommu->nr_pools; pool_nr++) {
719 pool = &(iommu->pools[pool_nr]);
720 for (i = pool->start; i <= pool->end; i++) {
721 unsigned long ret, io_attrs, ra;
722
723 ret = pci_sun4v_iommu_getmap(devhandle,
724 HV_PCI_TSBID(0, i),
725 &io_attrs, &ra);
726 if (ret == HV_EOK) {
727 if (page_in_phys_avail(ra)) {
728 pci_sun4v_iommu_demap(devhandle,
729 HV_PCI_TSBID(0,
730 i), 1);
731 } else {
732 cnt++;
733 __set_bit(i, iommu->map);
734 }
735 }
736 }
737 }
738 return cnt;
739 }
740
pci_sun4v_atu_alloc_iotsb(struct pci_pbm_info * pbm)741 static int pci_sun4v_atu_alloc_iotsb(struct pci_pbm_info *pbm)
742 {
743 struct atu *atu = pbm->iommu->atu;
744 struct atu_iotsb *iotsb;
745 void *table;
746 u64 table_size;
747 u64 iotsb_num;
748 unsigned long order;
749 unsigned long err;
750
751 iotsb = kzalloc(sizeof(*iotsb), GFP_KERNEL);
752 if (!iotsb) {
753 err = -ENOMEM;
754 goto out_err;
755 }
756 atu->iotsb = iotsb;
757
758 /* calculate size of IOTSB */
759 table_size = (atu->size / IO_PAGE_SIZE) * 8;
760 order = get_order(table_size);
761 table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
762 if (!table) {
763 err = -ENOMEM;
764 goto table_failed;
765 }
766 iotsb->table = table;
767 iotsb->ra = __pa(table);
768 iotsb->dvma_size = atu->size;
769 iotsb->dvma_base = atu->base;
770 iotsb->table_size = table_size;
771 iotsb->page_size = IO_PAGE_SIZE;
772
773 /* configure and register IOTSB with HV */
774 err = pci_sun4v_iotsb_conf(pbm->devhandle,
775 iotsb->ra,
776 iotsb->table_size,
777 iotsb->page_size,
778 iotsb->dvma_base,
779 &iotsb_num);
780 if (err) {
781 pr_err(PFX "pci_iotsb_conf failed error: %ld\n", err);
782 goto iotsb_conf_failed;
783 }
784 iotsb->iotsb_num = iotsb_num;
785
786 err = dma_4v_iotsb_bind(pbm->devhandle, iotsb_num, pbm->pci_bus);
787 if (err) {
788 pr_err(PFX "pci_iotsb_bind failed error: %ld\n", err);
789 goto iotsb_conf_failed;
790 }
791
792 return 0;
793
794 iotsb_conf_failed:
795 free_pages((unsigned long)table, order);
796 table_failed:
797 kfree(iotsb);
798 out_err:
799 return err;
800 }
801
pci_sun4v_atu_init(struct pci_pbm_info * pbm)802 static int pci_sun4v_atu_init(struct pci_pbm_info *pbm)
803 {
804 struct atu *atu = pbm->iommu->atu;
805 unsigned long err;
806 const u64 *ranges;
807 u64 map_size, num_iotte;
808 u64 dma_mask;
809 const u32 *page_size;
810 int len;
811
812 ranges = of_get_property(pbm->op->dev.of_node, "iommu-address-ranges",
813 &len);
814 if (!ranges) {
815 pr_err(PFX "No iommu-address-ranges\n");
816 return -EINVAL;
817 }
818
819 page_size = of_get_property(pbm->op->dev.of_node, "iommu-pagesizes",
820 NULL);
821 if (!page_size) {
822 pr_err(PFX "No iommu-pagesizes\n");
823 return -EINVAL;
824 }
825
826 /* There are 4 iommu-address-ranges supported. Each range is pair of
827 * {base, size}. The ranges[0] and ranges[1] are 32bit address space
828 * while ranges[2] and ranges[3] are 64bit space. We want to use 64bit
829 * address ranges to support 64bit addressing. Because 'size' for
830 * address ranges[2] and ranges[3] are same we can select either of
831 * ranges[2] or ranges[3] for mapping. However due to 'size' is too
832 * large for OS to allocate IOTSB we are using fix size 32G
833 * (ATU_64_SPACE_SIZE) which is more than enough for all PCIe devices
834 * to share.
835 */
836 atu->ranges = (struct atu_ranges *)ranges;
837 atu->base = atu->ranges[3].base;
838 atu->size = ATU_64_SPACE_SIZE;
839
840 /* Create IOTSB */
841 err = pci_sun4v_atu_alloc_iotsb(pbm);
842 if (err) {
843 pr_err(PFX "Error creating ATU IOTSB\n");
844 return err;
845 }
846
847 /* Create ATU iommu map.
848 * One bit represents one iotte in IOTSB table.
849 */
850 dma_mask = (roundup_pow_of_two(atu->size) - 1UL);
851 num_iotte = atu->size / IO_PAGE_SIZE;
852 map_size = num_iotte / 8;
853 atu->tbl.table_map_base = atu->base;
854 atu->dma_addr_mask = dma_mask;
855 atu->tbl.map = kzalloc(map_size, GFP_KERNEL);
856 if (!atu->tbl.map)
857 return -ENOMEM;
858
859 iommu_tbl_pool_init(&atu->tbl, num_iotte, IO_PAGE_SHIFT,
860 NULL, false /* no large_pool */,
861 0 /* default npools */,
862 false /* want span boundary checking */);
863
864 return 0;
865 }
866
pci_sun4v_iommu_init(struct pci_pbm_info * pbm)867 static int pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
868 {
869 static const u32 vdma_default[] = { 0x80000000, 0x80000000 };
870 struct iommu *iommu = pbm->iommu;
871 unsigned long num_tsb_entries, sz;
872 u32 dma_mask, dma_offset;
873 const u32 *vdma;
874
875 vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL);
876 if (!vdma)
877 vdma = vdma_default;
878
879 if ((vdma[0] | vdma[1]) & ~IO_PAGE_MASK) {
880 printk(KERN_ERR PFX "Strange virtual-dma[%08x:%08x].\n",
881 vdma[0], vdma[1]);
882 return -EINVAL;
883 }
884
885 dma_mask = (roundup_pow_of_two(vdma[1]) - 1UL);
886 num_tsb_entries = vdma[1] / IO_PAGE_SIZE;
887
888 dma_offset = vdma[0];
889
890 /* Setup initial software IOMMU state. */
891 spin_lock_init(&iommu->lock);
892 iommu->ctx_lowest_free = 1;
893 iommu->tbl.table_map_base = dma_offset;
894 iommu->dma_addr_mask = dma_mask;
895
896 /* Allocate and initialize the free area map. */
897 sz = (num_tsb_entries + 7) / 8;
898 sz = (sz + 7UL) & ~7UL;
899 iommu->tbl.map = kzalloc(sz, GFP_KERNEL);
900 if (!iommu->tbl.map) {
901 printk(KERN_ERR PFX "Error, kmalloc(arena.map) failed.\n");
902 return -ENOMEM;
903 }
904 iommu_tbl_pool_init(&iommu->tbl, num_tsb_entries, IO_PAGE_SHIFT,
905 NULL, false /* no large_pool */,
906 0 /* default npools */,
907 false /* want span boundary checking */);
908 sz = probe_existing_entries(pbm, &iommu->tbl);
909 if (sz)
910 printk("%s: Imported %lu TSB entries from OBP\n",
911 pbm->name, sz);
912
913 return 0;
914 }
915
916 #ifdef CONFIG_PCI_MSI
917 struct pci_sun4v_msiq_entry {
918 u64 version_type;
919 #define MSIQ_VERSION_MASK 0xffffffff00000000UL
920 #define MSIQ_VERSION_SHIFT 32
921 #define MSIQ_TYPE_MASK 0x00000000000000ffUL
922 #define MSIQ_TYPE_SHIFT 0
923 #define MSIQ_TYPE_NONE 0x00
924 #define MSIQ_TYPE_MSG 0x01
925 #define MSIQ_TYPE_MSI32 0x02
926 #define MSIQ_TYPE_MSI64 0x03
927 #define MSIQ_TYPE_INTX 0x08
928 #define MSIQ_TYPE_NONE2 0xff
929
930 u64 intx_sysino;
931 u64 reserved1;
932 u64 stick;
933 u64 req_id; /* bus/device/func */
934 #define MSIQ_REQID_BUS_MASK 0xff00UL
935 #define MSIQ_REQID_BUS_SHIFT 8
936 #define MSIQ_REQID_DEVICE_MASK 0x00f8UL
937 #define MSIQ_REQID_DEVICE_SHIFT 3
938 #define MSIQ_REQID_FUNC_MASK 0x0007UL
939 #define MSIQ_REQID_FUNC_SHIFT 0
940
941 u64 msi_address;
942
943 /* The format of this value is message type dependent.
944 * For MSI bits 15:0 are the data from the MSI packet.
945 * For MSI-X bits 31:0 are the data from the MSI packet.
946 * For MSG, the message code and message routing code where:
947 * bits 39:32 is the bus/device/fn of the msg target-id
948 * bits 18:16 is the message routing code
949 * bits 7:0 is the message code
950 * For INTx the low order 2-bits are:
951 * 00 - INTA
952 * 01 - INTB
953 * 10 - INTC
954 * 11 - INTD
955 */
956 u64 msi_data;
957
958 u64 reserved2;
959 };
960
pci_sun4v_get_head(struct pci_pbm_info * pbm,unsigned long msiqid,unsigned long * head)961 static int pci_sun4v_get_head(struct pci_pbm_info *pbm, unsigned long msiqid,
962 unsigned long *head)
963 {
964 unsigned long err, limit;
965
966 err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, head);
967 if (unlikely(err))
968 return -ENXIO;
969
970 limit = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
971 if (unlikely(*head >= limit))
972 return -EFBIG;
973
974 return 0;
975 }
976
pci_sun4v_dequeue_msi(struct pci_pbm_info * pbm,unsigned long msiqid,unsigned long * head,unsigned long * msi)977 static int pci_sun4v_dequeue_msi(struct pci_pbm_info *pbm,
978 unsigned long msiqid, unsigned long *head,
979 unsigned long *msi)
980 {
981 struct pci_sun4v_msiq_entry *ep;
982 unsigned long err, type;
983
984 /* Note: void pointer arithmetic, 'head' is a byte offset */
985 ep = (pbm->msi_queues + ((msiqid - pbm->msiq_first) *
986 (pbm->msiq_ent_count *
987 sizeof(struct pci_sun4v_msiq_entry))) +
988 *head);
989
990 if ((ep->version_type & MSIQ_TYPE_MASK) == 0)
991 return 0;
992
993 type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT;
994 if (unlikely(type != MSIQ_TYPE_MSI32 &&
995 type != MSIQ_TYPE_MSI64))
996 return -EINVAL;
997
998 *msi = ep->msi_data;
999
1000 err = pci_sun4v_msi_setstate(pbm->devhandle,
1001 ep->msi_data /* msi_num */,
1002 HV_MSISTATE_IDLE);
1003 if (unlikely(err))
1004 return -ENXIO;
1005
1006 /* Clear the entry. */
1007 ep->version_type &= ~MSIQ_TYPE_MASK;
1008
1009 (*head) += sizeof(struct pci_sun4v_msiq_entry);
1010 if (*head >=
1011 (pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry)))
1012 *head = 0;
1013
1014 return 1;
1015 }
1016
pci_sun4v_set_head(struct pci_pbm_info * pbm,unsigned long msiqid,unsigned long head)1017 static int pci_sun4v_set_head(struct pci_pbm_info *pbm, unsigned long msiqid,
1018 unsigned long head)
1019 {
1020 unsigned long err;
1021
1022 err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head);
1023 if (unlikely(err))
1024 return -EINVAL;
1025
1026 return 0;
1027 }
1028
pci_sun4v_msi_setup(struct pci_pbm_info * pbm,unsigned long msiqid,unsigned long msi,int is_msi64)1029 static int pci_sun4v_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid,
1030 unsigned long msi, int is_msi64)
1031 {
1032 if (pci_sun4v_msi_setmsiq(pbm->devhandle, msi, msiqid,
1033 (is_msi64 ?
1034 HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32)))
1035 return -ENXIO;
1036 if (pci_sun4v_msi_setstate(pbm->devhandle, msi, HV_MSISTATE_IDLE))
1037 return -ENXIO;
1038 if (pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_VALID))
1039 return -ENXIO;
1040 return 0;
1041 }
1042
pci_sun4v_msi_teardown(struct pci_pbm_info * pbm,unsigned long msi)1043 static int pci_sun4v_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi)
1044 {
1045 unsigned long err, msiqid;
1046
1047 err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi, &msiqid);
1048 if (err)
1049 return -ENXIO;
1050
1051 pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_INVALID);
1052
1053 return 0;
1054 }
1055
pci_sun4v_msiq_alloc(struct pci_pbm_info * pbm)1056 static int pci_sun4v_msiq_alloc(struct pci_pbm_info *pbm)
1057 {
1058 unsigned long q_size, alloc_size, pages, order;
1059 int i;
1060
1061 q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
1062 alloc_size = (pbm->msiq_num * q_size);
1063 order = get_order(alloc_size);
1064 pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
1065 if (pages == 0UL) {
1066 printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
1067 order);
1068 return -ENOMEM;
1069 }
1070 memset((char *)pages, 0, PAGE_SIZE << order);
1071 pbm->msi_queues = (void *) pages;
1072
1073 for (i = 0; i < pbm->msiq_num; i++) {
1074 unsigned long err, base = __pa(pages + (i * q_size));
1075 unsigned long ret1, ret2;
1076
1077 err = pci_sun4v_msiq_conf(pbm->devhandle,
1078 pbm->msiq_first + i,
1079 base, pbm->msiq_ent_count);
1080 if (err) {
1081 printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n",
1082 err);
1083 goto h_error;
1084 }
1085
1086 err = pci_sun4v_msiq_info(pbm->devhandle,
1087 pbm->msiq_first + i,
1088 &ret1, &ret2);
1089 if (err) {
1090 printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n",
1091 err);
1092 goto h_error;
1093 }
1094 if (ret1 != base || ret2 != pbm->msiq_ent_count) {
1095 printk(KERN_ERR "MSI: Bogus qconf "
1096 "expected[%lx:%x] got[%lx:%lx]\n",
1097 base, pbm->msiq_ent_count,
1098 ret1, ret2);
1099 goto h_error;
1100 }
1101 }
1102
1103 return 0;
1104
1105 h_error:
1106 free_pages(pages, order);
1107 return -EINVAL;
1108 }
1109
pci_sun4v_msiq_free(struct pci_pbm_info * pbm)1110 static void pci_sun4v_msiq_free(struct pci_pbm_info *pbm)
1111 {
1112 unsigned long q_size, alloc_size, pages, order;
1113 int i;
1114
1115 for (i = 0; i < pbm->msiq_num; i++) {
1116 unsigned long msiqid = pbm->msiq_first + i;
1117
1118 (void) pci_sun4v_msiq_conf(pbm->devhandle, msiqid, 0UL, 0);
1119 }
1120
1121 q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
1122 alloc_size = (pbm->msiq_num * q_size);
1123 order = get_order(alloc_size);
1124
1125 pages = (unsigned long) pbm->msi_queues;
1126
1127 free_pages(pages, order);
1128
1129 pbm->msi_queues = NULL;
1130 }
1131
pci_sun4v_msiq_build_irq(struct pci_pbm_info * pbm,unsigned long msiqid,unsigned long devino)1132 static int pci_sun4v_msiq_build_irq(struct pci_pbm_info *pbm,
1133 unsigned long msiqid,
1134 unsigned long devino)
1135 {
1136 unsigned int irq = sun4v_build_irq(pbm->devhandle, devino);
1137
1138 if (!irq)
1139 return -ENOMEM;
1140
1141 if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID))
1142 return -EINVAL;
1143 if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE))
1144 return -EINVAL;
1145
1146 return irq;
1147 }
1148
1149 static const struct sparc64_msiq_ops pci_sun4v_msiq_ops = {
1150 .get_head = pci_sun4v_get_head,
1151 .dequeue_msi = pci_sun4v_dequeue_msi,
1152 .set_head = pci_sun4v_set_head,
1153 .msi_setup = pci_sun4v_msi_setup,
1154 .msi_teardown = pci_sun4v_msi_teardown,
1155 .msiq_alloc = pci_sun4v_msiq_alloc,
1156 .msiq_free = pci_sun4v_msiq_free,
1157 .msiq_build_irq = pci_sun4v_msiq_build_irq,
1158 };
1159
pci_sun4v_msi_init(struct pci_pbm_info * pbm)1160 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
1161 {
1162 sparc64_pbm_msi_init(pbm, &pci_sun4v_msiq_ops);
1163 }
1164 #else /* CONFIG_PCI_MSI */
pci_sun4v_msi_init(struct pci_pbm_info * pbm)1165 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
1166 {
1167 }
1168 #endif /* !(CONFIG_PCI_MSI) */
1169
pci_sun4v_pbm_init(struct pci_pbm_info * pbm,struct platform_device * op,u32 devhandle)1170 static int pci_sun4v_pbm_init(struct pci_pbm_info *pbm,
1171 struct platform_device *op, u32 devhandle)
1172 {
1173 struct device_node *dp = op->dev.of_node;
1174 int err;
1175
1176 pbm->numa_node = of_node_to_nid(dp);
1177
1178 pbm->pci_ops = &sun4v_pci_ops;
1179 pbm->config_space_reg_bits = 12;
1180
1181 pbm->index = pci_num_pbms++;
1182
1183 pbm->op = op;
1184
1185 pbm->devhandle = devhandle;
1186
1187 pbm->name = dp->full_name;
1188
1189 printk("%s: SUN4V PCI Bus Module\n", pbm->name);
1190 printk("%s: On NUMA node %d\n", pbm->name, pbm->numa_node);
1191
1192 pci_determine_mem_io_space(pbm);
1193
1194 pci_get_pbm_props(pbm);
1195
1196 err = pci_sun4v_iommu_init(pbm);
1197 if (err)
1198 return err;
1199
1200 pci_sun4v_msi_init(pbm);
1201
1202 pci_sun4v_scan_bus(pbm, &op->dev);
1203
1204 /* if atu_init fails its not complete failure.
1205 * we can still continue using legacy iommu.
1206 */
1207 if (pbm->iommu->atu) {
1208 err = pci_sun4v_atu_init(pbm);
1209 if (err) {
1210 kfree(pbm->iommu->atu);
1211 pbm->iommu->atu = NULL;
1212 pr_err(PFX "ATU init failed, err=%d\n", err);
1213 }
1214 }
1215
1216 pbm->next = pci_pbm_root;
1217 pci_pbm_root = pbm;
1218
1219 return 0;
1220 }
1221
pci_sun4v_probe(struct platform_device * op)1222 static int pci_sun4v_probe(struct platform_device *op)
1223 {
1224 const struct linux_prom64_registers *regs;
1225 static int hvapi_negotiated = 0;
1226 struct pci_pbm_info *pbm;
1227 struct device_node *dp;
1228 struct iommu *iommu;
1229 struct atu *atu;
1230 u32 devhandle;
1231 int i, err = -ENODEV;
1232 static bool hv_atu = true;
1233
1234 dp = op->dev.of_node;
1235
1236 if (!hvapi_negotiated++) {
1237 for (i = 0; i < ARRAY_SIZE(vpci_versions); i++) {
1238 vpci_major = vpci_versions[i].major;
1239 vpci_minor = vpci_versions[i].minor;
1240
1241 err = sun4v_hvapi_register(HV_GRP_PCI, vpci_major,
1242 &vpci_minor);
1243 if (!err)
1244 break;
1245 }
1246
1247 if (err) {
1248 pr_err(PFX "Could not register hvapi, err=%d\n", err);
1249 return err;
1250 }
1251 pr_info(PFX "Registered hvapi major[%lu] minor[%lu]\n",
1252 vpci_major, vpci_minor);
1253
1254 err = sun4v_hvapi_register(HV_GRP_ATU, vatu_major, &vatu_minor);
1255 if (err) {
1256 /* don't return an error if we fail to register the
1257 * ATU group, but ATU hcalls won't be available.
1258 */
1259 hv_atu = false;
1260 } else {
1261 pr_info(PFX "Registered hvapi ATU major[%lu] minor[%lu]\n",
1262 vatu_major, vatu_minor);
1263 }
1264
1265 dma_ops = &sun4v_dma_ops;
1266 }
1267
1268 regs = of_get_property(dp, "reg", NULL);
1269 err = -ENODEV;
1270 if (!regs) {
1271 printk(KERN_ERR PFX "Could not find config registers\n");
1272 goto out_err;
1273 }
1274 devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1275
1276 err = -ENOMEM;
1277 if (!iommu_batch_initialized) {
1278 for_each_possible_cpu(i) {
1279 unsigned long page = get_zeroed_page(GFP_KERNEL);
1280
1281 if (!page)
1282 goto out_err;
1283
1284 per_cpu(iommu_batch, i).pglist = (u64 *) page;
1285 }
1286 iommu_batch_initialized = 1;
1287 }
1288
1289 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
1290 if (!pbm) {
1291 printk(KERN_ERR PFX "Could not allocate pci_pbm_info\n");
1292 goto out_err;
1293 }
1294
1295 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
1296 if (!iommu) {
1297 printk(KERN_ERR PFX "Could not allocate pbm iommu\n");
1298 goto out_free_controller;
1299 }
1300
1301 pbm->iommu = iommu;
1302 iommu->atu = NULL;
1303 if (hv_atu) {
1304 atu = kzalloc(sizeof(*atu), GFP_KERNEL);
1305 if (!atu)
1306 pr_err(PFX "Could not allocate atu\n");
1307 else
1308 iommu->atu = atu;
1309 }
1310
1311 err = pci_sun4v_pbm_init(pbm, op, devhandle);
1312 if (err)
1313 goto out_free_iommu;
1314
1315 dev_set_drvdata(&op->dev, pbm);
1316
1317 return 0;
1318
1319 out_free_iommu:
1320 kfree(iommu->atu);
1321 kfree(pbm->iommu);
1322
1323 out_free_controller:
1324 kfree(pbm);
1325
1326 out_err:
1327 return err;
1328 }
1329
1330 static const struct of_device_id pci_sun4v_match[] = {
1331 {
1332 .name = "pci",
1333 .compatible = "SUNW,sun4v-pci",
1334 },
1335 {},
1336 };
1337
1338 static struct platform_driver pci_sun4v_driver = {
1339 .driver = {
1340 .name = DRIVER_NAME,
1341 .of_match_table = pci_sun4v_match,
1342 },
1343 .probe = pci_sun4v_probe,
1344 };
1345
pci_sun4v_init(void)1346 static int __init pci_sun4v_init(void)
1347 {
1348 return platform_driver_register(&pci_sun4v_driver);
1349 }
1350
1351 subsys_initcall(pci_sun4v_init);
1352
