1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/printk.h>
25 #include <linux/slab.h>
26 #include <linux/uaccess.h>
27 #include "kfd_priv.h"
28 #include "kfd_mqd_manager.h"
29 #include "v11_structs.h"
30 #include "gc/gc_11_0_0_offset.h"
31 #include "gc/gc_11_0_0_sh_mask.h"
32 #include "amdgpu_amdkfd.h"
33
get_mqd(void * mqd)34 static inline struct v11_compute_mqd *get_mqd(void *mqd)
35 {
36 return (struct v11_compute_mqd *)mqd;
37 }
38
get_sdma_mqd(void * mqd)39 static inline struct v11_sdma_mqd *get_sdma_mqd(void *mqd)
40 {
41 return (struct v11_sdma_mqd *)mqd;
42 }
43
update_cu_mask(struct mqd_manager * mm,void * mqd,struct mqd_update_info * minfo)44 static void update_cu_mask(struct mqd_manager *mm, void *mqd,
45 struct mqd_update_info *minfo)
46 {
47 struct v11_compute_mqd *m;
48 uint32_t se_mask[KFD_MAX_NUM_SE] = {0};
49 bool has_wa_flag = minfo && (minfo->update_flag & (UPDATE_FLAG_DBG_WA_ENABLE |
50 UPDATE_FLAG_DBG_WA_DISABLE));
51
52 if (!minfo || !(has_wa_flag || minfo->cu_mask.ptr))
53 return;
54
55 m = get_mqd(mqd);
56
57 if (has_wa_flag) {
58 uint32_t wa_mask = minfo->update_flag == UPDATE_FLAG_DBG_WA_ENABLE ?
59 0xffff : 0xffffffff;
60
61 m->compute_static_thread_mgmt_se0 = wa_mask;
62 m->compute_static_thread_mgmt_se1 = wa_mask;
63 m->compute_static_thread_mgmt_se2 = wa_mask;
64 m->compute_static_thread_mgmt_se3 = wa_mask;
65 m->compute_static_thread_mgmt_se4 = wa_mask;
66 m->compute_static_thread_mgmt_se5 = wa_mask;
67 m->compute_static_thread_mgmt_se6 = wa_mask;
68 m->compute_static_thread_mgmt_se7 = wa_mask;
69
70 return;
71 }
72
73 mqd_symmetrically_map_cu_mask(mm,
74 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0);
75
76 m->compute_static_thread_mgmt_se0 = se_mask[0];
77 m->compute_static_thread_mgmt_se1 = se_mask[1];
78 m->compute_static_thread_mgmt_se2 = se_mask[2];
79 m->compute_static_thread_mgmt_se3 = se_mask[3];
80 m->compute_static_thread_mgmt_se4 = se_mask[4];
81 m->compute_static_thread_mgmt_se5 = se_mask[5];
82 m->compute_static_thread_mgmt_se6 = se_mask[6];
83 m->compute_static_thread_mgmt_se7 = se_mask[7];
84
85 pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n",
86 m->compute_static_thread_mgmt_se0,
87 m->compute_static_thread_mgmt_se1,
88 m->compute_static_thread_mgmt_se2,
89 m->compute_static_thread_mgmt_se3,
90 m->compute_static_thread_mgmt_se4,
91 m->compute_static_thread_mgmt_se5,
92 m->compute_static_thread_mgmt_se6,
93 m->compute_static_thread_mgmt_se7);
94 }
95
set_priority(struct v11_compute_mqd * m,struct queue_properties * q)96 static void set_priority(struct v11_compute_mqd *m, struct queue_properties *q)
97 {
98 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority];
99 m->cp_hqd_queue_priority = q->priority;
100 }
101
allocate_mqd(struct kfd_node * node,struct queue_properties * q)102 static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,
103 struct queue_properties *q)
104 {
105 struct kfd_mem_obj *mqd_mem_obj;
106 int size;
107
108 /*
109 * MES write to areas beyond MQD size. So allocate
110 * 1 PAGE_SIZE memory for MQD is MES is enabled.
111 */
112 if (node->kfd->shared_resources.enable_mes)
113 size = PAGE_SIZE;
114 else
115 size = sizeof(struct v11_compute_mqd);
116
117 if (kfd_gtt_sa_allocate(node, size, &mqd_mem_obj))
118 return NULL;
119
120 return mqd_mem_obj;
121 }
122
init_mqd(struct mqd_manager * mm,void ** mqd,struct kfd_mem_obj * mqd_mem_obj,uint64_t * gart_addr,struct queue_properties * q)123 static void init_mqd(struct mqd_manager *mm, void **mqd,
124 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
125 struct queue_properties *q)
126 {
127 uint64_t addr;
128 struct v11_compute_mqd *m;
129 int size;
130 uint32_t wa_mask = q->is_dbg_wa ? 0xffff : 0xffffffff;
131
132 m = (struct v11_compute_mqd *) mqd_mem_obj->cpu_ptr;
133 addr = mqd_mem_obj->gpu_addr;
134
135 if (mm->dev->kfd->shared_resources.enable_mes)
136 size = PAGE_SIZE;
137 else
138 size = sizeof(struct v11_compute_mqd);
139
140 memset(m, 0, size);
141
142 m->header = 0xC0310800;
143 m->compute_pipelinestat_enable = 1;
144
145 m->compute_static_thread_mgmt_se0 = wa_mask;
146 m->compute_static_thread_mgmt_se1 = wa_mask;
147 m->compute_static_thread_mgmt_se2 = wa_mask;
148 m->compute_static_thread_mgmt_se3 = wa_mask;
149 m->compute_static_thread_mgmt_se4 = wa_mask;
150 m->compute_static_thread_mgmt_se5 = wa_mask;
151 m->compute_static_thread_mgmt_se6 = wa_mask;
152 m->compute_static_thread_mgmt_se7 = wa_mask;
153
154 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
155 0x55 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
156
157 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT;
158
159 m->cp_mqd_base_addr_lo = lower_32_bits(addr);
160 m->cp_mqd_base_addr_hi = upper_32_bits(addr);
161
162 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT |
163 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT |
164 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;
165
166 /* Set cp_hqd_hq_scheduler0 bit 14 to 1 to have the CP set up the
167 * DISPATCH_PTR. This is required for the kfd debugger
168 */
169 m->cp_hqd_hq_status0 = 1 << 14;
170
171 /*
172 * GFX11 RS64 CPFW version >= 509 supports PCIe atomics support
173 * acknowledgment.
174 */
175 if (amdgpu_amdkfd_have_atomics_support(mm->dev->adev))
176 m->cp_hqd_hq_status0 |= 1 << 29;
177
178 if (q->format == KFD_QUEUE_FORMAT_AQL) {
179 m->cp_hqd_aql_control =
180 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT;
181 }
182
183 if (mm->dev->kfd->cwsr_enabled) {
184 m->cp_hqd_persistent_state |=
185 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT);
186 m->cp_hqd_ctx_save_base_addr_lo =
187 lower_32_bits(q->ctx_save_restore_area_address);
188 m->cp_hqd_ctx_save_base_addr_hi =
189 upper_32_bits(q->ctx_save_restore_area_address);
190 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size;
191 m->cp_hqd_cntl_stack_size = q->ctl_stack_size;
192 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size;
193 m->cp_hqd_wg_state_offset = q->ctl_stack_size;
194 }
195
196 *mqd = m;
197 if (gart_addr)
198 *gart_addr = addr;
199 mm->update_mqd(mm, m, q, NULL);
200 }
201
load_mqd(struct mqd_manager * mm,void * mqd,uint32_t pipe_id,uint32_t queue_id,struct queue_properties * p,struct mm_struct * mms)202 static int load_mqd(struct mqd_manager *mm, void *mqd,
203 uint32_t pipe_id, uint32_t queue_id,
204 struct queue_properties *p, struct mm_struct *mms)
205 {
206 int r = 0;
207 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */
208 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
209
210 r = mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id,
211 (uint32_t __user *)p->write_ptr,
212 wptr_shift, 0, mms, 0);
213 return r;
214 }
215
update_mqd(struct mqd_manager * mm,void * mqd,struct queue_properties * q,struct mqd_update_info * minfo)216 static void update_mqd(struct mqd_manager *mm, void *mqd,
217 struct queue_properties *q,
218 struct mqd_update_info *minfo)
219 {
220 struct v11_compute_mqd *m;
221
222 m = get_mqd(mqd);
223
224 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
225 m->cp_hqd_pq_control |=
226 ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;
227 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
228
229 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
230 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
231
232 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
233 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
234 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
235 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);
236
237 m->cp_hqd_pq_doorbell_control =
238 q->doorbell_off <<
239 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
240 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
241 m->cp_hqd_pq_doorbell_control);
242
243 m->cp_hqd_ib_control = 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT;
244
245 /*
246 * HW does not clamp this field correctly. Maximum EOP queue size
247 * is constrained by per-SE EOP done signal count, which is 8-bit.
248 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit
249 * more than (EOP entry count - 1) so a queue size of 0x800 dwords
250 * is safe, giving a maximum field value of 0xA.
251 */
252 m->cp_hqd_eop_control = min(0xA,
253 ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1);
254 m->cp_hqd_eop_base_addr_lo =
255 lower_32_bits(q->eop_ring_buffer_address >> 8);
256 m->cp_hqd_eop_base_addr_hi =
257 upper_32_bits(q->eop_ring_buffer_address >> 8);
258
259 m->cp_hqd_iq_timer = 0;
260
261 m->cp_hqd_vmid = q->vmid;
262
263 if (q->format == KFD_QUEUE_FORMAT_AQL) {
264 /* GC 10 removed WPP_CLAMP from PQ Control */
265 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK |
266 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT |
267 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT ;
268 m->cp_hqd_pq_doorbell_control |=
269 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT;
270 }
271 if (mm->dev->kfd->cwsr_enabled)
272 m->cp_hqd_ctx_save_control = 0;
273
274 update_cu_mask(mm, mqd, minfo);
275 set_priority(m, q);
276
277 q->is_active = QUEUE_IS_ACTIVE(*q);
278 }
279
read_doorbell_id(void * mqd)280 static uint32_t read_doorbell_id(void *mqd)
281 {
282 struct v11_compute_mqd *m = (struct v11_compute_mqd *)mqd;
283
284 return m->queue_doorbell_id0;
285 }
286
get_wave_state(struct mqd_manager * mm,void * mqd,struct queue_properties * q,void __user * ctl_stack,u32 * ctl_stack_used_size,u32 * save_area_used_size)287 static int get_wave_state(struct mqd_manager *mm, void *mqd,
288 struct queue_properties *q,
289 void __user *ctl_stack,
290 u32 *ctl_stack_used_size,
291 u32 *save_area_used_size)
292 {
293 struct v11_compute_mqd *m;
294 struct kfd_context_save_area_header header;
295
296 m = get_mqd(mqd);
297
298 /* Control stack is written backwards, while workgroup context data
299 * is written forwards. Both starts from m->cp_hqd_cntl_stack_size.
300 * Current position is at m->cp_hqd_cntl_stack_offset and
301 * m->cp_hqd_wg_state_offset, respectively.
302 */
303 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size -
304 m->cp_hqd_cntl_stack_offset;
305 *save_area_used_size = m->cp_hqd_wg_state_offset -
306 m->cp_hqd_cntl_stack_size;
307
308 /* Control stack is not copied to user mode for GFXv11 because
309 * it's part of the context save area that is already
310 * accessible to user mode
311 */
312 header.wave_state.control_stack_size = *ctl_stack_used_size;
313 header.wave_state.wave_state_size = *save_area_used_size;
314
315 header.wave_state.wave_state_offset = m->cp_hqd_wg_state_offset;
316 header.wave_state.control_stack_offset = m->cp_hqd_cntl_stack_offset;
317
318 if (copy_to_user(ctl_stack, &header, sizeof(header.wave_state)))
319 return -EFAULT;
320
321 return 0;
322 }
323
checkpoint_mqd(struct mqd_manager * mm,void * mqd,void * mqd_dst,void * ctl_stack_dst)324 static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst)
325 {
326 struct v11_compute_mqd *m;
327
328 m = get_mqd(mqd);
329
330 memcpy(mqd_dst, m, sizeof(struct v11_compute_mqd));
331 }
332
restore_mqd(struct mqd_manager * mm,void ** mqd,struct kfd_mem_obj * mqd_mem_obj,uint64_t * gart_addr,struct queue_properties * qp,const void * mqd_src,const void * ctl_stack_src,const u32 ctl_stack_size)333 static void restore_mqd(struct mqd_manager *mm, void **mqd,
334 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
335 struct queue_properties *qp,
336 const void *mqd_src,
337 const void *ctl_stack_src, const u32 ctl_stack_size)
338 {
339 uint64_t addr;
340 struct v11_compute_mqd *m;
341
342 m = (struct v11_compute_mqd *) mqd_mem_obj->cpu_ptr;
343 addr = mqd_mem_obj->gpu_addr;
344
345 memcpy(m, mqd_src, sizeof(*m));
346
347 *mqd = m;
348 if (gart_addr)
349 *gart_addr = addr;
350
351 m->cp_hqd_pq_doorbell_control =
352 qp->doorbell_off <<
353 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
354 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
355 m->cp_hqd_pq_doorbell_control);
356
357 qp->is_active = 0;
358 }
359
360
init_mqd_hiq(struct mqd_manager * mm,void ** mqd,struct kfd_mem_obj * mqd_mem_obj,uint64_t * gart_addr,struct queue_properties * q)361 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,
362 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
363 struct queue_properties *q)
364 {
365 struct v11_compute_mqd *m;
366
367 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q);
368
369 m = get_mqd(*mqd);
370
371 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT |
372 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;
373 }
374
destroy_hiq_mqd(struct mqd_manager * mm,void * mqd,enum kfd_preempt_type type,unsigned int timeout,uint32_t pipe_id,uint32_t queue_id)375 static int destroy_hiq_mqd(struct mqd_manager *mm, void *mqd,
376 enum kfd_preempt_type type, unsigned int timeout,
377 uint32_t pipe_id, uint32_t queue_id)
378 {
379 int err;
380 struct v11_compute_mqd *m;
381 u32 doorbell_off;
382
383 m = get_mqd(mqd);
384
385 doorbell_off = m->cp_hqd_pq_doorbell_control >>
386 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
387
388 err = amdgpu_amdkfd_unmap_hiq(mm->dev->adev, doorbell_off, 0);
389 if (err)
390 pr_debug("Destroy HIQ MQD failed: %d\n", err);
391
392 return err;
393 }
394
init_mqd_sdma(struct mqd_manager * mm,void ** mqd,struct kfd_mem_obj * mqd_mem_obj,uint64_t * gart_addr,struct queue_properties * q)395 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd,
396 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
397 struct queue_properties *q)
398 {
399 struct v11_sdma_mqd *m;
400 int size;
401
402 m = (struct v11_sdma_mqd *) mqd_mem_obj->cpu_ptr;
403
404 if (mm->dev->kfd->shared_resources.enable_mes)
405 size = PAGE_SIZE;
406 else
407 size = sizeof(struct v11_sdma_mqd);
408
409 memset(m, 0, size);
410 *mqd = m;
411 if (gart_addr)
412 *gart_addr = mqd_mem_obj->gpu_addr;
413
414 mm->update_mqd(mm, m, q, NULL);
415 }
416
417 #define SDMA_RLC_DUMMY_DEFAULT 0xf
418
update_mqd_sdma(struct mqd_manager * mm,void * mqd,struct queue_properties * q,struct mqd_update_info * minfo)419 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd,
420 struct queue_properties *q,
421 struct mqd_update_info *minfo)
422 {
423 struct v11_sdma_mqd *m;
424
425 m = get_sdma_mqd(mqd);
426 m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1)
427 << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT |
428 q->vmid << SDMA0_QUEUE0_RB_CNTL__RB_VMID__SHIFT |
429 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
430 6 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
431 1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT;
432
433 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
434 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
435 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
436 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
437 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
438 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);
439 m->sdmax_rlcx_doorbell_offset =
440 q->doorbell_off << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT;
441
442 m->sdmax_rlcx_sched_cntl = (amdgpu_sdma_phase_quantum
443 << SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT)
444 & SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK;
445
446 m->sdma_engine_id = q->sdma_engine_id;
447 m->sdma_queue_id = q->sdma_queue_id;
448 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT;
449
450 q->is_active = QUEUE_IS_ACTIVE(*q);
451 }
452
453 #if defined(CONFIG_DEBUG_FS)
454
debugfs_show_mqd(struct seq_file * m,void * data)455 static int debugfs_show_mqd(struct seq_file *m, void *data)
456 {
457 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
458 data, sizeof(struct v11_compute_mqd), false);
459 return 0;
460 }
461
debugfs_show_mqd_sdma(struct seq_file * m,void * data)462 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data)
463 {
464 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
465 data, sizeof(struct v11_sdma_mqd), false);
466 return 0;
467 }
468
469 #endif
470
mqd_manager_init_v11(enum KFD_MQD_TYPE type,struct kfd_node * dev)471 struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type,
472 struct kfd_node *dev)
473 {
474 struct mqd_manager *mqd;
475
476 if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
477 return NULL;
478
479 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
480 if (!mqd)
481 return NULL;
482
483 mqd->dev = dev;
484
485 switch (type) {
486 case KFD_MQD_TYPE_CP:
487 pr_debug("%s@%i\n", __func__, __LINE__);
488 mqd->allocate_mqd = allocate_mqd;
489 mqd->init_mqd = init_mqd;
490 mqd->free_mqd = kfd_free_mqd_cp;
491 mqd->load_mqd = load_mqd;
492 mqd->update_mqd = update_mqd;
493 mqd->destroy_mqd = kfd_destroy_mqd_cp;
494 mqd->is_occupied = kfd_is_occupied_cp;
495 mqd->mqd_size = sizeof(struct v11_compute_mqd);
496 mqd->get_wave_state = get_wave_state;
497 mqd->mqd_stride = kfd_mqd_stride;
498 mqd->checkpoint_mqd = checkpoint_mqd;
499 mqd->restore_mqd = restore_mqd;
500 #if defined(CONFIG_DEBUG_FS)
501 mqd->debugfs_show_mqd = debugfs_show_mqd;
502 #endif
503 pr_debug("%s@%i\n", __func__, __LINE__);
504 break;
505 case KFD_MQD_TYPE_HIQ:
506 pr_debug("%s@%i\n", __func__, __LINE__);
507 mqd->allocate_mqd = allocate_hiq_mqd;
508 mqd->init_mqd = init_mqd_hiq;
509 mqd->free_mqd = free_mqd_hiq_sdma;
510 mqd->load_mqd = kfd_hiq_load_mqd_kiq;
511 mqd->update_mqd = update_mqd;
512 mqd->destroy_mqd = destroy_hiq_mqd;
513 mqd->is_occupied = kfd_is_occupied_cp;
514 mqd->mqd_size = sizeof(struct v11_compute_mqd);
515 mqd->mqd_stride = kfd_mqd_stride;
516 #if defined(CONFIG_DEBUG_FS)
517 mqd->debugfs_show_mqd = debugfs_show_mqd;
518 #endif
519 mqd->read_doorbell_id = read_doorbell_id;
520 pr_debug("%s@%i\n", __func__, __LINE__);
521 break;
522 case KFD_MQD_TYPE_DIQ:
523 mqd->allocate_mqd = allocate_mqd;
524 mqd->init_mqd = init_mqd_hiq;
525 mqd->free_mqd = kfd_free_mqd_cp;
526 mqd->load_mqd = load_mqd;
527 mqd->update_mqd = update_mqd;
528 mqd->destroy_mqd = kfd_destroy_mqd_cp;
529 mqd->is_occupied = kfd_is_occupied_cp;
530 mqd->mqd_size = sizeof(struct v11_compute_mqd);
531 #if defined(CONFIG_DEBUG_FS)
532 mqd->debugfs_show_mqd = debugfs_show_mqd;
533 #endif
534 break;
535 case KFD_MQD_TYPE_SDMA:
536 pr_debug("%s@%i\n", __func__, __LINE__);
537 mqd->allocate_mqd = allocate_sdma_mqd;
538 mqd->init_mqd = init_mqd_sdma;
539 mqd->free_mqd = free_mqd_hiq_sdma;
540 mqd->load_mqd = kfd_load_mqd_sdma;
541 mqd->update_mqd = update_mqd_sdma;
542 mqd->destroy_mqd = kfd_destroy_mqd_sdma;
543 mqd->is_occupied = kfd_is_occupied_sdma;
544 mqd->checkpoint_mqd = checkpoint_mqd;
545 mqd->restore_mqd = restore_mqd;
546 mqd->mqd_size = sizeof(struct v11_sdma_mqd);
547 mqd->mqd_stride = kfd_mqd_stride;
548 #if defined(CONFIG_DEBUG_FS)
549 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;
550 #endif
551 /*
552 * To allocate SDMA MQDs by generic functions
553 * when MES is enabled.
554 */
555 if (dev->kfd->shared_resources.enable_mes) {
556 mqd->allocate_mqd = allocate_mqd;
557 mqd->free_mqd = kfd_free_mqd_cp;
558 }
559 pr_debug("%s@%i\n", __func__, __LINE__);
560 break;
561 default:
562 kfree(mqd);
563 return NULL;
564 }
565
566 return mqd;
567 }
568
