1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for Broadcom MPI3 Storage Controllers
4 *
5 * Copyright (C) 2017-2023 Broadcom Inc.
6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
7 *
8 */
9
10 #include "mpi3mr.h"
11 #include <linux/io-64-nonatomic-lo-hi.h>
12
13 static int
14 mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, u32 reset_reason);
15 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc);
16 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
17 struct mpi3_ioc_facts_data *facts_data);
18 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
19 struct mpi3mr_drv_cmd *drv_cmd);
20
21 static int poll_queues;
22 module_param(poll_queues, int, 0444);
23 MODULE_PARM_DESC(poll_queues, "Number of queues for io_uring poll mode. (Range 1 - 126)");
24
25 #if defined(writeq) && defined(CONFIG_64BIT)
mpi3mr_writeq(__u64 b,volatile void __iomem * addr)26 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)
27 {
28 writeq(b, addr);
29 }
30 #else
mpi3mr_writeq(__u64 b,volatile void __iomem * addr)31 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)
32 {
33 __u64 data_out = b;
34
35 writel((u32)(data_out), addr);
36 writel((u32)(data_out >> 32), (addr + 4));
37 }
38 #endif
39
40 static inline bool
mpi3mr_check_req_qfull(struct op_req_qinfo * op_req_q)41 mpi3mr_check_req_qfull(struct op_req_qinfo *op_req_q)
42 {
43 u16 pi, ci, max_entries;
44 bool is_qfull = false;
45
46 pi = op_req_q->pi;
47 ci = READ_ONCE(op_req_q->ci);
48 max_entries = op_req_q->num_requests;
49
50 if ((ci == (pi + 1)) || ((!ci) && (pi == (max_entries - 1))))
51 is_qfull = true;
52
53 return is_qfull;
54 }
55
mpi3mr_sync_irqs(struct mpi3mr_ioc * mrioc)56 static void mpi3mr_sync_irqs(struct mpi3mr_ioc *mrioc)
57 {
58 u16 i, max_vectors;
59
60 max_vectors = mrioc->intr_info_count;
61
62 for (i = 0; i < max_vectors; i++)
63 synchronize_irq(pci_irq_vector(mrioc->pdev, i));
64 }
65
mpi3mr_ioc_disable_intr(struct mpi3mr_ioc * mrioc)66 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc)
67 {
68 mrioc->intr_enabled = 0;
69 mpi3mr_sync_irqs(mrioc);
70 }
71
mpi3mr_ioc_enable_intr(struct mpi3mr_ioc * mrioc)72 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc)
73 {
74 mrioc->intr_enabled = 1;
75 }
76
mpi3mr_cleanup_isr(struct mpi3mr_ioc * mrioc)77 static void mpi3mr_cleanup_isr(struct mpi3mr_ioc *mrioc)
78 {
79 u16 i;
80
81 mpi3mr_ioc_disable_intr(mrioc);
82
83 if (!mrioc->intr_info)
84 return;
85
86 for (i = 0; i < mrioc->intr_info_count; i++)
87 free_irq(pci_irq_vector(mrioc->pdev, i),
88 (mrioc->intr_info + i));
89
90 kfree(mrioc->intr_info);
91 mrioc->intr_info = NULL;
92 mrioc->intr_info_count = 0;
93 mrioc->is_intr_info_set = false;
94 pci_free_irq_vectors(mrioc->pdev);
95 }
96
mpi3mr_add_sg_single(void * paddr,u8 flags,u32 length,dma_addr_t dma_addr)97 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
98 dma_addr_t dma_addr)
99 {
100 struct mpi3_sge_common *sgel = paddr;
101
102 sgel->flags = flags;
103 sgel->length = cpu_to_le32(length);
104 sgel->address = cpu_to_le64(dma_addr);
105 }
106
mpi3mr_build_zero_len_sge(void * paddr)107 void mpi3mr_build_zero_len_sge(void *paddr)
108 {
109 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
110
111 mpi3mr_add_sg_single(paddr, sgl_flags, 0, -1);
112 }
113
mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc * mrioc,dma_addr_t phys_addr)114 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
115 dma_addr_t phys_addr)
116 {
117 if (!phys_addr)
118 return NULL;
119
120 if ((phys_addr < mrioc->reply_buf_dma) ||
121 (phys_addr > mrioc->reply_buf_dma_max_address))
122 return NULL;
123
124 return mrioc->reply_buf + (phys_addr - mrioc->reply_buf_dma);
125 }
126
mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc * mrioc,dma_addr_t phys_addr)127 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
128 dma_addr_t phys_addr)
129 {
130 if (!phys_addr)
131 return NULL;
132
133 return mrioc->sense_buf + (phys_addr - mrioc->sense_buf_dma);
134 }
135
mpi3mr_repost_reply_buf(struct mpi3mr_ioc * mrioc,u64 reply_dma)136 static void mpi3mr_repost_reply_buf(struct mpi3mr_ioc *mrioc,
137 u64 reply_dma)
138 {
139 u32 old_idx = 0;
140 unsigned long flags;
141
142 spin_lock_irqsave(&mrioc->reply_free_queue_lock, flags);
143 old_idx = mrioc->reply_free_queue_host_index;
144 mrioc->reply_free_queue_host_index = (
145 (mrioc->reply_free_queue_host_index ==
146 (mrioc->reply_free_qsz - 1)) ? 0 :
147 (mrioc->reply_free_queue_host_index + 1));
148 mrioc->reply_free_q[old_idx] = cpu_to_le64(reply_dma);
149 writel(mrioc->reply_free_queue_host_index,
150 &mrioc->sysif_regs->reply_free_host_index);
151 spin_unlock_irqrestore(&mrioc->reply_free_queue_lock, flags);
152 }
153
mpi3mr_repost_sense_buf(struct mpi3mr_ioc * mrioc,u64 sense_buf_dma)154 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
155 u64 sense_buf_dma)
156 {
157 u32 old_idx = 0;
158 unsigned long flags;
159
160 spin_lock_irqsave(&mrioc->sbq_lock, flags);
161 old_idx = mrioc->sbq_host_index;
162 mrioc->sbq_host_index = ((mrioc->sbq_host_index ==
163 (mrioc->sense_buf_q_sz - 1)) ? 0 :
164 (mrioc->sbq_host_index + 1));
165 mrioc->sense_buf_q[old_idx] = cpu_to_le64(sense_buf_dma);
166 writel(mrioc->sbq_host_index,
167 &mrioc->sysif_regs->sense_buffer_free_host_index);
168 spin_unlock_irqrestore(&mrioc->sbq_lock, flags);
169 }
170
mpi3mr_print_event_data(struct mpi3mr_ioc * mrioc,struct mpi3_event_notification_reply * event_reply)171 static void mpi3mr_print_event_data(struct mpi3mr_ioc *mrioc,
172 struct mpi3_event_notification_reply *event_reply)
173 {
174 char *desc = NULL;
175 u16 event;
176
177 event = event_reply->event;
178
179 switch (event) {
180 case MPI3_EVENT_LOG_DATA:
181 desc = "Log Data";
182 break;
183 case MPI3_EVENT_CHANGE:
184 desc = "Event Change";
185 break;
186 case MPI3_EVENT_GPIO_INTERRUPT:
187 desc = "GPIO Interrupt";
188 break;
189 case MPI3_EVENT_CABLE_MGMT:
190 desc = "Cable Management";
191 break;
192 case MPI3_EVENT_ENERGY_PACK_CHANGE:
193 desc = "Energy Pack Change";
194 break;
195 case MPI3_EVENT_DEVICE_ADDED:
196 {
197 struct mpi3_device_page0 *event_data =
198 (struct mpi3_device_page0 *)event_reply->event_data;
199 ioc_info(mrioc, "Device Added: dev=0x%04x Form=0x%x\n",
200 event_data->dev_handle, event_data->device_form);
201 return;
202 }
203 case MPI3_EVENT_DEVICE_INFO_CHANGED:
204 {
205 struct mpi3_device_page0 *event_data =
206 (struct mpi3_device_page0 *)event_reply->event_data;
207 ioc_info(mrioc, "Device Info Changed: dev=0x%04x Form=0x%x\n",
208 event_data->dev_handle, event_data->device_form);
209 return;
210 }
211 case MPI3_EVENT_DEVICE_STATUS_CHANGE:
212 {
213 struct mpi3_event_data_device_status_change *event_data =
214 (struct mpi3_event_data_device_status_change *)event_reply->event_data;
215 ioc_info(mrioc, "Device status Change: dev=0x%04x RC=0x%x\n",
216 event_data->dev_handle, event_data->reason_code);
217 return;
218 }
219 case MPI3_EVENT_SAS_DISCOVERY:
220 {
221 struct mpi3_event_data_sas_discovery *event_data =
222 (struct mpi3_event_data_sas_discovery *)event_reply->event_data;
223 ioc_info(mrioc, "SAS Discovery: (%s) status (0x%08x)\n",
224 (event_data->reason_code == MPI3_EVENT_SAS_DISC_RC_STARTED) ?
225 "start" : "stop",
226 le32_to_cpu(event_data->discovery_status));
227 return;
228 }
229 case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE:
230 desc = "SAS Broadcast Primitive";
231 break;
232 case MPI3_EVENT_SAS_NOTIFY_PRIMITIVE:
233 desc = "SAS Notify Primitive";
234 break;
235 case MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
236 desc = "SAS Init Device Status Change";
237 break;
238 case MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW:
239 desc = "SAS Init Table Overflow";
240 break;
241 case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
242 desc = "SAS Topology Change List";
243 break;
244 case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE:
245 desc = "Enclosure Device Status Change";
246 break;
247 case MPI3_EVENT_ENCL_DEVICE_ADDED:
248 desc = "Enclosure Added";
249 break;
250 case MPI3_EVENT_HARD_RESET_RECEIVED:
251 desc = "Hard Reset Received";
252 break;
253 case MPI3_EVENT_SAS_PHY_COUNTER:
254 desc = "SAS PHY Counter";
255 break;
256 case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR:
257 desc = "SAS Device Discovery Error";
258 break;
259 case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
260 desc = "PCIE Topology Change List";
261 break;
262 case MPI3_EVENT_PCIE_ENUMERATION:
263 {
264 struct mpi3_event_data_pcie_enumeration *event_data =
265 (struct mpi3_event_data_pcie_enumeration *)event_reply->event_data;
266 ioc_info(mrioc, "PCIE Enumeration: (%s)",
267 (event_data->reason_code ==
268 MPI3_EVENT_PCIE_ENUM_RC_STARTED) ? "start" : "stop");
269 if (event_data->enumeration_status)
270 ioc_info(mrioc, "enumeration_status(0x%08x)\n",
271 le32_to_cpu(event_data->enumeration_status));
272 return;
273 }
274 case MPI3_EVENT_PREPARE_FOR_RESET:
275 desc = "Prepare For Reset";
276 break;
277 }
278
279 if (!desc)
280 return;
281
282 ioc_info(mrioc, "%s\n", desc);
283 }
284
mpi3mr_handle_events(struct mpi3mr_ioc * mrioc,struct mpi3_default_reply * def_reply)285 static void mpi3mr_handle_events(struct mpi3mr_ioc *mrioc,
286 struct mpi3_default_reply *def_reply)
287 {
288 struct mpi3_event_notification_reply *event_reply =
289 (struct mpi3_event_notification_reply *)def_reply;
290
291 mrioc->change_count = le16_to_cpu(event_reply->ioc_change_count);
292 mpi3mr_print_event_data(mrioc, event_reply);
293 mpi3mr_os_handle_events(mrioc, event_reply);
294 }
295
296 static struct mpi3mr_drv_cmd *
mpi3mr_get_drv_cmd(struct mpi3mr_ioc * mrioc,u16 host_tag,struct mpi3_default_reply * def_reply)297 mpi3mr_get_drv_cmd(struct mpi3mr_ioc *mrioc, u16 host_tag,
298 struct mpi3_default_reply *def_reply)
299 {
300 u16 idx;
301
302 switch (host_tag) {
303 case MPI3MR_HOSTTAG_INITCMDS:
304 return &mrioc->init_cmds;
305 case MPI3MR_HOSTTAG_CFG_CMDS:
306 return &mrioc->cfg_cmds;
307 case MPI3MR_HOSTTAG_BSG_CMDS:
308 return &mrioc->bsg_cmds;
309 case MPI3MR_HOSTTAG_BLK_TMS:
310 return &mrioc->host_tm_cmds;
311 case MPI3MR_HOSTTAG_PEL_ABORT:
312 return &mrioc->pel_abort_cmd;
313 case MPI3MR_HOSTTAG_PEL_WAIT:
314 return &mrioc->pel_cmds;
315 case MPI3MR_HOSTTAG_TRANSPORT_CMDS:
316 return &mrioc->transport_cmds;
317 case MPI3MR_HOSTTAG_INVALID:
318 if (def_reply && def_reply->function ==
319 MPI3_FUNCTION_EVENT_NOTIFICATION)
320 mpi3mr_handle_events(mrioc, def_reply);
321 return NULL;
322 default:
323 break;
324 }
325 if (host_tag >= MPI3MR_HOSTTAG_DEVRMCMD_MIN &&
326 host_tag <= MPI3MR_HOSTTAG_DEVRMCMD_MAX) {
327 idx = host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN;
328 return &mrioc->dev_rmhs_cmds[idx];
329 }
330
331 if (host_tag >= MPI3MR_HOSTTAG_EVTACKCMD_MIN &&
332 host_tag <= MPI3MR_HOSTTAG_EVTACKCMD_MAX) {
333 idx = host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN;
334 return &mrioc->evtack_cmds[idx];
335 }
336
337 return NULL;
338 }
339
mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc * mrioc,struct mpi3_default_reply_descriptor * reply_desc,u64 * reply_dma)340 static void mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc *mrioc,
341 struct mpi3_default_reply_descriptor *reply_desc, u64 *reply_dma)
342 {
343 u16 reply_desc_type, host_tag = 0;
344 u16 ioc_status = MPI3_IOCSTATUS_SUCCESS;
345 u32 ioc_loginfo = 0;
346 struct mpi3_status_reply_descriptor *status_desc;
347 struct mpi3_address_reply_descriptor *addr_desc;
348 struct mpi3_success_reply_descriptor *success_desc;
349 struct mpi3_default_reply *def_reply = NULL;
350 struct mpi3mr_drv_cmd *cmdptr = NULL;
351 struct mpi3_scsi_io_reply *scsi_reply;
352 u8 *sense_buf = NULL;
353
354 *reply_dma = 0;
355 reply_desc_type = le16_to_cpu(reply_desc->reply_flags) &
356 MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK;
357 switch (reply_desc_type) {
358 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS:
359 status_desc = (struct mpi3_status_reply_descriptor *)reply_desc;
360 host_tag = le16_to_cpu(status_desc->host_tag);
361 ioc_status = le16_to_cpu(status_desc->ioc_status);
362 if (ioc_status &
363 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
364 ioc_loginfo = le32_to_cpu(status_desc->ioc_log_info);
365 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK;
366 break;
367 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY:
368 addr_desc = (struct mpi3_address_reply_descriptor *)reply_desc;
369 *reply_dma = le64_to_cpu(addr_desc->reply_frame_address);
370 def_reply = mpi3mr_get_reply_virt_addr(mrioc, *reply_dma);
371 if (!def_reply)
372 goto out;
373 host_tag = le16_to_cpu(def_reply->host_tag);
374 ioc_status = le16_to_cpu(def_reply->ioc_status);
375 if (ioc_status &
376 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
377 ioc_loginfo = le32_to_cpu(def_reply->ioc_log_info);
378 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK;
379 if (def_reply->function == MPI3_FUNCTION_SCSI_IO) {
380 scsi_reply = (struct mpi3_scsi_io_reply *)def_reply;
381 sense_buf = mpi3mr_get_sensebuf_virt_addr(mrioc,
382 le64_to_cpu(scsi_reply->sense_data_buffer_address));
383 }
384 break;
385 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS:
386 success_desc = (struct mpi3_success_reply_descriptor *)reply_desc;
387 host_tag = le16_to_cpu(success_desc->host_tag);
388 break;
389 default:
390 break;
391 }
392
393 cmdptr = mpi3mr_get_drv_cmd(mrioc, host_tag, def_reply);
394 if (cmdptr) {
395 if (cmdptr->state & MPI3MR_CMD_PENDING) {
396 cmdptr->state |= MPI3MR_CMD_COMPLETE;
397 cmdptr->ioc_loginfo = ioc_loginfo;
398 cmdptr->ioc_status = ioc_status;
399 cmdptr->state &= ~MPI3MR_CMD_PENDING;
400 if (def_reply) {
401 cmdptr->state |= MPI3MR_CMD_REPLY_VALID;
402 memcpy((u8 *)cmdptr->reply, (u8 *)def_reply,
403 mrioc->reply_sz);
404 }
405 if (sense_buf && cmdptr->sensebuf) {
406 cmdptr->is_sense = 1;
407 memcpy(cmdptr->sensebuf, sense_buf,
408 MPI3MR_SENSE_BUF_SZ);
409 }
410 if (cmdptr->is_waiting) {
411 complete(&cmdptr->done);
412 cmdptr->is_waiting = 0;
413 } else if (cmdptr->callback)
414 cmdptr->callback(mrioc, cmdptr);
415 }
416 }
417 out:
418 if (sense_buf)
419 mpi3mr_repost_sense_buf(mrioc,
420 le64_to_cpu(scsi_reply->sense_data_buffer_address));
421 }
422
mpi3mr_process_admin_reply_q(struct mpi3mr_ioc * mrioc)423 int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc)
424 {
425 u32 exp_phase = mrioc->admin_reply_ephase;
426 u32 admin_reply_ci = mrioc->admin_reply_ci;
427 u32 num_admin_replies = 0;
428 u64 reply_dma = 0;
429 struct mpi3_default_reply_descriptor *reply_desc;
430
431 if (!atomic_add_unless(&mrioc->admin_reply_q_in_use, 1, 1))
432 return 0;
433
434 reply_desc = (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
435 admin_reply_ci;
436
437 if ((le16_to_cpu(reply_desc->reply_flags) &
438 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) {
439 atomic_dec(&mrioc->admin_reply_q_in_use);
440 return 0;
441 }
442
443 do {
444 if (mrioc->unrecoverable)
445 break;
446
447 mrioc->admin_req_ci = le16_to_cpu(reply_desc->request_queue_ci);
448 mpi3mr_process_admin_reply_desc(mrioc, reply_desc, &reply_dma);
449 if (reply_dma)
450 mpi3mr_repost_reply_buf(mrioc, reply_dma);
451 num_admin_replies++;
452 if (++admin_reply_ci == mrioc->num_admin_replies) {
453 admin_reply_ci = 0;
454 exp_phase ^= 1;
455 }
456 reply_desc =
457 (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
458 admin_reply_ci;
459 if ((le16_to_cpu(reply_desc->reply_flags) &
460 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
461 break;
462 } while (1);
463
464 writel(admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
465 mrioc->admin_reply_ci = admin_reply_ci;
466 mrioc->admin_reply_ephase = exp_phase;
467 atomic_dec(&mrioc->admin_reply_q_in_use);
468
469 return num_admin_replies;
470 }
471
472 /**
473 * mpi3mr_get_reply_desc - get reply descriptor frame corresponding to
474 * queue's consumer index from operational reply descriptor queue.
475 * @op_reply_q: op_reply_qinfo object
476 * @reply_ci: operational reply descriptor's queue consumer index
477 *
478 * Returns reply descriptor frame address
479 */
480 static inline struct mpi3_default_reply_descriptor *
mpi3mr_get_reply_desc(struct op_reply_qinfo * op_reply_q,u32 reply_ci)481 mpi3mr_get_reply_desc(struct op_reply_qinfo *op_reply_q, u32 reply_ci)
482 {
483 void *segment_base_addr;
484 struct segments *segments = op_reply_q->q_segments;
485 struct mpi3_default_reply_descriptor *reply_desc = NULL;
486
487 segment_base_addr =
488 segments[reply_ci / op_reply_q->segment_qd].segment;
489 reply_desc = (struct mpi3_default_reply_descriptor *)segment_base_addr +
490 (reply_ci % op_reply_q->segment_qd);
491 return reply_desc;
492 }
493
494 /**
495 * mpi3mr_process_op_reply_q - Operational reply queue handler
496 * @mrioc: Adapter instance reference
497 * @op_reply_q: Operational reply queue info
498 *
499 * Checks the specific operational reply queue and drains the
500 * reply queue entries until the queue is empty and process the
501 * individual reply descriptors.
502 *
503 * Return: 0 if queue is already processed,or number of reply
504 * descriptors processed.
505 */
mpi3mr_process_op_reply_q(struct mpi3mr_ioc * mrioc,struct op_reply_qinfo * op_reply_q)506 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,
507 struct op_reply_qinfo *op_reply_q)
508 {
509 struct op_req_qinfo *op_req_q;
510 u32 exp_phase;
511 u32 reply_ci;
512 u32 num_op_reply = 0;
513 u64 reply_dma = 0;
514 struct mpi3_default_reply_descriptor *reply_desc;
515 u16 req_q_idx = 0, reply_qidx;
516
517 reply_qidx = op_reply_q->qid - 1;
518
519 if (!atomic_add_unless(&op_reply_q->in_use, 1, 1))
520 return 0;
521
522 exp_phase = op_reply_q->ephase;
523 reply_ci = op_reply_q->ci;
524
525 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
526 if ((le16_to_cpu(reply_desc->reply_flags) &
527 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) {
528 atomic_dec(&op_reply_q->in_use);
529 return 0;
530 }
531
532 do {
533 if (mrioc->unrecoverable)
534 break;
535
536 req_q_idx = le16_to_cpu(reply_desc->request_queue_id) - 1;
537 op_req_q = &mrioc->req_qinfo[req_q_idx];
538
539 WRITE_ONCE(op_req_q->ci, le16_to_cpu(reply_desc->request_queue_ci));
540 mpi3mr_process_op_reply_desc(mrioc, reply_desc, &reply_dma,
541 reply_qidx);
542 atomic_dec(&op_reply_q->pend_ios);
543 if (reply_dma)
544 mpi3mr_repost_reply_buf(mrioc, reply_dma);
545 num_op_reply++;
546
547 if (++reply_ci == op_reply_q->num_replies) {
548 reply_ci = 0;
549 exp_phase ^= 1;
550 }
551
552 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
553
554 if ((le16_to_cpu(reply_desc->reply_flags) &
555 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
556 break;
557 #ifndef CONFIG_PREEMPT_RT
558 /*
559 * Exit completion loop to avoid CPU lockup
560 * Ensure remaining completion happens from threaded ISR.
561 */
562 if (num_op_reply > mrioc->max_host_ios) {
563 op_reply_q->enable_irq_poll = true;
564 break;
565 }
566 #endif
567 } while (1);
568
569 writel(reply_ci,
570 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index);
571 op_reply_q->ci = reply_ci;
572 op_reply_q->ephase = exp_phase;
573
574 atomic_dec(&op_reply_q->in_use);
575 return num_op_reply;
576 }
577
578 /**
579 * mpi3mr_blk_mq_poll - Operational reply queue handler
580 * @shost: SCSI Host reference
581 * @queue_num: Request queue number (w.r.t OS it is hardware context number)
582 *
583 * Checks the specific operational reply queue and drains the
584 * reply queue entries until the queue is empty and process the
585 * individual reply descriptors.
586 *
587 * Return: 0 if queue is already processed,or number of reply
588 * descriptors processed.
589 */
mpi3mr_blk_mq_poll(struct Scsi_Host * shost,unsigned int queue_num)590 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num)
591 {
592 int num_entries = 0;
593 struct mpi3mr_ioc *mrioc;
594
595 mrioc = (struct mpi3mr_ioc *)shost->hostdata;
596
597 if ((mrioc->reset_in_progress || mrioc->prepare_for_reset ||
598 mrioc->unrecoverable))
599 return 0;
600
601 num_entries = mpi3mr_process_op_reply_q(mrioc,
602 &mrioc->op_reply_qinfo[queue_num]);
603
604 return num_entries;
605 }
606
mpi3mr_isr_primary(int irq,void * privdata)607 static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata)
608 {
609 struct mpi3mr_intr_info *intr_info = privdata;
610 struct mpi3mr_ioc *mrioc;
611 u16 midx;
612 u32 num_admin_replies = 0, num_op_reply = 0;
613
614 if (!intr_info)
615 return IRQ_NONE;
616
617 mrioc = intr_info->mrioc;
618
619 if (!mrioc->intr_enabled)
620 return IRQ_NONE;
621
622 midx = intr_info->msix_index;
623
624 if (!midx)
625 num_admin_replies = mpi3mr_process_admin_reply_q(mrioc);
626 if (intr_info->op_reply_q)
627 num_op_reply = mpi3mr_process_op_reply_q(mrioc,
628 intr_info->op_reply_q);
629
630 if (num_admin_replies || num_op_reply)
631 return IRQ_HANDLED;
632 else
633 return IRQ_NONE;
634 }
635
636 #ifndef CONFIG_PREEMPT_RT
637
mpi3mr_isr(int irq,void * privdata)638 static irqreturn_t mpi3mr_isr(int irq, void *privdata)
639 {
640 struct mpi3mr_intr_info *intr_info = privdata;
641 int ret;
642
643 if (!intr_info)
644 return IRQ_NONE;
645
646 /* Call primary ISR routine */
647 ret = mpi3mr_isr_primary(irq, privdata);
648
649 /*
650 * If more IOs are expected, schedule IRQ polling thread.
651 * Otherwise exit from ISR.
652 */
653 if (!intr_info->op_reply_q)
654 return ret;
655
656 if (!intr_info->op_reply_q->enable_irq_poll ||
657 !atomic_read(&intr_info->op_reply_q->pend_ios))
658 return ret;
659
660 disable_irq_nosync(intr_info->os_irq);
661
662 return IRQ_WAKE_THREAD;
663 }
664
665 /**
666 * mpi3mr_isr_poll - Reply queue polling routine
667 * @irq: IRQ
668 * @privdata: Interrupt info
669 *
670 * poll for pending I/O completions in a loop until pending I/Os
671 * present or controller queue depth I/Os are processed.
672 *
673 * Return: IRQ_NONE or IRQ_HANDLED
674 */
mpi3mr_isr_poll(int irq,void * privdata)675 static irqreturn_t mpi3mr_isr_poll(int irq, void *privdata)
676 {
677 struct mpi3mr_intr_info *intr_info = privdata;
678 struct mpi3mr_ioc *mrioc;
679 u16 midx;
680 u32 num_op_reply = 0;
681
682 if (!intr_info || !intr_info->op_reply_q)
683 return IRQ_NONE;
684
685 mrioc = intr_info->mrioc;
686 midx = intr_info->msix_index;
687
688 /* Poll for pending IOs completions */
689 do {
690 if (!mrioc->intr_enabled || mrioc->unrecoverable)
691 break;
692
693 if (!midx)
694 mpi3mr_process_admin_reply_q(mrioc);
695 if (intr_info->op_reply_q)
696 num_op_reply +=
697 mpi3mr_process_op_reply_q(mrioc,
698 intr_info->op_reply_q);
699
700 usleep_range(MPI3MR_IRQ_POLL_SLEEP, 10 * MPI3MR_IRQ_POLL_SLEEP);
701
702 } while (atomic_read(&intr_info->op_reply_q->pend_ios) &&
703 (num_op_reply < mrioc->max_host_ios));
704
705 intr_info->op_reply_q->enable_irq_poll = false;
706 enable_irq(intr_info->os_irq);
707
708 return IRQ_HANDLED;
709 }
710
711 #endif
712
713 /**
714 * mpi3mr_request_irq - Request IRQ and register ISR
715 * @mrioc: Adapter instance reference
716 * @index: IRQ vector index
717 *
718 * Request threaded ISR with primary ISR and secondary
719 *
720 * Return: 0 on success and non zero on failures.
721 */
mpi3mr_request_irq(struct mpi3mr_ioc * mrioc,u16 index)722 static inline int mpi3mr_request_irq(struct mpi3mr_ioc *mrioc, u16 index)
723 {
724 struct pci_dev *pdev = mrioc->pdev;
725 struct mpi3mr_intr_info *intr_info = mrioc->intr_info + index;
726 int retval = 0;
727
728 intr_info->mrioc = mrioc;
729 intr_info->msix_index = index;
730 intr_info->op_reply_q = NULL;
731
732 snprintf(intr_info->name, MPI3MR_NAME_LENGTH, "%s%d-msix%d",
733 mrioc->driver_name, mrioc->id, index);
734
735 #ifndef CONFIG_PREEMPT_RT
736 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr,
737 mpi3mr_isr_poll, IRQF_SHARED, intr_info->name, intr_info);
738 #else
739 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr_primary,
740 NULL, IRQF_SHARED, intr_info->name, intr_info);
741 #endif
742 if (retval) {
743 ioc_err(mrioc, "%s: Unable to allocate interrupt %d!\n",
744 intr_info->name, pci_irq_vector(pdev, index));
745 return retval;
746 }
747
748 intr_info->os_irq = pci_irq_vector(pdev, index);
749 return retval;
750 }
751
mpi3mr_calc_poll_queues(struct mpi3mr_ioc * mrioc,u16 max_vectors)752 static void mpi3mr_calc_poll_queues(struct mpi3mr_ioc *mrioc, u16 max_vectors)
753 {
754 if (!mrioc->requested_poll_qcount)
755 return;
756
757 /* Reserved for Admin and Default Queue */
758 if (max_vectors > 2 &&
759 (mrioc->requested_poll_qcount < max_vectors - 2)) {
760 ioc_info(mrioc,
761 "enabled polled queues (%d) msix (%d)\n",
762 mrioc->requested_poll_qcount, max_vectors);
763 } else {
764 ioc_info(mrioc,
765 "disabled polled queues (%d) msix (%d) because of no resources for default queue\n",
766 mrioc->requested_poll_qcount, max_vectors);
767 mrioc->requested_poll_qcount = 0;
768 }
769 }
770
771 /**
772 * mpi3mr_setup_isr - Setup ISR for the controller
773 * @mrioc: Adapter instance reference
774 * @setup_one: Request one IRQ or more
775 *
776 * Allocate IRQ vectors and call mpi3mr_request_irq to setup ISR
777 *
778 * Return: 0 on success and non zero on failures.
779 */
mpi3mr_setup_isr(struct mpi3mr_ioc * mrioc,u8 setup_one)780 static int mpi3mr_setup_isr(struct mpi3mr_ioc *mrioc, u8 setup_one)
781 {
782 unsigned int irq_flags = PCI_IRQ_MSIX;
783 int max_vectors, min_vec;
784 int retval;
785 int i;
786 struct irq_affinity desc = { .pre_vectors = 1, .post_vectors = 1 };
787
788 if (mrioc->is_intr_info_set)
789 return 0;
790
791 mpi3mr_cleanup_isr(mrioc);
792
793 if (setup_one || reset_devices) {
794 max_vectors = 1;
795 retval = pci_alloc_irq_vectors(mrioc->pdev,
796 1, max_vectors, irq_flags);
797 if (retval < 0) {
798 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
799 retval);
800 goto out_failed;
801 }
802 } else {
803 max_vectors =
804 min_t(int, mrioc->cpu_count + 1 +
805 mrioc->requested_poll_qcount, mrioc->msix_count);
806
807 mpi3mr_calc_poll_queues(mrioc, max_vectors);
808
809 ioc_info(mrioc,
810 "MSI-X vectors supported: %d, no of cores: %d,",
811 mrioc->msix_count, mrioc->cpu_count);
812 ioc_info(mrioc,
813 "MSI-x vectors requested: %d poll_queues %d\n",
814 max_vectors, mrioc->requested_poll_qcount);
815
816 desc.post_vectors = mrioc->requested_poll_qcount;
817 min_vec = desc.pre_vectors + desc.post_vectors;
818 irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES;
819
820 retval = pci_alloc_irq_vectors_affinity(mrioc->pdev,
821 min_vec, max_vectors, irq_flags, &desc);
822
823 if (retval < 0) {
824 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
825 retval);
826 goto out_failed;
827 }
828
829
830 /*
831 * If only one MSI-x is allocated, then MSI-x 0 will be shared
832 * between Admin queue and operational queue
833 */
834 if (retval == min_vec)
835 mrioc->op_reply_q_offset = 0;
836 else if (retval != (max_vectors)) {
837 ioc_info(mrioc,
838 "allocated vectors (%d) are less than configured (%d)\n",
839 retval, max_vectors);
840 }
841
842 max_vectors = retval;
843 mrioc->op_reply_q_offset = (max_vectors > 1) ? 1 : 0;
844
845 mpi3mr_calc_poll_queues(mrioc, max_vectors);
846
847 }
848
849 mrioc->intr_info = kzalloc(sizeof(struct mpi3mr_intr_info) * max_vectors,
850 GFP_KERNEL);
851 if (!mrioc->intr_info) {
852 retval = -ENOMEM;
853 pci_free_irq_vectors(mrioc->pdev);
854 goto out_failed;
855 }
856 for (i = 0; i < max_vectors; i++) {
857 retval = mpi3mr_request_irq(mrioc, i);
858 if (retval) {
859 mrioc->intr_info_count = i;
860 goto out_failed;
861 }
862 }
863 if (reset_devices || !setup_one)
864 mrioc->is_intr_info_set = true;
865 mrioc->intr_info_count = max_vectors;
866 mpi3mr_ioc_enable_intr(mrioc);
867 return 0;
868
869 out_failed:
870 mpi3mr_cleanup_isr(mrioc);
871
872 return retval;
873 }
874
875 static const struct {
876 enum mpi3mr_iocstate value;
877 char *name;
878 } mrioc_states[] = {
879 { MRIOC_STATE_READY, "ready" },
880 { MRIOC_STATE_FAULT, "fault" },
881 { MRIOC_STATE_RESET, "reset" },
882 { MRIOC_STATE_BECOMING_READY, "becoming ready" },
883 { MRIOC_STATE_RESET_REQUESTED, "reset requested" },
884 { MRIOC_STATE_UNRECOVERABLE, "unrecoverable error" },
885 };
886
mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state)887 static const char *mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state)
888 {
889 int i;
890 char *name = NULL;
891
892 for (i = 0; i < ARRAY_SIZE(mrioc_states); i++) {
893 if (mrioc_states[i].value == mrioc_state) {
894 name = mrioc_states[i].name;
895 break;
896 }
897 }
898 return name;
899 }
900
901 /* Reset reason to name mapper structure*/
902 static const struct {
903 enum mpi3mr_reset_reason value;
904 char *name;
905 } mpi3mr_reset_reason_codes[] = {
906 { MPI3MR_RESET_FROM_BRINGUP, "timeout in bringup" },
907 { MPI3MR_RESET_FROM_FAULT_WATCH, "fault" },
908 { MPI3MR_RESET_FROM_APP, "application invocation" },
909 { MPI3MR_RESET_FROM_EH_HOS, "error handling" },
910 { MPI3MR_RESET_FROM_TM_TIMEOUT, "TM timeout" },
911 { MPI3MR_RESET_FROM_APP_TIMEOUT, "application command timeout" },
912 { MPI3MR_RESET_FROM_MUR_FAILURE, "MUR failure" },
913 { MPI3MR_RESET_FROM_CTLR_CLEANUP, "timeout in controller cleanup" },
914 { MPI3MR_RESET_FROM_CIACTIV_FAULT, "component image activation fault" },
915 { MPI3MR_RESET_FROM_PE_TIMEOUT, "port enable timeout" },
916 { MPI3MR_RESET_FROM_TSU_TIMEOUT, "time stamp update timeout" },
917 { MPI3MR_RESET_FROM_DELREQQ_TIMEOUT, "delete request queue timeout" },
918 { MPI3MR_RESET_FROM_DELREPQ_TIMEOUT, "delete reply queue timeout" },
919 {
920 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT,
921 "create request queue timeout"
922 },
923 {
924 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT,
925 "create reply queue timeout"
926 },
927 { MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT, "IOC facts timeout" },
928 { MPI3MR_RESET_FROM_IOCINIT_TIMEOUT, "IOC init timeout" },
929 { MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT, "event notify timeout" },
930 { MPI3MR_RESET_FROM_EVTACK_TIMEOUT, "event acknowledgment timeout" },
931 {
932 MPI3MR_RESET_FROM_CIACTVRST_TIMER,
933 "component image activation timeout"
934 },
935 {
936 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT,
937 "get package version timeout"
938 },
939 { MPI3MR_RESET_FROM_SYSFS, "sysfs invocation" },
940 { MPI3MR_RESET_FROM_SYSFS_TIMEOUT, "sysfs TM timeout" },
941 { MPI3MR_RESET_FROM_FIRMWARE, "firmware asynchronous reset" },
942 { MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT, "configuration request timeout"},
943 { MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT, "timeout of a SAS transport layer request" },
944 };
945
946 /**
947 * mpi3mr_reset_rc_name - get reset reason code name
948 * @reason_code: reset reason code value
949 *
950 * Map reset reason to an NULL terminated ASCII string
951 *
952 * Return: name corresponding to reset reason value or NULL.
953 */
mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code)954 static const char *mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code)
955 {
956 int i;
957 char *name = NULL;
958
959 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_reason_codes); i++) {
960 if (mpi3mr_reset_reason_codes[i].value == reason_code) {
961 name = mpi3mr_reset_reason_codes[i].name;
962 break;
963 }
964 }
965 return name;
966 }
967
968 /* Reset type to name mapper structure*/
969 static const struct {
970 u16 reset_type;
971 char *name;
972 } mpi3mr_reset_types[] = {
973 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, "soft" },
974 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, "diag fault" },
975 };
976
977 /**
978 * mpi3mr_reset_type_name - get reset type name
979 * @reset_type: reset type value
980 *
981 * Map reset type to an NULL terminated ASCII string
982 *
983 * Return: name corresponding to reset type value or NULL.
984 */
mpi3mr_reset_type_name(u16 reset_type)985 static const char *mpi3mr_reset_type_name(u16 reset_type)
986 {
987 int i;
988 char *name = NULL;
989
990 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_types); i++) {
991 if (mpi3mr_reset_types[i].reset_type == reset_type) {
992 name = mpi3mr_reset_types[i].name;
993 break;
994 }
995 }
996 return name;
997 }
998
999 /**
1000 * mpi3mr_print_fault_info - Display fault information
1001 * @mrioc: Adapter instance reference
1002 *
1003 * Display the controller fault information if there is a
1004 * controller fault.
1005 *
1006 * Return: Nothing.
1007 */
mpi3mr_print_fault_info(struct mpi3mr_ioc * mrioc)1008 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc)
1009 {
1010 u32 ioc_status, code, code1, code2, code3;
1011
1012 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1013
1014 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1015 code = readl(&mrioc->sysif_regs->fault);
1016 code1 = readl(&mrioc->sysif_regs->fault_info[0]);
1017 code2 = readl(&mrioc->sysif_regs->fault_info[1]);
1018 code3 = readl(&mrioc->sysif_regs->fault_info[2]);
1019
1020 ioc_info(mrioc,
1021 "fault code(0x%08X): Additional code: (0x%08X:0x%08X:0x%08X)\n",
1022 code, code1, code2, code3);
1023 }
1024 }
1025
1026 /**
1027 * mpi3mr_get_iocstate - Get IOC State
1028 * @mrioc: Adapter instance reference
1029 *
1030 * Return a proper IOC state enum based on the IOC status and
1031 * IOC configuration and unrcoverable state of the controller.
1032 *
1033 * Return: Current IOC state.
1034 */
mpi3mr_get_iocstate(struct mpi3mr_ioc * mrioc)1035 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc)
1036 {
1037 u32 ioc_status, ioc_config;
1038 u8 ready, enabled;
1039
1040 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1041 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1042
1043 if (mrioc->unrecoverable)
1044 return MRIOC_STATE_UNRECOVERABLE;
1045 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)
1046 return MRIOC_STATE_FAULT;
1047
1048 ready = (ioc_status & MPI3_SYSIF_IOC_STATUS_READY);
1049 enabled = (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC);
1050
1051 if (ready && enabled)
1052 return MRIOC_STATE_READY;
1053 if ((!ready) && (!enabled))
1054 return MRIOC_STATE_RESET;
1055 if ((!ready) && (enabled))
1056 return MRIOC_STATE_BECOMING_READY;
1057
1058 return MRIOC_STATE_RESET_REQUESTED;
1059 }
1060
1061 /**
1062 * mpi3mr_clear_reset_history - clear reset history
1063 * @mrioc: Adapter instance reference
1064 *
1065 * Write the reset history bit in IOC status to clear the bit,
1066 * if it is already set.
1067 *
1068 * Return: Nothing.
1069 */
mpi3mr_clear_reset_history(struct mpi3mr_ioc * mrioc)1070 static inline void mpi3mr_clear_reset_history(struct mpi3mr_ioc *mrioc)
1071 {
1072 u32 ioc_status;
1073
1074 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1075 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1076 writel(ioc_status, &mrioc->sysif_regs->ioc_status);
1077 }
1078
1079 /**
1080 * mpi3mr_issue_and_process_mur - Message unit Reset handler
1081 * @mrioc: Adapter instance reference
1082 * @reset_reason: Reset reason code
1083 *
1084 * Issue Message unit Reset to the controller and wait for it to
1085 * be complete.
1086 *
1087 * Return: 0 on success, -1 on failure.
1088 */
mpi3mr_issue_and_process_mur(struct mpi3mr_ioc * mrioc,u32 reset_reason)1089 static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc,
1090 u32 reset_reason)
1091 {
1092 u32 ioc_config, timeout, ioc_status;
1093 int retval = -1;
1094
1095 ioc_info(mrioc, "Issuing Message unit Reset(MUR)\n");
1096 if (mrioc->unrecoverable) {
1097 ioc_info(mrioc, "IOC is unrecoverable MUR not issued\n");
1098 return retval;
1099 }
1100 mpi3mr_clear_reset_history(mrioc);
1101 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);
1102 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1103 ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1104 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1105
1106 timeout = MPI3MR_MUR_TIMEOUT * 10;
1107 do {
1108 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1109 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) {
1110 mpi3mr_clear_reset_history(mrioc);
1111 break;
1112 }
1113 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1114 mpi3mr_print_fault_info(mrioc);
1115 break;
1116 }
1117 msleep(100);
1118 } while (--timeout);
1119
1120 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1121 if (timeout && !((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1122 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) ||
1123 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1124 retval = 0;
1125
1126 ioc_info(mrioc, "Base IOC Sts/Config after %s MUR is (0x%x)/(0x%x)\n",
1127 (!retval) ? "successful" : "failed", ioc_status, ioc_config);
1128 return retval;
1129 }
1130
1131 /**
1132 * mpi3mr_revalidate_factsdata - validate IOCFacts parameters
1133 * during reset/resume
1134 * @mrioc: Adapter instance reference
1135 *
1136 * Return zero if the new IOCFacts parameters value is compatible with
1137 * older values else return -EPERM
1138 */
1139 static int
mpi3mr_revalidate_factsdata(struct mpi3mr_ioc * mrioc)1140 mpi3mr_revalidate_factsdata(struct mpi3mr_ioc *mrioc)
1141 {
1142 unsigned long *removepend_bitmap;
1143
1144 if (mrioc->facts.reply_sz > mrioc->reply_sz) {
1145 ioc_err(mrioc,
1146 "cannot increase reply size from %d to %d\n",
1147 mrioc->reply_sz, mrioc->facts.reply_sz);
1148 return -EPERM;
1149 }
1150
1151 if (mrioc->facts.max_op_reply_q < mrioc->num_op_reply_q) {
1152 ioc_err(mrioc,
1153 "cannot reduce number of operational reply queues from %d to %d\n",
1154 mrioc->num_op_reply_q,
1155 mrioc->facts.max_op_reply_q);
1156 return -EPERM;
1157 }
1158
1159 if (mrioc->facts.max_op_req_q < mrioc->num_op_req_q) {
1160 ioc_err(mrioc,
1161 "cannot reduce number of operational request queues from %d to %d\n",
1162 mrioc->num_op_req_q, mrioc->facts.max_op_req_q);
1163 return -EPERM;
1164 }
1165
1166 if (mrioc->shost->max_sectors != (mrioc->facts.max_data_length / 512))
1167 ioc_err(mrioc, "Warning: The maximum data transfer length\n"
1168 "\tchanged after reset: previous(%d), new(%d),\n"
1169 "the driver cannot change this at run time\n",
1170 mrioc->shost->max_sectors * 512, mrioc->facts.max_data_length);
1171
1172 if ((mrioc->sas_transport_enabled) && (mrioc->facts.ioc_capabilities &
1173 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED))
1174 ioc_err(mrioc,
1175 "critical error: multipath capability is enabled at the\n"
1176 "\tcontroller while sas transport support is enabled at the\n"
1177 "\tdriver, please reboot the system or reload the driver\n");
1178
1179 if (mrioc->facts.max_devhandle > mrioc->dev_handle_bitmap_bits) {
1180 removepend_bitmap = bitmap_zalloc(mrioc->facts.max_devhandle,
1181 GFP_KERNEL);
1182 if (!removepend_bitmap) {
1183 ioc_err(mrioc,
1184 "failed to increase removepend_bitmap bits from %d to %d\n",
1185 mrioc->dev_handle_bitmap_bits,
1186 mrioc->facts.max_devhandle);
1187 return -EPERM;
1188 }
1189 bitmap_free(mrioc->removepend_bitmap);
1190 mrioc->removepend_bitmap = removepend_bitmap;
1191 ioc_info(mrioc,
1192 "increased bits of dev_handle_bitmap from %d to %d\n",
1193 mrioc->dev_handle_bitmap_bits,
1194 mrioc->facts.max_devhandle);
1195 mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle;
1196 }
1197
1198 return 0;
1199 }
1200
1201 /**
1202 * mpi3mr_bring_ioc_ready - Bring controller to ready state
1203 * @mrioc: Adapter instance reference
1204 *
1205 * Set Enable IOC bit in IOC configuration register and wait for
1206 * the controller to become ready.
1207 *
1208 * Return: 0 on success, appropriate error on failure.
1209 */
mpi3mr_bring_ioc_ready(struct mpi3mr_ioc * mrioc)1210 static int mpi3mr_bring_ioc_ready(struct mpi3mr_ioc *mrioc)
1211 {
1212 u32 ioc_config, ioc_status, timeout, host_diagnostic;
1213 int retval = 0;
1214 enum mpi3mr_iocstate ioc_state;
1215 u64 base_info;
1216
1217 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1218 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1219 base_info = lo_hi_readq(&mrioc->sysif_regs->ioc_information);
1220 ioc_info(mrioc, "ioc_status(0x%08x), ioc_config(0x%08x), ioc_info(0x%016llx) at the bringup\n",
1221 ioc_status, ioc_config, base_info);
1222
1223 /*The timeout value is in 2sec unit, changing it to seconds*/
1224 mrioc->ready_timeout =
1225 ((base_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >>
1226 MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2;
1227
1228 ioc_info(mrioc, "ready timeout: %d seconds\n", mrioc->ready_timeout);
1229
1230 ioc_state = mpi3mr_get_iocstate(mrioc);
1231 ioc_info(mrioc, "controller is in %s state during detection\n",
1232 mpi3mr_iocstate_name(ioc_state));
1233
1234 if (ioc_state == MRIOC_STATE_BECOMING_READY ||
1235 ioc_state == MRIOC_STATE_RESET_REQUESTED) {
1236 timeout = mrioc->ready_timeout * 10;
1237 do {
1238 msleep(100);
1239 } while (--timeout);
1240
1241 if (!pci_device_is_present(mrioc->pdev)) {
1242 mrioc->unrecoverable = 1;
1243 ioc_err(mrioc,
1244 "controller is not present while waiting to reset\n");
1245 retval = -1;
1246 goto out_device_not_present;
1247 }
1248
1249 ioc_state = mpi3mr_get_iocstate(mrioc);
1250 ioc_info(mrioc,
1251 "controller is in %s state after waiting to reset\n",
1252 mpi3mr_iocstate_name(ioc_state));
1253 }
1254
1255 if (ioc_state == MRIOC_STATE_READY) {
1256 ioc_info(mrioc, "issuing message unit reset (MUR) to bring to reset state\n");
1257 retval = mpi3mr_issue_and_process_mur(mrioc,
1258 MPI3MR_RESET_FROM_BRINGUP);
1259 ioc_state = mpi3mr_get_iocstate(mrioc);
1260 if (retval)
1261 ioc_err(mrioc,
1262 "message unit reset failed with error %d current state %s\n",
1263 retval, mpi3mr_iocstate_name(ioc_state));
1264 }
1265 if (ioc_state != MRIOC_STATE_RESET) {
1266 if (ioc_state == MRIOC_STATE_FAULT) {
1267 timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
1268 mpi3mr_print_fault_info(mrioc);
1269 do {
1270 host_diagnostic =
1271 readl(&mrioc->sysif_regs->host_diagnostic);
1272 if (!(host_diagnostic &
1273 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
1274 break;
1275 if (!pci_device_is_present(mrioc->pdev)) {
1276 mrioc->unrecoverable = 1;
1277 ioc_err(mrioc, "controller is not present at the bringup\n");
1278 goto out_device_not_present;
1279 }
1280 msleep(100);
1281 } while (--timeout);
1282 }
1283 mpi3mr_print_fault_info(mrioc);
1284 ioc_info(mrioc, "issuing soft reset to bring to reset state\n");
1285 retval = mpi3mr_issue_reset(mrioc,
1286 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
1287 MPI3MR_RESET_FROM_BRINGUP);
1288 if (retval) {
1289 ioc_err(mrioc,
1290 "soft reset failed with error %d\n", retval);
1291 goto out_failed;
1292 }
1293 }
1294 ioc_state = mpi3mr_get_iocstate(mrioc);
1295 if (ioc_state != MRIOC_STATE_RESET) {
1296 ioc_err(mrioc,
1297 "cannot bring controller to reset state, current state: %s\n",
1298 mpi3mr_iocstate_name(ioc_state));
1299 goto out_failed;
1300 }
1301 mpi3mr_clear_reset_history(mrioc);
1302 retval = mpi3mr_setup_admin_qpair(mrioc);
1303 if (retval) {
1304 ioc_err(mrioc, "failed to setup admin queues: error %d\n",
1305 retval);
1306 goto out_failed;
1307 }
1308
1309 ioc_info(mrioc, "bringing controller to ready state\n");
1310 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1311 ioc_config |= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1312 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1313
1314 timeout = mrioc->ready_timeout * 10;
1315 do {
1316 ioc_state = mpi3mr_get_iocstate(mrioc);
1317 if (ioc_state == MRIOC_STATE_READY) {
1318 ioc_info(mrioc,
1319 "successfully transitioned to %s state\n",
1320 mpi3mr_iocstate_name(ioc_state));
1321 return 0;
1322 }
1323 if (!pci_device_is_present(mrioc->pdev)) {
1324 mrioc->unrecoverable = 1;
1325 ioc_err(mrioc,
1326 "controller is not present at the bringup\n");
1327 retval = -1;
1328 goto out_device_not_present;
1329 }
1330 msleep(100);
1331 } while (--timeout);
1332
1333 out_failed:
1334 ioc_state = mpi3mr_get_iocstate(mrioc);
1335 ioc_err(mrioc,
1336 "failed to bring to ready state, current state: %s\n",
1337 mpi3mr_iocstate_name(ioc_state));
1338 out_device_not_present:
1339 return retval;
1340 }
1341
1342 /**
1343 * mpi3mr_soft_reset_success - Check softreset is success or not
1344 * @ioc_status: IOC status register value
1345 * @ioc_config: IOC config register value
1346 *
1347 * Check whether the soft reset is successful or not based on
1348 * IOC status and IOC config register values.
1349 *
1350 * Return: True when the soft reset is success, false otherwise.
1351 */
1352 static inline bool
mpi3mr_soft_reset_success(u32 ioc_status,u32 ioc_config)1353 mpi3mr_soft_reset_success(u32 ioc_status, u32 ioc_config)
1354 {
1355 if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1356 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1357 return true;
1358 return false;
1359 }
1360
1361 /**
1362 * mpi3mr_diagfault_success - Check diag fault is success or not
1363 * @mrioc: Adapter reference
1364 * @ioc_status: IOC status register value
1365 *
1366 * Check whether the controller hit diag reset fault code.
1367 *
1368 * Return: True when there is diag fault, false otherwise.
1369 */
mpi3mr_diagfault_success(struct mpi3mr_ioc * mrioc,u32 ioc_status)1370 static inline bool mpi3mr_diagfault_success(struct mpi3mr_ioc *mrioc,
1371 u32 ioc_status)
1372 {
1373 u32 fault;
1374
1375 if (!(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT))
1376 return false;
1377 fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
1378 if (fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) {
1379 mpi3mr_print_fault_info(mrioc);
1380 return true;
1381 }
1382 return false;
1383 }
1384
1385 /**
1386 * mpi3mr_set_diagsave - Set diag save bit for snapdump
1387 * @mrioc: Adapter reference
1388 *
1389 * Set diag save bit in IOC configuration register to enable
1390 * snapdump.
1391 *
1392 * Return: Nothing.
1393 */
mpi3mr_set_diagsave(struct mpi3mr_ioc * mrioc)1394 static inline void mpi3mr_set_diagsave(struct mpi3mr_ioc *mrioc)
1395 {
1396 u32 ioc_config;
1397
1398 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1399 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE;
1400 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1401 }
1402
1403 /**
1404 * mpi3mr_issue_reset - Issue reset to the controller
1405 * @mrioc: Adapter reference
1406 * @reset_type: Reset type
1407 * @reset_reason: Reset reason code
1408 *
1409 * Unlock the host diagnostic registers and write the specific
1410 * reset type to that, wait for reset acknowledgment from the
1411 * controller, if the reset is not successful retry for the
1412 * predefined number of times.
1413 *
1414 * Return: 0 on success, non-zero on failure.
1415 */
mpi3mr_issue_reset(struct mpi3mr_ioc * mrioc,u16 reset_type,u32 reset_reason)1416 static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type,
1417 u32 reset_reason)
1418 {
1419 int retval = -1;
1420 u8 unlock_retry_count = 0;
1421 u32 host_diagnostic, ioc_status, ioc_config;
1422 u32 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10;
1423
1424 if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) &&
1425 (reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT))
1426 return retval;
1427 if (mrioc->unrecoverable)
1428 return retval;
1429 if (reset_reason == MPI3MR_RESET_FROM_FIRMWARE) {
1430 retval = 0;
1431 return retval;
1432 }
1433
1434 ioc_info(mrioc, "%s reset due to %s(0x%x)\n",
1435 mpi3mr_reset_type_name(reset_type),
1436 mpi3mr_reset_rc_name(reset_reason), reset_reason);
1437
1438 mpi3mr_clear_reset_history(mrioc);
1439 do {
1440 ioc_info(mrioc,
1441 "Write magic sequence to unlock host diag register (retry=%d)\n",
1442 ++unlock_retry_count);
1443 if (unlock_retry_count >= MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT) {
1444 ioc_err(mrioc,
1445 "%s reset failed due to unlock failure, host_diagnostic(0x%08x)\n",
1446 mpi3mr_reset_type_name(reset_type),
1447 host_diagnostic);
1448 mrioc->unrecoverable = 1;
1449 return retval;
1450 }
1451
1452 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH,
1453 &mrioc->sysif_regs->write_sequence);
1454 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST,
1455 &mrioc->sysif_regs->write_sequence);
1456 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1457 &mrioc->sysif_regs->write_sequence);
1458 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD,
1459 &mrioc->sysif_regs->write_sequence);
1460 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH,
1461 &mrioc->sysif_regs->write_sequence);
1462 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH,
1463 &mrioc->sysif_regs->write_sequence);
1464 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH,
1465 &mrioc->sysif_regs->write_sequence);
1466 usleep_range(1000, 1100);
1467 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
1468 ioc_info(mrioc,
1469 "wrote magic sequence: retry_count(%d), host_diagnostic(0x%08x)\n",
1470 unlock_retry_count, host_diagnostic);
1471 } while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE));
1472
1473 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);
1474 writel(host_diagnostic | reset_type,
1475 &mrioc->sysif_regs->host_diagnostic);
1476 switch (reset_type) {
1477 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET:
1478 do {
1479 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1480 ioc_config =
1481 readl(&mrioc->sysif_regs->ioc_configuration);
1482 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1483 && mpi3mr_soft_reset_success(ioc_status, ioc_config)
1484 ) {
1485 mpi3mr_clear_reset_history(mrioc);
1486 retval = 0;
1487 break;
1488 }
1489 msleep(100);
1490 } while (--timeout);
1491 mpi3mr_print_fault_info(mrioc);
1492 break;
1493 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT:
1494 do {
1495 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1496 if (mpi3mr_diagfault_success(mrioc, ioc_status)) {
1497 retval = 0;
1498 break;
1499 }
1500 msleep(100);
1501 } while (--timeout);
1502 break;
1503 default:
1504 break;
1505 }
1506
1507 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1508 &mrioc->sysif_regs->write_sequence);
1509
1510 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1511 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1512 ioc_info(mrioc,
1513 "ioc_status/ioc_onfig after %s reset is (0x%x)/(0x%x)\n",
1514 (!retval)?"successful":"failed", ioc_status,
1515 ioc_config);
1516 if (retval)
1517 mrioc->unrecoverable = 1;
1518 return retval;
1519 }
1520
1521 /**
1522 * mpi3mr_admin_request_post - Post request to admin queue
1523 * @mrioc: Adapter reference
1524 * @admin_req: MPI3 request
1525 * @admin_req_sz: Request size
1526 * @ignore_reset: Ignore reset in process
1527 *
1528 * Post the MPI3 request into admin request queue and
1529 * inform the controller, if the queue is full return
1530 * appropriate error.
1531 *
1532 * Return: 0 on success, non-zero on failure.
1533 */
mpi3mr_admin_request_post(struct mpi3mr_ioc * mrioc,void * admin_req,u16 admin_req_sz,u8 ignore_reset)1534 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
1535 u16 admin_req_sz, u8 ignore_reset)
1536 {
1537 u16 areq_pi = 0, areq_ci = 0, max_entries = 0;
1538 int retval = 0;
1539 unsigned long flags;
1540 u8 *areq_entry;
1541
1542 if (mrioc->unrecoverable) {
1543 ioc_err(mrioc, "%s : Unrecoverable controller\n", __func__);
1544 return -EFAULT;
1545 }
1546
1547 spin_lock_irqsave(&mrioc->admin_req_lock, flags);
1548 areq_pi = mrioc->admin_req_pi;
1549 areq_ci = mrioc->admin_req_ci;
1550 max_entries = mrioc->num_admin_req;
1551 if ((areq_ci == (areq_pi + 1)) || ((!areq_ci) &&
1552 (areq_pi == (max_entries - 1)))) {
1553 ioc_err(mrioc, "AdminReqQ full condition detected\n");
1554 retval = -EAGAIN;
1555 goto out;
1556 }
1557 if (!ignore_reset && mrioc->reset_in_progress) {
1558 ioc_err(mrioc, "AdminReqQ submit reset in progress\n");
1559 retval = -EAGAIN;
1560 goto out;
1561 }
1562 areq_entry = (u8 *)mrioc->admin_req_base +
1563 (areq_pi * MPI3MR_ADMIN_REQ_FRAME_SZ);
1564 memset(areq_entry, 0, MPI3MR_ADMIN_REQ_FRAME_SZ);
1565 memcpy(areq_entry, (u8 *)admin_req, admin_req_sz);
1566
1567 if (++areq_pi == max_entries)
1568 areq_pi = 0;
1569 mrioc->admin_req_pi = areq_pi;
1570
1571 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
1572
1573 out:
1574 spin_unlock_irqrestore(&mrioc->admin_req_lock, flags);
1575
1576 return retval;
1577 }
1578
1579 /**
1580 * mpi3mr_free_op_req_q_segments - free request memory segments
1581 * @mrioc: Adapter instance reference
1582 * @q_idx: operational request queue index
1583 *
1584 * Free memory segments allocated for operational request queue
1585 *
1586 * Return: Nothing.
1587 */
mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc * mrioc,u16 q_idx)1588 static void mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1589 {
1590 u16 j;
1591 int size;
1592 struct segments *segments;
1593
1594 segments = mrioc->req_qinfo[q_idx].q_segments;
1595 if (!segments)
1596 return;
1597
1598 if (mrioc->enable_segqueue) {
1599 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
1600 if (mrioc->req_qinfo[q_idx].q_segment_list) {
1601 dma_free_coherent(&mrioc->pdev->dev,
1602 MPI3MR_MAX_SEG_LIST_SIZE,
1603 mrioc->req_qinfo[q_idx].q_segment_list,
1604 mrioc->req_qinfo[q_idx].q_segment_list_dma);
1605 mrioc->req_qinfo[q_idx].q_segment_list = NULL;
1606 }
1607 } else
1608 size = mrioc->req_qinfo[q_idx].segment_qd *
1609 mrioc->facts.op_req_sz;
1610
1611 for (j = 0; j < mrioc->req_qinfo[q_idx].num_segments; j++) {
1612 if (!segments[j].segment)
1613 continue;
1614 dma_free_coherent(&mrioc->pdev->dev,
1615 size, segments[j].segment, segments[j].segment_dma);
1616 segments[j].segment = NULL;
1617 }
1618 kfree(mrioc->req_qinfo[q_idx].q_segments);
1619 mrioc->req_qinfo[q_idx].q_segments = NULL;
1620 mrioc->req_qinfo[q_idx].qid = 0;
1621 }
1622
1623 /**
1624 * mpi3mr_free_op_reply_q_segments - free reply memory segments
1625 * @mrioc: Adapter instance reference
1626 * @q_idx: operational reply queue index
1627 *
1628 * Free memory segments allocated for operational reply queue
1629 *
1630 * Return: Nothing.
1631 */
mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc * mrioc,u16 q_idx)1632 static void mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1633 {
1634 u16 j;
1635 int size;
1636 struct segments *segments;
1637
1638 segments = mrioc->op_reply_qinfo[q_idx].q_segments;
1639 if (!segments)
1640 return;
1641
1642 if (mrioc->enable_segqueue) {
1643 size = MPI3MR_OP_REP_Q_SEG_SIZE;
1644 if (mrioc->op_reply_qinfo[q_idx].q_segment_list) {
1645 dma_free_coherent(&mrioc->pdev->dev,
1646 MPI3MR_MAX_SEG_LIST_SIZE,
1647 mrioc->op_reply_qinfo[q_idx].q_segment_list,
1648 mrioc->op_reply_qinfo[q_idx].q_segment_list_dma);
1649 mrioc->op_reply_qinfo[q_idx].q_segment_list = NULL;
1650 }
1651 } else
1652 size = mrioc->op_reply_qinfo[q_idx].segment_qd *
1653 mrioc->op_reply_desc_sz;
1654
1655 for (j = 0; j < mrioc->op_reply_qinfo[q_idx].num_segments; j++) {
1656 if (!segments[j].segment)
1657 continue;
1658 dma_free_coherent(&mrioc->pdev->dev,
1659 size, segments[j].segment, segments[j].segment_dma);
1660 segments[j].segment = NULL;
1661 }
1662
1663 kfree(mrioc->op_reply_qinfo[q_idx].q_segments);
1664 mrioc->op_reply_qinfo[q_idx].q_segments = NULL;
1665 mrioc->op_reply_qinfo[q_idx].qid = 0;
1666 }
1667
1668 /**
1669 * mpi3mr_delete_op_reply_q - delete operational reply queue
1670 * @mrioc: Adapter instance reference
1671 * @qidx: operational reply queue index
1672 *
1673 * Delete operatinal reply queue by issuing MPI request
1674 * through admin queue.
1675 *
1676 * Return: 0 on success, non-zero on failure.
1677 */
mpi3mr_delete_op_reply_q(struct mpi3mr_ioc * mrioc,u16 qidx)1678 static int mpi3mr_delete_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
1679 {
1680 struct mpi3_delete_reply_queue_request delq_req;
1681 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1682 int retval = 0;
1683 u16 reply_qid = 0, midx;
1684
1685 reply_qid = op_reply_q->qid;
1686
1687 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
1688
1689 if (!reply_qid) {
1690 retval = -1;
1691 ioc_err(mrioc, "Issue DelRepQ: called with invalid ReqQID\n");
1692 goto out;
1693 }
1694
1695 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount-- :
1696 mrioc->active_poll_qcount--;
1697
1698 memset(&delq_req, 0, sizeof(delq_req));
1699 mutex_lock(&mrioc->init_cmds.mutex);
1700 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
1701 retval = -1;
1702 ioc_err(mrioc, "Issue DelRepQ: Init command is in use\n");
1703 mutex_unlock(&mrioc->init_cmds.mutex);
1704 goto out;
1705 }
1706 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
1707 mrioc->init_cmds.is_waiting = 1;
1708 mrioc->init_cmds.callback = NULL;
1709 delq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
1710 delq_req.function = MPI3_FUNCTION_DELETE_REPLY_QUEUE;
1711 delq_req.queue_id = cpu_to_le16(reply_qid);
1712
1713 init_completion(&mrioc->init_cmds.done);
1714 retval = mpi3mr_admin_request_post(mrioc, &delq_req, sizeof(delq_req),
1715 1);
1716 if (retval) {
1717 ioc_err(mrioc, "Issue DelRepQ: Admin Post failed\n");
1718 goto out_unlock;
1719 }
1720 wait_for_completion_timeout(&mrioc->init_cmds.done,
1721 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
1722 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1723 ioc_err(mrioc, "delete reply queue timed out\n");
1724 mpi3mr_check_rh_fault_ioc(mrioc,
1725 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT);
1726 retval = -1;
1727 goto out_unlock;
1728 }
1729 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
1730 != MPI3_IOCSTATUS_SUCCESS) {
1731 ioc_err(mrioc,
1732 "Issue DelRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
1733 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
1734 mrioc->init_cmds.ioc_loginfo);
1735 retval = -1;
1736 goto out_unlock;
1737 }
1738 mrioc->intr_info[midx].op_reply_q = NULL;
1739
1740 mpi3mr_free_op_reply_q_segments(mrioc, qidx);
1741 out_unlock:
1742 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
1743 mutex_unlock(&mrioc->init_cmds.mutex);
1744 out:
1745
1746 return retval;
1747 }
1748
1749 /**
1750 * mpi3mr_alloc_op_reply_q_segments -Alloc segmented reply pool
1751 * @mrioc: Adapter instance reference
1752 * @qidx: request queue index
1753 *
1754 * Allocate segmented memory pools for operational reply
1755 * queue.
1756 *
1757 * Return: 0 on success, non-zero on failure.
1758 */
mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc * mrioc,u16 qidx)1759 static int mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
1760 {
1761 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1762 int i, size;
1763 u64 *q_segment_list_entry = NULL;
1764 struct segments *segments;
1765
1766 if (mrioc->enable_segqueue) {
1767 op_reply_q->segment_qd =
1768 MPI3MR_OP_REP_Q_SEG_SIZE / mrioc->op_reply_desc_sz;
1769
1770 size = MPI3MR_OP_REP_Q_SEG_SIZE;
1771
1772 op_reply_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
1773 MPI3MR_MAX_SEG_LIST_SIZE, &op_reply_q->q_segment_list_dma,
1774 GFP_KERNEL);
1775 if (!op_reply_q->q_segment_list)
1776 return -ENOMEM;
1777 q_segment_list_entry = (u64 *)op_reply_q->q_segment_list;
1778 } else {
1779 op_reply_q->segment_qd = op_reply_q->num_replies;
1780 size = op_reply_q->num_replies * mrioc->op_reply_desc_sz;
1781 }
1782
1783 op_reply_q->num_segments = DIV_ROUND_UP(op_reply_q->num_replies,
1784 op_reply_q->segment_qd);
1785
1786 op_reply_q->q_segments = kcalloc(op_reply_q->num_segments,
1787 sizeof(struct segments), GFP_KERNEL);
1788 if (!op_reply_q->q_segments)
1789 return -ENOMEM;
1790
1791 segments = op_reply_q->q_segments;
1792 for (i = 0; i < op_reply_q->num_segments; i++) {
1793 segments[i].segment =
1794 dma_alloc_coherent(&mrioc->pdev->dev,
1795 size, &segments[i].segment_dma, GFP_KERNEL);
1796 if (!segments[i].segment)
1797 return -ENOMEM;
1798 if (mrioc->enable_segqueue)
1799 q_segment_list_entry[i] =
1800 (unsigned long)segments[i].segment_dma;
1801 }
1802
1803 return 0;
1804 }
1805
1806 /**
1807 * mpi3mr_alloc_op_req_q_segments - Alloc segmented req pool.
1808 * @mrioc: Adapter instance reference
1809 * @qidx: request queue index
1810 *
1811 * Allocate segmented memory pools for operational request
1812 * queue.
1813 *
1814 * Return: 0 on success, non-zero on failure.
1815 */
mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc * mrioc,u16 qidx)1816 static int mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
1817 {
1818 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
1819 int i, size;
1820 u64 *q_segment_list_entry = NULL;
1821 struct segments *segments;
1822
1823 if (mrioc->enable_segqueue) {
1824 op_req_q->segment_qd =
1825 MPI3MR_OP_REQ_Q_SEG_SIZE / mrioc->facts.op_req_sz;
1826
1827 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
1828
1829 op_req_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
1830 MPI3MR_MAX_SEG_LIST_SIZE, &op_req_q->q_segment_list_dma,
1831 GFP_KERNEL);
1832 if (!op_req_q->q_segment_list)
1833 return -ENOMEM;
1834 q_segment_list_entry = (u64 *)op_req_q->q_segment_list;
1835
1836 } else {
1837 op_req_q->segment_qd = op_req_q->num_requests;
1838 size = op_req_q->num_requests * mrioc->facts.op_req_sz;
1839 }
1840
1841 op_req_q->num_segments = DIV_ROUND_UP(op_req_q->num_requests,
1842 op_req_q->segment_qd);
1843
1844 op_req_q->q_segments = kcalloc(op_req_q->num_segments,
1845 sizeof(struct segments), GFP_KERNEL);
1846 if (!op_req_q->q_segments)
1847 return -ENOMEM;
1848
1849 segments = op_req_q->q_segments;
1850 for (i = 0; i < op_req_q->num_segments; i++) {
1851 segments[i].segment =
1852 dma_alloc_coherent(&mrioc->pdev->dev,
1853 size, &segments[i].segment_dma, GFP_KERNEL);
1854 if (!segments[i].segment)
1855 return -ENOMEM;
1856 if (mrioc->enable_segqueue)
1857 q_segment_list_entry[i] =
1858 (unsigned long)segments[i].segment_dma;
1859 }
1860
1861 return 0;
1862 }
1863
1864 /**
1865 * mpi3mr_create_op_reply_q - create operational reply queue
1866 * @mrioc: Adapter instance reference
1867 * @qidx: operational reply queue index
1868 *
1869 * Create operatinal reply queue by issuing MPI request
1870 * through admin queue.
1871 *
1872 * Return: 0 on success, non-zero on failure.
1873 */
mpi3mr_create_op_reply_q(struct mpi3mr_ioc * mrioc,u16 qidx)1874 static int mpi3mr_create_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
1875 {
1876 struct mpi3_create_reply_queue_request create_req;
1877 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1878 int retval = 0;
1879 u16 reply_qid = 0, midx;
1880
1881 reply_qid = op_reply_q->qid;
1882
1883 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
1884
1885 if (reply_qid) {
1886 retval = -1;
1887 ioc_err(mrioc, "CreateRepQ: called for duplicate qid %d\n",
1888 reply_qid);
1889
1890 return retval;
1891 }
1892
1893 reply_qid = qidx + 1;
1894 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD;
1895 if (!mrioc->pdev->revision)
1896 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD4K;
1897 op_reply_q->ci = 0;
1898 op_reply_q->ephase = 1;
1899 atomic_set(&op_reply_q->pend_ios, 0);
1900 atomic_set(&op_reply_q->in_use, 0);
1901 op_reply_q->enable_irq_poll = false;
1902
1903 if (!op_reply_q->q_segments) {
1904 retval = mpi3mr_alloc_op_reply_q_segments(mrioc, qidx);
1905 if (retval) {
1906 mpi3mr_free_op_reply_q_segments(mrioc, qidx);
1907 goto out;
1908 }
1909 }
1910
1911 memset(&create_req, 0, sizeof(create_req));
1912 mutex_lock(&mrioc->init_cmds.mutex);
1913 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
1914 retval = -1;
1915 ioc_err(mrioc, "CreateRepQ: Init command is in use\n");
1916 goto out_unlock;
1917 }
1918 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
1919 mrioc->init_cmds.is_waiting = 1;
1920 mrioc->init_cmds.callback = NULL;
1921 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
1922 create_req.function = MPI3_FUNCTION_CREATE_REPLY_QUEUE;
1923 create_req.queue_id = cpu_to_le16(reply_qid);
1924
1925 if (midx < (mrioc->intr_info_count - mrioc->requested_poll_qcount))
1926 op_reply_q->qtype = MPI3MR_DEFAULT_QUEUE;
1927 else
1928 op_reply_q->qtype = MPI3MR_POLL_QUEUE;
1929
1930 if (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) {
1931 create_req.flags =
1932 MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE;
1933 create_req.msix_index =
1934 cpu_to_le16(mrioc->intr_info[midx].msix_index);
1935 } else {
1936 create_req.msix_index = cpu_to_le16(mrioc->intr_info_count - 1);
1937 ioc_info(mrioc, "create reply queue(polled): for qid(%d), midx(%d)\n",
1938 reply_qid, midx);
1939 if (!mrioc->active_poll_qcount)
1940 disable_irq_nosync(pci_irq_vector(mrioc->pdev,
1941 mrioc->intr_info_count - 1));
1942 }
1943
1944 if (mrioc->enable_segqueue) {
1945 create_req.flags |=
1946 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
1947 create_req.base_address = cpu_to_le64(
1948 op_reply_q->q_segment_list_dma);
1949 } else
1950 create_req.base_address = cpu_to_le64(
1951 op_reply_q->q_segments[0].segment_dma);
1952
1953 create_req.size = cpu_to_le16(op_reply_q->num_replies);
1954
1955 init_completion(&mrioc->init_cmds.done);
1956 retval = mpi3mr_admin_request_post(mrioc, &create_req,
1957 sizeof(create_req), 1);
1958 if (retval) {
1959 ioc_err(mrioc, "CreateRepQ: Admin Post failed\n");
1960 goto out_unlock;
1961 }
1962 wait_for_completion_timeout(&mrioc->init_cmds.done,
1963 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
1964 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1965 ioc_err(mrioc, "create reply queue timed out\n");
1966 mpi3mr_check_rh_fault_ioc(mrioc,
1967 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT);
1968 retval = -1;
1969 goto out_unlock;
1970 }
1971 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
1972 != MPI3_IOCSTATUS_SUCCESS) {
1973 ioc_err(mrioc,
1974 "CreateRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
1975 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
1976 mrioc->init_cmds.ioc_loginfo);
1977 retval = -1;
1978 goto out_unlock;
1979 }
1980 op_reply_q->qid = reply_qid;
1981 if (midx < mrioc->intr_info_count)
1982 mrioc->intr_info[midx].op_reply_q = op_reply_q;
1983
1984 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount++ :
1985 mrioc->active_poll_qcount++;
1986
1987 out_unlock:
1988 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
1989 mutex_unlock(&mrioc->init_cmds.mutex);
1990 out:
1991
1992 return retval;
1993 }
1994
1995 /**
1996 * mpi3mr_create_op_req_q - create operational request queue
1997 * @mrioc: Adapter instance reference
1998 * @idx: operational request queue index
1999 * @reply_qid: Reply queue ID
2000 *
2001 * Create operatinal request queue by issuing MPI request
2002 * through admin queue.
2003 *
2004 * Return: 0 on success, non-zero on failure.
2005 */
mpi3mr_create_op_req_q(struct mpi3mr_ioc * mrioc,u16 idx,u16 reply_qid)2006 static int mpi3mr_create_op_req_q(struct mpi3mr_ioc *mrioc, u16 idx,
2007 u16 reply_qid)
2008 {
2009 struct mpi3_create_request_queue_request create_req;
2010 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + idx;
2011 int retval = 0;
2012 u16 req_qid = 0;
2013
2014 req_qid = op_req_q->qid;
2015
2016 if (req_qid) {
2017 retval = -1;
2018 ioc_err(mrioc, "CreateReqQ: called for duplicate qid %d\n",
2019 req_qid);
2020
2021 return retval;
2022 }
2023 req_qid = idx + 1;
2024
2025 op_req_q->num_requests = MPI3MR_OP_REQ_Q_QD;
2026 op_req_q->ci = 0;
2027 op_req_q->pi = 0;
2028 op_req_q->reply_qid = reply_qid;
2029 spin_lock_init(&op_req_q->q_lock);
2030
2031 if (!op_req_q->q_segments) {
2032 retval = mpi3mr_alloc_op_req_q_segments(mrioc, idx);
2033 if (retval) {
2034 mpi3mr_free_op_req_q_segments(mrioc, idx);
2035 goto out;
2036 }
2037 }
2038
2039 memset(&create_req, 0, sizeof(create_req));
2040 mutex_lock(&mrioc->init_cmds.mutex);
2041 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2042 retval = -1;
2043 ioc_err(mrioc, "CreateReqQ: Init command is in use\n");
2044 goto out_unlock;
2045 }
2046 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2047 mrioc->init_cmds.is_waiting = 1;
2048 mrioc->init_cmds.callback = NULL;
2049 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2050 create_req.function = MPI3_FUNCTION_CREATE_REQUEST_QUEUE;
2051 create_req.queue_id = cpu_to_le16(req_qid);
2052 if (mrioc->enable_segqueue) {
2053 create_req.flags =
2054 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
2055 create_req.base_address = cpu_to_le64(
2056 op_req_q->q_segment_list_dma);
2057 } else
2058 create_req.base_address = cpu_to_le64(
2059 op_req_q->q_segments[0].segment_dma);
2060 create_req.reply_queue_id = cpu_to_le16(reply_qid);
2061 create_req.size = cpu_to_le16(op_req_q->num_requests);
2062
2063 init_completion(&mrioc->init_cmds.done);
2064 retval = mpi3mr_admin_request_post(mrioc, &create_req,
2065 sizeof(create_req), 1);
2066 if (retval) {
2067 ioc_err(mrioc, "CreateReqQ: Admin Post failed\n");
2068 goto out_unlock;
2069 }
2070 wait_for_completion_timeout(&mrioc->init_cmds.done,
2071 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2072 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2073 ioc_err(mrioc, "create request queue timed out\n");
2074 mpi3mr_check_rh_fault_ioc(mrioc,
2075 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT);
2076 retval = -1;
2077 goto out_unlock;
2078 }
2079 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2080 != MPI3_IOCSTATUS_SUCCESS) {
2081 ioc_err(mrioc,
2082 "CreateReqQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2083 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2084 mrioc->init_cmds.ioc_loginfo);
2085 retval = -1;
2086 goto out_unlock;
2087 }
2088 op_req_q->qid = req_qid;
2089
2090 out_unlock:
2091 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2092 mutex_unlock(&mrioc->init_cmds.mutex);
2093 out:
2094
2095 return retval;
2096 }
2097
2098 /**
2099 * mpi3mr_create_op_queues - create operational queue pairs
2100 * @mrioc: Adapter instance reference
2101 *
2102 * Allocate memory for operational queue meta data and call
2103 * create request and reply queue functions.
2104 *
2105 * Return: 0 on success, non-zero on failures.
2106 */
mpi3mr_create_op_queues(struct mpi3mr_ioc * mrioc)2107 static int mpi3mr_create_op_queues(struct mpi3mr_ioc *mrioc)
2108 {
2109 int retval = 0;
2110 u16 num_queues = 0, i = 0, msix_count_op_q = 1;
2111
2112 num_queues = min_t(int, mrioc->facts.max_op_reply_q,
2113 mrioc->facts.max_op_req_q);
2114
2115 msix_count_op_q =
2116 mrioc->intr_info_count - mrioc->op_reply_q_offset;
2117 if (!mrioc->num_queues)
2118 mrioc->num_queues = min_t(int, num_queues, msix_count_op_q);
2119 /*
2120 * During reset set the num_queues to the number of queues
2121 * that was set before the reset.
2122 */
2123 num_queues = mrioc->num_op_reply_q ?
2124 mrioc->num_op_reply_q : mrioc->num_queues;
2125 ioc_info(mrioc, "trying to create %d operational queue pairs\n",
2126 num_queues);
2127
2128 if (!mrioc->req_qinfo) {
2129 mrioc->req_qinfo = kcalloc(num_queues,
2130 sizeof(struct op_req_qinfo), GFP_KERNEL);
2131 if (!mrioc->req_qinfo) {
2132 retval = -1;
2133 goto out_failed;
2134 }
2135
2136 mrioc->op_reply_qinfo = kzalloc(sizeof(struct op_reply_qinfo) *
2137 num_queues, GFP_KERNEL);
2138 if (!mrioc->op_reply_qinfo) {
2139 retval = -1;
2140 goto out_failed;
2141 }
2142 }
2143
2144 if (mrioc->enable_segqueue)
2145 ioc_info(mrioc,
2146 "allocating operational queues through segmented queues\n");
2147
2148 for (i = 0; i < num_queues; i++) {
2149 if (mpi3mr_create_op_reply_q(mrioc, i)) {
2150 ioc_err(mrioc, "Cannot create OP RepQ %d\n", i);
2151 break;
2152 }
2153 if (mpi3mr_create_op_req_q(mrioc, i,
2154 mrioc->op_reply_qinfo[i].qid)) {
2155 ioc_err(mrioc, "Cannot create OP ReqQ %d\n", i);
2156 mpi3mr_delete_op_reply_q(mrioc, i);
2157 break;
2158 }
2159 }
2160
2161 if (i == 0) {
2162 /* Not even one queue is created successfully*/
2163 retval = -1;
2164 goto out_failed;
2165 }
2166 mrioc->num_op_reply_q = mrioc->num_op_req_q = i;
2167 ioc_info(mrioc,
2168 "successfully created %d operational queue pairs(default/polled) queue = (%d/%d)\n",
2169 mrioc->num_op_reply_q, mrioc->default_qcount,
2170 mrioc->active_poll_qcount);
2171
2172 return retval;
2173 out_failed:
2174 kfree(mrioc->req_qinfo);
2175 mrioc->req_qinfo = NULL;
2176
2177 kfree(mrioc->op_reply_qinfo);
2178 mrioc->op_reply_qinfo = NULL;
2179
2180 return retval;
2181 }
2182
2183 /**
2184 * mpi3mr_op_request_post - Post request to operational queue
2185 * @mrioc: Adapter reference
2186 * @op_req_q: Operational request queue info
2187 * @req: MPI3 request
2188 *
2189 * Post the MPI3 request into operational request queue and
2190 * inform the controller, if the queue is full return
2191 * appropriate error.
2192 *
2193 * Return: 0 on success, non-zero on failure.
2194 */
mpi3mr_op_request_post(struct mpi3mr_ioc * mrioc,struct op_req_qinfo * op_req_q,u8 * req)2195 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
2196 struct op_req_qinfo *op_req_q, u8 *req)
2197 {
2198 u16 pi = 0, max_entries, reply_qidx = 0, midx;
2199 int retval = 0;
2200 unsigned long flags;
2201 u8 *req_entry;
2202 void *segment_base_addr;
2203 u16 req_sz = mrioc->facts.op_req_sz;
2204 struct segments *segments = op_req_q->q_segments;
2205
2206 reply_qidx = op_req_q->reply_qid - 1;
2207
2208 if (mrioc->unrecoverable)
2209 return -EFAULT;
2210
2211 spin_lock_irqsave(&op_req_q->q_lock, flags);
2212 pi = op_req_q->pi;
2213 max_entries = op_req_q->num_requests;
2214
2215 if (mpi3mr_check_req_qfull(op_req_q)) {
2216 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(
2217 reply_qidx, mrioc->op_reply_q_offset);
2218 mpi3mr_process_op_reply_q(mrioc, mrioc->intr_info[midx].op_reply_q);
2219
2220 if (mpi3mr_check_req_qfull(op_req_q)) {
2221 retval = -EAGAIN;
2222 goto out;
2223 }
2224 }
2225
2226 if (mrioc->reset_in_progress) {
2227 ioc_err(mrioc, "OpReqQ submit reset in progress\n");
2228 retval = -EAGAIN;
2229 goto out;
2230 }
2231
2232 segment_base_addr = segments[pi / op_req_q->segment_qd].segment;
2233 req_entry = (u8 *)segment_base_addr +
2234 ((pi % op_req_q->segment_qd) * req_sz);
2235
2236 memset(req_entry, 0, req_sz);
2237 memcpy(req_entry, req, MPI3MR_ADMIN_REQ_FRAME_SZ);
2238
2239 if (++pi == max_entries)
2240 pi = 0;
2241 op_req_q->pi = pi;
2242
2243 #ifndef CONFIG_PREEMPT_RT
2244 if (atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios)
2245 > MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT)
2246 mrioc->op_reply_qinfo[reply_qidx].enable_irq_poll = true;
2247 #else
2248 atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios);
2249 #endif
2250
2251 writel(op_req_q->pi,
2252 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].producer_index);
2253
2254 out:
2255 spin_unlock_irqrestore(&op_req_q->q_lock, flags);
2256 return retval;
2257 }
2258
2259 /**
2260 * mpi3mr_check_rh_fault_ioc - check reset history and fault
2261 * controller
2262 * @mrioc: Adapter instance reference
2263 * @reason_code: reason code for the fault.
2264 *
2265 * This routine will save snapdump and fault the controller with
2266 * the given reason code if it is not already in the fault or
2267 * not asynchronosuly reset. This will be used to handle
2268 * initilaization time faults/resets/timeout as in those cases
2269 * immediate soft reset invocation is not required.
2270 *
2271 * Return: None.
2272 */
mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc * mrioc,u32 reason_code)2273 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code)
2274 {
2275 u32 ioc_status, host_diagnostic, timeout;
2276
2277 if (mrioc->unrecoverable) {
2278 ioc_err(mrioc, "controller is unrecoverable\n");
2279 return;
2280 }
2281
2282 if (!pci_device_is_present(mrioc->pdev)) {
2283 mrioc->unrecoverable = 1;
2284 ioc_err(mrioc, "controller is not present\n");
2285 return;
2286 }
2287
2288 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2289 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
2290 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
2291 mpi3mr_print_fault_info(mrioc);
2292 return;
2293 }
2294 mpi3mr_set_diagsave(mrioc);
2295 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
2296 reason_code);
2297 timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
2298 do {
2299 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2300 if (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
2301 break;
2302 msleep(100);
2303 } while (--timeout);
2304 }
2305
2306 /**
2307 * mpi3mr_sync_timestamp - Issue time stamp sync request
2308 * @mrioc: Adapter reference
2309 *
2310 * Issue IO unit control MPI request to synchornize firmware
2311 * timestamp with host time.
2312 *
2313 * Return: 0 on success, non-zero on failure.
2314 */
mpi3mr_sync_timestamp(struct mpi3mr_ioc * mrioc)2315 static int mpi3mr_sync_timestamp(struct mpi3mr_ioc *mrioc)
2316 {
2317 ktime_t current_time;
2318 struct mpi3_iounit_control_request iou_ctrl;
2319 int retval = 0;
2320
2321 memset(&iou_ctrl, 0, sizeof(iou_ctrl));
2322 mutex_lock(&mrioc->init_cmds.mutex);
2323 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2324 retval = -1;
2325 ioc_err(mrioc, "Issue IOUCTL time_stamp: command is in use\n");
2326 mutex_unlock(&mrioc->init_cmds.mutex);
2327 goto out;
2328 }
2329 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2330 mrioc->init_cmds.is_waiting = 1;
2331 mrioc->init_cmds.callback = NULL;
2332 iou_ctrl.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2333 iou_ctrl.function = MPI3_FUNCTION_IO_UNIT_CONTROL;
2334 iou_ctrl.operation = MPI3_CTRL_OP_UPDATE_TIMESTAMP;
2335 current_time = ktime_get_real();
2336 iou_ctrl.param64[0] = cpu_to_le64(ktime_to_ms(current_time));
2337
2338 init_completion(&mrioc->init_cmds.done);
2339 retval = mpi3mr_admin_request_post(mrioc, &iou_ctrl,
2340 sizeof(iou_ctrl), 0);
2341 if (retval) {
2342 ioc_err(mrioc, "Issue IOUCTL time_stamp: Admin Post failed\n");
2343 goto out_unlock;
2344 }
2345
2346 wait_for_completion_timeout(&mrioc->init_cmds.done,
2347 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2348 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2349 ioc_err(mrioc, "Issue IOUCTL time_stamp: command timed out\n");
2350 mrioc->init_cmds.is_waiting = 0;
2351 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
2352 mpi3mr_check_rh_fault_ioc(mrioc,
2353 MPI3MR_RESET_FROM_TSU_TIMEOUT);
2354 retval = -1;
2355 goto out_unlock;
2356 }
2357 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2358 != MPI3_IOCSTATUS_SUCCESS) {
2359 ioc_err(mrioc,
2360 "Issue IOUCTL time_stamp: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2361 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2362 mrioc->init_cmds.ioc_loginfo);
2363 retval = -1;
2364 goto out_unlock;
2365 }
2366
2367 out_unlock:
2368 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2369 mutex_unlock(&mrioc->init_cmds.mutex);
2370
2371 out:
2372 return retval;
2373 }
2374
2375 /**
2376 * mpi3mr_print_pkg_ver - display controller fw package version
2377 * @mrioc: Adapter reference
2378 *
2379 * Retrieve firmware package version from the component image
2380 * header of the controller flash and display it.
2381 *
2382 * Return: 0 on success and non-zero on failure.
2383 */
mpi3mr_print_pkg_ver(struct mpi3mr_ioc * mrioc)2384 static int mpi3mr_print_pkg_ver(struct mpi3mr_ioc *mrioc)
2385 {
2386 struct mpi3_ci_upload_request ci_upload;
2387 int retval = -1;
2388 void *data = NULL;
2389 dma_addr_t data_dma;
2390 struct mpi3_ci_manifest_mpi *manifest;
2391 u32 data_len = sizeof(struct mpi3_ci_manifest_mpi);
2392 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
2393
2394 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2395 GFP_KERNEL);
2396 if (!data)
2397 return -ENOMEM;
2398
2399 memset(&ci_upload, 0, sizeof(ci_upload));
2400 mutex_lock(&mrioc->init_cmds.mutex);
2401 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2402 ioc_err(mrioc, "sending get package version failed due to command in use\n");
2403 mutex_unlock(&mrioc->init_cmds.mutex);
2404 goto out;
2405 }
2406 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2407 mrioc->init_cmds.is_waiting = 1;
2408 mrioc->init_cmds.callback = NULL;
2409 ci_upload.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2410 ci_upload.function = MPI3_FUNCTION_CI_UPLOAD;
2411 ci_upload.msg_flags = MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY;
2412 ci_upload.signature1 = cpu_to_le32(MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST);
2413 ci_upload.image_offset = cpu_to_le32(MPI3_IMAGE_HEADER_SIZE);
2414 ci_upload.segment_size = cpu_to_le32(data_len);
2415
2416 mpi3mr_add_sg_single(&ci_upload.sgl, sgl_flags, data_len,
2417 data_dma);
2418 init_completion(&mrioc->init_cmds.done);
2419 retval = mpi3mr_admin_request_post(mrioc, &ci_upload,
2420 sizeof(ci_upload), 1);
2421 if (retval) {
2422 ioc_err(mrioc, "posting get package version failed\n");
2423 goto out_unlock;
2424 }
2425 wait_for_completion_timeout(&mrioc->init_cmds.done,
2426 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2427 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2428 ioc_err(mrioc, "get package version timed out\n");
2429 mpi3mr_check_rh_fault_ioc(mrioc,
2430 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT);
2431 retval = -1;
2432 goto out_unlock;
2433 }
2434 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2435 == MPI3_IOCSTATUS_SUCCESS) {
2436 manifest = (struct mpi3_ci_manifest_mpi *) data;
2437 if (manifest->manifest_type == MPI3_CI_MANIFEST_TYPE_MPI) {
2438 ioc_info(mrioc,
2439 "firmware package version(%d.%d.%d.%d.%05d-%05d)\n",
2440 manifest->package_version.gen_major,
2441 manifest->package_version.gen_minor,
2442 manifest->package_version.phase_major,
2443 manifest->package_version.phase_minor,
2444 manifest->package_version.customer_id,
2445 manifest->package_version.build_num);
2446 }
2447 }
2448 retval = 0;
2449 out_unlock:
2450 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2451 mutex_unlock(&mrioc->init_cmds.mutex);
2452
2453 out:
2454 if (data)
2455 dma_free_coherent(&mrioc->pdev->dev, data_len, data,
2456 data_dma);
2457 return retval;
2458 }
2459
2460 /**
2461 * mpi3mr_watchdog_work - watchdog thread to monitor faults
2462 * @work: work struct
2463 *
2464 * Watch dog work periodically executed (1 second interval) to
2465 * monitor firmware fault and to issue periodic timer sync to
2466 * the firmware.
2467 *
2468 * Return: Nothing.
2469 */
mpi3mr_watchdog_work(struct work_struct * work)2470 static void mpi3mr_watchdog_work(struct work_struct *work)
2471 {
2472 struct mpi3mr_ioc *mrioc =
2473 container_of(work, struct mpi3mr_ioc, watchdog_work.work);
2474 unsigned long flags;
2475 enum mpi3mr_iocstate ioc_state;
2476 u32 fault, host_diagnostic, ioc_status;
2477 u32 reset_reason = MPI3MR_RESET_FROM_FAULT_WATCH;
2478
2479 if (mrioc->reset_in_progress)
2480 return;
2481
2482 if (!mrioc->unrecoverable && !pci_device_is_present(mrioc->pdev)) {
2483 ioc_err(mrioc, "watchdog could not detect the controller\n");
2484 mrioc->unrecoverable = 1;
2485 }
2486
2487 if (mrioc->unrecoverable) {
2488 ioc_err(mrioc,
2489 "flush pending commands for unrecoverable controller\n");
2490 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
2491 return;
2492 }
2493
2494 if (mrioc->ts_update_counter++ >= MPI3MR_TSUPDATE_INTERVAL) {
2495 mrioc->ts_update_counter = 0;
2496 mpi3mr_sync_timestamp(mrioc);
2497 }
2498
2499 if ((mrioc->prepare_for_reset) &&
2500 ((mrioc->prepare_for_reset_timeout_counter++) >=
2501 MPI3MR_PREPARE_FOR_RESET_TIMEOUT)) {
2502 mpi3mr_soft_reset_handler(mrioc,
2503 MPI3MR_RESET_FROM_CIACTVRST_TIMER, 1);
2504 return;
2505 }
2506
2507 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2508 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) {
2509 mpi3mr_soft_reset_handler(mrioc, MPI3MR_RESET_FROM_FIRMWARE, 0);
2510 return;
2511 }
2512
2513 /*Check for fault state every one second and issue Soft reset*/
2514 ioc_state = mpi3mr_get_iocstate(mrioc);
2515 if (ioc_state != MRIOC_STATE_FAULT)
2516 goto schedule_work;
2517
2518 fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
2519 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2520 if (host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS) {
2521 if (!mrioc->diagsave_timeout) {
2522 mpi3mr_print_fault_info(mrioc);
2523 ioc_warn(mrioc, "diag save in progress\n");
2524 }
2525 if ((mrioc->diagsave_timeout++) <= MPI3_SYSIF_DIAG_SAVE_TIMEOUT)
2526 goto schedule_work;
2527 }
2528
2529 mpi3mr_print_fault_info(mrioc);
2530 mrioc->diagsave_timeout = 0;
2531
2532 switch (fault) {
2533 case MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED:
2534 case MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED:
2535 ioc_warn(mrioc,
2536 "controller requires system power cycle, marking controller as unrecoverable\n");
2537 mrioc->unrecoverable = 1;
2538 goto schedule_work;
2539 case MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS:
2540 goto schedule_work;
2541 case MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET:
2542 reset_reason = MPI3MR_RESET_FROM_CIACTIV_FAULT;
2543 break;
2544 default:
2545 break;
2546 }
2547 mpi3mr_soft_reset_handler(mrioc, reset_reason, 0);
2548 return;
2549
2550 schedule_work:
2551 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2552 if (mrioc->watchdog_work_q)
2553 queue_delayed_work(mrioc->watchdog_work_q,
2554 &mrioc->watchdog_work,
2555 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2556 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2557 return;
2558 }
2559
2560 /**
2561 * mpi3mr_start_watchdog - Start watchdog
2562 * @mrioc: Adapter instance reference
2563 *
2564 * Create and start the watchdog thread to monitor controller
2565 * faults.
2566 *
2567 * Return: Nothing.
2568 */
mpi3mr_start_watchdog(struct mpi3mr_ioc * mrioc)2569 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc)
2570 {
2571 if (mrioc->watchdog_work_q)
2572 return;
2573
2574 INIT_DELAYED_WORK(&mrioc->watchdog_work, mpi3mr_watchdog_work);
2575 snprintf(mrioc->watchdog_work_q_name,
2576 sizeof(mrioc->watchdog_work_q_name), "watchdog_%s%d", mrioc->name,
2577 mrioc->id);
2578 mrioc->watchdog_work_q =
2579 create_singlethread_workqueue(mrioc->watchdog_work_q_name);
2580 if (!mrioc->watchdog_work_q) {
2581 ioc_err(mrioc, "%s: failed (line=%d)\n", __func__, __LINE__);
2582 return;
2583 }
2584
2585 if (mrioc->watchdog_work_q)
2586 queue_delayed_work(mrioc->watchdog_work_q,
2587 &mrioc->watchdog_work,
2588 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2589 }
2590
2591 /**
2592 * mpi3mr_stop_watchdog - Stop watchdog
2593 * @mrioc: Adapter instance reference
2594 *
2595 * Stop the watchdog thread created to monitor controller
2596 * faults.
2597 *
2598 * Return: Nothing.
2599 */
mpi3mr_stop_watchdog(struct mpi3mr_ioc * mrioc)2600 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc)
2601 {
2602 unsigned long flags;
2603 struct workqueue_struct *wq;
2604
2605 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2606 wq = mrioc->watchdog_work_q;
2607 mrioc->watchdog_work_q = NULL;
2608 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2609 if (wq) {
2610 if (!cancel_delayed_work_sync(&mrioc->watchdog_work))
2611 flush_workqueue(wq);
2612 destroy_workqueue(wq);
2613 }
2614 }
2615
2616 /**
2617 * mpi3mr_setup_admin_qpair - Setup admin queue pair
2618 * @mrioc: Adapter instance reference
2619 *
2620 * Allocate memory for admin queue pair if required and register
2621 * the admin queue with the controller.
2622 *
2623 * Return: 0 on success, non-zero on failures.
2624 */
mpi3mr_setup_admin_qpair(struct mpi3mr_ioc * mrioc)2625 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc)
2626 {
2627 int retval = 0;
2628 u32 num_admin_entries = 0;
2629
2630 mrioc->admin_req_q_sz = MPI3MR_ADMIN_REQ_Q_SIZE;
2631 mrioc->num_admin_req = mrioc->admin_req_q_sz /
2632 MPI3MR_ADMIN_REQ_FRAME_SZ;
2633 mrioc->admin_req_ci = mrioc->admin_req_pi = 0;
2634
2635 mrioc->admin_reply_q_sz = MPI3MR_ADMIN_REPLY_Q_SIZE;
2636 mrioc->num_admin_replies = mrioc->admin_reply_q_sz /
2637 MPI3MR_ADMIN_REPLY_FRAME_SZ;
2638 mrioc->admin_reply_ci = 0;
2639 mrioc->admin_reply_ephase = 1;
2640 atomic_set(&mrioc->admin_reply_q_in_use, 0);
2641
2642 if (!mrioc->admin_req_base) {
2643 mrioc->admin_req_base = dma_alloc_coherent(&mrioc->pdev->dev,
2644 mrioc->admin_req_q_sz, &mrioc->admin_req_dma, GFP_KERNEL);
2645
2646 if (!mrioc->admin_req_base) {
2647 retval = -1;
2648 goto out_failed;
2649 }
2650
2651 mrioc->admin_reply_base = dma_alloc_coherent(&mrioc->pdev->dev,
2652 mrioc->admin_reply_q_sz, &mrioc->admin_reply_dma,
2653 GFP_KERNEL);
2654
2655 if (!mrioc->admin_reply_base) {
2656 retval = -1;
2657 goto out_failed;
2658 }
2659 }
2660
2661 num_admin_entries = (mrioc->num_admin_replies << 16) |
2662 (mrioc->num_admin_req);
2663 writel(num_admin_entries, &mrioc->sysif_regs->admin_queue_num_entries);
2664 mpi3mr_writeq(mrioc->admin_req_dma,
2665 &mrioc->sysif_regs->admin_request_queue_address);
2666 mpi3mr_writeq(mrioc->admin_reply_dma,
2667 &mrioc->sysif_regs->admin_reply_queue_address);
2668 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
2669 writel(mrioc->admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
2670 return retval;
2671
2672 out_failed:
2673
2674 if (mrioc->admin_reply_base) {
2675 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
2676 mrioc->admin_reply_base, mrioc->admin_reply_dma);
2677 mrioc->admin_reply_base = NULL;
2678 }
2679 if (mrioc->admin_req_base) {
2680 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
2681 mrioc->admin_req_base, mrioc->admin_req_dma);
2682 mrioc->admin_req_base = NULL;
2683 }
2684 return retval;
2685 }
2686
2687 /**
2688 * mpi3mr_issue_iocfacts - Send IOC Facts
2689 * @mrioc: Adapter instance reference
2690 * @facts_data: Cached IOC facts data
2691 *
2692 * Issue IOC Facts MPI request through admin queue and wait for
2693 * the completion of it or time out.
2694 *
2695 * Return: 0 on success, non-zero on failures.
2696 */
mpi3mr_issue_iocfacts(struct mpi3mr_ioc * mrioc,struct mpi3_ioc_facts_data * facts_data)2697 static int mpi3mr_issue_iocfacts(struct mpi3mr_ioc *mrioc,
2698 struct mpi3_ioc_facts_data *facts_data)
2699 {
2700 struct mpi3_ioc_facts_request iocfacts_req;
2701 void *data = NULL;
2702 dma_addr_t data_dma;
2703 u32 data_len = sizeof(*facts_data);
2704 int retval = 0;
2705 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
2706
2707 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2708 GFP_KERNEL);
2709
2710 if (!data) {
2711 retval = -1;
2712 goto out;
2713 }
2714
2715 memset(&iocfacts_req, 0, sizeof(iocfacts_req));
2716 mutex_lock(&mrioc->init_cmds.mutex);
2717 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2718 retval = -1;
2719 ioc_err(mrioc, "Issue IOCFacts: Init command is in use\n");
2720 mutex_unlock(&mrioc->init_cmds.mutex);
2721 goto out;
2722 }
2723 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2724 mrioc->init_cmds.is_waiting = 1;
2725 mrioc->init_cmds.callback = NULL;
2726 iocfacts_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2727 iocfacts_req.function = MPI3_FUNCTION_IOC_FACTS;
2728
2729 mpi3mr_add_sg_single(&iocfacts_req.sgl, sgl_flags, data_len,
2730 data_dma);
2731
2732 init_completion(&mrioc->init_cmds.done);
2733 retval = mpi3mr_admin_request_post(mrioc, &iocfacts_req,
2734 sizeof(iocfacts_req), 1);
2735 if (retval) {
2736 ioc_err(mrioc, "Issue IOCFacts: Admin Post failed\n");
2737 goto out_unlock;
2738 }
2739 wait_for_completion_timeout(&mrioc->init_cmds.done,
2740 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2741 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2742 ioc_err(mrioc, "ioc_facts timed out\n");
2743 mpi3mr_check_rh_fault_ioc(mrioc,
2744 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT);
2745 retval = -1;
2746 goto out_unlock;
2747 }
2748 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2749 != MPI3_IOCSTATUS_SUCCESS) {
2750 ioc_err(mrioc,
2751 "Issue IOCFacts: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2752 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2753 mrioc->init_cmds.ioc_loginfo);
2754 retval = -1;
2755 goto out_unlock;
2756 }
2757 memcpy(facts_data, (u8 *)data, data_len);
2758 mpi3mr_process_factsdata(mrioc, facts_data);
2759 out_unlock:
2760 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2761 mutex_unlock(&mrioc->init_cmds.mutex);
2762
2763 out:
2764 if (data)
2765 dma_free_coherent(&mrioc->pdev->dev, data_len, data, data_dma);
2766
2767 return retval;
2768 }
2769
2770 /**
2771 * mpi3mr_check_reset_dma_mask - Process IOC facts data
2772 * @mrioc: Adapter instance reference
2773 *
2774 * Check whether the new DMA mask requested through IOCFacts by
2775 * firmware needs to be set, if so set it .
2776 *
2777 * Return: 0 on success, non-zero on failure.
2778 */
mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc * mrioc)2779 static inline int mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc *mrioc)
2780 {
2781 struct pci_dev *pdev = mrioc->pdev;
2782 int r;
2783 u64 facts_dma_mask = DMA_BIT_MASK(mrioc->facts.dma_mask);
2784
2785 if (!mrioc->facts.dma_mask || (mrioc->dma_mask <= facts_dma_mask))
2786 return 0;
2787
2788 ioc_info(mrioc, "Changing DMA mask from 0x%016llx to 0x%016llx\n",
2789 mrioc->dma_mask, facts_dma_mask);
2790
2791 r = dma_set_mask_and_coherent(&pdev->dev, facts_dma_mask);
2792 if (r) {
2793 ioc_err(mrioc, "Setting DMA mask to 0x%016llx failed: %d\n",
2794 facts_dma_mask, r);
2795 return r;
2796 }
2797 mrioc->dma_mask = facts_dma_mask;
2798 return r;
2799 }
2800
2801 /**
2802 * mpi3mr_process_factsdata - Process IOC facts data
2803 * @mrioc: Adapter instance reference
2804 * @facts_data: Cached IOC facts data
2805 *
2806 * Convert IOC facts data into cpu endianness and cache it in
2807 * the driver .
2808 *
2809 * Return: Nothing.
2810 */
mpi3mr_process_factsdata(struct mpi3mr_ioc * mrioc,struct mpi3_ioc_facts_data * facts_data)2811 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
2812 struct mpi3_ioc_facts_data *facts_data)
2813 {
2814 u32 ioc_config, req_sz, facts_flags;
2815
2816 if ((le16_to_cpu(facts_data->ioc_facts_data_length)) !=
2817 (sizeof(*facts_data) / 4)) {
2818 ioc_warn(mrioc,
2819 "IOCFactsdata length mismatch driver_sz(%zu) firmware_sz(%d)\n",
2820 sizeof(*facts_data),
2821 le16_to_cpu(facts_data->ioc_facts_data_length) * 4);
2822 }
2823
2824 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
2825 req_sz = 1 << ((ioc_config & MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ) >>
2826 MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT);
2827 if (le16_to_cpu(facts_data->ioc_request_frame_size) != (req_sz / 4)) {
2828 ioc_err(mrioc,
2829 "IOCFacts data reqFrameSize mismatch hw_size(%d) firmware_sz(%d)\n",
2830 req_sz / 4, le16_to_cpu(facts_data->ioc_request_frame_size));
2831 }
2832
2833 memset(&mrioc->facts, 0, sizeof(mrioc->facts));
2834
2835 facts_flags = le32_to_cpu(facts_data->flags);
2836 mrioc->facts.op_req_sz = req_sz;
2837 mrioc->op_reply_desc_sz = 1 << ((ioc_config &
2838 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ) >>
2839 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT);
2840
2841 mrioc->facts.ioc_num = facts_data->ioc_number;
2842 mrioc->facts.who_init = facts_data->who_init;
2843 mrioc->facts.max_msix_vectors = le16_to_cpu(facts_data->max_msix_vectors);
2844 mrioc->facts.personality = (facts_flags &
2845 MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK);
2846 mrioc->facts.dma_mask = (facts_flags &
2847 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >>
2848 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT;
2849 mrioc->facts.protocol_flags = facts_data->protocol_flags;
2850 mrioc->facts.mpi_version = le32_to_cpu(facts_data->mpi_version.word);
2851 mrioc->facts.max_reqs = le16_to_cpu(facts_data->max_outstanding_requests);
2852 mrioc->facts.product_id = le16_to_cpu(facts_data->product_id);
2853 mrioc->facts.reply_sz = le16_to_cpu(facts_data->reply_frame_size) * 4;
2854 mrioc->facts.exceptions = le16_to_cpu(facts_data->ioc_exceptions);
2855 mrioc->facts.max_perids = le16_to_cpu(facts_data->max_persistent_id);
2856 mrioc->facts.max_vds = le16_to_cpu(facts_data->max_vds);
2857 mrioc->facts.max_hpds = le16_to_cpu(facts_data->max_host_pds);
2858 mrioc->facts.max_advhpds = le16_to_cpu(facts_data->max_adv_host_pds);
2859 mrioc->facts.max_raid_pds = le16_to_cpu(facts_data->max_raid_pds);
2860 mrioc->facts.max_nvme = le16_to_cpu(facts_data->max_nvme);
2861 mrioc->facts.max_pcie_switches =
2862 le16_to_cpu(facts_data->max_pcie_switches);
2863 mrioc->facts.max_sasexpanders =
2864 le16_to_cpu(facts_data->max_sas_expanders);
2865 mrioc->facts.max_data_length = le16_to_cpu(facts_data->max_data_length);
2866 mrioc->facts.max_sasinitiators =
2867 le16_to_cpu(facts_data->max_sas_initiators);
2868 mrioc->facts.max_enclosures = le16_to_cpu(facts_data->max_enclosures);
2869 mrioc->facts.min_devhandle = le16_to_cpu(facts_data->min_dev_handle);
2870 mrioc->facts.max_devhandle = le16_to_cpu(facts_data->max_dev_handle);
2871 mrioc->facts.max_op_req_q =
2872 le16_to_cpu(facts_data->max_operational_request_queues);
2873 mrioc->facts.max_op_reply_q =
2874 le16_to_cpu(facts_data->max_operational_reply_queues);
2875 mrioc->facts.ioc_capabilities =
2876 le32_to_cpu(facts_data->ioc_capabilities);
2877 mrioc->facts.fw_ver.build_num =
2878 le16_to_cpu(facts_data->fw_version.build_num);
2879 mrioc->facts.fw_ver.cust_id =
2880 le16_to_cpu(facts_data->fw_version.customer_id);
2881 mrioc->facts.fw_ver.ph_minor = facts_data->fw_version.phase_minor;
2882 mrioc->facts.fw_ver.ph_major = facts_data->fw_version.phase_major;
2883 mrioc->facts.fw_ver.gen_minor = facts_data->fw_version.gen_minor;
2884 mrioc->facts.fw_ver.gen_major = facts_data->fw_version.gen_major;
2885 mrioc->msix_count = min_t(int, mrioc->msix_count,
2886 mrioc->facts.max_msix_vectors);
2887 mrioc->facts.sge_mod_mask = facts_data->sge_modifier_mask;
2888 mrioc->facts.sge_mod_value = facts_data->sge_modifier_value;
2889 mrioc->facts.sge_mod_shift = facts_data->sge_modifier_shift;
2890 mrioc->facts.shutdown_timeout =
2891 le16_to_cpu(facts_data->shutdown_timeout);
2892
2893 mrioc->facts.max_dev_per_tg =
2894 facts_data->max_devices_per_throttle_group;
2895 mrioc->facts.io_throttle_data_length =
2896 le16_to_cpu(facts_data->io_throttle_data_length);
2897 mrioc->facts.max_io_throttle_group =
2898 le16_to_cpu(facts_data->max_io_throttle_group);
2899 mrioc->facts.io_throttle_low = le16_to_cpu(facts_data->io_throttle_low);
2900 mrioc->facts.io_throttle_high =
2901 le16_to_cpu(facts_data->io_throttle_high);
2902
2903 if (mrioc->facts.max_data_length ==
2904 MPI3_IOCFACTS_MAX_DATA_LENGTH_NOT_REPORTED)
2905 mrioc->facts.max_data_length = MPI3MR_DEFAULT_MAX_IO_SIZE;
2906 else
2907 mrioc->facts.max_data_length *= MPI3MR_PAGE_SIZE_4K;
2908 /* Store in 512b block count */
2909 if (mrioc->facts.io_throttle_data_length)
2910 mrioc->io_throttle_data_length =
2911 (mrioc->facts.io_throttle_data_length * 2 * 4);
2912 else
2913 /* set the length to 1MB + 1K to disable throttle */
2914 mrioc->io_throttle_data_length = (mrioc->facts.max_data_length / 512) + 2;
2915
2916 mrioc->io_throttle_high = (mrioc->facts.io_throttle_high * 2 * 1024);
2917 mrioc->io_throttle_low = (mrioc->facts.io_throttle_low * 2 * 1024);
2918
2919 ioc_info(mrioc, "ioc_num(%d), maxopQ(%d), maxopRepQ(%d), maxdh(%d),",
2920 mrioc->facts.ioc_num, mrioc->facts.max_op_req_q,
2921 mrioc->facts.max_op_reply_q, mrioc->facts.max_devhandle);
2922 ioc_info(mrioc,
2923 "maxreqs(%d), mindh(%d) maxvectors(%d) maxperids(%d)\n",
2924 mrioc->facts.max_reqs, mrioc->facts.min_devhandle,
2925 mrioc->facts.max_msix_vectors, mrioc->facts.max_perids);
2926 ioc_info(mrioc, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x ",
2927 mrioc->facts.sge_mod_mask, mrioc->facts.sge_mod_value,
2928 mrioc->facts.sge_mod_shift);
2929 ioc_info(mrioc, "DMA mask %d InitialPE status 0x%x max_data_len (%d)\n",
2930 mrioc->facts.dma_mask, (facts_flags &
2931 MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK), mrioc->facts.max_data_length);
2932 ioc_info(mrioc,
2933 "max_dev_per_throttle_group(%d), max_throttle_groups(%d)\n",
2934 mrioc->facts.max_dev_per_tg, mrioc->facts.max_io_throttle_group);
2935 ioc_info(mrioc,
2936 "io_throttle_data_len(%dKiB), io_throttle_high(%dMiB), io_throttle_low(%dMiB)\n",
2937 mrioc->facts.io_throttle_data_length * 4,
2938 mrioc->facts.io_throttle_high, mrioc->facts.io_throttle_low);
2939 }
2940
2941 /**
2942 * mpi3mr_alloc_reply_sense_bufs - Send IOC Init
2943 * @mrioc: Adapter instance reference
2944 *
2945 * Allocate and initialize the reply free buffers, sense
2946 * buffers, reply free queue and sense buffer queue.
2947 *
2948 * Return: 0 on success, non-zero on failures.
2949 */
mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc * mrioc)2950 static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc)
2951 {
2952 int retval = 0;
2953 u32 sz, i;
2954
2955 if (mrioc->init_cmds.reply)
2956 return retval;
2957
2958 mrioc->init_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2959 if (!mrioc->init_cmds.reply)
2960 goto out_failed;
2961
2962 mrioc->bsg_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2963 if (!mrioc->bsg_cmds.reply)
2964 goto out_failed;
2965
2966 mrioc->transport_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2967 if (!mrioc->transport_cmds.reply)
2968 goto out_failed;
2969
2970 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
2971 mrioc->dev_rmhs_cmds[i].reply = kzalloc(mrioc->reply_sz,
2972 GFP_KERNEL);
2973 if (!mrioc->dev_rmhs_cmds[i].reply)
2974 goto out_failed;
2975 }
2976
2977 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
2978 mrioc->evtack_cmds[i].reply = kzalloc(mrioc->reply_sz,
2979 GFP_KERNEL);
2980 if (!mrioc->evtack_cmds[i].reply)
2981 goto out_failed;
2982 }
2983
2984 mrioc->host_tm_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2985 if (!mrioc->host_tm_cmds.reply)
2986 goto out_failed;
2987
2988 mrioc->pel_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2989 if (!mrioc->pel_cmds.reply)
2990 goto out_failed;
2991
2992 mrioc->pel_abort_cmd.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2993 if (!mrioc->pel_abort_cmd.reply)
2994 goto out_failed;
2995
2996 mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle;
2997 mrioc->removepend_bitmap = bitmap_zalloc(mrioc->dev_handle_bitmap_bits,
2998 GFP_KERNEL);
2999 if (!mrioc->removepend_bitmap)
3000 goto out_failed;
3001
3002 mrioc->devrem_bitmap = bitmap_zalloc(MPI3MR_NUM_DEVRMCMD, GFP_KERNEL);
3003 if (!mrioc->devrem_bitmap)
3004 goto out_failed;
3005
3006 mrioc->evtack_cmds_bitmap = bitmap_zalloc(MPI3MR_NUM_EVTACKCMD,
3007 GFP_KERNEL);
3008 if (!mrioc->evtack_cmds_bitmap)
3009 goto out_failed;
3010
3011 mrioc->num_reply_bufs = mrioc->facts.max_reqs + MPI3MR_NUM_EVT_REPLIES;
3012 mrioc->reply_free_qsz = mrioc->num_reply_bufs + 1;
3013 mrioc->num_sense_bufs = mrioc->facts.max_reqs / MPI3MR_SENSEBUF_FACTOR;
3014 mrioc->sense_buf_q_sz = mrioc->num_sense_bufs + 1;
3015
3016 /* reply buffer pool, 16 byte align */
3017 sz = mrioc->num_reply_bufs * mrioc->reply_sz;
3018 mrioc->reply_buf_pool = dma_pool_create("reply_buf pool",
3019 &mrioc->pdev->dev, sz, 16, 0);
3020 if (!mrioc->reply_buf_pool) {
3021 ioc_err(mrioc, "reply buf pool: dma_pool_create failed\n");
3022 goto out_failed;
3023 }
3024
3025 mrioc->reply_buf = dma_pool_zalloc(mrioc->reply_buf_pool, GFP_KERNEL,
3026 &mrioc->reply_buf_dma);
3027 if (!mrioc->reply_buf)
3028 goto out_failed;
3029
3030 mrioc->reply_buf_dma_max_address = mrioc->reply_buf_dma + sz;
3031
3032 /* reply free queue, 8 byte align */
3033 sz = mrioc->reply_free_qsz * 8;
3034 mrioc->reply_free_q_pool = dma_pool_create("reply_free_q pool",
3035 &mrioc->pdev->dev, sz, 8, 0);
3036 if (!mrioc->reply_free_q_pool) {
3037 ioc_err(mrioc, "reply_free_q pool: dma_pool_create failed\n");
3038 goto out_failed;
3039 }
3040 mrioc->reply_free_q = dma_pool_zalloc(mrioc->reply_free_q_pool,
3041 GFP_KERNEL, &mrioc->reply_free_q_dma);
3042 if (!mrioc->reply_free_q)
3043 goto out_failed;
3044
3045 /* sense buffer pool, 4 byte align */
3046 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3047 mrioc->sense_buf_pool = dma_pool_create("sense_buf pool",
3048 &mrioc->pdev->dev, sz, 4, 0);
3049 if (!mrioc->sense_buf_pool) {
3050 ioc_err(mrioc, "sense_buf pool: dma_pool_create failed\n");
3051 goto out_failed;
3052 }
3053 mrioc->sense_buf = dma_pool_zalloc(mrioc->sense_buf_pool, GFP_KERNEL,
3054 &mrioc->sense_buf_dma);
3055 if (!mrioc->sense_buf)
3056 goto out_failed;
3057
3058 /* sense buffer queue, 8 byte align */
3059 sz = mrioc->sense_buf_q_sz * 8;
3060 mrioc->sense_buf_q_pool = dma_pool_create("sense_buf_q pool",
3061 &mrioc->pdev->dev, sz, 8, 0);
3062 if (!mrioc->sense_buf_q_pool) {
3063 ioc_err(mrioc, "sense_buf_q pool: dma_pool_create failed\n");
3064 goto out_failed;
3065 }
3066 mrioc->sense_buf_q = dma_pool_zalloc(mrioc->sense_buf_q_pool,
3067 GFP_KERNEL, &mrioc->sense_buf_q_dma);
3068 if (!mrioc->sense_buf_q)
3069 goto out_failed;
3070
3071 return retval;
3072
3073 out_failed:
3074 retval = -1;
3075 return retval;
3076 }
3077
3078 /**
3079 * mpimr_initialize_reply_sbuf_queues - initialize reply sense
3080 * buffers
3081 * @mrioc: Adapter instance reference
3082 *
3083 * Helper function to initialize reply and sense buffers along
3084 * with some debug prints.
3085 *
3086 * Return: None.
3087 */
mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc * mrioc)3088 static void mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc *mrioc)
3089 {
3090 u32 sz, i;
3091 dma_addr_t phy_addr;
3092
3093 sz = mrioc->num_reply_bufs * mrioc->reply_sz;
3094 ioc_info(mrioc,
3095 "reply buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3096 mrioc->reply_buf, mrioc->num_reply_bufs, mrioc->reply_sz,
3097 (sz / 1024), (unsigned long long)mrioc->reply_buf_dma);
3098 sz = mrioc->reply_free_qsz * 8;
3099 ioc_info(mrioc,
3100 "reply_free_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3101 mrioc->reply_free_q, mrioc->reply_free_qsz, 8, (sz / 1024),
3102 (unsigned long long)mrioc->reply_free_q_dma);
3103 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3104 ioc_info(mrioc,
3105 "sense_buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3106 mrioc->sense_buf, mrioc->num_sense_bufs, MPI3MR_SENSE_BUF_SZ,
3107 (sz / 1024), (unsigned long long)mrioc->sense_buf_dma);
3108 sz = mrioc->sense_buf_q_sz * 8;
3109 ioc_info(mrioc,
3110 "sense_buf_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3111 mrioc->sense_buf_q, mrioc->sense_buf_q_sz, 8, (sz / 1024),
3112 (unsigned long long)mrioc->sense_buf_q_dma);
3113
3114 /* initialize Reply buffer Queue */
3115 for (i = 0, phy_addr = mrioc->reply_buf_dma;
3116 i < mrioc->num_reply_bufs; i++, phy_addr += mrioc->reply_sz)
3117 mrioc->reply_free_q[i] = cpu_to_le64(phy_addr);
3118 mrioc->reply_free_q[i] = cpu_to_le64(0);
3119
3120 /* initialize Sense Buffer Queue */
3121 for (i = 0, phy_addr = mrioc->sense_buf_dma;
3122 i < mrioc->num_sense_bufs; i++, phy_addr += MPI3MR_SENSE_BUF_SZ)
3123 mrioc->sense_buf_q[i] = cpu_to_le64(phy_addr);
3124 mrioc->sense_buf_q[i] = cpu_to_le64(0);
3125 }
3126
3127 /**
3128 * mpi3mr_issue_iocinit - Send IOC Init
3129 * @mrioc: Adapter instance reference
3130 *
3131 * Issue IOC Init MPI request through admin queue and wait for
3132 * the completion of it or time out.
3133 *
3134 * Return: 0 on success, non-zero on failures.
3135 */
mpi3mr_issue_iocinit(struct mpi3mr_ioc * mrioc)3136 static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc)
3137 {
3138 struct mpi3_ioc_init_request iocinit_req;
3139 struct mpi3_driver_info_layout *drv_info;
3140 dma_addr_t data_dma;
3141 u32 data_len = sizeof(*drv_info);
3142 int retval = 0;
3143 ktime_t current_time;
3144
3145 drv_info = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
3146 GFP_KERNEL);
3147 if (!drv_info) {
3148 retval = -1;
3149 goto out;
3150 }
3151 mpimr_initialize_reply_sbuf_queues(mrioc);
3152
3153 drv_info->information_length = cpu_to_le32(data_len);
3154 strscpy(drv_info->driver_signature, "Broadcom", sizeof(drv_info->driver_signature));
3155 strscpy(drv_info->os_name, utsname()->sysname, sizeof(drv_info->os_name));
3156 strscpy(drv_info->os_version, utsname()->release, sizeof(drv_info->os_version));
3157 strscpy(drv_info->driver_name, MPI3MR_DRIVER_NAME, sizeof(drv_info->driver_name));
3158 strscpy(drv_info->driver_version, MPI3MR_DRIVER_VERSION, sizeof(drv_info->driver_version));
3159 strscpy(drv_info->driver_release_date, MPI3MR_DRIVER_RELDATE,
3160 sizeof(drv_info->driver_release_date));
3161 drv_info->driver_capabilities = 0;
3162 memcpy((u8 *)&mrioc->driver_info, (u8 *)drv_info,
3163 sizeof(mrioc->driver_info));
3164
3165 memset(&iocinit_req, 0, sizeof(iocinit_req));
3166 mutex_lock(&mrioc->init_cmds.mutex);
3167 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3168 retval = -1;
3169 ioc_err(mrioc, "Issue IOCInit: Init command is in use\n");
3170 mutex_unlock(&mrioc->init_cmds.mutex);
3171 goto out;
3172 }
3173 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3174 mrioc->init_cmds.is_waiting = 1;
3175 mrioc->init_cmds.callback = NULL;
3176 iocinit_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3177 iocinit_req.function = MPI3_FUNCTION_IOC_INIT;
3178 iocinit_req.mpi_version.mpi3_version.dev = MPI3_VERSION_DEV;
3179 iocinit_req.mpi_version.mpi3_version.unit = MPI3_VERSION_UNIT;
3180 iocinit_req.mpi_version.mpi3_version.major = MPI3_VERSION_MAJOR;
3181 iocinit_req.mpi_version.mpi3_version.minor = MPI3_VERSION_MINOR;
3182 iocinit_req.who_init = MPI3_WHOINIT_HOST_DRIVER;
3183 iocinit_req.reply_free_queue_depth = cpu_to_le16(mrioc->reply_free_qsz);
3184 iocinit_req.reply_free_queue_address =
3185 cpu_to_le64(mrioc->reply_free_q_dma);
3186 iocinit_req.sense_buffer_length = cpu_to_le16(MPI3MR_SENSE_BUF_SZ);
3187 iocinit_req.sense_buffer_free_queue_depth =
3188 cpu_to_le16(mrioc->sense_buf_q_sz);
3189 iocinit_req.sense_buffer_free_queue_address =
3190 cpu_to_le64(mrioc->sense_buf_q_dma);
3191 iocinit_req.driver_information_address = cpu_to_le64(data_dma);
3192
3193 current_time = ktime_get_real();
3194 iocinit_req.time_stamp = cpu_to_le64(ktime_to_ms(current_time));
3195
3196 init_completion(&mrioc->init_cmds.done);
3197 retval = mpi3mr_admin_request_post(mrioc, &iocinit_req,
3198 sizeof(iocinit_req), 1);
3199 if (retval) {
3200 ioc_err(mrioc, "Issue IOCInit: Admin Post failed\n");
3201 goto out_unlock;
3202 }
3203 wait_for_completion_timeout(&mrioc->init_cmds.done,
3204 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3205 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3206 mpi3mr_check_rh_fault_ioc(mrioc,
3207 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT);
3208 ioc_err(mrioc, "ioc_init timed out\n");
3209 retval = -1;
3210 goto out_unlock;
3211 }
3212 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3213 != MPI3_IOCSTATUS_SUCCESS) {
3214 ioc_err(mrioc,
3215 "Issue IOCInit: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3216 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3217 mrioc->init_cmds.ioc_loginfo);
3218 retval = -1;
3219 goto out_unlock;
3220 }
3221
3222 mrioc->reply_free_queue_host_index = mrioc->num_reply_bufs;
3223 writel(mrioc->reply_free_queue_host_index,
3224 &mrioc->sysif_regs->reply_free_host_index);
3225
3226 mrioc->sbq_host_index = mrioc->num_sense_bufs;
3227 writel(mrioc->sbq_host_index,
3228 &mrioc->sysif_regs->sense_buffer_free_host_index);
3229 out_unlock:
3230 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3231 mutex_unlock(&mrioc->init_cmds.mutex);
3232
3233 out:
3234 if (drv_info)
3235 dma_free_coherent(&mrioc->pdev->dev, data_len, drv_info,
3236 data_dma);
3237
3238 return retval;
3239 }
3240
3241 /**
3242 * mpi3mr_unmask_events - Unmask events in event mask bitmap
3243 * @mrioc: Adapter instance reference
3244 * @event: MPI event ID
3245 *
3246 * Un mask the specific event by resetting the event_mask
3247 * bitmap.
3248 *
3249 * Return: 0 on success, non-zero on failures.
3250 */
mpi3mr_unmask_events(struct mpi3mr_ioc * mrioc,u16 event)3251 static void mpi3mr_unmask_events(struct mpi3mr_ioc *mrioc, u16 event)
3252 {
3253 u32 desired_event;
3254 u8 word;
3255
3256 if (event >= 128)
3257 return;
3258
3259 desired_event = (1 << (event % 32));
3260 word = event / 32;
3261
3262 mrioc->event_masks[word] &= ~desired_event;
3263 }
3264
3265 /**
3266 * mpi3mr_issue_event_notification - Send event notification
3267 * @mrioc: Adapter instance reference
3268 *
3269 * Issue event notification MPI request through admin queue and
3270 * wait for the completion of it or time out.
3271 *
3272 * Return: 0 on success, non-zero on failures.
3273 */
mpi3mr_issue_event_notification(struct mpi3mr_ioc * mrioc)3274 static int mpi3mr_issue_event_notification(struct mpi3mr_ioc *mrioc)
3275 {
3276 struct mpi3_event_notification_request evtnotify_req;
3277 int retval = 0;
3278 u8 i;
3279
3280 memset(&evtnotify_req, 0, sizeof(evtnotify_req));
3281 mutex_lock(&mrioc->init_cmds.mutex);
3282 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3283 retval = -1;
3284 ioc_err(mrioc, "Issue EvtNotify: Init command is in use\n");
3285 mutex_unlock(&mrioc->init_cmds.mutex);
3286 goto out;
3287 }
3288 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3289 mrioc->init_cmds.is_waiting = 1;
3290 mrioc->init_cmds.callback = NULL;
3291 evtnotify_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3292 evtnotify_req.function = MPI3_FUNCTION_EVENT_NOTIFICATION;
3293 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3294 evtnotify_req.event_masks[i] =
3295 cpu_to_le32(mrioc->event_masks[i]);
3296 init_completion(&mrioc->init_cmds.done);
3297 retval = mpi3mr_admin_request_post(mrioc, &evtnotify_req,
3298 sizeof(evtnotify_req), 1);
3299 if (retval) {
3300 ioc_err(mrioc, "Issue EvtNotify: Admin Post failed\n");
3301 goto out_unlock;
3302 }
3303 wait_for_completion_timeout(&mrioc->init_cmds.done,
3304 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3305 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3306 ioc_err(mrioc, "event notification timed out\n");
3307 mpi3mr_check_rh_fault_ioc(mrioc,
3308 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT);
3309 retval = -1;
3310 goto out_unlock;
3311 }
3312 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3313 != MPI3_IOCSTATUS_SUCCESS) {
3314 ioc_err(mrioc,
3315 "Issue EvtNotify: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3316 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3317 mrioc->init_cmds.ioc_loginfo);
3318 retval = -1;
3319 goto out_unlock;
3320 }
3321
3322 out_unlock:
3323 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3324 mutex_unlock(&mrioc->init_cmds.mutex);
3325 out:
3326 return retval;
3327 }
3328
3329 /**
3330 * mpi3mr_process_event_ack - Process event acknowledgment
3331 * @mrioc: Adapter instance reference
3332 * @event: MPI3 event ID
3333 * @event_ctx: event context
3334 *
3335 * Send event acknowledgment through admin queue and wait for
3336 * it to complete.
3337 *
3338 * Return: 0 on success, non-zero on failures.
3339 */
mpi3mr_process_event_ack(struct mpi3mr_ioc * mrioc,u8 event,u32 event_ctx)3340 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
3341 u32 event_ctx)
3342 {
3343 struct mpi3_event_ack_request evtack_req;
3344 int retval = 0;
3345
3346 memset(&evtack_req, 0, sizeof(evtack_req));
3347 mutex_lock(&mrioc->init_cmds.mutex);
3348 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3349 retval = -1;
3350 ioc_err(mrioc, "Send EvtAck: Init command is in use\n");
3351 mutex_unlock(&mrioc->init_cmds.mutex);
3352 goto out;
3353 }
3354 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3355 mrioc->init_cmds.is_waiting = 1;
3356 mrioc->init_cmds.callback = NULL;
3357 evtack_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3358 evtack_req.function = MPI3_FUNCTION_EVENT_ACK;
3359 evtack_req.event = event;
3360 evtack_req.event_context = cpu_to_le32(event_ctx);
3361
3362 init_completion(&mrioc->init_cmds.done);
3363 retval = mpi3mr_admin_request_post(mrioc, &evtack_req,
3364 sizeof(evtack_req), 1);
3365 if (retval) {
3366 ioc_err(mrioc, "Send EvtAck: Admin Post failed\n");
3367 goto out_unlock;
3368 }
3369 wait_for_completion_timeout(&mrioc->init_cmds.done,
3370 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3371 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3372 ioc_err(mrioc, "Issue EvtNotify: command timed out\n");
3373 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
3374 mpi3mr_check_rh_fault_ioc(mrioc,
3375 MPI3MR_RESET_FROM_EVTACK_TIMEOUT);
3376 retval = -1;
3377 goto out_unlock;
3378 }
3379 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3380 != MPI3_IOCSTATUS_SUCCESS) {
3381 ioc_err(mrioc,
3382 "Send EvtAck: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3383 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3384 mrioc->init_cmds.ioc_loginfo);
3385 retval = -1;
3386 goto out_unlock;
3387 }
3388
3389 out_unlock:
3390 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3391 mutex_unlock(&mrioc->init_cmds.mutex);
3392 out:
3393 return retval;
3394 }
3395
3396 /**
3397 * mpi3mr_alloc_chain_bufs - Allocate chain buffers
3398 * @mrioc: Adapter instance reference
3399 *
3400 * Allocate chain buffers and set a bitmap to indicate free
3401 * chain buffers. Chain buffers are used to pass the SGE
3402 * information along with MPI3 SCSI IO requests for host I/O.
3403 *
3404 * Return: 0 on success, non-zero on failure
3405 */
mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc * mrioc)3406 static int mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc *mrioc)
3407 {
3408 int retval = 0;
3409 u32 sz, i;
3410 u16 num_chains;
3411
3412 if (mrioc->chain_sgl_list)
3413 return retval;
3414
3415 num_chains = mrioc->max_host_ios / MPI3MR_CHAINBUF_FACTOR;
3416
3417 if (prot_mask & (SHOST_DIX_TYPE0_PROTECTION
3418 | SHOST_DIX_TYPE1_PROTECTION
3419 | SHOST_DIX_TYPE2_PROTECTION
3420 | SHOST_DIX_TYPE3_PROTECTION))
3421 num_chains += (num_chains / MPI3MR_CHAINBUFDIX_FACTOR);
3422
3423 mrioc->chain_buf_count = num_chains;
3424 sz = sizeof(struct chain_element) * num_chains;
3425 mrioc->chain_sgl_list = kzalloc(sz, GFP_KERNEL);
3426 if (!mrioc->chain_sgl_list)
3427 goto out_failed;
3428
3429 if (mrioc->max_sgl_entries > (mrioc->facts.max_data_length /
3430 MPI3MR_PAGE_SIZE_4K))
3431 mrioc->max_sgl_entries = mrioc->facts.max_data_length /
3432 MPI3MR_PAGE_SIZE_4K;
3433 sz = mrioc->max_sgl_entries * sizeof(struct mpi3_sge_common);
3434 ioc_info(mrioc, "number of sgl entries=%d chain buffer size=%dKB\n",
3435 mrioc->max_sgl_entries, sz/1024);
3436
3437 mrioc->chain_buf_pool = dma_pool_create("chain_buf pool",
3438 &mrioc->pdev->dev, sz, 16, 0);
3439 if (!mrioc->chain_buf_pool) {
3440 ioc_err(mrioc, "chain buf pool: dma_pool_create failed\n");
3441 goto out_failed;
3442 }
3443
3444 for (i = 0; i < num_chains; i++) {
3445 mrioc->chain_sgl_list[i].addr =
3446 dma_pool_zalloc(mrioc->chain_buf_pool, GFP_KERNEL,
3447 &mrioc->chain_sgl_list[i].dma_addr);
3448
3449 if (!mrioc->chain_sgl_list[i].addr)
3450 goto out_failed;
3451 }
3452 mrioc->chain_bitmap = bitmap_zalloc(num_chains, GFP_KERNEL);
3453 if (!mrioc->chain_bitmap)
3454 goto out_failed;
3455 return retval;
3456 out_failed:
3457 retval = -1;
3458 return retval;
3459 }
3460
3461 /**
3462 * mpi3mr_port_enable_complete - Mark port enable complete
3463 * @mrioc: Adapter instance reference
3464 * @drv_cmd: Internal command tracker
3465 *
3466 * Call back for asynchronous port enable request sets the
3467 * driver command to indicate port enable request is complete.
3468 *
3469 * Return: Nothing
3470 */
mpi3mr_port_enable_complete(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)3471 static void mpi3mr_port_enable_complete(struct mpi3mr_ioc *mrioc,
3472 struct mpi3mr_drv_cmd *drv_cmd)
3473 {
3474 drv_cmd->callback = NULL;
3475 mrioc->scan_started = 0;
3476 if (drv_cmd->state & MPI3MR_CMD_RESET)
3477 mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR;
3478 else
3479 mrioc->scan_failed = drv_cmd->ioc_status;
3480 drv_cmd->state = MPI3MR_CMD_NOTUSED;
3481 }
3482
3483 /**
3484 * mpi3mr_issue_port_enable - Issue Port Enable
3485 * @mrioc: Adapter instance reference
3486 * @async: Flag to wait for completion or not
3487 *
3488 * Issue Port Enable MPI request through admin queue and if the
3489 * async flag is not set wait for the completion of the port
3490 * enable or time out.
3491 *
3492 * Return: 0 on success, non-zero on failures.
3493 */
mpi3mr_issue_port_enable(struct mpi3mr_ioc * mrioc,u8 async)3494 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async)
3495 {
3496 struct mpi3_port_enable_request pe_req;
3497 int retval = 0;
3498 u32 pe_timeout = MPI3MR_PORTENABLE_TIMEOUT;
3499
3500 memset(&pe_req, 0, sizeof(pe_req));
3501 mutex_lock(&mrioc->init_cmds.mutex);
3502 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3503 retval = -1;
3504 ioc_err(mrioc, "Issue PortEnable: Init command is in use\n");
3505 mutex_unlock(&mrioc->init_cmds.mutex);
3506 goto out;
3507 }
3508 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3509 if (async) {
3510 mrioc->init_cmds.is_waiting = 0;
3511 mrioc->init_cmds.callback = mpi3mr_port_enable_complete;
3512 } else {
3513 mrioc->init_cmds.is_waiting = 1;
3514 mrioc->init_cmds.callback = NULL;
3515 init_completion(&mrioc->init_cmds.done);
3516 }
3517 pe_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3518 pe_req.function = MPI3_FUNCTION_PORT_ENABLE;
3519
3520 retval = mpi3mr_admin_request_post(mrioc, &pe_req, sizeof(pe_req), 1);
3521 if (retval) {
3522 ioc_err(mrioc, "Issue PortEnable: Admin Post failed\n");
3523 goto out_unlock;
3524 }
3525 if (async) {
3526 mutex_unlock(&mrioc->init_cmds.mutex);
3527 goto out;
3528 }
3529
3530 wait_for_completion_timeout(&mrioc->init_cmds.done, (pe_timeout * HZ));
3531 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3532 ioc_err(mrioc, "port enable timed out\n");
3533 retval = -1;
3534 mpi3mr_check_rh_fault_ioc(mrioc, MPI3MR_RESET_FROM_PE_TIMEOUT);
3535 goto out_unlock;
3536 }
3537 mpi3mr_port_enable_complete(mrioc, &mrioc->init_cmds);
3538
3539 out_unlock:
3540 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3541 mutex_unlock(&mrioc->init_cmds.mutex);
3542 out:
3543 return retval;
3544 }
3545
3546 /* Protocol type to name mapper structure */
3547 static const struct {
3548 u8 protocol;
3549 char *name;
3550 } mpi3mr_protocols[] = {
3551 { MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR, "Initiator" },
3552 { MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET, "Target" },
3553 { MPI3_IOCFACTS_PROTOCOL_NVME, "NVMe attachment" },
3554 };
3555
3556 /* Capability to name mapper structure*/
3557 static const struct {
3558 u32 capability;
3559 char *name;
3560 } mpi3mr_capabilities[] = {
3561 { MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE, "RAID" },
3562 { MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED, "MultiPath" },
3563 };
3564
3565 /**
3566 * mpi3mr_print_ioc_info - Display controller information
3567 * @mrioc: Adapter instance reference
3568 *
3569 * Display controller personalit, capability, supported
3570 * protocols etc.
3571 *
3572 * Return: Nothing
3573 */
3574 static void
mpi3mr_print_ioc_info(struct mpi3mr_ioc * mrioc)3575 mpi3mr_print_ioc_info(struct mpi3mr_ioc *mrioc)
3576 {
3577 int i = 0, bytes_written = 0;
3578 char personality[16];
3579 char protocol[50] = {0};
3580 char capabilities[100] = {0};
3581 struct mpi3mr_compimg_ver *fwver = &mrioc->facts.fw_ver;
3582
3583 switch (mrioc->facts.personality) {
3584 case MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA:
3585 strncpy(personality, "Enhanced HBA", sizeof(personality));
3586 break;
3587 case MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR:
3588 strncpy(personality, "RAID", sizeof(personality));
3589 break;
3590 default:
3591 strncpy(personality, "Unknown", sizeof(personality));
3592 break;
3593 }
3594
3595 ioc_info(mrioc, "Running in %s Personality", personality);
3596
3597 ioc_info(mrioc, "FW version(%d.%d.%d.%d.%d.%d)\n",
3598 fwver->gen_major, fwver->gen_minor, fwver->ph_major,
3599 fwver->ph_minor, fwver->cust_id, fwver->build_num);
3600
3601 for (i = 0; i < ARRAY_SIZE(mpi3mr_protocols); i++) {
3602 if (mrioc->facts.protocol_flags &
3603 mpi3mr_protocols[i].protocol) {
3604 bytes_written += scnprintf(protocol + bytes_written,
3605 sizeof(protocol) - bytes_written, "%s%s",
3606 bytes_written ? "," : "",
3607 mpi3mr_protocols[i].name);
3608 }
3609 }
3610
3611 bytes_written = 0;
3612 for (i = 0; i < ARRAY_SIZE(mpi3mr_capabilities); i++) {
3613 if (mrioc->facts.protocol_flags &
3614 mpi3mr_capabilities[i].capability) {
3615 bytes_written += scnprintf(capabilities + bytes_written,
3616 sizeof(capabilities) - bytes_written, "%s%s",
3617 bytes_written ? "," : "",
3618 mpi3mr_capabilities[i].name);
3619 }
3620 }
3621
3622 ioc_info(mrioc, "Protocol=(%s), Capabilities=(%s)\n",
3623 protocol, capabilities);
3624 }
3625
3626 /**
3627 * mpi3mr_cleanup_resources - Free PCI resources
3628 * @mrioc: Adapter instance reference
3629 *
3630 * Unmap PCI device memory and disable PCI device.
3631 *
3632 * Return: 0 on success and non-zero on failure.
3633 */
mpi3mr_cleanup_resources(struct mpi3mr_ioc * mrioc)3634 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc)
3635 {
3636 struct pci_dev *pdev = mrioc->pdev;
3637
3638 mpi3mr_cleanup_isr(mrioc);
3639
3640 if (mrioc->sysif_regs) {
3641 iounmap((void __iomem *)mrioc->sysif_regs);
3642 mrioc->sysif_regs = NULL;
3643 }
3644
3645 if (pci_is_enabled(pdev)) {
3646 if (mrioc->bars)
3647 pci_release_selected_regions(pdev, mrioc->bars);
3648 pci_disable_device(pdev);
3649 }
3650 }
3651
3652 /**
3653 * mpi3mr_setup_resources - Enable PCI resources
3654 * @mrioc: Adapter instance reference
3655 *
3656 * Enable PCI device memory, MSI-x registers and set DMA mask.
3657 *
3658 * Return: 0 on success and non-zero on failure.
3659 */
mpi3mr_setup_resources(struct mpi3mr_ioc * mrioc)3660 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc)
3661 {
3662 struct pci_dev *pdev = mrioc->pdev;
3663 u32 memap_sz = 0;
3664 int i, retval = 0, capb = 0;
3665 u16 message_control;
3666 u64 dma_mask = mrioc->dma_mask ? mrioc->dma_mask :
3667 ((sizeof(dma_addr_t) > 4) ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32));
3668
3669 if (pci_enable_device_mem(pdev)) {
3670 ioc_err(mrioc, "pci_enable_device_mem: failed\n");
3671 retval = -ENODEV;
3672 goto out_failed;
3673 }
3674
3675 capb = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3676 if (!capb) {
3677 ioc_err(mrioc, "Unable to find MSI-X Capabilities\n");
3678 retval = -ENODEV;
3679 goto out_failed;
3680 }
3681 mrioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
3682
3683 if (pci_request_selected_regions(pdev, mrioc->bars,
3684 mrioc->driver_name)) {
3685 ioc_err(mrioc, "pci_request_selected_regions: failed\n");
3686 retval = -ENODEV;
3687 goto out_failed;
3688 }
3689
3690 for (i = 0; (i < DEVICE_COUNT_RESOURCE); i++) {
3691 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3692 mrioc->sysif_regs_phys = pci_resource_start(pdev, i);
3693 memap_sz = pci_resource_len(pdev, i);
3694 mrioc->sysif_regs =
3695 ioremap(mrioc->sysif_regs_phys, memap_sz);
3696 break;
3697 }
3698 }
3699
3700 pci_set_master(pdev);
3701
3702 retval = dma_set_mask_and_coherent(&pdev->dev, dma_mask);
3703 if (retval) {
3704 if (dma_mask != DMA_BIT_MASK(32)) {
3705 ioc_warn(mrioc, "Setting 64 bit DMA mask failed\n");
3706 dma_mask = DMA_BIT_MASK(32);
3707 retval = dma_set_mask_and_coherent(&pdev->dev,
3708 dma_mask);
3709 }
3710 if (retval) {
3711 mrioc->dma_mask = 0;
3712 ioc_err(mrioc, "Setting 32 bit DMA mask also failed\n");
3713 goto out_failed;
3714 }
3715 }
3716 mrioc->dma_mask = dma_mask;
3717
3718 if (!mrioc->sysif_regs) {
3719 ioc_err(mrioc,
3720 "Unable to map adapter memory or resource not found\n");
3721 retval = -EINVAL;
3722 goto out_failed;
3723 }
3724
3725 pci_read_config_word(pdev, capb + 2, &message_control);
3726 mrioc->msix_count = (message_control & 0x3FF) + 1;
3727
3728 pci_save_state(pdev);
3729
3730 pci_set_drvdata(pdev, mrioc->shost);
3731
3732 mpi3mr_ioc_disable_intr(mrioc);
3733
3734 ioc_info(mrioc, "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
3735 (unsigned long long)mrioc->sysif_regs_phys,
3736 mrioc->sysif_regs, memap_sz);
3737 ioc_info(mrioc, "Number of MSI-X vectors found in capabilities: (%d)\n",
3738 mrioc->msix_count);
3739
3740 if (!reset_devices && poll_queues > 0)
3741 mrioc->requested_poll_qcount = min_t(int, poll_queues,
3742 mrioc->msix_count - 2);
3743 return retval;
3744
3745 out_failed:
3746 mpi3mr_cleanup_resources(mrioc);
3747 return retval;
3748 }
3749
3750 /**
3751 * mpi3mr_enable_events - Enable required events
3752 * @mrioc: Adapter instance reference
3753 *
3754 * This routine unmasks the events required by the driver by
3755 * sennding appropriate event mask bitmapt through an event
3756 * notification request.
3757 *
3758 * Return: 0 on success and non-zero on failure.
3759 */
mpi3mr_enable_events(struct mpi3mr_ioc * mrioc)3760 static int mpi3mr_enable_events(struct mpi3mr_ioc *mrioc)
3761 {
3762 int retval = 0;
3763 u32 i;
3764
3765 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3766 mrioc->event_masks[i] = -1;
3767
3768 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_ADDED);
3769 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_INFO_CHANGED);
3770 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_STATUS_CHANGE);
3771 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE);
3772 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_ADDED);
3773 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
3774 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DISCOVERY);
3775 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR);
3776 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_BROADCAST_PRIMITIVE);
3777 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST);
3778 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_ENUMERATION);
3779 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PREPARE_FOR_RESET);
3780 mpi3mr_unmask_events(mrioc, MPI3_EVENT_CABLE_MGMT);
3781 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENERGY_PACK_CHANGE);
3782
3783 retval = mpi3mr_issue_event_notification(mrioc);
3784 if (retval)
3785 ioc_err(mrioc, "failed to issue event notification %d\n",
3786 retval);
3787 return retval;
3788 }
3789
3790 /**
3791 * mpi3mr_init_ioc - Initialize the controller
3792 * @mrioc: Adapter instance reference
3793 *
3794 * This the controller initialization routine, executed either
3795 * after soft reset or from pci probe callback.
3796 * Setup the required resources, memory map the controller
3797 * registers, create admin and operational reply queue pairs,
3798 * allocate required memory for reply pool, sense buffer pool,
3799 * issue IOC init request to the firmware, unmask the events and
3800 * issue port enable to discover SAS/SATA/NVMe devies and RAID
3801 * volumes.
3802 *
3803 * Return: 0 on success and non-zero on failure.
3804 */
mpi3mr_init_ioc(struct mpi3mr_ioc * mrioc)3805 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc)
3806 {
3807 int retval = 0;
3808 u8 retry = 0;
3809 struct mpi3_ioc_facts_data facts_data;
3810 u32 sz;
3811
3812 retry_init:
3813 retval = mpi3mr_bring_ioc_ready(mrioc);
3814 if (retval) {
3815 ioc_err(mrioc, "Failed to bring ioc ready: error %d\n",
3816 retval);
3817 goto out_failed_noretry;
3818 }
3819
3820 retval = mpi3mr_setup_isr(mrioc, 1);
3821 if (retval) {
3822 ioc_err(mrioc, "Failed to setup ISR error %d\n",
3823 retval);
3824 goto out_failed_noretry;
3825 }
3826
3827 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
3828 if (retval) {
3829 ioc_err(mrioc, "Failed to Issue IOC Facts %d\n",
3830 retval);
3831 goto out_failed;
3832 }
3833
3834 mrioc->max_host_ios = mrioc->facts.max_reqs - MPI3MR_INTERNAL_CMDS_RESVD;
3835 mrioc->shost->max_sectors = mrioc->facts.max_data_length / 512;
3836 mrioc->num_io_throttle_group = mrioc->facts.max_io_throttle_group;
3837 atomic_set(&mrioc->pend_large_data_sz, 0);
3838
3839 if (reset_devices)
3840 mrioc->max_host_ios = min_t(int, mrioc->max_host_ios,
3841 MPI3MR_HOST_IOS_KDUMP);
3842
3843 if (!(mrioc->facts.ioc_capabilities &
3844 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED)) {
3845 mrioc->sas_transport_enabled = 1;
3846 mrioc->scsi_device_channel = 1;
3847 mrioc->shost->max_channel = 1;
3848 mrioc->shost->transportt = mpi3mr_transport_template;
3849 }
3850
3851 mrioc->reply_sz = mrioc->facts.reply_sz;
3852
3853 retval = mpi3mr_check_reset_dma_mask(mrioc);
3854 if (retval) {
3855 ioc_err(mrioc, "Resetting dma mask failed %d\n",
3856 retval);
3857 goto out_failed_noretry;
3858 }
3859
3860 mpi3mr_print_ioc_info(mrioc);
3861
3862 if (!mrioc->cfg_page) {
3863 dprint_init(mrioc, "allocating config page buffers\n");
3864 mrioc->cfg_page_sz = MPI3MR_DEFAULT_CFG_PAGE_SZ;
3865 mrioc->cfg_page = dma_alloc_coherent(&mrioc->pdev->dev,
3866 mrioc->cfg_page_sz, &mrioc->cfg_page_dma, GFP_KERNEL);
3867 if (!mrioc->cfg_page) {
3868 retval = -1;
3869 goto out_failed_noretry;
3870 }
3871 }
3872
3873 if (!mrioc->init_cmds.reply) {
3874 retval = mpi3mr_alloc_reply_sense_bufs(mrioc);
3875 if (retval) {
3876 ioc_err(mrioc,
3877 "%s :Failed to allocated reply sense buffers %d\n",
3878 __func__, retval);
3879 goto out_failed_noretry;
3880 }
3881 }
3882
3883 if (!mrioc->chain_sgl_list) {
3884 retval = mpi3mr_alloc_chain_bufs(mrioc);
3885 if (retval) {
3886 ioc_err(mrioc, "Failed to allocated chain buffers %d\n",
3887 retval);
3888 goto out_failed_noretry;
3889 }
3890 }
3891
3892 retval = mpi3mr_issue_iocinit(mrioc);
3893 if (retval) {
3894 ioc_err(mrioc, "Failed to Issue IOC Init %d\n",
3895 retval);
3896 goto out_failed;
3897 }
3898
3899 retval = mpi3mr_print_pkg_ver(mrioc);
3900 if (retval) {
3901 ioc_err(mrioc, "failed to get package version\n");
3902 goto out_failed;
3903 }
3904
3905 retval = mpi3mr_setup_isr(mrioc, 0);
3906 if (retval) {
3907 ioc_err(mrioc, "Failed to re-setup ISR, error %d\n",
3908 retval);
3909 goto out_failed_noretry;
3910 }
3911
3912 retval = mpi3mr_create_op_queues(mrioc);
3913 if (retval) {
3914 ioc_err(mrioc, "Failed to create OpQueues error %d\n",
3915 retval);
3916 goto out_failed;
3917 }
3918
3919 if (!mrioc->pel_seqnum_virt) {
3920 dprint_init(mrioc, "allocating memory for pel_seqnum_virt\n");
3921 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
3922 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
3923 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
3924 GFP_KERNEL);
3925 if (!mrioc->pel_seqnum_virt) {
3926 retval = -ENOMEM;
3927 goto out_failed_noretry;
3928 }
3929 }
3930
3931 if (!mrioc->throttle_groups && mrioc->num_io_throttle_group) {
3932 dprint_init(mrioc, "allocating memory for throttle groups\n");
3933 sz = sizeof(struct mpi3mr_throttle_group_info);
3934 mrioc->throttle_groups = kcalloc(mrioc->num_io_throttle_group, sz, GFP_KERNEL);
3935 if (!mrioc->throttle_groups) {
3936 retval = -1;
3937 goto out_failed_noretry;
3938 }
3939 }
3940
3941 retval = mpi3mr_enable_events(mrioc);
3942 if (retval) {
3943 ioc_err(mrioc, "failed to enable events %d\n",
3944 retval);
3945 goto out_failed;
3946 }
3947
3948 ioc_info(mrioc, "controller initialization completed successfully\n");
3949 return retval;
3950 out_failed:
3951 if (retry < 2) {
3952 retry++;
3953 ioc_warn(mrioc, "retrying controller initialization, retry_count:%d\n",
3954 retry);
3955 mpi3mr_memset_buffers(mrioc);
3956 goto retry_init;
3957 }
3958 retval = -1;
3959 out_failed_noretry:
3960 ioc_err(mrioc, "controller initialization failed\n");
3961 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
3962 MPI3MR_RESET_FROM_CTLR_CLEANUP);
3963 mrioc->unrecoverable = 1;
3964 return retval;
3965 }
3966
3967 /**
3968 * mpi3mr_reinit_ioc - Re-Initialize the controller
3969 * @mrioc: Adapter instance reference
3970 * @is_resume: Called from resume or reset path
3971 *
3972 * This the controller re-initialization routine, executed from
3973 * the soft reset handler or resume callback. Creates
3974 * operational reply queue pairs, allocate required memory for
3975 * reply pool, sense buffer pool, issue IOC init request to the
3976 * firmware, unmask the events and issue port enable to discover
3977 * SAS/SATA/NVMe devices and RAID volumes.
3978 *
3979 * Return: 0 on success and non-zero on failure.
3980 */
mpi3mr_reinit_ioc(struct mpi3mr_ioc * mrioc,u8 is_resume)3981 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume)
3982 {
3983 int retval = 0;
3984 u8 retry = 0;
3985 struct mpi3_ioc_facts_data facts_data;
3986 u32 pe_timeout, ioc_status;
3987
3988 retry_init:
3989 pe_timeout =
3990 (MPI3MR_PORTENABLE_TIMEOUT / MPI3MR_PORTENABLE_POLL_INTERVAL);
3991
3992 dprint_reset(mrioc, "bringing up the controller to ready state\n");
3993 retval = mpi3mr_bring_ioc_ready(mrioc);
3994 if (retval) {
3995 ioc_err(mrioc, "failed to bring to ready state\n");
3996 goto out_failed_noretry;
3997 }
3998
3999 if (is_resume) {
4000 dprint_reset(mrioc, "setting up single ISR\n");
4001 retval = mpi3mr_setup_isr(mrioc, 1);
4002 if (retval) {
4003 ioc_err(mrioc, "failed to setup ISR\n");
4004 goto out_failed_noretry;
4005 }
4006 } else
4007 mpi3mr_ioc_enable_intr(mrioc);
4008
4009 dprint_reset(mrioc, "getting ioc_facts\n");
4010 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
4011 if (retval) {
4012 ioc_err(mrioc, "failed to get ioc_facts\n");
4013 goto out_failed;
4014 }
4015
4016 dprint_reset(mrioc, "validating ioc_facts\n");
4017 retval = mpi3mr_revalidate_factsdata(mrioc);
4018 if (retval) {
4019 ioc_err(mrioc, "failed to revalidate ioc_facts data\n");
4020 goto out_failed_noretry;
4021 }
4022
4023 mpi3mr_print_ioc_info(mrioc);
4024
4025 dprint_reset(mrioc, "sending ioc_init\n");
4026 retval = mpi3mr_issue_iocinit(mrioc);
4027 if (retval) {
4028 ioc_err(mrioc, "failed to send ioc_init\n");
4029 goto out_failed;
4030 }
4031
4032 dprint_reset(mrioc, "getting package version\n");
4033 retval = mpi3mr_print_pkg_ver(mrioc);
4034 if (retval) {
4035 ioc_err(mrioc, "failed to get package version\n");
4036 goto out_failed;
4037 }
4038
4039 if (is_resume) {
4040 dprint_reset(mrioc, "setting up multiple ISR\n");
4041 retval = mpi3mr_setup_isr(mrioc, 0);
4042 if (retval) {
4043 ioc_err(mrioc, "failed to re-setup ISR\n");
4044 goto out_failed_noretry;
4045 }
4046 }
4047
4048 dprint_reset(mrioc, "creating operational queue pairs\n");
4049 retval = mpi3mr_create_op_queues(mrioc);
4050 if (retval) {
4051 ioc_err(mrioc, "failed to create operational queue pairs\n");
4052 goto out_failed;
4053 }
4054
4055 if (!mrioc->pel_seqnum_virt) {
4056 dprint_reset(mrioc, "allocating memory for pel_seqnum_virt\n");
4057 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
4058 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
4059 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
4060 GFP_KERNEL);
4061 if (!mrioc->pel_seqnum_virt) {
4062 retval = -ENOMEM;
4063 goto out_failed_noretry;
4064 }
4065 }
4066
4067 if (mrioc->shost->nr_hw_queues > mrioc->num_op_reply_q) {
4068 ioc_err(mrioc,
4069 "cannot create minimum number of operational queues expected:%d created:%d\n",
4070 mrioc->shost->nr_hw_queues, mrioc->num_op_reply_q);
4071 retval = -1;
4072 goto out_failed_noretry;
4073 }
4074
4075 dprint_reset(mrioc, "enabling events\n");
4076 retval = mpi3mr_enable_events(mrioc);
4077 if (retval) {
4078 ioc_err(mrioc, "failed to enable events\n");
4079 goto out_failed;
4080 }
4081
4082 mrioc->device_refresh_on = 1;
4083 mpi3mr_add_event_wait_for_device_refresh(mrioc);
4084
4085 ioc_info(mrioc, "sending port enable\n");
4086 retval = mpi3mr_issue_port_enable(mrioc, 1);
4087 if (retval) {
4088 ioc_err(mrioc, "failed to issue port enable\n");
4089 goto out_failed;
4090 }
4091 do {
4092 ssleep(MPI3MR_PORTENABLE_POLL_INTERVAL);
4093 if (mrioc->init_cmds.state == MPI3MR_CMD_NOTUSED)
4094 break;
4095 if (!pci_device_is_present(mrioc->pdev))
4096 mrioc->unrecoverable = 1;
4097 if (mrioc->unrecoverable) {
4098 retval = -1;
4099 goto out_failed_noretry;
4100 }
4101 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4102 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
4103 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
4104 mpi3mr_print_fault_info(mrioc);
4105 mrioc->init_cmds.is_waiting = 0;
4106 mrioc->init_cmds.callback = NULL;
4107 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4108 goto out_failed;
4109 }
4110 } while (--pe_timeout);
4111
4112 if (!pe_timeout) {
4113 ioc_err(mrioc, "port enable timed out\n");
4114 mpi3mr_check_rh_fault_ioc(mrioc,
4115 MPI3MR_RESET_FROM_PE_TIMEOUT);
4116 mrioc->init_cmds.is_waiting = 0;
4117 mrioc->init_cmds.callback = NULL;
4118 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4119 goto out_failed;
4120 } else if (mrioc->scan_failed) {
4121 ioc_err(mrioc,
4122 "port enable failed with status=0x%04x\n",
4123 mrioc->scan_failed);
4124 } else
4125 ioc_info(mrioc, "port enable completed successfully\n");
4126
4127 ioc_info(mrioc, "controller %s completed successfully\n",
4128 (is_resume)?"resume":"re-initialization");
4129 return retval;
4130 out_failed:
4131 if (retry < 2) {
4132 retry++;
4133 ioc_warn(mrioc, "retrying controller %s, retry_count:%d\n",
4134 (is_resume)?"resume":"re-initialization", retry);
4135 mpi3mr_memset_buffers(mrioc);
4136 goto retry_init;
4137 }
4138 retval = -1;
4139 out_failed_noretry:
4140 ioc_err(mrioc, "controller %s is failed\n",
4141 (is_resume)?"resume":"re-initialization");
4142 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
4143 MPI3MR_RESET_FROM_CTLR_CLEANUP);
4144 mrioc->unrecoverable = 1;
4145 return retval;
4146 }
4147
4148 /**
4149 * mpi3mr_memset_op_reply_q_buffers - memset the operational reply queue's
4150 * segments
4151 * @mrioc: Adapter instance reference
4152 * @qidx: Operational reply queue index
4153 *
4154 * Return: Nothing.
4155 */
mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc * mrioc,u16 qidx)4156 static void mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4157 {
4158 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
4159 struct segments *segments;
4160 int i, size;
4161
4162 if (!op_reply_q->q_segments)
4163 return;
4164
4165 size = op_reply_q->segment_qd * mrioc->op_reply_desc_sz;
4166 segments = op_reply_q->q_segments;
4167 for (i = 0; i < op_reply_q->num_segments; i++)
4168 memset(segments[i].segment, 0, size);
4169 }
4170
4171 /**
4172 * mpi3mr_memset_op_req_q_buffers - memset the operational request queue's
4173 * segments
4174 * @mrioc: Adapter instance reference
4175 * @qidx: Operational request queue index
4176 *
4177 * Return: Nothing.
4178 */
mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc * mrioc,u16 qidx)4179 static void mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4180 {
4181 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
4182 struct segments *segments;
4183 int i, size;
4184
4185 if (!op_req_q->q_segments)
4186 return;
4187
4188 size = op_req_q->segment_qd * mrioc->facts.op_req_sz;
4189 segments = op_req_q->q_segments;
4190 for (i = 0; i < op_req_q->num_segments; i++)
4191 memset(segments[i].segment, 0, size);
4192 }
4193
4194 /**
4195 * mpi3mr_memset_buffers - memset memory for a controller
4196 * @mrioc: Adapter instance reference
4197 *
4198 * clear all the memory allocated for a controller, typically
4199 * called post reset to reuse the memory allocated during the
4200 * controller init.
4201 *
4202 * Return: Nothing.
4203 */
mpi3mr_memset_buffers(struct mpi3mr_ioc * mrioc)4204 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc)
4205 {
4206 u16 i;
4207 struct mpi3mr_throttle_group_info *tg;
4208
4209 mrioc->change_count = 0;
4210 mrioc->active_poll_qcount = 0;
4211 mrioc->default_qcount = 0;
4212 if (mrioc->admin_req_base)
4213 memset(mrioc->admin_req_base, 0, mrioc->admin_req_q_sz);
4214 if (mrioc->admin_reply_base)
4215 memset(mrioc->admin_reply_base, 0, mrioc->admin_reply_q_sz);
4216 atomic_set(&mrioc->admin_reply_q_in_use, 0);
4217
4218 if (mrioc->init_cmds.reply) {
4219 memset(mrioc->init_cmds.reply, 0, sizeof(*mrioc->init_cmds.reply));
4220 memset(mrioc->bsg_cmds.reply, 0,
4221 sizeof(*mrioc->bsg_cmds.reply));
4222 memset(mrioc->host_tm_cmds.reply, 0,
4223 sizeof(*mrioc->host_tm_cmds.reply));
4224 memset(mrioc->pel_cmds.reply, 0,
4225 sizeof(*mrioc->pel_cmds.reply));
4226 memset(mrioc->pel_abort_cmd.reply, 0,
4227 sizeof(*mrioc->pel_abort_cmd.reply));
4228 memset(mrioc->transport_cmds.reply, 0,
4229 sizeof(*mrioc->transport_cmds.reply));
4230 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++)
4231 memset(mrioc->dev_rmhs_cmds[i].reply, 0,
4232 sizeof(*mrioc->dev_rmhs_cmds[i].reply));
4233 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++)
4234 memset(mrioc->evtack_cmds[i].reply, 0,
4235 sizeof(*mrioc->evtack_cmds[i].reply));
4236 bitmap_clear(mrioc->removepend_bitmap, 0,
4237 mrioc->dev_handle_bitmap_bits);
4238 bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD);
4239 bitmap_clear(mrioc->evtack_cmds_bitmap, 0,
4240 MPI3MR_NUM_EVTACKCMD);
4241 }
4242
4243 for (i = 0; i < mrioc->num_queues; i++) {
4244 mrioc->op_reply_qinfo[i].qid = 0;
4245 mrioc->op_reply_qinfo[i].ci = 0;
4246 mrioc->op_reply_qinfo[i].num_replies = 0;
4247 mrioc->op_reply_qinfo[i].ephase = 0;
4248 atomic_set(&mrioc->op_reply_qinfo[i].pend_ios, 0);
4249 atomic_set(&mrioc->op_reply_qinfo[i].in_use, 0);
4250 mpi3mr_memset_op_reply_q_buffers(mrioc, i);
4251
4252 mrioc->req_qinfo[i].ci = 0;
4253 mrioc->req_qinfo[i].pi = 0;
4254 mrioc->req_qinfo[i].num_requests = 0;
4255 mrioc->req_qinfo[i].qid = 0;
4256 mrioc->req_qinfo[i].reply_qid = 0;
4257 spin_lock_init(&mrioc->req_qinfo[i].q_lock);
4258 mpi3mr_memset_op_req_q_buffers(mrioc, i);
4259 }
4260
4261 atomic_set(&mrioc->pend_large_data_sz, 0);
4262 if (mrioc->throttle_groups) {
4263 tg = mrioc->throttle_groups;
4264 for (i = 0; i < mrioc->num_io_throttle_group; i++, tg++) {
4265 tg->id = 0;
4266 tg->fw_qd = 0;
4267 tg->modified_qd = 0;
4268 tg->io_divert = 0;
4269 tg->need_qd_reduction = 0;
4270 tg->high = 0;
4271 tg->low = 0;
4272 tg->qd_reduction = 0;
4273 atomic_set(&tg->pend_large_data_sz, 0);
4274 }
4275 }
4276 }
4277
4278 /**
4279 * mpi3mr_free_mem - Free memory allocated for a controller
4280 * @mrioc: Adapter instance reference
4281 *
4282 * Free all the memory allocated for a controller.
4283 *
4284 * Return: Nothing.
4285 */
mpi3mr_free_mem(struct mpi3mr_ioc * mrioc)4286 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc)
4287 {
4288 u16 i;
4289 struct mpi3mr_intr_info *intr_info;
4290
4291 mpi3mr_free_enclosure_list(mrioc);
4292
4293 if (mrioc->sense_buf_pool) {
4294 if (mrioc->sense_buf)
4295 dma_pool_free(mrioc->sense_buf_pool, mrioc->sense_buf,
4296 mrioc->sense_buf_dma);
4297 dma_pool_destroy(mrioc->sense_buf_pool);
4298 mrioc->sense_buf = NULL;
4299 mrioc->sense_buf_pool = NULL;
4300 }
4301 if (mrioc->sense_buf_q_pool) {
4302 if (mrioc->sense_buf_q)
4303 dma_pool_free(mrioc->sense_buf_q_pool,
4304 mrioc->sense_buf_q, mrioc->sense_buf_q_dma);
4305 dma_pool_destroy(mrioc->sense_buf_q_pool);
4306 mrioc->sense_buf_q = NULL;
4307 mrioc->sense_buf_q_pool = NULL;
4308 }
4309
4310 if (mrioc->reply_buf_pool) {
4311 if (mrioc->reply_buf)
4312 dma_pool_free(mrioc->reply_buf_pool, mrioc->reply_buf,
4313 mrioc->reply_buf_dma);
4314 dma_pool_destroy(mrioc->reply_buf_pool);
4315 mrioc->reply_buf = NULL;
4316 mrioc->reply_buf_pool = NULL;
4317 }
4318 if (mrioc->reply_free_q_pool) {
4319 if (mrioc->reply_free_q)
4320 dma_pool_free(mrioc->reply_free_q_pool,
4321 mrioc->reply_free_q, mrioc->reply_free_q_dma);
4322 dma_pool_destroy(mrioc->reply_free_q_pool);
4323 mrioc->reply_free_q = NULL;
4324 mrioc->reply_free_q_pool = NULL;
4325 }
4326
4327 for (i = 0; i < mrioc->num_op_req_q; i++)
4328 mpi3mr_free_op_req_q_segments(mrioc, i);
4329
4330 for (i = 0; i < mrioc->num_op_reply_q; i++)
4331 mpi3mr_free_op_reply_q_segments(mrioc, i);
4332
4333 for (i = 0; i < mrioc->intr_info_count; i++) {
4334 intr_info = mrioc->intr_info + i;
4335 intr_info->op_reply_q = NULL;
4336 }
4337
4338 kfree(mrioc->req_qinfo);
4339 mrioc->req_qinfo = NULL;
4340 mrioc->num_op_req_q = 0;
4341
4342 kfree(mrioc->op_reply_qinfo);
4343 mrioc->op_reply_qinfo = NULL;
4344 mrioc->num_op_reply_q = 0;
4345
4346 kfree(mrioc->init_cmds.reply);
4347 mrioc->init_cmds.reply = NULL;
4348
4349 kfree(mrioc->bsg_cmds.reply);
4350 mrioc->bsg_cmds.reply = NULL;
4351
4352 kfree(mrioc->host_tm_cmds.reply);
4353 mrioc->host_tm_cmds.reply = NULL;
4354
4355 kfree(mrioc->pel_cmds.reply);
4356 mrioc->pel_cmds.reply = NULL;
4357
4358 kfree(mrioc->pel_abort_cmd.reply);
4359 mrioc->pel_abort_cmd.reply = NULL;
4360
4361 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
4362 kfree(mrioc->evtack_cmds[i].reply);
4363 mrioc->evtack_cmds[i].reply = NULL;
4364 }
4365
4366 bitmap_free(mrioc->removepend_bitmap);
4367 mrioc->removepend_bitmap = NULL;
4368
4369 bitmap_free(mrioc->devrem_bitmap);
4370 mrioc->devrem_bitmap = NULL;
4371
4372 bitmap_free(mrioc->evtack_cmds_bitmap);
4373 mrioc->evtack_cmds_bitmap = NULL;
4374
4375 bitmap_free(mrioc->chain_bitmap);
4376 mrioc->chain_bitmap = NULL;
4377
4378 kfree(mrioc->transport_cmds.reply);
4379 mrioc->transport_cmds.reply = NULL;
4380
4381 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
4382 kfree(mrioc->dev_rmhs_cmds[i].reply);
4383 mrioc->dev_rmhs_cmds[i].reply = NULL;
4384 }
4385
4386 if (mrioc->chain_buf_pool) {
4387 for (i = 0; i < mrioc->chain_buf_count; i++) {
4388 if (mrioc->chain_sgl_list[i].addr) {
4389 dma_pool_free(mrioc->chain_buf_pool,
4390 mrioc->chain_sgl_list[i].addr,
4391 mrioc->chain_sgl_list[i].dma_addr);
4392 mrioc->chain_sgl_list[i].addr = NULL;
4393 }
4394 }
4395 dma_pool_destroy(mrioc->chain_buf_pool);
4396 mrioc->chain_buf_pool = NULL;
4397 }
4398
4399 kfree(mrioc->chain_sgl_list);
4400 mrioc->chain_sgl_list = NULL;
4401
4402 if (mrioc->admin_reply_base) {
4403 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
4404 mrioc->admin_reply_base, mrioc->admin_reply_dma);
4405 mrioc->admin_reply_base = NULL;
4406 }
4407 if (mrioc->admin_req_base) {
4408 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
4409 mrioc->admin_req_base, mrioc->admin_req_dma);
4410 mrioc->admin_req_base = NULL;
4411 }
4412 if (mrioc->cfg_page) {
4413 dma_free_coherent(&mrioc->pdev->dev, mrioc->cfg_page_sz,
4414 mrioc->cfg_page, mrioc->cfg_page_dma);
4415 mrioc->cfg_page = NULL;
4416 }
4417 if (mrioc->pel_seqnum_virt) {
4418 dma_free_coherent(&mrioc->pdev->dev, mrioc->pel_seqnum_sz,
4419 mrioc->pel_seqnum_virt, mrioc->pel_seqnum_dma);
4420 mrioc->pel_seqnum_virt = NULL;
4421 }
4422
4423 kfree(mrioc->throttle_groups);
4424 mrioc->throttle_groups = NULL;
4425
4426 kfree(mrioc->logdata_buf);
4427 mrioc->logdata_buf = NULL;
4428
4429 }
4430
4431 /**
4432 * mpi3mr_issue_ioc_shutdown - shutdown controller
4433 * @mrioc: Adapter instance reference
4434 *
4435 * Send shutodwn notification to the controller and wait for the
4436 * shutdown_timeout for it to be completed.
4437 *
4438 * Return: Nothing.
4439 */
mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc * mrioc)4440 static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc *mrioc)
4441 {
4442 u32 ioc_config, ioc_status;
4443 u8 retval = 1;
4444 u32 timeout = MPI3MR_DEFAULT_SHUTDOWN_TIME * 10;
4445
4446 ioc_info(mrioc, "Issuing shutdown Notification\n");
4447 if (mrioc->unrecoverable) {
4448 ioc_warn(mrioc,
4449 "IOC is unrecoverable shutdown is not issued\n");
4450 return;
4451 }
4452 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4453 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4454 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) {
4455 ioc_info(mrioc, "shutdown already in progress\n");
4456 return;
4457 }
4458
4459 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
4460 ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL;
4461 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ;
4462
4463 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
4464
4465 if (mrioc->facts.shutdown_timeout)
4466 timeout = mrioc->facts.shutdown_timeout * 10;
4467
4468 do {
4469 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4470 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4471 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE) {
4472 retval = 0;
4473 break;
4474 }
4475 msleep(100);
4476 } while (--timeout);
4477
4478 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4479 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
4480
4481 if (retval) {
4482 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4483 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS)
4484 ioc_warn(mrioc,
4485 "shutdown still in progress after timeout\n");
4486 }
4487
4488 ioc_info(mrioc,
4489 "Base IOC Sts/Config after %s shutdown is (0x%x)/(0x%x)\n",
4490 (!retval) ? "successful" : "failed", ioc_status,
4491 ioc_config);
4492 }
4493
4494 /**
4495 * mpi3mr_cleanup_ioc - Cleanup controller
4496 * @mrioc: Adapter instance reference
4497 *
4498 * controller cleanup handler, Message unit reset or soft reset
4499 * and shutdown notification is issued to the controller.
4500 *
4501 * Return: Nothing.
4502 */
mpi3mr_cleanup_ioc(struct mpi3mr_ioc * mrioc)4503 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc)
4504 {
4505 enum mpi3mr_iocstate ioc_state;
4506
4507 dprint_exit(mrioc, "cleaning up the controller\n");
4508 mpi3mr_ioc_disable_intr(mrioc);
4509
4510 ioc_state = mpi3mr_get_iocstate(mrioc);
4511
4512 if ((!mrioc->unrecoverable) && (!mrioc->reset_in_progress) &&
4513 (ioc_state == MRIOC_STATE_READY)) {
4514 if (mpi3mr_issue_and_process_mur(mrioc,
4515 MPI3MR_RESET_FROM_CTLR_CLEANUP))
4516 mpi3mr_issue_reset(mrioc,
4517 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
4518 MPI3MR_RESET_FROM_MUR_FAILURE);
4519 mpi3mr_issue_ioc_shutdown(mrioc);
4520 }
4521 dprint_exit(mrioc, "controller cleanup completed\n");
4522 }
4523
4524 /**
4525 * mpi3mr_drv_cmd_comp_reset - Flush a internal driver command
4526 * @mrioc: Adapter instance reference
4527 * @cmdptr: Internal command tracker
4528 *
4529 * Complete an internal driver commands with state indicating it
4530 * is completed due to reset.
4531 *
4532 * Return: Nothing.
4533 */
mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * cmdptr)4534 static inline void mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc *mrioc,
4535 struct mpi3mr_drv_cmd *cmdptr)
4536 {
4537 if (cmdptr->state & MPI3MR_CMD_PENDING) {
4538 cmdptr->state |= MPI3MR_CMD_RESET;
4539 cmdptr->state &= ~MPI3MR_CMD_PENDING;
4540 if (cmdptr->is_waiting) {
4541 complete(&cmdptr->done);
4542 cmdptr->is_waiting = 0;
4543 } else if (cmdptr->callback)
4544 cmdptr->callback(mrioc, cmdptr);
4545 }
4546 }
4547
4548 /**
4549 * mpi3mr_flush_drv_cmds - Flush internaldriver commands
4550 * @mrioc: Adapter instance reference
4551 *
4552 * Flush all internal driver commands post reset
4553 *
4554 * Return: Nothing.
4555 */
mpi3mr_flush_drv_cmds(struct mpi3mr_ioc * mrioc)4556 void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc)
4557 {
4558 struct mpi3mr_drv_cmd *cmdptr;
4559 u8 i;
4560
4561 cmdptr = &mrioc->init_cmds;
4562 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4563
4564 cmdptr = &mrioc->cfg_cmds;
4565 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4566
4567 cmdptr = &mrioc->bsg_cmds;
4568 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4569 cmdptr = &mrioc->host_tm_cmds;
4570 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4571
4572 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
4573 cmdptr = &mrioc->dev_rmhs_cmds[i];
4574 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4575 }
4576
4577 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
4578 cmdptr = &mrioc->evtack_cmds[i];
4579 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4580 }
4581
4582 cmdptr = &mrioc->pel_cmds;
4583 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4584
4585 cmdptr = &mrioc->pel_abort_cmd;
4586 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4587
4588 cmdptr = &mrioc->transport_cmds;
4589 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4590 }
4591
4592 /**
4593 * mpi3mr_pel_wait_post - Issue PEL Wait
4594 * @mrioc: Adapter instance reference
4595 * @drv_cmd: Internal command tracker
4596 *
4597 * Issue PEL Wait MPI request through admin queue and return.
4598 *
4599 * Return: Nothing.
4600 */
mpi3mr_pel_wait_post(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)4601 static void mpi3mr_pel_wait_post(struct mpi3mr_ioc *mrioc,
4602 struct mpi3mr_drv_cmd *drv_cmd)
4603 {
4604 struct mpi3_pel_req_action_wait pel_wait;
4605
4606 mrioc->pel_abort_requested = false;
4607
4608 memset(&pel_wait, 0, sizeof(pel_wait));
4609 drv_cmd->state = MPI3MR_CMD_PENDING;
4610 drv_cmd->is_waiting = 0;
4611 drv_cmd->callback = mpi3mr_pel_wait_complete;
4612 drv_cmd->ioc_status = 0;
4613 drv_cmd->ioc_loginfo = 0;
4614 pel_wait.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
4615 pel_wait.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
4616 pel_wait.action = MPI3_PEL_ACTION_WAIT;
4617 pel_wait.starting_sequence_number = cpu_to_le32(mrioc->pel_newest_seqnum);
4618 pel_wait.locale = cpu_to_le16(mrioc->pel_locale);
4619 pel_wait.class = cpu_to_le16(mrioc->pel_class);
4620 pel_wait.wait_time = MPI3_PEL_WAITTIME_INFINITE_WAIT;
4621 dprint_bsg_info(mrioc, "sending pel_wait seqnum(%d), class(%d), locale(0x%08x)\n",
4622 mrioc->pel_newest_seqnum, mrioc->pel_class, mrioc->pel_locale);
4623
4624 if (mpi3mr_admin_request_post(mrioc, &pel_wait, sizeof(pel_wait), 0)) {
4625 dprint_bsg_err(mrioc,
4626 "Issuing PELWait: Admin post failed\n");
4627 drv_cmd->state = MPI3MR_CMD_NOTUSED;
4628 drv_cmd->callback = NULL;
4629 drv_cmd->retry_count = 0;
4630 mrioc->pel_enabled = false;
4631 }
4632 }
4633
4634 /**
4635 * mpi3mr_pel_get_seqnum_post - Issue PEL Get Sequence number
4636 * @mrioc: Adapter instance reference
4637 * @drv_cmd: Internal command tracker
4638 *
4639 * Issue PEL get sequence number MPI request through admin queue
4640 * and return.
4641 *
4642 * Return: 0 on success, non-zero on failure.
4643 */
mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)4644 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc,
4645 struct mpi3mr_drv_cmd *drv_cmd)
4646 {
4647 struct mpi3_pel_req_action_get_sequence_numbers pel_getseq_req;
4648 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
4649 int retval = 0;
4650
4651 memset(&pel_getseq_req, 0, sizeof(pel_getseq_req));
4652 mrioc->pel_cmds.state = MPI3MR_CMD_PENDING;
4653 mrioc->pel_cmds.is_waiting = 0;
4654 mrioc->pel_cmds.ioc_status = 0;
4655 mrioc->pel_cmds.ioc_loginfo = 0;
4656 mrioc->pel_cmds.callback = mpi3mr_pel_get_seqnum_complete;
4657 pel_getseq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
4658 pel_getseq_req.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
4659 pel_getseq_req.action = MPI3_PEL_ACTION_GET_SEQNUM;
4660 mpi3mr_add_sg_single(&pel_getseq_req.sgl, sgl_flags,
4661 mrioc->pel_seqnum_sz, mrioc->pel_seqnum_dma);
4662
4663 retval = mpi3mr_admin_request_post(mrioc, &pel_getseq_req,
4664 sizeof(pel_getseq_req), 0);
4665 if (retval) {
4666 if (drv_cmd) {
4667 drv_cmd->state = MPI3MR_CMD_NOTUSED;
4668 drv_cmd->callback = NULL;
4669 drv_cmd->retry_count = 0;
4670 }
4671 mrioc->pel_enabled = false;
4672 }
4673
4674 return retval;
4675 }
4676
4677 /**
4678 * mpi3mr_pel_wait_complete - PELWait Completion callback
4679 * @mrioc: Adapter instance reference
4680 * @drv_cmd: Internal command tracker
4681 *
4682 * This is a callback handler for the PELWait request and
4683 * firmware completes a PELWait request when it is aborted or a
4684 * new PEL entry is available. This sends AEN to the application
4685 * and if the PELwait completion is not due to PELAbort then
4686 * this will send a request for new PEL Sequence number
4687 *
4688 * Return: Nothing.
4689 */
mpi3mr_pel_wait_complete(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)4690 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
4691 struct mpi3mr_drv_cmd *drv_cmd)
4692 {
4693 struct mpi3_pel_reply *pel_reply = NULL;
4694 u16 ioc_status, pe_log_status;
4695 bool do_retry = false;
4696
4697 if (drv_cmd->state & MPI3MR_CMD_RESET)
4698 goto cleanup_drv_cmd;
4699
4700 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
4701 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
4702 ioc_err(mrioc, "%s: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
4703 __func__, ioc_status, drv_cmd->ioc_loginfo);
4704 dprint_bsg_err(mrioc,
4705 "pel_wait: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
4706 ioc_status, drv_cmd->ioc_loginfo);
4707 do_retry = true;
4708 }
4709
4710 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
4711 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
4712
4713 if (!pel_reply) {
4714 dprint_bsg_err(mrioc,
4715 "pel_wait: failed due to no reply\n");
4716 goto out_failed;
4717 }
4718
4719 pe_log_status = le16_to_cpu(pel_reply->pe_log_status);
4720 if ((pe_log_status != MPI3_PEL_STATUS_SUCCESS) &&
4721 (pe_log_status != MPI3_PEL_STATUS_ABORTED)) {
4722 ioc_err(mrioc, "%s: Failed pe_log_status(0x%04x)\n",
4723 __func__, pe_log_status);
4724 dprint_bsg_err(mrioc,
4725 "pel_wait: failed due to pel_log_status(0x%04x)\n",
4726 pe_log_status);
4727 do_retry = true;
4728 }
4729
4730 if (do_retry) {
4731 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
4732 drv_cmd->retry_count++;
4733 dprint_bsg_err(mrioc, "pel_wait: retrying(%d)\n",
4734 drv_cmd->retry_count);
4735 mpi3mr_pel_wait_post(mrioc, drv_cmd);
4736 return;
4737 }
4738 dprint_bsg_err(mrioc,
4739 "pel_wait: failed after all retries(%d)\n",
4740 drv_cmd->retry_count);
4741 goto out_failed;
4742 }
4743 atomic64_inc(&event_counter);
4744 if (!mrioc->pel_abort_requested) {
4745 mrioc->pel_cmds.retry_count = 0;
4746 mpi3mr_pel_get_seqnum_post(mrioc, &mrioc->pel_cmds);
4747 }
4748
4749 return;
4750 out_failed:
4751 mrioc->pel_enabled = false;
4752 cleanup_drv_cmd:
4753 drv_cmd->state = MPI3MR_CMD_NOTUSED;
4754 drv_cmd->callback = NULL;
4755 drv_cmd->retry_count = 0;
4756 }
4757
4758 /**
4759 * mpi3mr_pel_get_seqnum_complete - PELGetSeqNum Completion callback
4760 * @mrioc: Adapter instance reference
4761 * @drv_cmd: Internal command tracker
4762 *
4763 * This is a callback handler for the PEL get sequence number
4764 * request and a new PEL wait request will be issued to the
4765 * firmware from this
4766 *
4767 * Return: Nothing.
4768 */
mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)4769 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc,
4770 struct mpi3mr_drv_cmd *drv_cmd)
4771 {
4772 struct mpi3_pel_reply *pel_reply = NULL;
4773 struct mpi3_pel_seq *pel_seqnum_virt;
4774 u16 ioc_status;
4775 bool do_retry = false;
4776
4777 pel_seqnum_virt = (struct mpi3_pel_seq *)mrioc->pel_seqnum_virt;
4778
4779 if (drv_cmd->state & MPI3MR_CMD_RESET)
4780 goto cleanup_drv_cmd;
4781
4782 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
4783 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
4784 dprint_bsg_err(mrioc,
4785 "pel_get_seqnum: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
4786 ioc_status, drv_cmd->ioc_loginfo);
4787 do_retry = true;
4788 }
4789
4790 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
4791 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
4792 if (!pel_reply) {
4793 dprint_bsg_err(mrioc,
4794 "pel_get_seqnum: failed due to no reply\n");
4795 goto out_failed;
4796 }
4797
4798 if (le16_to_cpu(pel_reply->pe_log_status) != MPI3_PEL_STATUS_SUCCESS) {
4799 dprint_bsg_err(mrioc,
4800 "pel_get_seqnum: failed due to pel_log_status(0x%04x)\n",
4801 le16_to_cpu(pel_reply->pe_log_status));
4802 do_retry = true;
4803 }
4804
4805 if (do_retry) {
4806 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
4807 drv_cmd->retry_count++;
4808 dprint_bsg_err(mrioc,
4809 "pel_get_seqnum: retrying(%d)\n",
4810 drv_cmd->retry_count);
4811 mpi3mr_pel_get_seqnum_post(mrioc, drv_cmd);
4812 return;
4813 }
4814
4815 dprint_bsg_err(mrioc,
4816 "pel_get_seqnum: failed after all retries(%d)\n",
4817 drv_cmd->retry_count);
4818 goto out_failed;
4819 }
4820 mrioc->pel_newest_seqnum = le32_to_cpu(pel_seqnum_virt->newest) + 1;
4821 drv_cmd->retry_count = 0;
4822 mpi3mr_pel_wait_post(mrioc, drv_cmd);
4823
4824 return;
4825 out_failed:
4826 mrioc->pel_enabled = false;
4827 cleanup_drv_cmd:
4828 drv_cmd->state = MPI3MR_CMD_NOTUSED;
4829 drv_cmd->callback = NULL;
4830 drv_cmd->retry_count = 0;
4831 }
4832
4833 /**
4834 * mpi3mr_soft_reset_handler - Reset the controller
4835 * @mrioc: Adapter instance reference
4836 * @reset_reason: Reset reason code
4837 * @snapdump: Flag to generate snapdump in firmware or not
4838 *
4839 * This is an handler for recovering controller by issuing soft
4840 * reset are diag fault reset. This is a blocking function and
4841 * when one reset is executed if any other resets they will be
4842 * blocked. All BSG requests will be blocked during the reset. If
4843 * controller reset is successful then the controller will be
4844 * reinitalized, otherwise the controller will be marked as not
4845 * recoverable
4846 *
4847 * In snapdump bit is set, the controller is issued with diag
4848 * fault reset so that the firmware can create a snap dump and
4849 * post that the firmware will result in F000 fault and the
4850 * driver will issue soft reset to recover from that.
4851 *
4852 * Return: 0 on success, non-zero on failure.
4853 */
mpi3mr_soft_reset_handler(struct mpi3mr_ioc * mrioc,u32 reset_reason,u8 snapdump)4854 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
4855 u32 reset_reason, u8 snapdump)
4856 {
4857 int retval = 0, i;
4858 unsigned long flags;
4859 u32 host_diagnostic, timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
4860
4861 /* Block the reset handler until diag save in progress*/
4862 dprint_reset(mrioc,
4863 "soft_reset_handler: check and block on diagsave_timeout(%d)\n",
4864 mrioc->diagsave_timeout);
4865 while (mrioc->diagsave_timeout)
4866 ssleep(1);
4867 /*
4868 * Block new resets until the currently executing one is finished and
4869 * return the status of the existing reset for all blocked resets
4870 */
4871 dprint_reset(mrioc, "soft_reset_handler: acquiring reset_mutex\n");
4872 if (!mutex_trylock(&mrioc->reset_mutex)) {
4873 ioc_info(mrioc,
4874 "controller reset triggered by %s is blocked due to another reset in progress\n",
4875 mpi3mr_reset_rc_name(reset_reason));
4876 do {
4877 ssleep(1);
4878 } while (mrioc->reset_in_progress == 1);
4879 ioc_info(mrioc,
4880 "returning previous reset result(%d) for the reset triggered by %s\n",
4881 mrioc->prev_reset_result,
4882 mpi3mr_reset_rc_name(reset_reason));
4883 return mrioc->prev_reset_result;
4884 }
4885 ioc_info(mrioc, "controller reset is triggered by %s\n",
4886 mpi3mr_reset_rc_name(reset_reason));
4887
4888 mrioc->device_refresh_on = 0;
4889 mrioc->reset_in_progress = 1;
4890 mrioc->stop_bsgs = 1;
4891 mrioc->prev_reset_result = -1;
4892
4893 if ((!snapdump) && (reset_reason != MPI3MR_RESET_FROM_FAULT_WATCH) &&
4894 (reset_reason != MPI3MR_RESET_FROM_FIRMWARE) &&
4895 (reset_reason != MPI3MR_RESET_FROM_CIACTIV_FAULT)) {
4896 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4897 mrioc->event_masks[i] = -1;
4898
4899 dprint_reset(mrioc, "soft_reset_handler: masking events\n");
4900 mpi3mr_issue_event_notification(mrioc);
4901 }
4902
4903 mpi3mr_wait_for_host_io(mrioc, MPI3MR_RESET_HOST_IOWAIT_TIMEOUT);
4904
4905 mpi3mr_ioc_disable_intr(mrioc);
4906
4907 if (snapdump) {
4908 mpi3mr_set_diagsave(mrioc);
4909 retval = mpi3mr_issue_reset(mrioc,
4910 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
4911 if (!retval) {
4912 do {
4913 host_diagnostic =
4914 readl(&mrioc->sysif_regs->host_diagnostic);
4915 if (!(host_diagnostic &
4916 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
4917 break;
4918 msleep(100);
4919 } while (--timeout);
4920 }
4921 }
4922
4923 retval = mpi3mr_issue_reset(mrioc,
4924 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, reset_reason);
4925 if (retval) {
4926 ioc_err(mrioc, "Failed to issue soft reset to the ioc\n");
4927 goto out;
4928 }
4929 if (mrioc->num_io_throttle_group !=
4930 mrioc->facts.max_io_throttle_group) {
4931 ioc_err(mrioc,
4932 "max io throttle group doesn't match old(%d), new(%d)\n",
4933 mrioc->num_io_throttle_group,
4934 mrioc->facts.max_io_throttle_group);
4935 retval = -EPERM;
4936 goto out;
4937 }
4938
4939 mpi3mr_flush_delayed_cmd_lists(mrioc);
4940 mpi3mr_flush_drv_cmds(mrioc);
4941 bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD);
4942 bitmap_clear(mrioc->removepend_bitmap, 0,
4943 mrioc->dev_handle_bitmap_bits);
4944 bitmap_clear(mrioc->evtack_cmds_bitmap, 0, MPI3MR_NUM_EVTACKCMD);
4945 mpi3mr_flush_host_io(mrioc);
4946 mpi3mr_cleanup_fwevt_list(mrioc);
4947 mpi3mr_invalidate_devhandles(mrioc);
4948 mpi3mr_free_enclosure_list(mrioc);
4949
4950 if (mrioc->prepare_for_reset) {
4951 mrioc->prepare_for_reset = 0;
4952 mrioc->prepare_for_reset_timeout_counter = 0;
4953 }
4954 mpi3mr_memset_buffers(mrioc);
4955 retval = mpi3mr_reinit_ioc(mrioc, 0);
4956 if (retval) {
4957 pr_err(IOCNAME "reinit after soft reset failed: reason %d\n",
4958 mrioc->name, reset_reason);
4959 goto out;
4960 }
4961 ssleep(MPI3MR_RESET_TOPOLOGY_SETTLE_TIME);
4962
4963 out:
4964 if (!retval) {
4965 mrioc->diagsave_timeout = 0;
4966 mrioc->reset_in_progress = 0;
4967 mrioc->pel_abort_requested = 0;
4968 if (mrioc->pel_enabled) {
4969 mrioc->pel_cmds.retry_count = 0;
4970 mpi3mr_pel_wait_post(mrioc, &mrioc->pel_cmds);
4971 }
4972
4973 mrioc->device_refresh_on = 0;
4974
4975 mrioc->ts_update_counter = 0;
4976 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
4977 if (mrioc->watchdog_work_q)
4978 queue_delayed_work(mrioc->watchdog_work_q,
4979 &mrioc->watchdog_work,
4980 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
4981 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
4982 mrioc->stop_bsgs = 0;
4983 if (mrioc->pel_enabled)
4984 atomic64_inc(&event_counter);
4985 } else {
4986 mpi3mr_issue_reset(mrioc,
4987 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
4988 mrioc->device_refresh_on = 0;
4989 mrioc->unrecoverable = 1;
4990 mrioc->reset_in_progress = 0;
4991 retval = -1;
4992 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
4993 }
4994 mrioc->prev_reset_result = retval;
4995 mutex_unlock(&mrioc->reset_mutex);
4996 ioc_info(mrioc, "controller reset is %s\n",
4997 ((retval == 0) ? "successful" : "failed"));
4998 return retval;
4999 }
5000
5001
5002 /**
5003 * mpi3mr_free_config_dma_memory - free memory for config page
5004 * @mrioc: Adapter instance reference
5005 * @mem_desc: memory descriptor structure
5006 *
5007 * Check whether the size of the buffer specified by the memory
5008 * descriptor is greater than the default page size if so then
5009 * free the memory pointed by the descriptor.
5010 *
5011 * Return: Nothing.
5012 */
mpi3mr_free_config_dma_memory(struct mpi3mr_ioc * mrioc,struct dma_memory_desc * mem_desc)5013 static void mpi3mr_free_config_dma_memory(struct mpi3mr_ioc *mrioc,
5014 struct dma_memory_desc *mem_desc)
5015 {
5016 if ((mem_desc->size > mrioc->cfg_page_sz) && mem_desc->addr) {
5017 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size,
5018 mem_desc->addr, mem_desc->dma_addr);
5019 mem_desc->addr = NULL;
5020 }
5021 }
5022
5023 /**
5024 * mpi3mr_alloc_config_dma_memory - Alloc memory for config page
5025 * @mrioc: Adapter instance reference
5026 * @mem_desc: Memory descriptor to hold dma memory info
5027 *
5028 * This function allocates new dmaable memory or provides the
5029 * default config page dmaable memory based on the memory size
5030 * described by the descriptor.
5031 *
5032 * Return: 0 on success, non-zero on failure.
5033 */
mpi3mr_alloc_config_dma_memory(struct mpi3mr_ioc * mrioc,struct dma_memory_desc * mem_desc)5034 static int mpi3mr_alloc_config_dma_memory(struct mpi3mr_ioc *mrioc,
5035 struct dma_memory_desc *mem_desc)
5036 {
5037 if (mem_desc->size > mrioc->cfg_page_sz) {
5038 mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev,
5039 mem_desc->size, &mem_desc->dma_addr, GFP_KERNEL);
5040 if (!mem_desc->addr)
5041 return -ENOMEM;
5042 } else {
5043 mem_desc->addr = mrioc->cfg_page;
5044 mem_desc->dma_addr = mrioc->cfg_page_dma;
5045 memset(mem_desc->addr, 0, mrioc->cfg_page_sz);
5046 }
5047 return 0;
5048 }
5049
5050 /**
5051 * mpi3mr_post_cfg_req - Issue config requests and wait
5052 * @mrioc: Adapter instance reference
5053 * @cfg_req: Configuration request
5054 * @timeout: Timeout in seconds
5055 * @ioc_status: Pointer to return ioc status
5056 *
5057 * A generic function for posting MPI3 configuration request to
5058 * the firmware. This blocks for the completion of request for
5059 * timeout seconds and if the request times out this function
5060 * faults the controller with proper reason code.
5061 *
5062 * On successful completion of the request this function returns
5063 * appropriate ioc status from the firmware back to the caller.
5064 *
5065 * Return: 0 on success, non-zero on failure.
5066 */
mpi3mr_post_cfg_req(struct mpi3mr_ioc * mrioc,struct mpi3_config_request * cfg_req,int timeout,u16 * ioc_status)5067 static int mpi3mr_post_cfg_req(struct mpi3mr_ioc *mrioc,
5068 struct mpi3_config_request *cfg_req, int timeout, u16 *ioc_status)
5069 {
5070 int retval = 0;
5071
5072 mutex_lock(&mrioc->cfg_cmds.mutex);
5073 if (mrioc->cfg_cmds.state & MPI3MR_CMD_PENDING) {
5074 retval = -1;
5075 ioc_err(mrioc, "sending config request failed due to command in use\n");
5076 mutex_unlock(&mrioc->cfg_cmds.mutex);
5077 goto out;
5078 }
5079 mrioc->cfg_cmds.state = MPI3MR_CMD_PENDING;
5080 mrioc->cfg_cmds.is_waiting = 1;
5081 mrioc->cfg_cmds.callback = NULL;
5082 mrioc->cfg_cmds.ioc_status = 0;
5083 mrioc->cfg_cmds.ioc_loginfo = 0;
5084
5085 cfg_req->host_tag = cpu_to_le16(MPI3MR_HOSTTAG_CFG_CMDS);
5086 cfg_req->function = MPI3_FUNCTION_CONFIG;
5087
5088 init_completion(&mrioc->cfg_cmds.done);
5089 dprint_cfg_info(mrioc, "posting config request\n");
5090 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5091 dprint_dump(cfg_req, sizeof(struct mpi3_config_request),
5092 "mpi3_cfg_req");
5093 retval = mpi3mr_admin_request_post(mrioc, cfg_req, sizeof(*cfg_req), 1);
5094 if (retval) {
5095 ioc_err(mrioc, "posting config request failed\n");
5096 goto out_unlock;
5097 }
5098 wait_for_completion_timeout(&mrioc->cfg_cmds.done, (timeout * HZ));
5099 if (!(mrioc->cfg_cmds.state & MPI3MR_CMD_COMPLETE)) {
5100 mpi3mr_check_rh_fault_ioc(mrioc,
5101 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT);
5102 ioc_err(mrioc, "config request timed out\n");
5103 retval = -1;
5104 goto out_unlock;
5105 }
5106 *ioc_status = mrioc->cfg_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
5107 if ((*ioc_status) != MPI3_IOCSTATUS_SUCCESS)
5108 dprint_cfg_err(mrioc,
5109 "cfg_page request returned with ioc_status(0x%04x), log_info(0x%08x)\n",
5110 *ioc_status, mrioc->cfg_cmds.ioc_loginfo);
5111
5112 out_unlock:
5113 mrioc->cfg_cmds.state = MPI3MR_CMD_NOTUSED;
5114 mutex_unlock(&mrioc->cfg_cmds.mutex);
5115
5116 out:
5117 return retval;
5118 }
5119
5120 /**
5121 * mpi3mr_process_cfg_req - config page request processor
5122 * @mrioc: Adapter instance reference
5123 * @cfg_req: Configuration request
5124 * @cfg_hdr: Configuration page header
5125 * @timeout: Timeout in seconds
5126 * @ioc_status: Pointer to return ioc status
5127 * @cfg_buf: Memory pointer to copy config page or header
5128 * @cfg_buf_sz: Size of the memory to get config page or header
5129 *
5130 * This is handler for config page read, write and config page
5131 * header read operations.
5132 *
5133 * This function expects the cfg_req to be populated with page
5134 * type, page number, action for the header read and with page
5135 * address for all other operations.
5136 *
5137 * The cfg_hdr can be passed as null for reading required header
5138 * details for read/write pages the cfg_hdr should point valid
5139 * configuration page header.
5140 *
5141 * This allocates dmaable memory based on the size of the config
5142 * buffer and set the SGE of the cfg_req.
5143 *
5144 * For write actions, the config page data has to be passed in
5145 * the cfg_buf and size of the data has to be mentioned in the
5146 * cfg_buf_sz.
5147 *
5148 * For read/header actions, on successful completion of the
5149 * request with successful ioc_status the data will be copied
5150 * into the cfg_buf limited to a minimum of actual page size and
5151 * cfg_buf_sz
5152 *
5153 *
5154 * Return: 0 on success, non-zero on failure.
5155 */
mpi3mr_process_cfg_req(struct mpi3mr_ioc * mrioc,struct mpi3_config_request * cfg_req,struct mpi3_config_page_header * cfg_hdr,int timeout,u16 * ioc_status,void * cfg_buf,u32 cfg_buf_sz)5156 static int mpi3mr_process_cfg_req(struct mpi3mr_ioc *mrioc,
5157 struct mpi3_config_request *cfg_req,
5158 struct mpi3_config_page_header *cfg_hdr, int timeout, u16 *ioc_status,
5159 void *cfg_buf, u32 cfg_buf_sz)
5160 {
5161 struct dma_memory_desc mem_desc;
5162 int retval = -1;
5163 u8 invalid_action = 0;
5164 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
5165
5166 memset(&mem_desc, 0, sizeof(struct dma_memory_desc));
5167
5168 if (cfg_req->action == MPI3_CONFIG_ACTION_PAGE_HEADER)
5169 mem_desc.size = sizeof(struct mpi3_config_page_header);
5170 else {
5171 if (!cfg_hdr) {
5172 ioc_err(mrioc, "null config header passed for config action(%d), page_type(0x%02x), page_num(%d)\n",
5173 cfg_req->action, cfg_req->page_type,
5174 cfg_req->page_number);
5175 goto out;
5176 }
5177 switch (cfg_hdr->page_attribute & MPI3_CONFIG_PAGEATTR_MASK) {
5178 case MPI3_CONFIG_PAGEATTR_READ_ONLY:
5179 if (cfg_req->action
5180 != MPI3_CONFIG_ACTION_READ_CURRENT)
5181 invalid_action = 1;
5182 break;
5183 case MPI3_CONFIG_PAGEATTR_CHANGEABLE:
5184 if ((cfg_req->action ==
5185 MPI3_CONFIG_ACTION_READ_PERSISTENT) ||
5186 (cfg_req->action ==
5187 MPI3_CONFIG_ACTION_WRITE_PERSISTENT))
5188 invalid_action = 1;
5189 break;
5190 case MPI3_CONFIG_PAGEATTR_PERSISTENT:
5191 default:
5192 break;
5193 }
5194 if (invalid_action) {
5195 ioc_err(mrioc,
5196 "config action(%d) is not allowed for page_type(0x%02x), page_num(%d) with page_attribute(0x%02x)\n",
5197 cfg_req->action, cfg_req->page_type,
5198 cfg_req->page_number, cfg_hdr->page_attribute);
5199 goto out;
5200 }
5201 mem_desc.size = le16_to_cpu(cfg_hdr->page_length) * 4;
5202 cfg_req->page_length = cfg_hdr->page_length;
5203 cfg_req->page_version = cfg_hdr->page_version;
5204 }
5205 if (mpi3mr_alloc_config_dma_memory(mrioc, &mem_desc))
5206 goto out;
5207
5208 mpi3mr_add_sg_single(&cfg_req->sgl, sgl_flags, mem_desc.size,
5209 mem_desc.dma_addr);
5210
5211 if ((cfg_req->action == MPI3_CONFIG_ACTION_WRITE_PERSISTENT) ||
5212 (cfg_req->action == MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5213 memcpy(mem_desc.addr, cfg_buf, min_t(u16, mem_desc.size,
5214 cfg_buf_sz));
5215 dprint_cfg_info(mrioc, "config buffer to be written\n");
5216 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5217 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5218 }
5219
5220 if (mpi3mr_post_cfg_req(mrioc, cfg_req, timeout, ioc_status))
5221 goto out;
5222
5223 retval = 0;
5224 if ((*ioc_status == MPI3_IOCSTATUS_SUCCESS) &&
5225 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_PERSISTENT) &&
5226 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5227 memcpy(cfg_buf, mem_desc.addr, min_t(u16, mem_desc.size,
5228 cfg_buf_sz));
5229 dprint_cfg_info(mrioc, "config buffer read\n");
5230 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5231 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5232 }
5233
5234 out:
5235 mpi3mr_free_config_dma_memory(mrioc, &mem_desc);
5236 return retval;
5237 }
5238
5239 /**
5240 * mpi3mr_cfg_get_dev_pg0 - Read current device page0
5241 * @mrioc: Adapter instance reference
5242 * @ioc_status: Pointer to return ioc status
5243 * @dev_pg0: Pointer to return device page 0
5244 * @pg_sz: Size of the memory allocated to the page pointer
5245 * @form: The form to be used for addressing the page
5246 * @form_spec: Form specific information like device handle
5247 *
5248 * This is handler for config page read for a specific device
5249 * page0. The ioc_status has the controller returned ioc_status.
5250 * This routine doesn't check ioc_status to decide whether the
5251 * page read is success or not and it is the callers
5252 * responsibility.
5253 *
5254 * Return: 0 on success, non-zero on failure.
5255 */
mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_device_page0 * dev_pg0,u16 pg_sz,u32 form,u32 form_spec)5256 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5257 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec)
5258 {
5259 struct mpi3_config_page_header cfg_hdr;
5260 struct mpi3_config_request cfg_req;
5261 u32 page_address;
5262
5263 memset(dev_pg0, 0, pg_sz);
5264 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5265 memset(&cfg_req, 0, sizeof(cfg_req));
5266
5267 cfg_req.function = MPI3_FUNCTION_CONFIG;
5268 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5269 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DEVICE;
5270 cfg_req.page_number = 0;
5271 cfg_req.page_address = 0;
5272
5273 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5274 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5275 ioc_err(mrioc, "device page0 header read failed\n");
5276 goto out_failed;
5277 }
5278 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5279 ioc_err(mrioc, "device page0 header read failed with ioc_status(0x%04x)\n",
5280 *ioc_status);
5281 goto out_failed;
5282 }
5283 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5284 page_address = ((form & MPI3_DEVICE_PGAD_FORM_MASK) |
5285 (form_spec & MPI3_DEVICE_PGAD_HANDLE_MASK));
5286 cfg_req.page_address = cpu_to_le32(page_address);
5287 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5288 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, dev_pg0, pg_sz)) {
5289 ioc_err(mrioc, "device page0 read failed\n");
5290 goto out_failed;
5291 }
5292 return 0;
5293 out_failed:
5294 return -1;
5295 }
5296
5297
5298 /**
5299 * mpi3mr_cfg_get_sas_phy_pg0 - Read current SAS Phy page0
5300 * @mrioc: Adapter instance reference
5301 * @ioc_status: Pointer to return ioc status
5302 * @phy_pg0: Pointer to return SAS Phy page 0
5303 * @pg_sz: Size of the memory allocated to the page pointer
5304 * @form: The form to be used for addressing the page
5305 * @form_spec: Form specific information like phy number
5306 *
5307 * This is handler for config page read for a specific SAS Phy
5308 * page0. The ioc_status has the controller returned ioc_status.
5309 * This routine doesn't check ioc_status to decide whether the
5310 * page read is success or not and it is the callers
5311 * responsibility.
5312 *
5313 * Return: 0 on success, non-zero on failure.
5314 */
mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_sas_phy_page0 * phy_pg0,u16 pg_sz,u32 form,u32 form_spec)5315 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5316 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form,
5317 u32 form_spec)
5318 {
5319 struct mpi3_config_page_header cfg_hdr;
5320 struct mpi3_config_request cfg_req;
5321 u32 page_address;
5322
5323 memset(phy_pg0, 0, pg_sz);
5324 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5325 memset(&cfg_req, 0, sizeof(cfg_req));
5326
5327 cfg_req.function = MPI3_FUNCTION_CONFIG;
5328 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5329 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
5330 cfg_req.page_number = 0;
5331 cfg_req.page_address = 0;
5332
5333 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5334 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5335 ioc_err(mrioc, "sas phy page0 header read failed\n");
5336 goto out_failed;
5337 }
5338 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5339 ioc_err(mrioc, "sas phy page0 header read failed with ioc_status(0x%04x)\n",
5340 *ioc_status);
5341 goto out_failed;
5342 }
5343 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5344 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
5345 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
5346 cfg_req.page_address = cpu_to_le32(page_address);
5347 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5348 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg0, pg_sz)) {
5349 ioc_err(mrioc, "sas phy page0 read failed\n");
5350 goto out_failed;
5351 }
5352 return 0;
5353 out_failed:
5354 return -1;
5355 }
5356
5357 /**
5358 * mpi3mr_cfg_get_sas_phy_pg1 - Read current SAS Phy page1
5359 * @mrioc: Adapter instance reference
5360 * @ioc_status: Pointer to return ioc status
5361 * @phy_pg1: Pointer to return SAS Phy page 1
5362 * @pg_sz: Size of the memory allocated to the page pointer
5363 * @form: The form to be used for addressing the page
5364 * @form_spec: Form specific information like phy number
5365 *
5366 * This is handler for config page read for a specific SAS Phy
5367 * page1. The ioc_status has the controller returned ioc_status.
5368 * This routine doesn't check ioc_status to decide whether the
5369 * page read is success or not and it is the callers
5370 * responsibility.
5371 *
5372 * Return: 0 on success, non-zero on failure.
5373 */
mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_sas_phy_page1 * phy_pg1,u16 pg_sz,u32 form,u32 form_spec)5374 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5375 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form,
5376 u32 form_spec)
5377 {
5378 struct mpi3_config_page_header cfg_hdr;
5379 struct mpi3_config_request cfg_req;
5380 u32 page_address;
5381
5382 memset(phy_pg1, 0, pg_sz);
5383 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5384 memset(&cfg_req, 0, sizeof(cfg_req));
5385
5386 cfg_req.function = MPI3_FUNCTION_CONFIG;
5387 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5388 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
5389 cfg_req.page_number = 1;
5390 cfg_req.page_address = 0;
5391
5392 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5393 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5394 ioc_err(mrioc, "sas phy page1 header read failed\n");
5395 goto out_failed;
5396 }
5397 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5398 ioc_err(mrioc, "sas phy page1 header read failed with ioc_status(0x%04x)\n",
5399 *ioc_status);
5400 goto out_failed;
5401 }
5402 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5403 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
5404 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
5405 cfg_req.page_address = cpu_to_le32(page_address);
5406 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5407 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg1, pg_sz)) {
5408 ioc_err(mrioc, "sas phy page1 read failed\n");
5409 goto out_failed;
5410 }
5411 return 0;
5412 out_failed:
5413 return -1;
5414 }
5415
5416
5417 /**
5418 * mpi3mr_cfg_get_sas_exp_pg0 - Read current SAS Expander page0
5419 * @mrioc: Adapter instance reference
5420 * @ioc_status: Pointer to return ioc status
5421 * @exp_pg0: Pointer to return SAS Expander page 0
5422 * @pg_sz: Size of the memory allocated to the page pointer
5423 * @form: The form to be used for addressing the page
5424 * @form_spec: Form specific information like device handle
5425 *
5426 * This is handler for config page read for a specific SAS
5427 * Expander page0. The ioc_status has the controller returned
5428 * ioc_status. This routine doesn't check ioc_status to decide
5429 * whether the page read is success or not and it is the callers
5430 * responsibility.
5431 *
5432 * Return: 0 on success, non-zero on failure.
5433 */
mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_sas_expander_page0 * exp_pg0,u16 pg_sz,u32 form,u32 form_spec)5434 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5435 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form,
5436 u32 form_spec)
5437 {
5438 struct mpi3_config_page_header cfg_hdr;
5439 struct mpi3_config_request cfg_req;
5440 u32 page_address;
5441
5442 memset(exp_pg0, 0, pg_sz);
5443 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5444 memset(&cfg_req, 0, sizeof(cfg_req));
5445
5446 cfg_req.function = MPI3_FUNCTION_CONFIG;
5447 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5448 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
5449 cfg_req.page_number = 0;
5450 cfg_req.page_address = 0;
5451
5452 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5453 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5454 ioc_err(mrioc, "expander page0 header read failed\n");
5455 goto out_failed;
5456 }
5457 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5458 ioc_err(mrioc, "expander page0 header read failed with ioc_status(0x%04x)\n",
5459 *ioc_status);
5460 goto out_failed;
5461 }
5462 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5463 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
5464 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
5465 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
5466 cfg_req.page_address = cpu_to_le32(page_address);
5467 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5468 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg0, pg_sz)) {
5469 ioc_err(mrioc, "expander page0 read failed\n");
5470 goto out_failed;
5471 }
5472 return 0;
5473 out_failed:
5474 return -1;
5475 }
5476
5477 /**
5478 * mpi3mr_cfg_get_sas_exp_pg1 - Read current SAS Expander page1
5479 * @mrioc: Adapter instance reference
5480 * @ioc_status: Pointer to return ioc status
5481 * @exp_pg1: Pointer to return SAS Expander page 1
5482 * @pg_sz: Size of the memory allocated to the page pointer
5483 * @form: The form to be used for addressing the page
5484 * @form_spec: Form specific information like phy number
5485 *
5486 * This is handler for config page read for a specific SAS
5487 * Expander page1. The ioc_status has the controller returned
5488 * ioc_status. This routine doesn't check ioc_status to decide
5489 * whether the page read is success or not and it is the callers
5490 * responsibility.
5491 *
5492 * Return: 0 on success, non-zero on failure.
5493 */
mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_sas_expander_page1 * exp_pg1,u16 pg_sz,u32 form,u32 form_spec)5494 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5495 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form,
5496 u32 form_spec)
5497 {
5498 struct mpi3_config_page_header cfg_hdr;
5499 struct mpi3_config_request cfg_req;
5500 u32 page_address;
5501
5502 memset(exp_pg1, 0, pg_sz);
5503 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5504 memset(&cfg_req, 0, sizeof(cfg_req));
5505
5506 cfg_req.function = MPI3_FUNCTION_CONFIG;
5507 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5508 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
5509 cfg_req.page_number = 1;
5510 cfg_req.page_address = 0;
5511
5512 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5513 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5514 ioc_err(mrioc, "expander page1 header read failed\n");
5515 goto out_failed;
5516 }
5517 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5518 ioc_err(mrioc, "expander page1 header read failed with ioc_status(0x%04x)\n",
5519 *ioc_status);
5520 goto out_failed;
5521 }
5522 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5523 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
5524 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
5525 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
5526 cfg_req.page_address = cpu_to_le32(page_address);
5527 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5528 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg1, pg_sz)) {
5529 ioc_err(mrioc, "expander page1 read failed\n");
5530 goto out_failed;
5531 }
5532 return 0;
5533 out_failed:
5534 return -1;
5535 }
5536
5537 /**
5538 * mpi3mr_cfg_get_enclosure_pg0 - Read current Enclosure page0
5539 * @mrioc: Adapter instance reference
5540 * @ioc_status: Pointer to return ioc status
5541 * @encl_pg0: Pointer to return Enclosure page 0
5542 * @pg_sz: Size of the memory allocated to the page pointer
5543 * @form: The form to be used for addressing the page
5544 * @form_spec: Form specific information like device handle
5545 *
5546 * This is handler for config page read for a specific Enclosure
5547 * page0. The ioc_status has the controller returned ioc_status.
5548 * This routine doesn't check ioc_status to decide whether the
5549 * page read is success or not and it is the callers
5550 * responsibility.
5551 *
5552 * Return: 0 on success, non-zero on failure.
5553 */
mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_enclosure_page0 * encl_pg0,u16 pg_sz,u32 form,u32 form_spec)5554 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5555 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form,
5556 u32 form_spec)
5557 {
5558 struct mpi3_config_page_header cfg_hdr;
5559 struct mpi3_config_request cfg_req;
5560 u32 page_address;
5561
5562 memset(encl_pg0, 0, pg_sz);
5563 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5564 memset(&cfg_req, 0, sizeof(cfg_req));
5565
5566 cfg_req.function = MPI3_FUNCTION_CONFIG;
5567 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5568 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_ENCLOSURE;
5569 cfg_req.page_number = 0;
5570 cfg_req.page_address = 0;
5571
5572 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5573 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5574 ioc_err(mrioc, "enclosure page0 header read failed\n");
5575 goto out_failed;
5576 }
5577 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5578 ioc_err(mrioc, "enclosure page0 header read failed with ioc_status(0x%04x)\n",
5579 *ioc_status);
5580 goto out_failed;
5581 }
5582 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5583 page_address = ((form & MPI3_ENCLOS_PGAD_FORM_MASK) |
5584 (form_spec & MPI3_ENCLOS_PGAD_HANDLE_MASK));
5585 cfg_req.page_address = cpu_to_le32(page_address);
5586 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5587 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, encl_pg0, pg_sz)) {
5588 ioc_err(mrioc, "enclosure page0 read failed\n");
5589 goto out_failed;
5590 }
5591 return 0;
5592 out_failed:
5593 return -1;
5594 }
5595
5596
5597 /**
5598 * mpi3mr_cfg_get_sas_io_unit_pg0 - Read current SASIOUnit page0
5599 * @mrioc: Adapter instance reference
5600 * @sas_io_unit_pg0: Pointer to return SAS IO Unit page 0
5601 * @pg_sz: Size of the memory allocated to the page pointer
5602 *
5603 * This is handler for config page read for the SAS IO Unit
5604 * page0. This routine checks ioc_status to decide whether the
5605 * page read is success or not.
5606 *
5607 * Return: 0 on success, non-zero on failure.
5608 */
mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc * mrioc,struct mpi3_sas_io_unit_page0 * sas_io_unit_pg0,u16 pg_sz)5609 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc,
5610 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz)
5611 {
5612 struct mpi3_config_page_header cfg_hdr;
5613 struct mpi3_config_request cfg_req;
5614 u16 ioc_status = 0;
5615
5616 memset(sas_io_unit_pg0, 0, pg_sz);
5617 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5618 memset(&cfg_req, 0, sizeof(cfg_req));
5619
5620 cfg_req.function = MPI3_FUNCTION_CONFIG;
5621 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5622 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
5623 cfg_req.page_number = 0;
5624 cfg_req.page_address = 0;
5625
5626 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5627 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5628 ioc_err(mrioc, "sas io unit page0 header read failed\n");
5629 goto out_failed;
5630 }
5631 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5632 ioc_err(mrioc, "sas io unit page0 header read failed with ioc_status(0x%04x)\n",
5633 ioc_status);
5634 goto out_failed;
5635 }
5636 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5637
5638 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5639 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg0, pg_sz)) {
5640 ioc_err(mrioc, "sas io unit page0 read failed\n");
5641 goto out_failed;
5642 }
5643 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5644 ioc_err(mrioc, "sas io unit page0 read failed with ioc_status(0x%04x)\n",
5645 ioc_status);
5646 goto out_failed;
5647 }
5648 return 0;
5649 out_failed:
5650 return -1;
5651 }
5652
5653 /**
5654 * mpi3mr_cfg_get_sas_io_unit_pg1 - Read current SASIOUnit page1
5655 * @mrioc: Adapter instance reference
5656 * @sas_io_unit_pg1: Pointer to return SAS IO Unit page 1
5657 * @pg_sz: Size of the memory allocated to the page pointer
5658 *
5659 * This is handler for config page read for the SAS IO Unit
5660 * page1. This routine checks ioc_status to decide whether the
5661 * page read is success or not.
5662 *
5663 * Return: 0 on success, non-zero on failure.
5664 */
mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc * mrioc,struct mpi3_sas_io_unit_page1 * sas_io_unit_pg1,u16 pg_sz)5665 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
5666 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
5667 {
5668 struct mpi3_config_page_header cfg_hdr;
5669 struct mpi3_config_request cfg_req;
5670 u16 ioc_status = 0;
5671
5672 memset(sas_io_unit_pg1, 0, pg_sz);
5673 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5674 memset(&cfg_req, 0, sizeof(cfg_req));
5675
5676 cfg_req.function = MPI3_FUNCTION_CONFIG;
5677 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5678 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
5679 cfg_req.page_number = 1;
5680 cfg_req.page_address = 0;
5681
5682 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5683 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5684 ioc_err(mrioc, "sas io unit page1 header read failed\n");
5685 goto out_failed;
5686 }
5687 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5688 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
5689 ioc_status);
5690 goto out_failed;
5691 }
5692 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5693
5694 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5695 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
5696 ioc_err(mrioc, "sas io unit page1 read failed\n");
5697 goto out_failed;
5698 }
5699 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5700 ioc_err(mrioc, "sas io unit page1 read failed with ioc_status(0x%04x)\n",
5701 ioc_status);
5702 goto out_failed;
5703 }
5704 return 0;
5705 out_failed:
5706 return -1;
5707 }
5708
5709 /**
5710 * mpi3mr_cfg_set_sas_io_unit_pg1 - Write SASIOUnit page1
5711 * @mrioc: Adapter instance reference
5712 * @sas_io_unit_pg1: Pointer to the SAS IO Unit page 1 to write
5713 * @pg_sz: Size of the memory allocated to the page pointer
5714 *
5715 * This is handler for config page write for the SAS IO Unit
5716 * page1. This routine checks ioc_status to decide whether the
5717 * page read is success or not. This will modify both current
5718 * and persistent page.
5719 *
5720 * Return: 0 on success, non-zero on failure.
5721 */
mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc * mrioc,struct mpi3_sas_io_unit_page1 * sas_io_unit_pg1,u16 pg_sz)5722 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
5723 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
5724 {
5725 struct mpi3_config_page_header cfg_hdr;
5726 struct mpi3_config_request cfg_req;
5727 u16 ioc_status = 0;
5728
5729 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5730 memset(&cfg_req, 0, sizeof(cfg_req));
5731
5732 cfg_req.function = MPI3_FUNCTION_CONFIG;
5733 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5734 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
5735 cfg_req.page_number = 1;
5736 cfg_req.page_address = 0;
5737
5738 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5739 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5740 ioc_err(mrioc, "sas io unit page1 header read failed\n");
5741 goto out_failed;
5742 }
5743 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5744 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
5745 ioc_status);
5746 goto out_failed;
5747 }
5748 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_CURRENT;
5749
5750 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5751 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
5752 ioc_err(mrioc, "sas io unit page1 write current failed\n");
5753 goto out_failed;
5754 }
5755 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5756 ioc_err(mrioc, "sas io unit page1 write current failed with ioc_status(0x%04x)\n",
5757 ioc_status);
5758 goto out_failed;
5759 }
5760
5761 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_PERSISTENT;
5762
5763 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5764 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
5765 ioc_err(mrioc, "sas io unit page1 write persistent failed\n");
5766 goto out_failed;
5767 }
5768 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5769 ioc_err(mrioc, "sas io unit page1 write persistent failed with ioc_status(0x%04x)\n",
5770 ioc_status);
5771 goto out_failed;
5772 }
5773 return 0;
5774 out_failed:
5775 return -1;
5776 }
5777
5778 /**
5779 * mpi3mr_cfg_get_driver_pg1 - Read current Driver page1
5780 * @mrioc: Adapter instance reference
5781 * @driver_pg1: Pointer to return Driver page 1
5782 * @pg_sz: Size of the memory allocated to the page pointer
5783 *
5784 * This is handler for config page read for the Driver page1.
5785 * This routine checks ioc_status to decide whether the page
5786 * read is success or not.
5787 *
5788 * Return: 0 on success, non-zero on failure.
5789 */
mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc * mrioc,struct mpi3_driver_page1 * driver_pg1,u16 pg_sz)5790 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc,
5791 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz)
5792 {
5793 struct mpi3_config_page_header cfg_hdr;
5794 struct mpi3_config_request cfg_req;
5795 u16 ioc_status = 0;
5796
5797 memset(driver_pg1, 0, pg_sz);
5798 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5799 memset(&cfg_req, 0, sizeof(cfg_req));
5800
5801 cfg_req.function = MPI3_FUNCTION_CONFIG;
5802 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5803 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DRIVER;
5804 cfg_req.page_number = 1;
5805 cfg_req.page_address = 0;
5806
5807 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5808 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5809 ioc_err(mrioc, "driver page1 header read failed\n");
5810 goto out_failed;
5811 }
5812 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5813 ioc_err(mrioc, "driver page1 header read failed with ioc_status(0x%04x)\n",
5814 ioc_status);
5815 goto out_failed;
5816 }
5817 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5818
5819 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5820 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, driver_pg1, pg_sz)) {
5821 ioc_err(mrioc, "driver page1 read failed\n");
5822 goto out_failed;
5823 }
5824 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5825 ioc_err(mrioc, "driver page1 read failed with ioc_status(0x%04x)\n",
5826 ioc_status);
5827 goto out_failed;
5828 }
5829 return 0;
5830 out_failed:
5831 return -1;
5832 }
5833
