1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 6 * Adapted for Power Macintosh by Paul Mackerras. 7 * Low-level exception handlers and MMU support 8 * rewritten by Paul Mackerras. 9 * Copyright (C) 1996 Paul Mackerras. 10 * 11 * This file contains low-level assembler routines for managing 12 * the PowerPC MMU hash table. (PPC 8xx processors don't use a 13 * hash table, so this file is not used on them.) 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License 17 * as published by the Free Software Foundation; either version 18 * 2 of the License, or (at your option) any later version. 19 * 20 */ 21 22#include <asm/reg.h> 23#include <asm/page.h> 24#include <asm/pgtable.h> 25#include <asm/cputable.h> 26#include <asm/ppc_asm.h> 27#include <asm/thread_info.h> 28#include <asm/asm-offsets.h> 29#include <asm/export.h> 30#include <asm/feature-fixups.h> 31 32#ifdef CONFIG_SMP 33 .section .bss 34 .align 2 35mmu_hash_lock: 36 .space 4 37#endif /* CONFIG_SMP */ 38 39/* 40 * Load a PTE into the hash table, if possible. 41 * The address is in r4, and r3 contains an access flag: 42 * _PAGE_RW (0x400) if a write. 43 * r9 contains the SRR1 value, from which we use the MSR_PR bit. 44 * SPRG_THREAD contains the physical address of the current task's thread. 45 * 46 * Returns to the caller if the access is illegal or there is no 47 * mapping for the address. Otherwise it places an appropriate PTE 48 * in the hash table and returns from the exception. 49 * Uses r0, r3 - r8, r10, ctr, lr. 50 */ 51 .text 52_GLOBAL(hash_page) 53 tophys(r7,0) /* gets -KERNELBASE into r7 */ 54#ifdef CONFIG_SMP 55 addis r8,r7,mmu_hash_lock@h 56 ori r8,r8,mmu_hash_lock@l 57 lis r0,0x0fff 58 b 10f 5911: lwz r6,0(r8) 60 cmpwi 0,r6,0 61 bne 11b 6210: lwarx r6,0,r8 63 cmpwi 0,r6,0 64 bne- 11b 65 stwcx. r0,0,r8 66 bne- 10b 67 isync 68#endif 69 /* Get PTE (linux-style) and check access */ 70 lis r0,KERNELBASE@h /* check if kernel address */ 71 cmplw 0,r4,r0 72 mfspr r8,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ 73 ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */ 74 lwz r5,PGDIR(r8) /* virt page-table root */ 75 blt+ 112f /* assume user more likely */ 76 lis r5,swapper_pg_dir@ha /* if kernel address, use */ 77 addi r5,r5,swapper_pg_dir@l /* kernel page table */ 78 rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */ 79112: add r5,r5,r7 /* convert to phys addr */ 80#ifndef CONFIG_PTE_64BIT 81 rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */ 82 lwz r8,0(r5) /* get pmd entry */ 83 rlwinm. r8,r8,0,0,19 /* extract address of pte page */ 84#else 85 rlwinm r8,r4,13,19,29 /* Compute pgdir/pmd offset */ 86 lwzx r8,r8,r5 /* Get L1 entry */ 87 rlwinm. r8,r8,0,0,20 /* extract pt base address */ 88#endif 89#ifdef CONFIG_SMP 90 beq- hash_page_out /* return if no mapping */ 91#else 92 /* XXX it seems like the 601 will give a machine fault on the 93 rfi if its alignment is wrong (bottom 4 bits of address are 94 8 or 0xc) and we have had a not-taken conditional branch 95 to the address following the rfi. */ 96 beqlr- 97#endif 98#ifndef CONFIG_PTE_64BIT 99 rlwimi r8,r4,22,20,29 /* insert next 10 bits of address */ 100#else 101 rlwimi r8,r4,23,20,28 /* compute pte address */ 102#endif 103 rlwinm r0,r3,32-3,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */ 104 ori r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE 105 106 /* 107 * Update the linux PTE atomically. We do the lwarx up-front 108 * because almost always, there won't be a permission violation 109 * and there won't already be an HPTE, and thus we will have 110 * to update the PTE to set _PAGE_HASHPTE. -- paulus. 111 * 112 * If PTE_64BIT is set, the low word is the flags word; use that 113 * word for locking since it contains all the interesting bits. 114 */ 115#if (PTE_FLAGS_OFFSET != 0) 116 addi r8,r8,PTE_FLAGS_OFFSET 117#endif 118retry: 119 lwarx r6,0,r8 /* get linux-style pte, flag word */ 120 andc. r5,r3,r6 /* check access & ~permission */ 121#ifdef CONFIG_SMP 122 bne- hash_page_out /* return if access not permitted */ 123#else 124 bnelr- 125#endif 126 or r5,r0,r6 /* set accessed/dirty bits */ 127#ifdef CONFIG_PTE_64BIT 128#ifdef CONFIG_SMP 129 subf r10,r6,r8 /* create false data dependency */ 130 subi r10,r10,PTE_FLAGS_OFFSET 131 lwzx r10,r6,r10 /* Get upper PTE word */ 132#else 133 lwz r10,-PTE_FLAGS_OFFSET(r8) 134#endif /* CONFIG_SMP */ 135#endif /* CONFIG_PTE_64BIT */ 136 stwcx. r5,0,r8 /* attempt to update PTE */ 137 bne- retry /* retry if someone got there first */ 138 139 mfsrin r3,r4 /* get segment reg for segment */ 140 mfctr r0 141 stw r0,_CTR(r11) 142 bl create_hpte /* add the hash table entry */ 143 144#ifdef CONFIG_SMP 145 eieio 146 addis r8,r7,mmu_hash_lock@ha 147 li r0,0 148 stw r0,mmu_hash_lock@l(r8) 149#endif 150 151 /* Return from the exception */ 152 lwz r5,_CTR(r11) 153 mtctr r5 154 lwz r0,GPR0(r11) 155 lwz r7,GPR7(r11) 156 lwz r8,GPR8(r11) 157 b fast_exception_return 158 159#ifdef CONFIG_SMP 160hash_page_out: 161 eieio 162 addis r8,r7,mmu_hash_lock@ha 163 li r0,0 164 stw r0,mmu_hash_lock@l(r8) 165 blr 166#endif /* CONFIG_SMP */ 167 168/* 169 * Add an entry for a particular page to the hash table. 170 * 171 * add_hash_page(unsigned context, unsigned long va, unsigned long pmdval) 172 * 173 * We assume any necessary modifications to the pte (e.g. setting 174 * the accessed bit) have already been done and that there is actually 175 * a hash table in use (i.e. we're not on a 603). 176 */ 177_GLOBAL(add_hash_page) 178 mflr r0 179 stw r0,4(r1) 180 181 /* Convert context and va to VSID */ 182 mulli r3,r3,897*16 /* multiply context by context skew */ 183 rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */ 184 mulli r0,r0,0x111 /* multiply by ESID skew */ 185 add r3,r3,r0 /* note create_hpte trims to 24 bits */ 186 187#ifdef CONFIG_SMP 188 CURRENT_THREAD_INFO(r8, r1) /* use cpu number to make tag */ 189 lwz r8,TI_CPU(r8) /* to go in mmu_hash_lock */ 190 oris r8,r8,12 191#endif /* CONFIG_SMP */ 192 193 /* 194 * We disable interrupts here, even on UP, because we don't 195 * want to race with hash_page, and because we want the 196 * _PAGE_HASHPTE bit to be a reliable indication of whether 197 * the HPTE exists (or at least whether one did once). 198 * We also turn off the MMU for data accesses so that we 199 * we can't take a hash table miss (assuming the code is 200 * covered by a BAT). -- paulus 201 */ 202 mfmsr r9 203 SYNC 204 rlwinm r0,r9,0,17,15 /* clear bit 16 (MSR_EE) */ 205 rlwinm r0,r0,0,28,26 /* clear MSR_DR */ 206 mtmsr r0 207 SYNC_601 208 isync 209 210 tophys(r7,0) 211 212#ifdef CONFIG_SMP 213 addis r6,r7,mmu_hash_lock@ha 214 addi r6,r6,mmu_hash_lock@l 21510: lwarx r0,0,r6 /* take the mmu_hash_lock */ 216 cmpi 0,r0,0 217 bne- 11f 218 stwcx. r8,0,r6 219 beq+ 12f 22011: lwz r0,0(r6) 221 cmpi 0,r0,0 222 beq 10b 223 b 11b 22412: isync 225#endif 226 227 /* 228 * Fetch the linux pte and test and set _PAGE_HASHPTE atomically. 229 * If _PAGE_HASHPTE was already set, we don't replace the existing 230 * HPTE, so we just unlock and return. 231 */ 232 mr r8,r5 233#ifndef CONFIG_PTE_64BIT 234 rlwimi r8,r4,22,20,29 235#else 236 rlwimi r8,r4,23,20,28 237 addi r8,r8,PTE_FLAGS_OFFSET 238#endif 2391: lwarx r6,0,r8 240 andi. r0,r6,_PAGE_HASHPTE 241 bne 9f /* if HASHPTE already set, done */ 242#ifdef CONFIG_PTE_64BIT 243#ifdef CONFIG_SMP 244 subf r10,r6,r8 /* create false data dependency */ 245 subi r10,r10,PTE_FLAGS_OFFSET 246 lwzx r10,r6,r10 /* Get upper PTE word */ 247#else 248 lwz r10,-PTE_FLAGS_OFFSET(r8) 249#endif /* CONFIG_SMP */ 250#endif /* CONFIG_PTE_64BIT */ 251 ori r5,r6,_PAGE_HASHPTE 252 stwcx. r5,0,r8 253 bne- 1b 254 255 bl create_hpte 256 2579: 258#ifdef CONFIG_SMP 259 addis r6,r7,mmu_hash_lock@ha 260 addi r6,r6,mmu_hash_lock@l 261 eieio 262 li r0,0 263 stw r0,0(r6) /* clear mmu_hash_lock */ 264#endif 265 266 /* reenable interrupts and DR */ 267 mtmsr r9 268 SYNC_601 269 isync 270 271 lwz r0,4(r1) 272 mtlr r0 273 blr 274 275/* 276 * This routine adds a hardware PTE to the hash table. 277 * It is designed to be called with the MMU either on or off. 278 * r3 contains the VSID, r4 contains the virtual address, 279 * r5 contains the linux PTE, r6 contains the old value of the 280 * linux PTE (before setting _PAGE_HASHPTE) and r7 contains the 281 * offset to be added to addresses (0 if the MMU is on, 282 * -KERNELBASE if it is off). r10 contains the upper half of 283 * the PTE if CONFIG_PTE_64BIT. 284 * On SMP, the caller should have the mmu_hash_lock held. 285 * We assume that the caller has (or will) set the _PAGE_HASHPTE 286 * bit in the linux PTE in memory. The value passed in r6 should 287 * be the old linux PTE value; if it doesn't have _PAGE_HASHPTE set 288 * this routine will skip the search for an existing HPTE. 289 * This procedure modifies r0, r3 - r6, r8, cr0. 290 * -- paulus. 291 * 292 * For speed, 4 of the instructions get patched once the size and 293 * physical address of the hash table are known. These definitions 294 * of Hash_base and Hash_bits below are just an example. 295 */ 296Hash_base = 0xc0180000 297Hash_bits = 12 /* e.g. 256kB hash table */ 298Hash_msk = (((1 << Hash_bits) - 1) * 64) 299 300/* defines for the PTE format for 32-bit PPCs */ 301#define HPTE_SIZE 8 302#define PTEG_SIZE 64 303#define LG_PTEG_SIZE 6 304#define LDPTEu lwzu 305#define LDPTE lwz 306#define STPTE stw 307#define CMPPTE cmpw 308#define PTE_H 0x40 309#define PTE_V 0x80000000 310#define TST_V(r) rlwinm. r,r,0,0,0 311#define SET_V(r) oris r,r,PTE_V@h 312#define CLR_V(r,t) rlwinm r,r,0,1,31 313 314#define HASH_LEFT 31-(LG_PTEG_SIZE+Hash_bits-1) 315#define HASH_RIGHT 31-LG_PTEG_SIZE 316 317_GLOBAL(create_hpte) 318 /* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */ 319 rlwinm r8,r5,32-10,31,31 /* _PAGE_RW -> PP lsb */ 320 rlwinm r0,r5,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */ 321 and r8,r8,r0 /* writable if _RW & _DIRTY */ 322 rlwimi r5,r5,32-1,30,30 /* _PAGE_USER -> PP msb */ 323 rlwimi r5,r5,32-2,31,31 /* _PAGE_USER -> PP lsb */ 324 ori r8,r8,0xe04 /* clear out reserved bits */ 325 andc r8,r5,r8 /* PP = user? (rw&dirty? 2: 3): 0 */ 326BEGIN_FTR_SECTION 327 rlwinm r8,r8,0,~_PAGE_COHERENT /* clear M (coherence not required) */ 328END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT) 329#ifdef CONFIG_PTE_64BIT 330 /* Put the XPN bits into the PTE */ 331 rlwimi r8,r10,8,20,22 332 rlwimi r8,r10,2,29,29 333#endif 334 335 /* Construct the high word of the PPC-style PTE (r5) */ 336 rlwinm r5,r3,7,1,24 /* put VSID in 0x7fffff80 bits */ 337 rlwimi r5,r4,10,26,31 /* put in API (abbrev page index) */ 338 SET_V(r5) /* set V (valid) bit */ 339 340 /* Get the address of the primary PTE group in the hash table (r3) */ 341_GLOBAL(hash_page_patch_A) 342 addis r0,r7,Hash_base@h /* base address of hash table */ 343 rlwimi r0,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */ 344 rlwinm r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */ 345 xor r3,r3,r0 /* make primary hash */ 346 li r0,8 /* PTEs/group */ 347 348 /* 349 * Test the _PAGE_HASHPTE bit in the old linux PTE, and skip the search 350 * if it is clear, meaning that the HPTE isn't there already... 351 */ 352 andi. r6,r6,_PAGE_HASHPTE 353 beq+ 10f /* no PTE: go look for an empty slot */ 354 tlbie r4 355 356 addis r4,r7,htab_hash_searches@ha 357 lwz r6,htab_hash_searches@l(r4) 358 addi r6,r6,1 /* count how many searches we do */ 359 stw r6,htab_hash_searches@l(r4) 360 361 /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */ 362 mtctr r0 363 addi r4,r3,-HPTE_SIZE 3641: LDPTEu r6,HPTE_SIZE(r4) /* get next PTE */ 365 CMPPTE 0,r6,r5 366 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ 367 beq+ found_slot 368 369 /* Search the secondary PTEG for a matching PTE */ 370 ori r5,r5,PTE_H /* set H (secondary hash) bit */ 371_GLOBAL(hash_page_patch_B) 372 xoris r4,r3,Hash_msk>>16 /* compute secondary hash */ 373 xori r4,r4,(-PTEG_SIZE & 0xffff) 374 addi r4,r4,-HPTE_SIZE 375 mtctr r0 3762: LDPTEu r6,HPTE_SIZE(r4) 377 CMPPTE 0,r6,r5 378 bdnzf 2,2b 379 beq+ found_slot 380 xori r5,r5,PTE_H /* clear H bit again */ 381 382 /* Search the primary PTEG for an empty slot */ 38310: mtctr r0 384 addi r4,r3,-HPTE_SIZE /* search primary PTEG */ 3851: LDPTEu r6,HPTE_SIZE(r4) /* get next PTE */ 386 TST_V(r6) /* test valid bit */ 387 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ 388 beq+ found_empty 389 390 /* update counter of times that the primary PTEG is full */ 391 addis r4,r7,primary_pteg_full@ha 392 lwz r6,primary_pteg_full@l(r4) 393 addi r6,r6,1 394 stw r6,primary_pteg_full@l(r4) 395 396 /* Search the secondary PTEG for an empty slot */ 397 ori r5,r5,PTE_H /* set H (secondary hash) bit */ 398_GLOBAL(hash_page_patch_C) 399 xoris r4,r3,Hash_msk>>16 /* compute secondary hash */ 400 xori r4,r4,(-PTEG_SIZE & 0xffff) 401 addi r4,r4,-HPTE_SIZE 402 mtctr r0 4032: LDPTEu r6,HPTE_SIZE(r4) 404 TST_V(r6) 405 bdnzf 2,2b 406 beq+ found_empty 407 xori r5,r5,PTE_H /* clear H bit again */ 408 409 /* 410 * Choose an arbitrary slot in the primary PTEG to overwrite. 411 * Since both the primary and secondary PTEGs are full, and we 412 * have no information that the PTEs in the primary PTEG are 413 * more important or useful than those in the secondary PTEG, 414 * and we know there is a definite (although small) speed 415 * advantage to putting the PTE in the primary PTEG, we always 416 * put the PTE in the primary PTEG. 417 * 418 * In addition, we skip any slot that is mapping kernel text in 419 * order to avoid a deadlock when not using BAT mappings if 420 * trying to hash in the kernel hash code itself after it has 421 * already taken the hash table lock. This works in conjunction 422 * with pre-faulting of the kernel text. 423 * 424 * If the hash table bucket is full of kernel text entries, we'll 425 * lockup here but that shouldn't happen 426 */ 427 4281: addis r4,r7,next_slot@ha /* get next evict slot */ 429 lwz r6,next_slot@l(r4) 430 addi r6,r6,HPTE_SIZE /* search for candidate */ 431 andi. r6,r6,7*HPTE_SIZE 432 stw r6,next_slot@l(r4) 433 add r4,r3,r6 434 LDPTE r0,HPTE_SIZE/2(r4) /* get PTE second word */ 435 clrrwi r0,r0,12 436 lis r6,etext@h 437 ori r6,r6,etext@l /* get etext */ 438 tophys(r6,r6) 439 cmpl cr0,r0,r6 /* compare and try again */ 440 blt 1b 441 442#ifndef CONFIG_SMP 443 /* Store PTE in PTEG */ 444found_empty: 445 STPTE r5,0(r4) 446found_slot: 447 STPTE r8,HPTE_SIZE/2(r4) 448 449#else /* CONFIG_SMP */ 450/* 451 * Between the tlbie above and updating the hash table entry below, 452 * another CPU could read the hash table entry and put it in its TLB. 453 * There are 3 cases: 454 * 1. using an empty slot 455 * 2. updating an earlier entry to change permissions (i.e. enable write) 456 * 3. taking over the PTE for an unrelated address 457 * 458 * In each case it doesn't really matter if the other CPUs have the old 459 * PTE in their TLB. So we don't need to bother with another tlbie here, 460 * which is convenient as we've overwritten the register that had the 461 * address. :-) The tlbie above is mainly to make sure that this CPU comes 462 * and gets the new PTE from the hash table. 463 * 464 * We do however have to make sure that the PTE is never in an invalid 465 * state with the V bit set. 466 */ 467found_empty: 468found_slot: 469 CLR_V(r5,r0) /* clear V (valid) bit in PTE */ 470 STPTE r5,0(r4) 471 sync 472 TLBSYNC 473 STPTE r8,HPTE_SIZE/2(r4) /* put in correct RPN, WIMG, PP bits */ 474 sync 475 SET_V(r5) 476 STPTE r5,0(r4) /* finally set V bit in PTE */ 477#endif /* CONFIG_SMP */ 478 479 sync /* make sure pte updates get to memory */ 480 blr 481 482 .section .bss 483 .align 2 484next_slot: 485 .space 4 486primary_pteg_full: 487 .space 4 488htab_hash_searches: 489 .space 4 490 .previous 491 492/* 493 * Flush the entry for a particular page from the hash table. 494 * 495 * flush_hash_pages(unsigned context, unsigned long va, unsigned long pmdval, 496 * int count) 497 * 498 * We assume that there is a hash table in use (Hash != 0). 499 */ 500_GLOBAL(flush_hash_pages) 501 tophys(r7,0) 502 503 /* 504 * We disable interrupts here, even on UP, because we want 505 * the _PAGE_HASHPTE bit to be a reliable indication of 506 * whether the HPTE exists (or at least whether one did once). 507 * We also turn off the MMU for data accesses so that we 508 * we can't take a hash table miss (assuming the code is 509 * covered by a BAT). -- paulus 510 */ 511 mfmsr r10 512 SYNC 513 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ 514 rlwinm r0,r0,0,28,26 /* clear MSR_DR */ 515 mtmsr r0 516 SYNC_601 517 isync 518 519 /* First find a PTE in the range that has _PAGE_HASHPTE set */ 520#ifndef CONFIG_PTE_64BIT 521 rlwimi r5,r4,22,20,29 522#else 523 rlwimi r5,r4,23,20,28 524#endif 5251: lwz r0,PTE_FLAGS_OFFSET(r5) 526 cmpwi cr1,r6,1 527 andi. r0,r0,_PAGE_HASHPTE 528 bne 2f 529 ble cr1,19f 530 addi r4,r4,0x1000 531 addi r5,r5,PTE_SIZE 532 addi r6,r6,-1 533 b 1b 534 535 /* Convert context and va to VSID */ 5362: mulli r3,r3,897*16 /* multiply context by context skew */ 537 rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */ 538 mulli r0,r0,0x111 /* multiply by ESID skew */ 539 add r3,r3,r0 /* note code below trims to 24 bits */ 540 541 /* Construct the high word of the PPC-style PTE (r11) */ 542 rlwinm r11,r3,7,1,24 /* put VSID in 0x7fffff80 bits */ 543 rlwimi r11,r4,10,26,31 /* put in API (abbrev page index) */ 544 SET_V(r11) /* set V (valid) bit */ 545 546#ifdef CONFIG_SMP 547 addis r9,r7,mmu_hash_lock@ha 548 addi r9,r9,mmu_hash_lock@l 549 CURRENT_THREAD_INFO(r8, r1) 550 add r8,r8,r7 551 lwz r8,TI_CPU(r8) 552 oris r8,r8,9 55310: lwarx r0,0,r9 554 cmpi 0,r0,0 555 bne- 11f 556 stwcx. r8,0,r9 557 beq+ 12f 55811: lwz r0,0(r9) 559 cmpi 0,r0,0 560 beq 10b 561 b 11b 56212: isync 563#endif 564 565 /* 566 * Check the _PAGE_HASHPTE bit in the linux PTE. If it is 567 * already clear, we're done (for this pte). If not, 568 * clear it (atomically) and proceed. -- paulus. 569 */ 570#if (PTE_FLAGS_OFFSET != 0) 571 addi r5,r5,PTE_FLAGS_OFFSET 572#endif 57333: lwarx r8,0,r5 /* fetch the pte flags word */ 574 andi. r0,r8,_PAGE_HASHPTE 575 beq 8f /* done if HASHPTE is already clear */ 576 rlwinm r8,r8,0,31,29 /* clear HASHPTE bit */ 577 stwcx. r8,0,r5 /* update the pte */ 578 bne- 33b 579 580 /* Get the address of the primary PTE group in the hash table (r3) */ 581_GLOBAL(flush_hash_patch_A) 582 addis r8,r7,Hash_base@h /* base address of hash table */ 583 rlwimi r8,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */ 584 rlwinm r0,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */ 585 xor r8,r0,r8 /* make primary hash */ 586 587 /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */ 588 li r0,8 /* PTEs/group */ 589 mtctr r0 590 addi r12,r8,-HPTE_SIZE 5911: LDPTEu r0,HPTE_SIZE(r12) /* get next PTE */ 592 CMPPTE 0,r0,r11 593 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ 594 beq+ 3f 595 596 /* Search the secondary PTEG for a matching PTE */ 597 ori r11,r11,PTE_H /* set H (secondary hash) bit */ 598 li r0,8 /* PTEs/group */ 599_GLOBAL(flush_hash_patch_B) 600 xoris r12,r8,Hash_msk>>16 /* compute secondary hash */ 601 xori r12,r12,(-PTEG_SIZE & 0xffff) 602 addi r12,r12,-HPTE_SIZE 603 mtctr r0 6042: LDPTEu r0,HPTE_SIZE(r12) 605 CMPPTE 0,r0,r11 606 bdnzf 2,2b 607 xori r11,r11,PTE_H /* clear H again */ 608 bne- 4f /* should rarely fail to find it */ 609 6103: li r0,0 611 STPTE r0,0(r12) /* invalidate entry */ 6124: sync 613 tlbie r4 /* in hw tlb too */ 614 sync 615 6168: ble cr1,9f /* if all ptes checked */ 61781: addi r6,r6,-1 618 addi r5,r5,PTE_SIZE 619 addi r4,r4,0x1000 620 lwz r0,0(r5) /* check next pte */ 621 cmpwi cr1,r6,1 622 andi. r0,r0,_PAGE_HASHPTE 623 bne 33b 624 bgt cr1,81b 625 6269: 627#ifdef CONFIG_SMP 628 TLBSYNC 629 li r0,0 630 stw r0,0(r9) /* clear mmu_hash_lock */ 631#endif 632 63319: mtmsr r10 634 SYNC_601 635 isync 636 blr 637EXPORT_SYMBOL(flush_hash_pages) 638 639/* 640 * Flush an entry from the TLB 641 */ 642_GLOBAL(_tlbie) 643#ifdef CONFIG_SMP 644 CURRENT_THREAD_INFO(r8, r1) 645 lwz r8,TI_CPU(r8) 646 oris r8,r8,11 647 mfmsr r10 648 SYNC 649 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ 650 rlwinm r0,r0,0,28,26 /* clear DR */ 651 mtmsr r0 652 SYNC_601 653 isync 654 lis r9,mmu_hash_lock@h 655 ori r9,r9,mmu_hash_lock@l 656 tophys(r9,r9) 65710: lwarx r7,0,r9 658 cmpwi 0,r7,0 659 bne- 10b 660 stwcx. r8,0,r9 661 bne- 10b 662 eieio 663 tlbie r3 664 sync 665 TLBSYNC 666 li r0,0 667 stw r0,0(r9) /* clear mmu_hash_lock */ 668 mtmsr r10 669 SYNC_601 670 isync 671#else /* CONFIG_SMP */ 672 tlbie r3 673 sync 674#endif /* CONFIG_SMP */ 675 blr 676 677/* 678 * Flush the entire TLB. 603/603e only 679 */ 680_GLOBAL(_tlbia) 681#if defined(CONFIG_SMP) 682 CURRENT_THREAD_INFO(r8, r1) 683 lwz r8,TI_CPU(r8) 684 oris r8,r8,10 685 mfmsr r10 686 SYNC 687 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ 688 rlwinm r0,r0,0,28,26 /* clear DR */ 689 mtmsr r0 690 SYNC_601 691 isync 692 lis r9,mmu_hash_lock@h 693 ori r9,r9,mmu_hash_lock@l 694 tophys(r9,r9) 69510: lwarx r7,0,r9 696 cmpwi 0,r7,0 697 bne- 10b 698 stwcx. r8,0,r9 699 bne- 10b 700 sync 701 tlbia 702 sync 703 TLBSYNC 704 li r0,0 705 stw r0,0(r9) /* clear mmu_hash_lock */ 706 mtmsr r10 707 SYNC_601 708 isync 709#else /* CONFIG_SMP */ 710 sync 711 tlbia 712 sync 713#endif /* CONFIG_SMP */ 714 blr 715
