1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
4 * {mikejc|engebret}@us.ibm.com
5 *
6 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 *
8 * SMP scalability work:
9 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
10 *
11 * Module name: htab.c
12 *
13 * Description:
14 * PowerPC Hashed Page Table functions
15 */
16
17 #undef DEBUG
18 #undef DEBUG_LOW
19
20 #define pr_fmt(fmt) "hash-mmu: " fmt
21 #include <linux/spinlock.h>
22 #include <linux/errno.h>
23 #include <linux/sched/mm.h>
24 #include <linux/proc_fs.h>
25 #include <linux/stat.h>
26 #include <linux/sysctl.h>
27 #include <linux/export.h>
28 #include <linux/ctype.h>
29 #include <linux/cache.h>
30 #include <linux/init.h>
31 #include <linux/signal.h>
32 #include <linux/memblock.h>
33 #include <linux/context_tracking.h>
34 #include <linux/libfdt.h>
35 #include <linux/pkeys.h>
36 #include <linux/hugetlb.h>
37 #include <linux/cpu.h>
38
39 #include <asm/debugfs.h>
40 #include <asm/processor.h>
41 #include <asm/pgtable.h>
42 #include <asm/mmu.h>
43 #include <asm/mmu_context.h>
44 #include <asm/page.h>
45 #include <asm/types.h>
46 #include <linux/uaccess.h>
47 #include <asm/machdep.h>
48 #include <asm/prom.h>
49 #include <asm/io.h>
50 #include <asm/eeh.h>
51 #include <asm/tlb.h>
52 #include <asm/cacheflush.h>
53 #include <asm/cputable.h>
54 #include <asm/sections.h>
55 #include <asm/copro.h>
56 #include <asm/udbg.h>
57 #include <asm/code-patching.h>
58 #include <asm/fadump.h>
59 #include <asm/firmware.h>
60 #include <asm/tm.h>
61 #include <asm/trace.h>
62 #include <asm/ps3.h>
63 #include <asm/pte-walk.h>
64 #include <asm/asm-prototypes.h>
65 #include <asm/ultravisor.h>
66
67 #include <mm/mmu_decl.h>
68
69 #ifdef DEBUG
70 #define DBG(fmt...) udbg_printf(fmt)
71 #else
72 #define DBG(fmt...)
73 #endif
74
75 #ifdef DEBUG_LOW
76 #define DBG_LOW(fmt...) udbg_printf(fmt)
77 #else
78 #define DBG_LOW(fmt...)
79 #endif
80
81 #define KB (1024)
82 #define MB (1024*KB)
83 #define GB (1024L*MB)
84
85 /*
86 * Note: pte --> Linux PTE
87 * HPTE --> PowerPC Hashed Page Table Entry
88 *
89 * Execution context:
90 * htab_initialize is called with the MMU off (of course), but
91 * the kernel has been copied down to zero so it can directly
92 * reference global data. At this point it is very difficult
93 * to print debug info.
94 *
95 */
96
97 static unsigned long _SDR1;
98 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
99 EXPORT_SYMBOL_GPL(mmu_psize_defs);
100
101 u8 hpte_page_sizes[1 << LP_BITS];
102 EXPORT_SYMBOL_GPL(hpte_page_sizes);
103
104 struct hash_pte *htab_address;
105 unsigned long htab_size_bytes;
106 unsigned long htab_hash_mask;
107 EXPORT_SYMBOL_GPL(htab_hash_mask);
108 int mmu_linear_psize = MMU_PAGE_4K;
109 EXPORT_SYMBOL_GPL(mmu_linear_psize);
110 int mmu_virtual_psize = MMU_PAGE_4K;
111 int mmu_vmalloc_psize = MMU_PAGE_4K;
112 #ifdef CONFIG_SPARSEMEM_VMEMMAP
113 int mmu_vmemmap_psize = MMU_PAGE_4K;
114 #endif
115 int mmu_io_psize = MMU_PAGE_4K;
116 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
117 EXPORT_SYMBOL_GPL(mmu_kernel_ssize);
118 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
119 u16 mmu_slb_size = 64;
120 EXPORT_SYMBOL_GPL(mmu_slb_size);
121 #ifdef CONFIG_PPC_64K_PAGES
122 int mmu_ci_restrictions;
123 #endif
124 #ifdef CONFIG_DEBUG_PAGEALLOC
125 static u8 *linear_map_hash_slots;
126 static unsigned long linear_map_hash_count;
127 static DEFINE_SPINLOCK(linear_map_hash_lock);
128 #endif /* CONFIG_DEBUG_PAGEALLOC */
129 struct mmu_hash_ops mmu_hash_ops;
130 EXPORT_SYMBOL(mmu_hash_ops);
131
132 /*
133 * These are definitions of page sizes arrays to be used when none
134 * is provided by the firmware.
135 */
136
137 /*
138 * Fallback (4k pages only)
139 */
140 static struct mmu_psize_def mmu_psize_defaults[] = {
141 [MMU_PAGE_4K] = {
142 .shift = 12,
143 .sllp = 0,
144 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
145 .avpnm = 0,
146 .tlbiel = 0,
147 },
148 };
149
150 /*
151 * POWER4, GPUL, POWER5
152 *
153 * Support for 16Mb large pages
154 */
155 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
156 [MMU_PAGE_4K] = {
157 .shift = 12,
158 .sllp = 0,
159 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
160 .avpnm = 0,
161 .tlbiel = 1,
162 },
163 [MMU_PAGE_16M] = {
164 .shift = 24,
165 .sllp = SLB_VSID_L,
166 .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
167 [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
168 .avpnm = 0x1UL,
169 .tlbiel = 0,
170 },
171 };
172
173 /*
174 * 'R' and 'C' update notes:
175 * - Under pHyp or KVM, the updatepp path will not set C, thus it *will*
176 * create writeable HPTEs without C set, because the hcall H_PROTECT
177 * that we use in that case will not update C
178 * - The above is however not a problem, because we also don't do that
179 * fancy "no flush" variant of eviction and we use H_REMOVE which will
180 * do the right thing and thus we don't have the race I described earlier
181 *
182 * - Under bare metal, we do have the race, so we need R and C set
183 * - We make sure R is always set and never lost
184 * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping
185 */
htab_convert_pte_flags(unsigned long pteflags)186 unsigned long htab_convert_pte_flags(unsigned long pteflags)
187 {
188 unsigned long rflags = 0;
189
190 /* _PAGE_EXEC -> NOEXEC */
191 if ((pteflags & _PAGE_EXEC) == 0)
192 rflags |= HPTE_R_N;
193 /*
194 * PPP bits:
195 * Linux uses slb key 0 for kernel and 1 for user.
196 * kernel RW areas are mapped with PPP=0b000
197 * User area is mapped with PPP=0b010 for read/write
198 * or PPP=0b011 for read-only (including writeable but clean pages).
199 */
200 if (pteflags & _PAGE_PRIVILEGED) {
201 /*
202 * Kernel read only mapped with ppp bits 0b110
203 */
204 if (!(pteflags & _PAGE_WRITE)) {
205 if (mmu_has_feature(MMU_FTR_KERNEL_RO))
206 rflags |= (HPTE_R_PP0 | 0x2);
207 else
208 rflags |= 0x3;
209 }
210 } else {
211 if (pteflags & _PAGE_RWX)
212 rflags |= 0x2;
213 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY)))
214 rflags |= 0x1;
215 }
216 /*
217 * We can't allow hardware to update hpte bits. Hence always
218 * set 'R' bit and set 'C' if it is a write fault
219 */
220 rflags |= HPTE_R_R;
221
222 if (pteflags & _PAGE_DIRTY)
223 rflags |= HPTE_R_C;
224 /*
225 * Add in WIG bits
226 */
227
228 if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT)
229 rflags |= HPTE_R_I;
230 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)
231 rflags |= (HPTE_R_I | HPTE_R_G);
232 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
233 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M);
234 else
235 /*
236 * Add memory coherence if cache inhibited is not set
237 */
238 rflags |= HPTE_R_M;
239
240 rflags |= pte_to_hpte_pkey_bits(pteflags);
241 return rflags;
242 }
243
htab_bolt_mapping(unsigned long vstart,unsigned long vend,unsigned long pstart,unsigned long prot,int psize,int ssize)244 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
245 unsigned long pstart, unsigned long prot,
246 int psize, int ssize)
247 {
248 unsigned long vaddr, paddr;
249 unsigned int step, shift;
250 int ret = 0;
251
252 shift = mmu_psize_defs[psize].shift;
253 step = 1 << shift;
254
255 prot = htab_convert_pte_flags(prot);
256
257 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
258 vstart, vend, pstart, prot, psize, ssize);
259
260 for (vaddr = vstart, paddr = pstart; vaddr < vend;
261 vaddr += step, paddr += step) {
262 unsigned long hash, hpteg;
263 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
264 unsigned long vpn = hpt_vpn(vaddr, vsid, ssize);
265 unsigned long tprot = prot;
266
267 /*
268 * If we hit a bad address return error.
269 */
270 if (!vsid)
271 return -1;
272 /* Make kernel text executable */
273 if (overlaps_kernel_text(vaddr, vaddr + step))
274 tprot &= ~HPTE_R_N;
275
276 /*
277 * If relocatable, check if it overlaps interrupt vectors that
278 * are copied down to real 0. For relocatable kernel
279 * (e.g. kdump case) we copy interrupt vectors down to real
280 * address 0. Mark that region as executable. This is
281 * because on p8 system with relocation on exception feature
282 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
283 * in order to execute the interrupt handlers in virtual
284 * mode the vector region need to be marked as executable.
285 */
286 if ((PHYSICAL_START > MEMORY_START) &&
287 overlaps_interrupt_vector_text(vaddr, vaddr + step))
288 tprot &= ~HPTE_R_N;
289
290 hash = hpt_hash(vpn, shift, ssize);
291 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
292
293 BUG_ON(!mmu_hash_ops.hpte_insert);
294 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
295 HPTE_V_BOLTED, psize, psize,
296 ssize);
297
298 if (ret < 0)
299 break;
300
301 #ifdef CONFIG_DEBUG_PAGEALLOC
302 if (debug_pagealloc_enabled() &&
303 (paddr >> PAGE_SHIFT) < linear_map_hash_count)
304 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
305 #endif /* CONFIG_DEBUG_PAGEALLOC */
306 }
307 return ret < 0 ? ret : 0;
308 }
309
htab_remove_mapping(unsigned long vstart,unsigned long vend,int psize,int ssize)310 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
311 int psize, int ssize)
312 {
313 unsigned long vaddr;
314 unsigned int step, shift;
315 int rc;
316 int ret = 0;
317
318 shift = mmu_psize_defs[psize].shift;
319 step = 1 << shift;
320
321 if (!mmu_hash_ops.hpte_removebolted)
322 return -ENODEV;
323
324 for (vaddr = vstart; vaddr < vend; vaddr += step) {
325 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize);
326 if (rc == -ENOENT) {
327 ret = -ENOENT;
328 continue;
329 }
330 if (rc < 0)
331 return rc;
332 }
333
334 return ret;
335 }
336
337 static bool disable_1tb_segments = false;
338
parse_disable_1tb_segments(char * p)339 static int __init parse_disable_1tb_segments(char *p)
340 {
341 disable_1tb_segments = true;
342 return 0;
343 }
344 early_param("disable_1tb_segments", parse_disable_1tb_segments);
345
htab_dt_scan_seg_sizes(unsigned long node,const char * uname,int depth,void * data)346 static int __init htab_dt_scan_seg_sizes(unsigned long node,
347 const char *uname, int depth,
348 void *data)
349 {
350 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
351 const __be32 *prop;
352 int size = 0;
353
354 /* We are scanning "cpu" nodes only */
355 if (type == NULL || strcmp(type, "cpu") != 0)
356 return 0;
357
358 prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
359 if (prop == NULL)
360 return 0;
361 for (; size >= 4; size -= 4, ++prop) {
362 if (be32_to_cpu(prop[0]) == 40) {
363 DBG("1T segment support detected\n");
364
365 if (disable_1tb_segments) {
366 DBG("1T segments disabled by command line\n");
367 break;
368 }
369
370 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
371 return 1;
372 }
373 }
374 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
375 return 0;
376 }
377
get_idx_from_shift(unsigned int shift)378 static int __init get_idx_from_shift(unsigned int shift)
379 {
380 int idx = -1;
381
382 switch (shift) {
383 case 0xc:
384 idx = MMU_PAGE_4K;
385 break;
386 case 0x10:
387 idx = MMU_PAGE_64K;
388 break;
389 case 0x14:
390 idx = MMU_PAGE_1M;
391 break;
392 case 0x18:
393 idx = MMU_PAGE_16M;
394 break;
395 case 0x22:
396 idx = MMU_PAGE_16G;
397 break;
398 }
399 return idx;
400 }
401
htab_dt_scan_page_sizes(unsigned long node,const char * uname,int depth,void * data)402 static int __init htab_dt_scan_page_sizes(unsigned long node,
403 const char *uname, int depth,
404 void *data)
405 {
406 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
407 const __be32 *prop;
408 int size = 0;
409
410 /* We are scanning "cpu" nodes only */
411 if (type == NULL || strcmp(type, "cpu") != 0)
412 return 0;
413
414 prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
415 if (!prop)
416 return 0;
417
418 pr_info("Page sizes from device-tree:\n");
419 size /= 4;
420 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
421 while(size > 0) {
422 unsigned int base_shift = be32_to_cpu(prop[0]);
423 unsigned int slbenc = be32_to_cpu(prop[1]);
424 unsigned int lpnum = be32_to_cpu(prop[2]);
425 struct mmu_psize_def *def;
426 int idx, base_idx;
427
428 size -= 3; prop += 3;
429 base_idx = get_idx_from_shift(base_shift);
430 if (base_idx < 0) {
431 /* skip the pte encoding also */
432 prop += lpnum * 2; size -= lpnum * 2;
433 continue;
434 }
435 def = &mmu_psize_defs[base_idx];
436 if (base_idx == MMU_PAGE_16M)
437 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
438
439 def->shift = base_shift;
440 if (base_shift <= 23)
441 def->avpnm = 0;
442 else
443 def->avpnm = (1 << (base_shift - 23)) - 1;
444 def->sllp = slbenc;
445 /*
446 * We don't know for sure what's up with tlbiel, so
447 * for now we only set it for 4K and 64K pages
448 */
449 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
450 def->tlbiel = 1;
451 else
452 def->tlbiel = 0;
453
454 while (size > 0 && lpnum) {
455 unsigned int shift = be32_to_cpu(prop[0]);
456 int penc = be32_to_cpu(prop[1]);
457
458 prop += 2; size -= 2;
459 lpnum--;
460
461 idx = get_idx_from_shift(shift);
462 if (idx < 0)
463 continue;
464
465 if (penc == -1)
466 pr_err("Invalid penc for base_shift=%d "
467 "shift=%d\n", base_shift, shift);
468
469 def->penc[idx] = penc;
470 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
471 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
472 base_shift, shift, def->sllp,
473 def->avpnm, def->tlbiel, def->penc[idx]);
474 }
475 }
476
477 return 1;
478 }
479
480 #ifdef CONFIG_HUGETLB_PAGE
481 /*
482 * Scan for 16G memory blocks that have been set aside for huge pages
483 * and reserve those blocks for 16G huge pages.
484 */
htab_dt_scan_hugepage_blocks(unsigned long node,const char * uname,int depth,void * data)485 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
486 const char *uname, int depth,
487 void *data) {
488 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
489 const __be64 *addr_prop;
490 const __be32 *page_count_prop;
491 unsigned int expected_pages;
492 long unsigned int phys_addr;
493 long unsigned int block_size;
494
495 /* We are scanning "memory" nodes only */
496 if (type == NULL || strcmp(type, "memory") != 0)
497 return 0;
498
499 /*
500 * This property is the log base 2 of the number of virtual pages that
501 * will represent this memory block.
502 */
503 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
504 if (page_count_prop == NULL)
505 return 0;
506 expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
507 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
508 if (addr_prop == NULL)
509 return 0;
510 phys_addr = be64_to_cpu(addr_prop[0]);
511 block_size = be64_to_cpu(addr_prop[1]);
512 if (block_size != (16 * GB))
513 return 0;
514 printk(KERN_INFO "Huge page(16GB) memory: "
515 "addr = 0x%lX size = 0x%lX pages = %d\n",
516 phys_addr, block_size, expected_pages);
517 if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) {
518 memblock_reserve(phys_addr, block_size * expected_pages);
519 pseries_add_gpage(phys_addr, block_size, expected_pages);
520 }
521 return 0;
522 }
523 #endif /* CONFIG_HUGETLB_PAGE */
524
mmu_psize_set_default_penc(void)525 static void mmu_psize_set_default_penc(void)
526 {
527 int bpsize, apsize;
528 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
529 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
530 mmu_psize_defs[bpsize].penc[apsize] = -1;
531 }
532
533 #ifdef CONFIG_PPC_64K_PAGES
534
might_have_hea(void)535 static bool might_have_hea(void)
536 {
537 /*
538 * The HEA ethernet adapter requires awareness of the
539 * GX bus. Without that awareness we can easily assume
540 * we will never see an HEA ethernet device.
541 */
542 #ifdef CONFIG_IBMEBUS
543 return !cpu_has_feature(CPU_FTR_ARCH_207S) &&
544 firmware_has_feature(FW_FEATURE_SPLPAR);
545 #else
546 return false;
547 #endif
548 }
549
550 #endif /* #ifdef CONFIG_PPC_64K_PAGES */
551
htab_scan_page_sizes(void)552 static void __init htab_scan_page_sizes(void)
553 {
554 int rc;
555
556 /* se the invalid penc to -1 */
557 mmu_psize_set_default_penc();
558
559 /* Default to 4K pages only */
560 memcpy(mmu_psize_defs, mmu_psize_defaults,
561 sizeof(mmu_psize_defaults));
562
563 /*
564 * Try to find the available page sizes in the device-tree
565 */
566 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
567 if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) {
568 /*
569 * Nothing in the device-tree, but the CPU supports 16M pages,
570 * so let's fallback on a known size list for 16M capable CPUs.
571 */
572 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
573 sizeof(mmu_psize_defaults_gp));
574 }
575
576 #ifdef CONFIG_HUGETLB_PAGE
577 if (!hugetlb_disabled) {
578 /* Reserve 16G huge page memory sections for huge pages */
579 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
580 }
581 #endif /* CONFIG_HUGETLB_PAGE */
582 }
583
584 /*
585 * Fill in the hpte_page_sizes[] array.
586 * We go through the mmu_psize_defs[] array looking for all the
587 * supported base/actual page size combinations. Each combination
588 * has a unique pagesize encoding (penc) value in the low bits of
589 * the LP field of the HPTE. For actual page sizes less than 1MB,
590 * some of the upper LP bits are used for RPN bits, meaning that
591 * we need to fill in several entries in hpte_page_sizes[].
592 *
593 * In diagrammatic form, with r = RPN bits and z = page size bits:
594 * PTE LP actual page size
595 * rrrr rrrz >=8KB
596 * rrrr rrzz >=16KB
597 * rrrr rzzz >=32KB
598 * rrrr zzzz >=64KB
599 * ...
600 *
601 * The zzzz bits are implementation-specific but are chosen so that
602 * no encoding for a larger page size uses the same value in its
603 * low-order N bits as the encoding for the 2^(12+N) byte page size
604 * (if it exists).
605 */
init_hpte_page_sizes(void)606 static void init_hpte_page_sizes(void)
607 {
608 long int ap, bp;
609 long int shift, penc;
610
611 for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) {
612 if (!mmu_psize_defs[bp].shift)
613 continue; /* not a supported page size */
614 for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) {
615 penc = mmu_psize_defs[bp].penc[ap];
616 if (penc == -1 || !mmu_psize_defs[ap].shift)
617 continue;
618 shift = mmu_psize_defs[ap].shift - LP_SHIFT;
619 if (shift <= 0)
620 continue; /* should never happen */
621 /*
622 * For page sizes less than 1MB, this loop
623 * replicates the entry for all possible values
624 * of the rrrr bits.
625 */
626 while (penc < (1 << LP_BITS)) {
627 hpte_page_sizes[penc] = (ap << 4) | bp;
628 penc += 1 << shift;
629 }
630 }
631 }
632 }
633
htab_init_page_sizes(void)634 static void __init htab_init_page_sizes(void)
635 {
636 init_hpte_page_sizes();
637
638 if (!debug_pagealloc_enabled()) {
639 /*
640 * Pick a size for the linear mapping. Currently, we only
641 * support 16M, 1M and 4K which is the default
642 */
643 if (mmu_psize_defs[MMU_PAGE_16M].shift)
644 mmu_linear_psize = MMU_PAGE_16M;
645 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
646 mmu_linear_psize = MMU_PAGE_1M;
647 }
648
649 #ifdef CONFIG_PPC_64K_PAGES
650 /*
651 * Pick a size for the ordinary pages. Default is 4K, we support
652 * 64K for user mappings and vmalloc if supported by the processor.
653 * We only use 64k for ioremap if the processor
654 * (and firmware) support cache-inhibited large pages.
655 * If not, we use 4k and set mmu_ci_restrictions so that
656 * hash_page knows to switch processes that use cache-inhibited
657 * mappings to 4k pages.
658 */
659 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
660 mmu_virtual_psize = MMU_PAGE_64K;
661 mmu_vmalloc_psize = MMU_PAGE_64K;
662 if (mmu_linear_psize == MMU_PAGE_4K)
663 mmu_linear_psize = MMU_PAGE_64K;
664 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
665 /*
666 * When running on pSeries using 64k pages for ioremap
667 * would stop us accessing the HEA ethernet. So if we
668 * have the chance of ever seeing one, stay at 4k.
669 */
670 if (!might_have_hea())
671 mmu_io_psize = MMU_PAGE_64K;
672 } else
673 mmu_ci_restrictions = 1;
674 }
675 #endif /* CONFIG_PPC_64K_PAGES */
676
677 #ifdef CONFIG_SPARSEMEM_VMEMMAP
678 /*
679 * We try to use 16M pages for vmemmap if that is supported
680 * and we have at least 1G of RAM at boot
681 */
682 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
683 memblock_phys_mem_size() >= 0x40000000)
684 mmu_vmemmap_psize = MMU_PAGE_16M;
685 else
686 mmu_vmemmap_psize = mmu_virtual_psize;
687 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
688
689 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
690 "virtual = %d, io = %d"
691 #ifdef CONFIG_SPARSEMEM_VMEMMAP
692 ", vmemmap = %d"
693 #endif
694 "\n",
695 mmu_psize_defs[mmu_linear_psize].shift,
696 mmu_psize_defs[mmu_virtual_psize].shift,
697 mmu_psize_defs[mmu_io_psize].shift
698 #ifdef CONFIG_SPARSEMEM_VMEMMAP
699 ,mmu_psize_defs[mmu_vmemmap_psize].shift
700 #endif
701 );
702 }
703
htab_dt_scan_pftsize(unsigned long node,const char * uname,int depth,void * data)704 static int __init htab_dt_scan_pftsize(unsigned long node,
705 const char *uname, int depth,
706 void *data)
707 {
708 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
709 const __be32 *prop;
710
711 /* We are scanning "cpu" nodes only */
712 if (type == NULL || strcmp(type, "cpu") != 0)
713 return 0;
714
715 prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
716 if (prop != NULL) {
717 /* pft_size[0] is the NUMA CEC cookie */
718 ppc64_pft_size = be32_to_cpu(prop[1]);
719 return 1;
720 }
721 return 0;
722 }
723
htab_shift_for_mem_size(unsigned long mem_size)724 unsigned htab_shift_for_mem_size(unsigned long mem_size)
725 {
726 unsigned memshift = __ilog2(mem_size);
727 unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift;
728 unsigned pteg_shift;
729
730 /* round mem_size up to next power of 2 */
731 if ((1UL << memshift) < mem_size)
732 memshift += 1;
733
734 /* aim for 2 pages / pteg */
735 pteg_shift = memshift - (pshift + 1);
736
737 /*
738 * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab
739 * size permitted by the architecture.
740 */
741 return max(pteg_shift + 7, 18U);
742 }
743
htab_get_table_size(void)744 static unsigned long __init htab_get_table_size(void)
745 {
746 /*
747 * If hash size isn't already provided by the platform, we try to
748 * retrieve it from the device-tree. If it's not there neither, we
749 * calculate it now based on the total RAM size
750 */
751 if (ppc64_pft_size == 0)
752 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
753 if (ppc64_pft_size)
754 return 1UL << ppc64_pft_size;
755
756 return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size());
757 }
758
759 #ifdef CONFIG_MEMORY_HOTPLUG
resize_hpt_for_hotplug(unsigned long new_mem_size)760 int resize_hpt_for_hotplug(unsigned long new_mem_size)
761 {
762 unsigned target_hpt_shift;
763
764 if (!mmu_hash_ops.resize_hpt)
765 return 0;
766
767 target_hpt_shift = htab_shift_for_mem_size(new_mem_size);
768
769 /*
770 * To avoid lots of HPT resizes if memory size is fluctuating
771 * across a boundary, we deliberately have some hysterisis
772 * here: we immediately increase the HPT size if the target
773 * shift exceeds the current shift, but we won't attempt to
774 * reduce unless the target shift is at least 2 below the
775 * current shift
776 */
777 if (target_hpt_shift > ppc64_pft_size ||
778 target_hpt_shift < ppc64_pft_size - 1)
779 return mmu_hash_ops.resize_hpt(target_hpt_shift);
780
781 return 0;
782 }
783
hash__create_section_mapping(unsigned long start,unsigned long end,int nid)784 int hash__create_section_mapping(unsigned long start, unsigned long end, int nid)
785 {
786 int rc;
787
788 if (end >= H_VMALLOC_START) {
789 pr_warn("Outside the supported range\n");
790 return -1;
791 }
792
793 rc = htab_bolt_mapping(start, end, __pa(start),
794 pgprot_val(PAGE_KERNEL), mmu_linear_psize,
795 mmu_kernel_ssize);
796
797 if (rc < 0) {
798 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize,
799 mmu_kernel_ssize);
800 BUG_ON(rc2 && (rc2 != -ENOENT));
801 }
802 return rc;
803 }
804
hash__remove_section_mapping(unsigned long start,unsigned long end)805 int hash__remove_section_mapping(unsigned long start, unsigned long end)
806 {
807 int rc = htab_remove_mapping(start, end, mmu_linear_psize,
808 mmu_kernel_ssize);
809 WARN_ON(rc < 0);
810 return rc;
811 }
812 #endif /* CONFIG_MEMORY_HOTPLUG */
813
hash_init_partition_table(phys_addr_t hash_table,unsigned long htab_size)814 static void __init hash_init_partition_table(phys_addr_t hash_table,
815 unsigned long htab_size)
816 {
817 mmu_partition_table_init();
818
819 /*
820 * PS field (VRMA page size) is not used for LPID 0, hence set to 0.
821 * For now, UPRT is 0 and we have no segment table.
822 */
823 htab_size = __ilog2(htab_size) - 18;
824 mmu_partition_table_set_entry(0, hash_table | htab_size, 0, false);
825 pr_info("Partition table %p\n", partition_tb);
826 }
827
htab_initialize(void)828 static void __init htab_initialize(void)
829 {
830 unsigned long table;
831 unsigned long pteg_count;
832 unsigned long prot;
833 unsigned long base = 0, size = 0;
834 struct memblock_region *reg;
835
836 DBG(" -> htab_initialize()\n");
837
838 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
839 mmu_kernel_ssize = MMU_SEGSIZE_1T;
840 mmu_highuser_ssize = MMU_SEGSIZE_1T;
841 printk(KERN_INFO "Using 1TB segments\n");
842 }
843
844 /*
845 * Calculate the required size of the htab. We want the number of
846 * PTEGs to equal one half the number of real pages.
847 */
848 htab_size_bytes = htab_get_table_size();
849 pteg_count = htab_size_bytes >> 7;
850
851 htab_hash_mask = pteg_count - 1;
852
853 if (firmware_has_feature(FW_FEATURE_LPAR) ||
854 firmware_has_feature(FW_FEATURE_PS3_LV1)) {
855 /* Using a hypervisor which owns the htab */
856 htab_address = NULL;
857 _SDR1 = 0;
858 #ifdef CONFIG_FA_DUMP
859 /*
860 * If firmware assisted dump is active firmware preserves
861 * the contents of htab along with entire partition memory.
862 * Clear the htab if firmware assisted dump is active so
863 * that we dont end up using old mappings.
864 */
865 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all)
866 mmu_hash_ops.hpte_clear_all();
867 #endif
868 } else {
869 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE;
870
871 #ifdef CONFIG_PPC_CELL
872 /*
873 * Cell may require the hash table down low when using the
874 * Axon IOMMU in order to fit the dynamic region over it, see
875 * comments in cell/iommu.c
876 */
877 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) {
878 limit = 0x80000000;
879 pr_info("Hash table forced below 2G for Axon IOMMU\n");
880 }
881 #endif /* CONFIG_PPC_CELL */
882
883 table = memblock_phys_alloc_range(htab_size_bytes,
884 htab_size_bytes,
885 0, limit);
886 if (!table)
887 panic("ERROR: Failed to allocate %pa bytes below %pa\n",
888 &htab_size_bytes, &limit);
889
890 DBG("Hash table allocated at %lx, size: %lx\n", table,
891 htab_size_bytes);
892
893 htab_address = __va(table);
894
895 /* htab absolute addr + encoded htabsize */
896 _SDR1 = table + __ilog2(htab_size_bytes) - 18;
897
898 /* Initialize the HPT with no entries */
899 memset((void *)table, 0, htab_size_bytes);
900
901 if (!cpu_has_feature(CPU_FTR_ARCH_300))
902 /* Set SDR1 */
903 mtspr(SPRN_SDR1, _SDR1);
904 else
905 hash_init_partition_table(table, htab_size_bytes);
906 }
907
908 prot = pgprot_val(PAGE_KERNEL);
909
910 #ifdef CONFIG_DEBUG_PAGEALLOC
911 if (debug_pagealloc_enabled()) {
912 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
913 linear_map_hash_slots = memblock_alloc_try_nid(
914 linear_map_hash_count, 1, MEMBLOCK_LOW_LIMIT,
915 ppc64_rma_size, NUMA_NO_NODE);
916 if (!linear_map_hash_slots)
917 panic("%s: Failed to allocate %lu bytes max_addr=%pa\n",
918 __func__, linear_map_hash_count, &ppc64_rma_size);
919 }
920 #endif /* CONFIG_DEBUG_PAGEALLOC */
921
922 /* create bolted the linear mapping in the hash table */
923 for_each_memblock(memory, reg) {
924 base = (unsigned long)__va(reg->base);
925 size = reg->size;
926
927 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
928 base, size, prot);
929
930 if ((base + size) >= H_VMALLOC_START) {
931 pr_warn("Outside the supported range\n");
932 continue;
933 }
934
935 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
936 prot, mmu_linear_psize, mmu_kernel_ssize));
937 }
938 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
939
940 /*
941 * If we have a memory_limit and we've allocated TCEs then we need to
942 * explicitly map the TCE area at the top of RAM. We also cope with the
943 * case that the TCEs start below memory_limit.
944 * tce_alloc_start/end are 16MB aligned so the mapping should work
945 * for either 4K or 16MB pages.
946 */
947 if (tce_alloc_start) {
948 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
949 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
950
951 if (base + size >= tce_alloc_start)
952 tce_alloc_start = base + size + 1;
953
954 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
955 __pa(tce_alloc_start), prot,
956 mmu_linear_psize, mmu_kernel_ssize));
957 }
958
959
960 DBG(" <- htab_initialize()\n");
961 }
962 #undef KB
963 #undef MB
964
hash__early_init_devtree(void)965 void __init hash__early_init_devtree(void)
966 {
967 /* Initialize segment sizes */
968 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
969
970 /* Initialize page sizes */
971 htab_scan_page_sizes();
972 }
973
974 static struct hash_mm_context init_hash_mm_context;
hash__early_init_mmu(void)975 void __init hash__early_init_mmu(void)
976 {
977 #ifndef CONFIG_PPC_64K_PAGES
978 /*
979 * We have code in __hash_page_4K() and elsewhere, which assumes it can
980 * do the following:
981 * new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX);
982 *
983 * Where the slot number is between 0-15, and values of 8-15 indicate
984 * the secondary bucket. For that code to work H_PAGE_F_SECOND and
985 * H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and
986 * H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here
987 * with a BUILD_BUG_ON().
988 */
989 BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3)));
990 #endif /* CONFIG_PPC_64K_PAGES */
991
992 htab_init_page_sizes();
993
994 /*
995 * initialize page table size
996 */
997 __pte_frag_nr = H_PTE_FRAG_NR;
998 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
999 __pmd_frag_nr = H_PMD_FRAG_NR;
1000 __pmd_frag_size_shift = H_PMD_FRAG_SIZE_SHIFT;
1001
1002 __pte_index_size = H_PTE_INDEX_SIZE;
1003 __pmd_index_size = H_PMD_INDEX_SIZE;
1004 __pud_index_size = H_PUD_INDEX_SIZE;
1005 __pgd_index_size = H_PGD_INDEX_SIZE;
1006 __pud_cache_index = H_PUD_CACHE_INDEX;
1007 __pte_table_size = H_PTE_TABLE_SIZE;
1008 __pmd_table_size = H_PMD_TABLE_SIZE;
1009 __pud_table_size = H_PUD_TABLE_SIZE;
1010 __pgd_table_size = H_PGD_TABLE_SIZE;
1011 /*
1012 * 4k use hugepd format, so for hash set then to
1013 * zero
1014 */
1015 __pmd_val_bits = HASH_PMD_VAL_BITS;
1016 __pud_val_bits = HASH_PUD_VAL_BITS;
1017 __pgd_val_bits = HASH_PGD_VAL_BITS;
1018
1019 __kernel_virt_start = H_KERN_VIRT_START;
1020 __vmalloc_start = H_VMALLOC_START;
1021 __vmalloc_end = H_VMALLOC_END;
1022 __kernel_io_start = H_KERN_IO_START;
1023 __kernel_io_end = H_KERN_IO_END;
1024 vmemmap = (struct page *)H_VMEMMAP_START;
1025 ioremap_bot = IOREMAP_BASE;
1026
1027 #ifdef CONFIG_PCI
1028 pci_io_base = ISA_IO_BASE;
1029 #endif
1030
1031 /* Select appropriate backend */
1032 if (firmware_has_feature(FW_FEATURE_PS3_LV1))
1033 ps3_early_mm_init();
1034 else if (firmware_has_feature(FW_FEATURE_LPAR))
1035 hpte_init_pseries();
1036 else if (IS_ENABLED(CONFIG_PPC_NATIVE))
1037 hpte_init_native();
1038
1039 if (!mmu_hash_ops.hpte_insert)
1040 panic("hash__early_init_mmu: No MMU hash ops defined!\n");
1041
1042 /*
1043 * Initialize the MMU Hash table and create the linear mapping
1044 * of memory. Has to be done before SLB initialization as this is
1045 * currently where the page size encoding is obtained.
1046 */
1047 htab_initialize();
1048
1049 init_mm.context.hash_context = &init_hash_mm_context;
1050 mm_ctx_set_slb_addr_limit(&init_mm.context, SLB_ADDR_LIMIT_DEFAULT);
1051
1052 pr_info("Initializing hash mmu with SLB\n");
1053 /* Initialize SLB management */
1054 slb_initialize();
1055
1056 if (cpu_has_feature(CPU_FTR_ARCH_206)
1057 && cpu_has_feature(CPU_FTR_HVMODE))
1058 tlbiel_all();
1059 }
1060
1061 #ifdef CONFIG_SMP
hash__early_init_mmu_secondary(void)1062 void hash__early_init_mmu_secondary(void)
1063 {
1064 /* Initialize hash table for that CPU */
1065 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
1066
1067 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1068 mtspr(SPRN_SDR1, _SDR1);
1069 else
1070 set_ptcr_when_no_uv(__pa(partition_tb) |
1071 (PATB_SIZE_SHIFT - 12));
1072 }
1073 /* Initialize SLB */
1074 slb_initialize();
1075
1076 if (cpu_has_feature(CPU_FTR_ARCH_206)
1077 && cpu_has_feature(CPU_FTR_HVMODE))
1078 tlbiel_all();
1079 }
1080 #endif /* CONFIG_SMP */
1081
1082 /*
1083 * Called by asm hashtable.S for doing lazy icache flush
1084 */
hash_page_do_lazy_icache(unsigned int pp,pte_t pte,int trap)1085 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
1086 {
1087 struct page *page;
1088
1089 if (!pfn_valid(pte_pfn(pte)))
1090 return pp;
1091
1092 page = pte_page(pte);
1093
1094 /* page is dirty */
1095 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
1096 if (trap == 0x400) {
1097 flush_dcache_icache_page(page);
1098 set_bit(PG_arch_1, &page->flags);
1099 } else
1100 pp |= HPTE_R_N;
1101 }
1102 return pp;
1103 }
1104
1105 #ifdef CONFIG_PPC_MM_SLICES
get_paca_psize(unsigned long addr)1106 static unsigned int get_paca_psize(unsigned long addr)
1107 {
1108 unsigned char *psizes;
1109 unsigned long index, mask_index;
1110
1111 if (addr < SLICE_LOW_TOP) {
1112 psizes = get_paca()->mm_ctx_low_slices_psize;
1113 index = GET_LOW_SLICE_INDEX(addr);
1114 } else {
1115 psizes = get_paca()->mm_ctx_high_slices_psize;
1116 index = GET_HIGH_SLICE_INDEX(addr);
1117 }
1118 mask_index = index & 0x1;
1119 return (psizes[index >> 1] >> (mask_index * 4)) & 0xF;
1120 }
1121
1122 #else
get_paca_psize(unsigned long addr)1123 unsigned int get_paca_psize(unsigned long addr)
1124 {
1125 return get_paca()->mm_ctx_user_psize;
1126 }
1127 #endif
1128
1129 /*
1130 * Demote a segment to using 4k pages.
1131 * For now this makes the whole process use 4k pages.
1132 */
1133 #ifdef CONFIG_PPC_64K_PAGES
demote_segment_4k(struct mm_struct * mm,unsigned long addr)1134 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
1135 {
1136 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
1137 return;
1138 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
1139 copro_flush_all_slbs(mm);
1140 if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) {
1141
1142 copy_mm_to_paca(mm);
1143 slb_flush_and_restore_bolted();
1144 }
1145 }
1146 #endif /* CONFIG_PPC_64K_PAGES */
1147
1148 #ifdef CONFIG_PPC_SUBPAGE_PROT
1149 /*
1150 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
1151 * Userspace sets the subpage permissions using the subpage_prot system call.
1152 *
1153 * Result is 0: full permissions, _PAGE_RW: read-only,
1154 * _PAGE_RWX: no access.
1155 */
subpage_protection(struct mm_struct * mm,unsigned long ea)1156 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
1157 {
1158 struct subpage_prot_table *spt = mm_ctx_subpage_prot(&mm->context);
1159 u32 spp = 0;
1160 u32 **sbpm, *sbpp;
1161
1162 if (!spt)
1163 return 0;
1164
1165 if (ea >= spt->maxaddr)
1166 return 0;
1167 if (ea < 0x100000000UL) {
1168 /* addresses below 4GB use spt->low_prot */
1169 sbpm = spt->low_prot;
1170 } else {
1171 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
1172 if (!sbpm)
1173 return 0;
1174 }
1175 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
1176 if (!sbpp)
1177 return 0;
1178 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
1179
1180 /* extract 2-bit bitfield for this 4k subpage */
1181 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
1182
1183 /*
1184 * 0 -> full premission
1185 * 1 -> Read only
1186 * 2 -> no access.
1187 * We return the flag that need to be cleared.
1188 */
1189 spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0);
1190 return spp;
1191 }
1192
1193 #else /* CONFIG_PPC_SUBPAGE_PROT */
subpage_protection(struct mm_struct * mm,unsigned long ea)1194 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
1195 {
1196 return 0;
1197 }
1198 #endif
1199
hash_failure_debug(unsigned long ea,unsigned long access,unsigned long vsid,unsigned long trap,int ssize,int psize,int lpsize,unsigned long pte)1200 void hash_failure_debug(unsigned long ea, unsigned long access,
1201 unsigned long vsid, unsigned long trap,
1202 int ssize, int psize, int lpsize, unsigned long pte)
1203 {
1204 if (!printk_ratelimit())
1205 return;
1206 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1207 ea, access, current->comm);
1208 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1209 trap, vsid, ssize, psize, lpsize, pte);
1210 }
1211
check_paca_psize(unsigned long ea,struct mm_struct * mm,int psize,bool user_region)1212 static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
1213 int psize, bool user_region)
1214 {
1215 if (user_region) {
1216 if (psize != get_paca_psize(ea)) {
1217 copy_mm_to_paca(mm);
1218 slb_flush_and_restore_bolted();
1219 }
1220 } else if (get_paca()->vmalloc_sllp !=
1221 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1222 get_paca()->vmalloc_sllp =
1223 mmu_psize_defs[mmu_vmalloc_psize].sllp;
1224 slb_vmalloc_update();
1225 }
1226 }
1227
1228 /*
1229 * Result code is:
1230 * 0 - handled
1231 * 1 - normal page fault
1232 * -1 - critical hash insertion error
1233 * -2 - access not permitted by subpage protection mechanism
1234 */
hash_page_mm(struct mm_struct * mm,unsigned long ea,unsigned long access,unsigned long trap,unsigned long flags)1235 int hash_page_mm(struct mm_struct *mm, unsigned long ea,
1236 unsigned long access, unsigned long trap,
1237 unsigned long flags)
1238 {
1239 bool is_thp;
1240 enum ctx_state prev_state = exception_enter();
1241 pgd_t *pgdir;
1242 unsigned long vsid;
1243 pte_t *ptep;
1244 unsigned hugeshift;
1245 int rc, user_region = 0;
1246 int psize, ssize;
1247
1248 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1249 ea, access, trap);
1250 trace_hash_fault(ea, access, trap);
1251
1252 /* Get region & vsid */
1253 switch (get_region_id(ea)) {
1254 case USER_REGION_ID:
1255 user_region = 1;
1256 if (! mm) {
1257 DBG_LOW(" user region with no mm !\n");
1258 rc = 1;
1259 goto bail;
1260 }
1261 psize = get_slice_psize(mm, ea);
1262 ssize = user_segment_size(ea);
1263 vsid = get_user_vsid(&mm->context, ea, ssize);
1264 break;
1265 case VMALLOC_REGION_ID:
1266 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1267 psize = mmu_vmalloc_psize;
1268 ssize = mmu_kernel_ssize;
1269 break;
1270
1271 case IO_REGION_ID:
1272 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1273 psize = mmu_io_psize;
1274 ssize = mmu_kernel_ssize;
1275 break;
1276 default:
1277 /*
1278 * Not a valid range
1279 * Send the problem up to do_page_fault()
1280 */
1281 rc = 1;
1282 goto bail;
1283 }
1284 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1285
1286 /* Bad address. */
1287 if (!vsid) {
1288 DBG_LOW("Bad address!\n");
1289 rc = 1;
1290 goto bail;
1291 }
1292 /* Get pgdir */
1293 pgdir = mm->pgd;
1294 if (pgdir == NULL) {
1295 rc = 1;
1296 goto bail;
1297 }
1298
1299 /* Check CPU locality */
1300 if (user_region && mm_is_thread_local(mm))
1301 flags |= HPTE_LOCAL_UPDATE;
1302
1303 #ifndef CONFIG_PPC_64K_PAGES
1304 /*
1305 * If we use 4K pages and our psize is not 4K, then we might
1306 * be hitting a special driver mapping, and need to align the
1307 * address before we fetch the PTE.
1308 *
1309 * It could also be a hugepage mapping, in which case this is
1310 * not necessary, but it's not harmful, either.
1311 */
1312 if (psize != MMU_PAGE_4K)
1313 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1314 #endif /* CONFIG_PPC_64K_PAGES */
1315
1316 /* Get PTE and page size from page tables */
1317 ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift);
1318 if (ptep == NULL || !pte_present(*ptep)) {
1319 DBG_LOW(" no PTE !\n");
1320 rc = 1;
1321 goto bail;
1322 }
1323
1324 /* Add _PAGE_PRESENT to the required access perm */
1325 access |= _PAGE_PRESENT;
1326
1327 /*
1328 * Pre-check access permissions (will be re-checked atomically
1329 * in __hash_page_XX but this pre-check is a fast path
1330 */
1331 if (!check_pte_access(access, pte_val(*ptep))) {
1332 DBG_LOW(" no access !\n");
1333 rc = 1;
1334 goto bail;
1335 }
1336
1337 if (hugeshift) {
1338 if (is_thp)
1339 rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1340 trap, flags, ssize, psize);
1341 #ifdef CONFIG_HUGETLB_PAGE
1342 else
1343 rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1344 flags, ssize, hugeshift, psize);
1345 #else
1346 else {
1347 /*
1348 * if we have hugeshift, and is not transhuge with
1349 * hugetlb disabled, something is really wrong.
1350 */
1351 rc = 1;
1352 WARN_ON(1);
1353 }
1354 #endif
1355 if (current->mm == mm)
1356 check_paca_psize(ea, mm, psize, user_region);
1357
1358 goto bail;
1359 }
1360
1361 #ifndef CONFIG_PPC_64K_PAGES
1362 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1363 #else
1364 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1365 pte_val(*(ptep + PTRS_PER_PTE)));
1366 #endif
1367 /* Do actual hashing */
1368 #ifdef CONFIG_PPC_64K_PAGES
1369 /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */
1370 if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1371 demote_segment_4k(mm, ea);
1372 psize = MMU_PAGE_4K;
1373 }
1374
1375 /*
1376 * If this PTE is non-cacheable and we have restrictions on
1377 * using non cacheable large pages, then we switch to 4k
1378 */
1379 if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {
1380 if (user_region) {
1381 demote_segment_4k(mm, ea);
1382 psize = MMU_PAGE_4K;
1383 } else if (ea < VMALLOC_END) {
1384 /*
1385 * some driver did a non-cacheable mapping
1386 * in vmalloc space, so switch vmalloc
1387 * to 4k pages
1388 */
1389 printk(KERN_ALERT "Reducing vmalloc segment "
1390 "to 4kB pages because of "
1391 "non-cacheable mapping\n");
1392 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1393 copro_flush_all_slbs(mm);
1394 }
1395 }
1396
1397 #endif /* CONFIG_PPC_64K_PAGES */
1398
1399 if (current->mm == mm)
1400 check_paca_psize(ea, mm, psize, user_region);
1401
1402 #ifdef CONFIG_PPC_64K_PAGES
1403 if (psize == MMU_PAGE_64K)
1404 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1405 flags, ssize);
1406 else
1407 #endif /* CONFIG_PPC_64K_PAGES */
1408 {
1409 int spp = subpage_protection(mm, ea);
1410 if (access & spp)
1411 rc = -2;
1412 else
1413 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1414 flags, ssize, spp);
1415 }
1416
1417 /*
1418 * Dump some info in case of hash insertion failure, they should
1419 * never happen so it is really useful to know if/when they do
1420 */
1421 if (rc == -1)
1422 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1423 psize, pte_val(*ptep));
1424 #ifndef CONFIG_PPC_64K_PAGES
1425 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1426 #else
1427 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1428 pte_val(*(ptep + PTRS_PER_PTE)));
1429 #endif
1430 DBG_LOW(" -> rc=%d\n", rc);
1431
1432 bail:
1433 exception_exit(prev_state);
1434 return rc;
1435 }
1436 EXPORT_SYMBOL_GPL(hash_page_mm);
1437
hash_page(unsigned long ea,unsigned long access,unsigned long trap,unsigned long dsisr)1438 int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
1439 unsigned long dsisr)
1440 {
1441 unsigned long flags = 0;
1442 struct mm_struct *mm = current->mm;
1443
1444 if ((get_region_id(ea) == VMALLOC_REGION_ID) ||
1445 (get_region_id(ea) == IO_REGION_ID))
1446 mm = &init_mm;
1447
1448 if (dsisr & DSISR_NOHPTE)
1449 flags |= HPTE_NOHPTE_UPDATE;
1450
1451 return hash_page_mm(mm, ea, access, trap, flags);
1452 }
1453 EXPORT_SYMBOL_GPL(hash_page);
1454
__hash_page(unsigned long trap,unsigned long ea,unsigned long dsisr,unsigned long msr)1455 int __hash_page(unsigned long trap, unsigned long ea, unsigned long dsisr,
1456 unsigned long msr)
1457 {
1458 unsigned long access = _PAGE_PRESENT | _PAGE_READ;
1459 unsigned long flags = 0;
1460 struct mm_struct *mm = current->mm;
1461 unsigned int region_id = get_region_id(ea);
1462
1463 if ((region_id == VMALLOC_REGION_ID) || (region_id == IO_REGION_ID))
1464 mm = &init_mm;
1465
1466 if (dsisr & DSISR_NOHPTE)
1467 flags |= HPTE_NOHPTE_UPDATE;
1468
1469 if (dsisr & DSISR_ISSTORE)
1470 access |= _PAGE_WRITE;
1471 /*
1472 * We set _PAGE_PRIVILEGED only when
1473 * kernel mode access kernel space.
1474 *
1475 * _PAGE_PRIVILEGED is NOT set
1476 * 1) when kernel mode access user space
1477 * 2) user space access kernel space.
1478 */
1479 access |= _PAGE_PRIVILEGED;
1480 if ((msr & MSR_PR) || (region_id == USER_REGION_ID))
1481 access &= ~_PAGE_PRIVILEGED;
1482
1483 if (trap == 0x400)
1484 access |= _PAGE_EXEC;
1485
1486 return hash_page_mm(mm, ea, access, trap, flags);
1487 }
1488
1489 #ifdef CONFIG_PPC_MM_SLICES
should_hash_preload(struct mm_struct * mm,unsigned long ea)1490 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1491 {
1492 int psize = get_slice_psize(mm, ea);
1493
1494 /* We only prefault standard pages for now */
1495 if (unlikely(psize != mm_ctx_user_psize(&mm->context)))
1496 return false;
1497
1498 /*
1499 * Don't prefault if subpage protection is enabled for the EA.
1500 */
1501 if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea)))
1502 return false;
1503
1504 return true;
1505 }
1506 #else
should_hash_preload(struct mm_struct * mm,unsigned long ea)1507 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1508 {
1509 return true;
1510 }
1511 #endif
1512
hash_preload(struct mm_struct * mm,unsigned long ea,bool is_exec,unsigned long trap)1513 static void hash_preload(struct mm_struct *mm, unsigned long ea,
1514 bool is_exec, unsigned long trap)
1515 {
1516 int hugepage_shift;
1517 unsigned long vsid;
1518 pgd_t *pgdir;
1519 pte_t *ptep;
1520 unsigned long flags;
1521 int rc, ssize, update_flags = 0;
1522 unsigned long access = _PAGE_PRESENT | _PAGE_READ | (is_exec ? _PAGE_EXEC : 0);
1523
1524 BUG_ON(get_region_id(ea) != USER_REGION_ID);
1525
1526 if (!should_hash_preload(mm, ea))
1527 return;
1528
1529 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1530 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1531
1532 /* Get Linux PTE if available */
1533 pgdir = mm->pgd;
1534 if (pgdir == NULL)
1535 return;
1536
1537 /* Get VSID */
1538 ssize = user_segment_size(ea);
1539 vsid = get_user_vsid(&mm->context, ea, ssize);
1540 if (!vsid)
1541 return;
1542 /*
1543 * Hash doesn't like irqs. Walking linux page table with irq disabled
1544 * saves us from holding multiple locks.
1545 */
1546 local_irq_save(flags);
1547
1548 /*
1549 * THP pages use update_mmu_cache_pmd. We don't do
1550 * hash preload there. Hence can ignore THP here
1551 */
1552 ptep = find_current_mm_pte(pgdir, ea, NULL, &hugepage_shift);
1553 if (!ptep)
1554 goto out_exit;
1555
1556 WARN_ON(hugepage_shift);
1557 #ifdef CONFIG_PPC_64K_PAGES
1558 /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on
1559 * a 64K kernel), then we don't preload, hash_page() will take
1560 * care of it once we actually try to access the page.
1561 * That way we don't have to duplicate all of the logic for segment
1562 * page size demotion here
1563 */
1564 if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep))
1565 goto out_exit;
1566 #endif /* CONFIG_PPC_64K_PAGES */
1567
1568 /* Is that local to this CPU ? */
1569 if (mm_is_thread_local(mm))
1570 update_flags |= HPTE_LOCAL_UPDATE;
1571
1572 /* Hash it in */
1573 #ifdef CONFIG_PPC_64K_PAGES
1574 if (mm_ctx_user_psize(&mm->context) == MMU_PAGE_64K)
1575 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1576 update_flags, ssize);
1577 else
1578 #endif /* CONFIG_PPC_64K_PAGES */
1579 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
1580 ssize, subpage_protection(mm, ea));
1581
1582 /* Dump some info in case of hash insertion failure, they should
1583 * never happen so it is really useful to know if/when they do
1584 */
1585 if (rc == -1)
1586 hash_failure_debug(ea, access, vsid, trap, ssize,
1587 mm_ctx_user_psize(&mm->context),
1588 mm_ctx_user_psize(&mm->context),
1589 pte_val(*ptep));
1590 out_exit:
1591 local_irq_restore(flags);
1592 }
1593
1594 /*
1595 * This is called at the end of handling a user page fault, when the
1596 * fault has been handled by updating a PTE in the linux page tables.
1597 * We use it to preload an HPTE into the hash table corresponding to
1598 * the updated linux PTE.
1599 *
1600 * This must always be called with the pte lock held.
1601 */
update_mmu_cache(struct vm_area_struct * vma,unsigned long address,pte_t * ptep)1602 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
1603 pte_t *ptep)
1604 {
1605 /*
1606 * We don't need to worry about _PAGE_PRESENT here because we are
1607 * called with either mm->page_table_lock held or ptl lock held
1608 */
1609 unsigned long trap;
1610 bool is_exec;
1611
1612 if (radix_enabled()) {
1613 prefetch((void *)address);
1614 return;
1615 }
1616
1617 /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */
1618 if (!pte_young(*ptep) || address >= TASK_SIZE)
1619 return;
1620
1621 /*
1622 * We try to figure out if we are coming from an instruction
1623 * access fault and pass that down to __hash_page so we avoid
1624 * double-faulting on execution of fresh text. We have to test
1625 * for regs NULL since init will get here first thing at boot.
1626 *
1627 * We also avoid filling the hash if not coming from a fault.
1628 */
1629
1630 trap = current->thread.regs ? TRAP(current->thread.regs) : 0UL;
1631 switch (trap) {
1632 case 0x300:
1633 is_exec = false;
1634 break;
1635 case 0x400:
1636 is_exec = true;
1637 break;
1638 default:
1639 return;
1640 }
1641
1642 hash_preload(vma->vm_mm, address, is_exec, trap);
1643 }
1644
1645 #ifdef CONFIG_PPC_MEM_KEYS
1646 /*
1647 * Return the protection key associated with the given address and the
1648 * mm_struct.
1649 */
get_mm_addr_key(struct mm_struct * mm,unsigned long address)1650 u16 get_mm_addr_key(struct mm_struct *mm, unsigned long address)
1651 {
1652 pte_t *ptep;
1653 u16 pkey = 0;
1654 unsigned long flags;
1655
1656 if (!mm || !mm->pgd)
1657 return 0;
1658
1659 local_irq_save(flags);
1660 ptep = find_linux_pte(mm->pgd, address, NULL, NULL);
1661 if (ptep)
1662 pkey = pte_to_pkey_bits(pte_val(READ_ONCE(*ptep)));
1663 local_irq_restore(flags);
1664
1665 return pkey;
1666 }
1667 #endif /* CONFIG_PPC_MEM_KEYS */
1668
1669 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
tm_flush_hash_page(int local)1670 static inline void tm_flush_hash_page(int local)
1671 {
1672 /*
1673 * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a
1674 * page back to a block device w/PIO could pick up transactional data
1675 * (bad!) so we force an abort here. Before the sync the page will be
1676 * made read-only, which will flush_hash_page. BIG ISSUE here: if the
1677 * kernel uses a page from userspace without unmapping it first, it may
1678 * see the speculated version.
1679 */
1680 if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs &&
1681 MSR_TM_ACTIVE(current->thread.regs->msr)) {
1682 tm_enable();
1683 tm_abort(TM_CAUSE_TLBI);
1684 }
1685 }
1686 #else
tm_flush_hash_page(int local)1687 static inline void tm_flush_hash_page(int local)
1688 {
1689 }
1690 #endif
1691
1692 /*
1693 * Return the global hash slot, corresponding to the given PTE, which contains
1694 * the HPTE.
1695 */
pte_get_hash_gslot(unsigned long vpn,unsigned long shift,int ssize,real_pte_t rpte,unsigned int subpg_index)1696 unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift,
1697 int ssize, real_pte_t rpte, unsigned int subpg_index)
1698 {
1699 unsigned long hash, gslot, hidx;
1700
1701 hash = hpt_hash(vpn, shift, ssize);
1702 hidx = __rpte_to_hidx(rpte, subpg_index);
1703 if (hidx & _PTEIDX_SECONDARY)
1704 hash = ~hash;
1705 gslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1706 gslot += hidx & _PTEIDX_GROUP_IX;
1707 return gslot;
1708 }
1709
1710 /*
1711 * WARNING: This is called from hash_low_64.S, if you change this prototype,
1712 * do not forget to update the assembly call site !
1713 */
flush_hash_page(unsigned long vpn,real_pte_t pte,int psize,int ssize,unsigned long flags)1714 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1715 unsigned long flags)
1716 {
1717 unsigned long index, shift, gslot;
1718 int local = flags & HPTE_LOCAL_UPDATE;
1719
1720 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1721 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1722 gslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index);
1723 DBG_LOW(" sub %ld: gslot=%lx\n", index, gslot);
1724 /*
1725 * We use same base page size and actual psize, because we don't
1726 * use these functions for hugepage
1727 */
1728 mmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize,
1729 ssize, local);
1730 } pte_iterate_hashed_end();
1731
1732 tm_flush_hash_page(local);
1733 }
1734
1735 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
flush_hash_hugepage(unsigned long vsid,unsigned long addr,pmd_t * pmdp,unsigned int psize,int ssize,unsigned long flags)1736 void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
1737 pmd_t *pmdp, unsigned int psize, int ssize,
1738 unsigned long flags)
1739 {
1740 int i, max_hpte_count, valid;
1741 unsigned long s_addr;
1742 unsigned char *hpte_slot_array;
1743 unsigned long hidx, shift, vpn, hash, slot;
1744 int local = flags & HPTE_LOCAL_UPDATE;
1745
1746 s_addr = addr & HPAGE_PMD_MASK;
1747 hpte_slot_array = get_hpte_slot_array(pmdp);
1748 /*
1749 * IF we try to do a HUGE PTE update after a withdraw is done.
1750 * we will find the below NULL. This happens when we do
1751 * split_huge_pmd
1752 */
1753 if (!hpte_slot_array)
1754 return;
1755
1756 if (mmu_hash_ops.hugepage_invalidate) {
1757 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array,
1758 psize, ssize, local);
1759 goto tm_abort;
1760 }
1761 /*
1762 * No bluk hpte removal support, invalidate each entry
1763 */
1764 shift = mmu_psize_defs[psize].shift;
1765 max_hpte_count = HPAGE_PMD_SIZE >> shift;
1766 for (i = 0; i < max_hpte_count; i++) {
1767 /*
1768 * 8 bits per each hpte entries
1769 * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
1770 */
1771 valid = hpte_valid(hpte_slot_array, i);
1772 if (!valid)
1773 continue;
1774 hidx = hpte_hash_index(hpte_slot_array, i);
1775
1776 /* get the vpn */
1777 addr = s_addr + (i * (1ul << shift));
1778 vpn = hpt_vpn(addr, vsid, ssize);
1779 hash = hpt_hash(vpn, shift, ssize);
1780 if (hidx & _PTEIDX_SECONDARY)
1781 hash = ~hash;
1782
1783 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1784 slot += hidx & _PTEIDX_GROUP_IX;
1785 mmu_hash_ops.hpte_invalidate(slot, vpn, psize,
1786 MMU_PAGE_16M, ssize, local);
1787 }
1788 tm_abort:
1789 tm_flush_hash_page(local);
1790 }
1791 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1792
flush_hash_range(unsigned long number,int local)1793 void flush_hash_range(unsigned long number, int local)
1794 {
1795 if (mmu_hash_ops.flush_hash_range)
1796 mmu_hash_ops.flush_hash_range(number, local);
1797 else {
1798 int i;
1799 struct ppc64_tlb_batch *batch =
1800 this_cpu_ptr(&ppc64_tlb_batch);
1801
1802 for (i = 0; i < number; i++)
1803 flush_hash_page(batch->vpn[i], batch->pte[i],
1804 batch->psize, batch->ssize, local);
1805 }
1806 }
1807
1808 /*
1809 * low_hash_fault is called when we the low level hash code failed
1810 * to instert a PTE due to an hypervisor error
1811 */
low_hash_fault(struct pt_regs * regs,unsigned long address,int rc)1812 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1813 {
1814 enum ctx_state prev_state = exception_enter();
1815
1816 if (user_mode(regs)) {
1817 #ifdef CONFIG_PPC_SUBPAGE_PROT
1818 if (rc == -2)
1819 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1820 else
1821 #endif
1822 _exception(SIGBUS, regs, BUS_ADRERR, address);
1823 } else
1824 bad_page_fault(regs, address, SIGBUS);
1825
1826 exception_exit(prev_state);
1827 }
1828
hpte_insert_repeating(unsigned long hash,unsigned long vpn,unsigned long pa,unsigned long rflags,unsigned long vflags,int psize,int ssize)1829 long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1830 unsigned long pa, unsigned long rflags,
1831 unsigned long vflags, int psize, int ssize)
1832 {
1833 unsigned long hpte_group;
1834 long slot;
1835
1836 repeat:
1837 hpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1838
1839 /* Insert into the hash table, primary slot */
1840 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1841 psize, psize, ssize);
1842
1843 /* Primary is full, try the secondary */
1844 if (unlikely(slot == -1)) {
1845 hpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP;
1846 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags,
1847 vflags | HPTE_V_SECONDARY,
1848 psize, psize, ssize);
1849 if (slot == -1) {
1850 if (mftb() & 0x1)
1851 hpte_group = (hash & htab_hash_mask) *
1852 HPTES_PER_GROUP;
1853
1854 mmu_hash_ops.hpte_remove(hpte_group);
1855 goto repeat;
1856 }
1857 }
1858
1859 return slot;
1860 }
1861
1862 #ifdef CONFIG_DEBUG_PAGEALLOC
kernel_map_linear_page(unsigned long vaddr,unsigned long lmi)1863 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1864 {
1865 unsigned long hash;
1866 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1867 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1868 unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL));
1869 long ret;
1870
1871 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1872
1873 /* Don't create HPTE entries for bad address */
1874 if (!vsid)
1875 return;
1876
1877 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1878 HPTE_V_BOLTED,
1879 mmu_linear_psize, mmu_kernel_ssize);
1880
1881 BUG_ON (ret < 0);
1882 spin_lock(&linear_map_hash_lock);
1883 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1884 linear_map_hash_slots[lmi] = ret | 0x80;
1885 spin_unlock(&linear_map_hash_lock);
1886 }
1887
kernel_unmap_linear_page(unsigned long vaddr,unsigned long lmi)1888 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1889 {
1890 unsigned long hash, hidx, slot;
1891 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1892 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1893
1894 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1895 spin_lock(&linear_map_hash_lock);
1896 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1897 hidx = linear_map_hash_slots[lmi] & 0x7f;
1898 linear_map_hash_slots[lmi] = 0;
1899 spin_unlock(&linear_map_hash_lock);
1900 if (hidx & _PTEIDX_SECONDARY)
1901 hash = ~hash;
1902 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1903 slot += hidx & _PTEIDX_GROUP_IX;
1904 mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize,
1905 mmu_linear_psize,
1906 mmu_kernel_ssize, 0);
1907 }
1908
__kernel_map_pages(struct page * page,int numpages,int enable)1909 void __kernel_map_pages(struct page *page, int numpages, int enable)
1910 {
1911 unsigned long flags, vaddr, lmi;
1912 int i;
1913
1914 local_irq_save(flags);
1915 for (i = 0; i < numpages; i++, page++) {
1916 vaddr = (unsigned long)page_address(page);
1917 lmi = __pa(vaddr) >> PAGE_SHIFT;
1918 if (lmi >= linear_map_hash_count)
1919 continue;
1920 if (enable)
1921 kernel_map_linear_page(vaddr, lmi);
1922 else
1923 kernel_unmap_linear_page(vaddr, lmi);
1924 }
1925 local_irq_restore(flags);
1926 }
1927 #endif /* CONFIG_DEBUG_PAGEALLOC */
1928
hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,phys_addr_t first_memblock_size)1929 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
1930 phys_addr_t first_memblock_size)
1931 {
1932 /*
1933 * We don't currently support the first MEMBLOCK not mapping 0
1934 * physical on those processors
1935 */
1936 BUG_ON(first_memblock_base != 0);
1937
1938 /*
1939 * On virtualized systems the first entry is our RMA region aka VRMA,
1940 * non-virtualized 64-bit hash MMU systems don't have a limitation
1941 * on real mode access.
1942 *
1943 * For guests on platforms before POWER9, we clamp the it limit to 1G
1944 * to avoid some funky things such as RTAS bugs etc...
1945 *
1946 * On POWER9 we limit to 1TB in case the host erroneously told us that
1947 * the RMA was >1TB. Effective address bits 0:23 are treated as zero
1948 * (meaning the access is aliased to zero i.e. addr = addr % 1TB)
1949 * for virtual real mode addressing and so it doesn't make sense to
1950 * have an area larger than 1TB as it can't be addressed.
1951 */
1952 if (!early_cpu_has_feature(CPU_FTR_HVMODE)) {
1953 ppc64_rma_size = first_memblock_size;
1954 if (!early_cpu_has_feature(CPU_FTR_ARCH_300))
1955 ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000);
1956 else
1957 ppc64_rma_size = min_t(u64, ppc64_rma_size,
1958 1UL << SID_SHIFT_1T);
1959
1960 /* Finally limit subsequent allocations */
1961 memblock_set_current_limit(ppc64_rma_size);
1962 } else {
1963 ppc64_rma_size = ULONG_MAX;
1964 }
1965 }
1966
1967 #ifdef CONFIG_DEBUG_FS
1968
hpt_order_get(void * data,u64 * val)1969 static int hpt_order_get(void *data, u64 *val)
1970 {
1971 *val = ppc64_pft_size;
1972 return 0;
1973 }
1974
hpt_order_set(void * data,u64 val)1975 static int hpt_order_set(void *data, u64 val)
1976 {
1977 int ret;
1978
1979 if (!mmu_hash_ops.resize_hpt)
1980 return -ENODEV;
1981
1982 cpus_read_lock();
1983 ret = mmu_hash_ops.resize_hpt(val);
1984 cpus_read_unlock();
1985
1986 return ret;
1987 }
1988
1989 DEFINE_DEBUGFS_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n");
1990
hash64_debugfs(void)1991 static int __init hash64_debugfs(void)
1992 {
1993 if (!debugfs_create_file_unsafe("hpt_order", 0600, powerpc_debugfs_root,
1994 NULL, &fops_hpt_order)) {
1995 pr_err("lpar: unable to create hpt_order debugsfs file\n");
1996 }
1997
1998 return 0;
1999 }
2000 machine_device_initcall(pseries, hash64_debugfs);
2001 #endif /* CONFIG_DEBUG_FS */
2002
print_system_hash_info(void)2003 void __init print_system_hash_info(void)
2004 {
2005 pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size);
2006
2007 if (htab_hash_mask)
2008 pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask);
2009 }
2010
