1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2019 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 #ifndef ASIC_REG_GOYA_REGS_H_ 9 #define ASIC_REG_GOYA_REGS_H_ 10 11 #include "goya_blocks.h" 12 #include "stlb_regs.h" 13 #include "mmu_regs.h" 14 #include "pcie_aux_regs.h" 15 #include "pcie_wrap_regs.h" 16 #include "psoc_global_conf_regs.h" 17 #include "psoc_spi_regs.h" 18 #include "psoc_mme_pll_regs.h" 19 #include "psoc_pci_pll_regs.h" 20 #include "psoc_emmc_pll_regs.h" 21 #include "cpu_if_regs.h" 22 #include "cpu_ca53_cfg_regs.h" 23 #include "cpu_pll_regs.h" 24 #include "ic_pll_regs.h" 25 #include "mc_pll_regs.h" 26 #include "tpc_pll_regs.h" 27 #include "dma_qm_0_regs.h" 28 #include "dma_qm_1_regs.h" 29 #include "dma_qm_2_regs.h" 30 #include "dma_qm_3_regs.h" 31 #include "dma_qm_4_regs.h" 32 #include "dma_ch_0_regs.h" 33 #include "dma_ch_1_regs.h" 34 #include "dma_ch_2_regs.h" 35 #include "dma_ch_3_regs.h" 36 #include "dma_ch_4_regs.h" 37 #include "dma_macro_regs.h" 38 #include "dma_nrtr_regs.h" 39 #include "pci_nrtr_regs.h" 40 #include "sram_y0_x0_rtr_regs.h" 41 #include "sram_y0_x1_rtr_regs.h" 42 #include "sram_y0_x2_rtr_regs.h" 43 #include "sram_y0_x3_rtr_regs.h" 44 #include "sram_y0_x4_rtr_regs.h" 45 #include "mme_regs.h" 46 #include "mme_qm_regs.h" 47 #include "mme_cmdq_regs.h" 48 #include "mme1_rtr_regs.h" 49 #include "mme2_rtr_regs.h" 50 #include "mme3_rtr_regs.h" 51 #include "mme4_rtr_regs.h" 52 #include "mme5_rtr_regs.h" 53 #include "mme6_rtr_regs.h" 54 #include "tpc0_cfg_regs.h" 55 #include "tpc1_cfg_regs.h" 56 #include "tpc2_cfg_regs.h" 57 #include "tpc3_cfg_regs.h" 58 #include "tpc4_cfg_regs.h" 59 #include "tpc5_cfg_regs.h" 60 #include "tpc6_cfg_regs.h" 61 #include "tpc7_cfg_regs.h" 62 #include "tpc0_qm_regs.h" 63 #include "tpc1_qm_regs.h" 64 #include "tpc2_qm_regs.h" 65 #include "tpc3_qm_regs.h" 66 #include "tpc4_qm_regs.h" 67 #include "tpc5_qm_regs.h" 68 #include "tpc6_qm_regs.h" 69 #include "tpc7_qm_regs.h" 70 #include "tpc0_cmdq_regs.h" 71 #include "tpc1_cmdq_regs.h" 72 #include "tpc2_cmdq_regs.h" 73 #include "tpc3_cmdq_regs.h" 74 #include "tpc4_cmdq_regs.h" 75 #include "tpc5_cmdq_regs.h" 76 #include "tpc6_cmdq_regs.h" 77 #include "tpc7_cmdq_regs.h" 78 #include "tpc0_nrtr_regs.h" 79 #include "tpc1_rtr_regs.h" 80 #include "tpc2_rtr_regs.h" 81 #include "tpc3_rtr_regs.h" 82 #include "tpc4_rtr_regs.h" 83 #include "tpc5_rtr_regs.h" 84 #include "tpc6_rtr_regs.h" 85 #include "tpc7_nrtr_regs.h" 86 #include "tpc0_eml_cfg_regs.h" 87 88 #include "psoc_global_conf_masks.h" 89 #include "dma_macro_masks.h" 90 #include "dma_qm_0_masks.h" 91 #include "dma_ch_0_masks.h" 92 #include "tpc0_qm_masks.h" 93 #include "tpc0_cmdq_masks.h" 94 #include "mme_qm_masks.h" 95 #include "mme_cmdq_masks.h" 96 #include "tpc0_cfg_masks.h" 97 #include "tpc0_eml_cfg_masks.h" 98 #include "mme1_rtr_masks.h" 99 #include "tpc0_nrtr_masks.h" 100 #include "dma_nrtr_masks.h" 101 #include "pci_nrtr_masks.h" 102 #include "stlb_masks.h" 103 #include "cpu_ca53_cfg_masks.h" 104 #include "mmu_masks.h" 105 #include "mme_masks.h" 106 107 #define mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG 0xC02000 108 #define mmPCIE_DBI_MSIX_DOORBELL_OFF 0xC02948 109 110 #define mmSYNC_MNGR_MON_PAY_ADDRL_0 0x113000 111 #define mmSYNC_MNGR_SOB_OBJ_0 0x112000 112 #define mmSYNC_MNGR_SOB_OBJ_1000 0x112FA0 113 #define mmSYNC_MNGR_SOB_OBJ_1007 0x112FBC 114 #define mmSYNC_MNGR_SOB_OBJ_1023 0x112FFC 115 #define mmSYNC_MNGR_MON_STATUS_0 0x114000 116 #define mmSYNC_MNGR_MON_STATUS_255 0x1143FC 117 118 #define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR 0x800040 119 120 #endif /* ASIC_REG_GOYA_REGS_H_ */ 121
