1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
3
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/types.h>
7 #include <linux/pci.h>
8 #include <linux/netdevice.h>
9 #include <linux/etherdevice.h>
10 #include <linux/ethtool.h>
11 #include <linux/slab.h>
12 #include <linux/device.h>
13 #include <linux/skbuff.h>
14 #include <linux/if_vlan.h>
15 #include <linux/if_bridge.h>
16 #include <linux/workqueue.h>
17 #include <linux/jiffies.h>
18 #include <linux/bitops.h>
19 #include <linux/list.h>
20 #include <linux/notifier.h>
21 #include <linux/dcbnl.h>
22 #include <linux/inetdevice.h>
23 #include <linux/netlink.h>
24 #include <net/switchdev.h>
25 #include <net/pkt_cls.h>
26 #include <net/tc_act/tc_mirred.h>
27 #include <net/netevent.h>
28 #include <net/tc_act/tc_sample.h>
29 #include <net/addrconf.h>
30
31 #include "spectrum.h"
32 #include "pci.h"
33 #include "core.h"
34 #include "reg.h"
35 #include "port.h"
36 #include "trap.h"
37 #include "txheader.h"
38 #include "spectrum_cnt.h"
39 #include "spectrum_dpipe.h"
40 #include "spectrum_acl_flex_actions.h"
41 #include "spectrum_span.h"
42 #include "../mlxfw/mlxfw.h"
43
44 #define MLXSW_SP_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100)
45
46 #define MLXSW_SP1_FWREV_MAJOR 13
47 #define MLXSW_SP1_FWREV_MINOR 1703
48 #define MLXSW_SP1_FWREV_SUBMINOR 4
49 #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702
50
51 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = {
52 .major = MLXSW_SP1_FWREV_MAJOR,
53 .minor = MLXSW_SP1_FWREV_MINOR,
54 .subminor = MLXSW_SP1_FWREV_SUBMINOR,
55 .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR,
56 };
57
58 #define MLXSW_SP1_FW_FILENAME \
59 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \
60 "." __stringify(MLXSW_SP1_FWREV_MINOR) \
61 "." __stringify(MLXSW_SP1_FWREV_SUBMINOR) ".mfa2"
62
63 static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum";
64 static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2";
65 static const char mlxsw_sp_driver_version[] = "1.0";
66
67 /* tx_hdr_version
68 * Tx header version.
69 * Must be set to 1.
70 */
71 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
72
73 /* tx_hdr_ctl
74 * Packet control type.
75 * 0 - Ethernet control (e.g. EMADs, LACP)
76 * 1 - Ethernet data
77 */
78 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
79
80 /* tx_hdr_proto
81 * Packet protocol type. Must be set to 1 (Ethernet).
82 */
83 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
84
85 /* tx_hdr_rx_is_router
86 * Packet is sent from the router. Valid for data packets only.
87 */
88 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
89
90 /* tx_hdr_fid_valid
91 * Indicates if the 'fid' field is valid and should be used for
92 * forwarding lookup. Valid for data packets only.
93 */
94 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
95
96 /* tx_hdr_swid
97 * Switch partition ID. Must be set to 0.
98 */
99 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
100
101 /* tx_hdr_control_tclass
102 * Indicates if the packet should use the control TClass and not one
103 * of the data TClasses.
104 */
105 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
106
107 /* tx_hdr_etclass
108 * Egress TClass to be used on the egress device on the egress port.
109 */
110 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
111
112 /* tx_hdr_port_mid
113 * Destination local port for unicast packets.
114 * Destination multicast ID for multicast packets.
115 *
116 * Control packets are directed to a specific egress port, while data
117 * packets are transmitted through the CPU port (0) into the switch partition,
118 * where forwarding rules are applied.
119 */
120 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
121
122 /* tx_hdr_fid
123 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
124 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
125 * Valid for data packets only.
126 */
127 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
128
129 /* tx_hdr_type
130 * 0 - Data packets
131 * 6 - Control packets
132 */
133 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
134
135 struct mlxsw_sp_mlxfw_dev {
136 struct mlxfw_dev mlxfw_dev;
137 struct mlxsw_sp *mlxsw_sp;
138 };
139
mlxsw_sp_component_query(struct mlxfw_dev * mlxfw_dev,u16 component_index,u32 * p_max_size,u8 * p_align_bits,u16 * p_max_write_size)140 static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
141 u16 component_index, u32 *p_max_size,
142 u8 *p_align_bits, u16 *p_max_write_size)
143 {
144 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
145 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
146 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
147 char mcqi_pl[MLXSW_REG_MCQI_LEN];
148 int err;
149
150 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
151 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
152 if (err)
153 return err;
154 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
155 p_max_write_size);
156
157 *p_align_bits = max_t(u8, *p_align_bits, 2);
158 *p_max_write_size = min_t(u16, *p_max_write_size,
159 MLXSW_REG_MCDA_MAX_DATA_LEN);
160 return 0;
161 }
162
mlxsw_sp_fsm_lock(struct mlxfw_dev * mlxfw_dev,u32 * fwhandle)163 static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
164 {
165 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
166 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
167 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
168 char mcc_pl[MLXSW_REG_MCC_LEN];
169 u8 control_state;
170 int err;
171
172 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
173 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
174 if (err)
175 return err;
176
177 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
178 if (control_state != MLXFW_FSM_STATE_IDLE)
179 return -EBUSY;
180
181 mlxsw_reg_mcc_pack(mcc_pl,
182 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
183 0, *fwhandle, 0);
184 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
185 }
186
mlxsw_sp_fsm_component_update(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,u16 component_index,u32 component_size)187 static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
188 u32 fwhandle, u16 component_index,
189 u32 component_size)
190 {
191 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
192 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
193 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
194 char mcc_pl[MLXSW_REG_MCC_LEN];
195
196 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
197 component_index, fwhandle, component_size);
198 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
199 }
200
mlxsw_sp_fsm_block_download(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,u8 * data,u16 size,u32 offset)201 static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
202 u32 fwhandle, u8 *data, u16 size,
203 u32 offset)
204 {
205 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
206 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
207 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
208 char mcda_pl[MLXSW_REG_MCDA_LEN];
209
210 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
211 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
212 }
213
mlxsw_sp_fsm_component_verify(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,u16 component_index)214 static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
215 u32 fwhandle, u16 component_index)
216 {
217 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
218 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
219 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
220 char mcc_pl[MLXSW_REG_MCC_LEN];
221
222 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
223 component_index, fwhandle, 0);
224 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
225 }
226
mlxsw_sp_fsm_activate(struct mlxfw_dev * mlxfw_dev,u32 fwhandle)227 static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
228 {
229 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
230 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
231 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
232 char mcc_pl[MLXSW_REG_MCC_LEN];
233
234 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
235 fwhandle, 0);
236 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
237 }
238
mlxsw_sp_fsm_query_state(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,enum mlxfw_fsm_state * fsm_state,enum mlxfw_fsm_state_err * fsm_state_err)239 static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
240 enum mlxfw_fsm_state *fsm_state,
241 enum mlxfw_fsm_state_err *fsm_state_err)
242 {
243 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
244 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
245 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
246 char mcc_pl[MLXSW_REG_MCC_LEN];
247 u8 control_state;
248 u8 error_code;
249 int err;
250
251 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
252 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
253 if (err)
254 return err;
255
256 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
257 *fsm_state = control_state;
258 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
259 MLXFW_FSM_STATE_ERR_MAX);
260 return 0;
261 }
262
mlxsw_sp_fsm_cancel(struct mlxfw_dev * mlxfw_dev,u32 fwhandle)263 static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
264 {
265 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
266 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
267 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
268 char mcc_pl[MLXSW_REG_MCC_LEN];
269
270 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
271 fwhandle, 0);
272 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
273 }
274
mlxsw_sp_fsm_release(struct mlxfw_dev * mlxfw_dev,u32 fwhandle)275 static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
276 {
277 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
278 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
279 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
280 char mcc_pl[MLXSW_REG_MCC_LEN];
281
282 mlxsw_reg_mcc_pack(mcc_pl,
283 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
284 fwhandle, 0);
285 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
286 }
287
288 static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
289 .component_query = mlxsw_sp_component_query,
290 .fsm_lock = mlxsw_sp_fsm_lock,
291 .fsm_component_update = mlxsw_sp_fsm_component_update,
292 .fsm_block_download = mlxsw_sp_fsm_block_download,
293 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
294 .fsm_activate = mlxsw_sp_fsm_activate,
295 .fsm_query_state = mlxsw_sp_fsm_query_state,
296 .fsm_cancel = mlxsw_sp_fsm_cancel,
297 .fsm_release = mlxsw_sp_fsm_release
298 };
299
mlxsw_sp_firmware_flash(struct mlxsw_sp * mlxsw_sp,const struct firmware * firmware)300 static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
301 const struct firmware *firmware)
302 {
303 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
304 .mlxfw_dev = {
305 .ops = &mlxsw_sp_mlxfw_dev_ops,
306 .psid = mlxsw_sp->bus_info->psid,
307 .psid_size = strlen(mlxsw_sp->bus_info->psid),
308 },
309 .mlxsw_sp = mlxsw_sp
310 };
311
312 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
313 }
314
mlxsw_sp_fw_rev_validate(struct mlxsw_sp * mlxsw_sp)315 static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
316 {
317 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
318 const struct mlxsw_fw_rev *req_rev = mlxsw_sp->req_rev;
319 const char *fw_filename = mlxsw_sp->fw_filename;
320 const struct firmware *firmware;
321 int err;
322
323 /* Don't check if driver does not require it */
324 if (!req_rev || !fw_filename)
325 return 0;
326
327 /* Validate driver & FW are compatible */
328 if (rev->major != req_rev->major) {
329 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
330 rev->major, req_rev->major);
331 return -EINVAL;
332 }
333 if (MLXSW_SP_FWREV_MINOR_TO_BRANCH(rev->minor) ==
334 MLXSW_SP_FWREV_MINOR_TO_BRANCH(req_rev->minor))
335 return 0;
336
337 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n",
338 rev->major, rev->minor, rev->subminor);
339 dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
340 fw_filename);
341
342 err = request_firmware_direct(&firmware, fw_filename,
343 mlxsw_sp->bus_info->dev);
344 if (err) {
345 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
346 fw_filename);
347 return err;
348 }
349
350 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
351 release_firmware(firmware);
352 if (err)
353 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
354
355 /* On FW flash success, tell the caller FW reset is needed
356 * if current FW supports it.
357 */
358 if (rev->minor >= req_rev->can_reset_minor)
359 return err ? err : -EAGAIN;
360 else
361 return 0;
362 }
363
mlxsw_sp_flow_counter_get(struct mlxsw_sp * mlxsw_sp,unsigned int counter_index,u64 * packets,u64 * bytes)364 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
365 unsigned int counter_index, u64 *packets,
366 u64 *bytes)
367 {
368 char mgpc_pl[MLXSW_REG_MGPC_LEN];
369 int err;
370
371 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
372 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
373 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
374 if (err)
375 return err;
376 if (packets)
377 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
378 if (bytes)
379 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
380 return 0;
381 }
382
mlxsw_sp_flow_counter_clear(struct mlxsw_sp * mlxsw_sp,unsigned int counter_index)383 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
384 unsigned int counter_index)
385 {
386 char mgpc_pl[MLXSW_REG_MGPC_LEN];
387
388 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
389 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
390 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
391 }
392
mlxsw_sp_flow_counter_alloc(struct mlxsw_sp * mlxsw_sp,unsigned int * p_counter_index)393 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
394 unsigned int *p_counter_index)
395 {
396 int err;
397
398 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
399 p_counter_index);
400 if (err)
401 return err;
402 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
403 if (err)
404 goto err_counter_clear;
405 return 0;
406
407 err_counter_clear:
408 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
409 *p_counter_index);
410 return err;
411 }
412
mlxsw_sp_flow_counter_free(struct mlxsw_sp * mlxsw_sp,unsigned int counter_index)413 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
414 unsigned int counter_index)
415 {
416 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
417 counter_index);
418 }
419
mlxsw_sp_txhdr_construct(struct sk_buff * skb,const struct mlxsw_tx_info * tx_info)420 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
421 const struct mlxsw_tx_info *tx_info)
422 {
423 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
424
425 memset(txhdr, 0, MLXSW_TXHDR_LEN);
426
427 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
428 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
429 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
430 mlxsw_tx_hdr_swid_set(txhdr, 0);
431 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
432 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
433 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
434 }
435
mlxsw_sp_stp_spms_state(u8 state)436 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state)
437 {
438 switch (state) {
439 case BR_STATE_FORWARDING:
440 return MLXSW_REG_SPMS_STATE_FORWARDING;
441 case BR_STATE_LEARNING:
442 return MLXSW_REG_SPMS_STATE_LEARNING;
443 case BR_STATE_LISTENING: /* fall-through */
444 case BR_STATE_DISABLED: /* fall-through */
445 case BR_STATE_BLOCKING:
446 return MLXSW_REG_SPMS_STATE_DISCARDING;
447 default:
448 BUG();
449 }
450 }
451
mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid,u8 state)452 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
453 u8 state)
454 {
455 enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state);
456 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
457 char *spms_pl;
458 int err;
459
460 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
461 if (!spms_pl)
462 return -ENOMEM;
463 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
464 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
465
466 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
467 kfree(spms_pl);
468 return err;
469 }
470
mlxsw_sp_base_mac_get(struct mlxsw_sp * mlxsw_sp)471 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
472 {
473 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
474 int err;
475
476 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
477 if (err)
478 return err;
479 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
480 return 0;
481 }
482
mlxsw_sp_port_sample_set(struct mlxsw_sp_port * mlxsw_sp_port,bool enable,u32 rate)483 static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
484 bool enable, u32 rate)
485 {
486 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
487 char mpsc_pl[MLXSW_REG_MPSC_LEN];
488
489 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
490 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
491 }
492
mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port * mlxsw_sp_port,bool is_up)493 static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
494 bool is_up)
495 {
496 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
497 char paos_pl[MLXSW_REG_PAOS_LEN];
498
499 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
500 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
501 MLXSW_PORT_ADMIN_STATUS_DOWN);
502 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
503 }
504
mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port * mlxsw_sp_port,unsigned char * addr)505 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
506 unsigned char *addr)
507 {
508 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
509 char ppad_pl[MLXSW_REG_PPAD_LEN];
510
511 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
512 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
513 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
514 }
515
mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port * mlxsw_sp_port)516 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
517 {
518 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
519 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
520
521 ether_addr_copy(addr, mlxsw_sp->base_mac);
522 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
523 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
524 }
525
mlxsw_sp_port_mtu_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 mtu)526 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
527 {
528 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
529 char pmtu_pl[MLXSW_REG_PMTU_LEN];
530 int max_mtu;
531 int err;
532
533 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
534 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
535 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
536 if (err)
537 return err;
538 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
539
540 if (mtu > max_mtu)
541 return -EINVAL;
542
543 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
544 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
545 }
546
mlxsw_sp_port_swid_set(struct mlxsw_sp_port * mlxsw_sp_port,u8 swid)547 static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
548 {
549 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
550 char pspa_pl[MLXSW_REG_PSPA_LEN];
551
552 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
553 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
554 }
555
mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port * mlxsw_sp_port,bool enable)556 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
557 {
558 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
559 char svpe_pl[MLXSW_REG_SVPE_LEN];
560
561 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
562 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
563 }
564
mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid,bool learn_enable)565 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
566 bool learn_enable)
567 {
568 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
569 char *spvmlr_pl;
570 int err;
571
572 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
573 if (!spvmlr_pl)
574 return -ENOMEM;
575 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
576 learn_enable);
577 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
578 kfree(spvmlr_pl);
579 return err;
580 }
581
__mlxsw_sp_port_pvid_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid)582 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
583 u16 vid)
584 {
585 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
586 char spvid_pl[MLXSW_REG_SPVID_LEN];
587
588 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
589 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
590 }
591
mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port * mlxsw_sp_port,bool allow)592 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
593 bool allow)
594 {
595 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
596 char spaft_pl[MLXSW_REG_SPAFT_LEN];
597
598 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
599 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
600 }
601
mlxsw_sp_port_pvid_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid)602 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
603 {
604 int err;
605
606 if (!vid) {
607 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
608 if (err)
609 return err;
610 } else {
611 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
612 if (err)
613 return err;
614 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
615 if (err)
616 goto err_port_allow_untagged_set;
617 }
618
619 mlxsw_sp_port->pvid = vid;
620 return 0;
621
622 err_port_allow_untagged_set:
623 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
624 return err;
625 }
626
627 static int
mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port * mlxsw_sp_port)628 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
629 {
630 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
631 char sspr_pl[MLXSW_REG_SSPR_LEN];
632
633 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
634 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
635 }
636
mlxsw_sp_port_module_info_get(struct mlxsw_sp * mlxsw_sp,u8 local_port,u8 * p_module,u8 * p_width,u8 * p_lane)637 static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
638 u8 local_port, u8 *p_module,
639 u8 *p_width, u8 *p_lane)
640 {
641 char pmlp_pl[MLXSW_REG_PMLP_LEN];
642 int err;
643
644 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
645 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
646 if (err)
647 return err;
648 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
649 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
650 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
651 return 0;
652 }
653
mlxsw_sp_port_module_map(struct mlxsw_sp_port * mlxsw_sp_port,u8 module,u8 width,u8 lane)654 static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
655 u8 module, u8 width, u8 lane)
656 {
657 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
658 char pmlp_pl[MLXSW_REG_PMLP_LEN];
659 int i;
660
661 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
662 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
663 for (i = 0; i < width; i++) {
664 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
665 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
666 }
667
668 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
669 }
670
mlxsw_sp_port_module_unmap(struct mlxsw_sp_port * mlxsw_sp_port)671 static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
672 {
673 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
674 char pmlp_pl[MLXSW_REG_PMLP_LEN];
675
676 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
677 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
678 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
679 }
680
mlxsw_sp_port_open(struct net_device * dev)681 static int mlxsw_sp_port_open(struct net_device *dev)
682 {
683 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
684 int err;
685
686 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
687 if (err)
688 return err;
689 netif_start_queue(dev);
690 return 0;
691 }
692
mlxsw_sp_port_stop(struct net_device * dev)693 static int mlxsw_sp_port_stop(struct net_device *dev)
694 {
695 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
696
697 netif_stop_queue(dev);
698 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
699 }
700
mlxsw_sp_port_xmit(struct sk_buff * skb,struct net_device * dev)701 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
702 struct net_device *dev)
703 {
704 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
705 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
706 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
707 const struct mlxsw_tx_info tx_info = {
708 .local_port = mlxsw_sp_port->local_port,
709 .is_emad = false,
710 };
711 u64 len;
712 int err;
713
714 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
715 return NETDEV_TX_BUSY;
716
717 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
718 struct sk_buff *skb_orig = skb;
719
720 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
721 if (!skb) {
722 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
723 dev_kfree_skb_any(skb_orig);
724 return NETDEV_TX_OK;
725 }
726 dev_consume_skb_any(skb_orig);
727 }
728
729 if (eth_skb_pad(skb)) {
730 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
731 return NETDEV_TX_OK;
732 }
733
734 mlxsw_sp_txhdr_construct(skb, &tx_info);
735 /* TX header is consumed by HW on the way so we shouldn't count its
736 * bytes as being sent.
737 */
738 len = skb->len - MLXSW_TXHDR_LEN;
739
740 /* Due to a race we might fail here because of a full queue. In that
741 * unlikely case we simply drop the packet.
742 */
743 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
744
745 if (!err) {
746 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
747 u64_stats_update_begin(&pcpu_stats->syncp);
748 pcpu_stats->tx_packets++;
749 pcpu_stats->tx_bytes += len;
750 u64_stats_update_end(&pcpu_stats->syncp);
751 } else {
752 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
753 dev_kfree_skb_any(skb);
754 }
755 return NETDEV_TX_OK;
756 }
757
mlxsw_sp_set_rx_mode(struct net_device * dev)758 static void mlxsw_sp_set_rx_mode(struct net_device *dev)
759 {
760 }
761
mlxsw_sp_port_set_mac_address(struct net_device * dev,void * p)762 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
763 {
764 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
765 struct sockaddr *addr = p;
766 int err;
767
768 if (!is_valid_ether_addr(addr->sa_data))
769 return -EADDRNOTAVAIL;
770
771 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
772 if (err)
773 return err;
774 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
775 return 0;
776 }
777
mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp * mlxsw_sp,int mtu)778 static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
779 int mtu)
780 {
781 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
782 }
783
784 #define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
785
mlxsw_sp_pfc_delay_get(const struct mlxsw_sp * mlxsw_sp,int mtu,u16 delay)786 static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
787 u16 delay)
788 {
789 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
790 BITS_PER_BYTE));
791 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
792 mtu);
793 }
794
795 /* Maximum delay buffer needed in case of PAUSE frames, in bytes.
796 * Assumes 100m cable and maximum MTU.
797 */
798 #define MLXSW_SP_PAUSE_DELAY 58752
799
mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp * mlxsw_sp,int mtu,u16 delay,bool pfc,bool pause)800 static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
801 u16 delay, bool pfc, bool pause)
802 {
803 if (pfc)
804 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
805 else if (pause)
806 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
807 else
808 return 0;
809 }
810
mlxsw_sp_pg_buf_pack(char * pbmc_pl,int index,u16 size,u16 thres,bool lossy)811 static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
812 bool lossy)
813 {
814 if (lossy)
815 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
816 else
817 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
818 thres);
819 }
820
__mlxsw_sp_port_headroom_set(struct mlxsw_sp_port * mlxsw_sp_port,int mtu,u8 * prio_tc,bool pause_en,struct ieee_pfc * my_pfc)821 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
822 u8 *prio_tc, bool pause_en,
823 struct ieee_pfc *my_pfc)
824 {
825 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
826 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
827 u16 delay = !!my_pfc ? my_pfc->delay : 0;
828 char pbmc_pl[MLXSW_REG_PBMC_LEN];
829 int i, j, err;
830
831 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
832 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
833 if (err)
834 return err;
835
836 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
837 bool configure = false;
838 bool pfc = false;
839 bool lossy;
840 u16 thres;
841
842 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
843 if (prio_tc[j] == i) {
844 pfc = pfc_en & BIT(j);
845 configure = true;
846 break;
847 }
848 }
849
850 if (!configure)
851 continue;
852
853 lossy = !(pfc || pause_en);
854 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
855 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
856 pause_en);
857 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
858 }
859
860 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
861 }
862
mlxsw_sp_port_headroom_set(struct mlxsw_sp_port * mlxsw_sp_port,int mtu,bool pause_en)863 static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
864 int mtu, bool pause_en)
865 {
866 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
867 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
868 struct ieee_pfc *my_pfc;
869 u8 *prio_tc;
870
871 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
872 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
873
874 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
875 pause_en, my_pfc);
876 }
877
mlxsw_sp_port_change_mtu(struct net_device * dev,int mtu)878 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
879 {
880 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
881 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
882 int err;
883
884 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
885 if (err)
886 return err;
887 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
888 if (err)
889 goto err_span_port_mtu_update;
890 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
891 if (err)
892 goto err_port_mtu_set;
893 dev->mtu = mtu;
894 return 0;
895
896 err_port_mtu_set:
897 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
898 err_span_port_mtu_update:
899 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
900 return err;
901 }
902
903 static int
mlxsw_sp_port_get_sw_stats64(const struct net_device * dev,struct rtnl_link_stats64 * stats)904 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
905 struct rtnl_link_stats64 *stats)
906 {
907 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
908 struct mlxsw_sp_port_pcpu_stats *p;
909 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
910 u32 tx_dropped = 0;
911 unsigned int start;
912 int i;
913
914 for_each_possible_cpu(i) {
915 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
916 do {
917 start = u64_stats_fetch_begin_irq(&p->syncp);
918 rx_packets = p->rx_packets;
919 rx_bytes = p->rx_bytes;
920 tx_packets = p->tx_packets;
921 tx_bytes = p->tx_bytes;
922 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
923
924 stats->rx_packets += rx_packets;
925 stats->rx_bytes += rx_bytes;
926 stats->tx_packets += tx_packets;
927 stats->tx_bytes += tx_bytes;
928 /* tx_dropped is u32, updated without syncp protection. */
929 tx_dropped += p->tx_dropped;
930 }
931 stats->tx_dropped = tx_dropped;
932 return 0;
933 }
934
mlxsw_sp_port_has_offload_stats(const struct net_device * dev,int attr_id)935 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
936 {
937 switch (attr_id) {
938 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
939 return true;
940 }
941
942 return false;
943 }
944
mlxsw_sp_port_get_offload_stats(int attr_id,const struct net_device * dev,void * sp)945 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
946 void *sp)
947 {
948 switch (attr_id) {
949 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
950 return mlxsw_sp_port_get_sw_stats64(dev, sp);
951 }
952
953 return -EINVAL;
954 }
955
mlxsw_sp_port_get_stats_raw(struct net_device * dev,int grp,int prio,char * ppcnt_pl)956 static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
957 int prio, char *ppcnt_pl)
958 {
959 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
960 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
961
962 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
963 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
964 }
965
mlxsw_sp_port_get_hw_stats(struct net_device * dev,struct rtnl_link_stats64 * stats)966 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
967 struct rtnl_link_stats64 *stats)
968 {
969 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
970 int err;
971
972 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
973 0, ppcnt_pl);
974 if (err)
975 goto out;
976
977 stats->tx_packets =
978 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
979 stats->rx_packets =
980 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
981 stats->tx_bytes =
982 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
983 stats->rx_bytes =
984 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
985 stats->multicast =
986 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
987
988 stats->rx_crc_errors =
989 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
990 stats->rx_frame_errors =
991 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
992
993 stats->rx_length_errors = (
994 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
995 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
996 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
997
998 stats->rx_errors = (stats->rx_crc_errors +
999 stats->rx_frame_errors + stats->rx_length_errors);
1000
1001 out:
1002 return err;
1003 }
1004
1005 static void
mlxsw_sp_port_get_hw_xstats(struct net_device * dev,struct mlxsw_sp_port_xstats * xstats)1006 mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1007 struct mlxsw_sp_port_xstats *xstats)
1008 {
1009 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1010 int err, i;
1011
1012 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1013 ppcnt_pl);
1014 if (!err)
1015 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1016
1017 for (i = 0; i < TC_MAX_QUEUE; i++) {
1018 err = mlxsw_sp_port_get_stats_raw(dev,
1019 MLXSW_REG_PPCNT_TC_CONG_TC,
1020 i, ppcnt_pl);
1021 if (!err)
1022 xstats->wred_drop[i] =
1023 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1024
1025 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1026 i, ppcnt_pl);
1027 if (err)
1028 continue;
1029
1030 xstats->backlog[i] =
1031 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1032 xstats->tail_drop[i] =
1033 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1034 }
1035
1036 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1037 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
1038 i, ppcnt_pl);
1039 if (err)
1040 continue;
1041
1042 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
1043 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
1044 }
1045 }
1046
update_stats_cache(struct work_struct * work)1047 static void update_stats_cache(struct work_struct *work)
1048 {
1049 struct mlxsw_sp_port *mlxsw_sp_port =
1050 container_of(work, struct mlxsw_sp_port,
1051 periodic_hw_stats.update_dw.work);
1052
1053 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1054 goto out;
1055
1056 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
1057 &mlxsw_sp_port->periodic_hw_stats.stats);
1058 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1059 &mlxsw_sp_port->periodic_hw_stats.xstats);
1060
1061 out:
1062 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
1063 MLXSW_HW_STATS_UPDATE_TIME);
1064 }
1065
1066 /* Return the stats from a cache that is updated periodically,
1067 * as this function might get called in an atomic context.
1068 */
1069 static void
mlxsw_sp_port_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * stats)1070 mlxsw_sp_port_get_stats64(struct net_device *dev,
1071 struct rtnl_link_stats64 *stats)
1072 {
1073 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1074
1075 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
1076 }
1077
__mlxsw_sp_port_vlan_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid_begin,u16 vid_end,bool is_member,bool untagged)1078 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1079 u16 vid_begin, u16 vid_end,
1080 bool is_member, bool untagged)
1081 {
1082 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1083 char *spvm_pl;
1084 int err;
1085
1086 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1087 if (!spvm_pl)
1088 return -ENOMEM;
1089
1090 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1091 vid_end, is_member, untagged);
1092 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1093 kfree(spvm_pl);
1094 return err;
1095 }
1096
mlxsw_sp_port_vlan_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid_begin,u16 vid_end,bool is_member,bool untagged)1097 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1098 u16 vid_end, bool is_member, bool untagged)
1099 {
1100 u16 vid, vid_e;
1101 int err;
1102
1103 for (vid = vid_begin; vid <= vid_end;
1104 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1105 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1106 vid_end);
1107
1108 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1109 is_member, untagged);
1110 if (err)
1111 return err;
1112 }
1113
1114 return 0;
1115 }
1116
mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port * mlxsw_sp_port)1117 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
1118 {
1119 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
1120
1121 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1122 &mlxsw_sp_port->vlans_list, list)
1123 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
1124 }
1125
1126 static struct mlxsw_sp_port_vlan *
mlxsw_sp_port_vlan_create(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid)1127 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1128 {
1129 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1130 bool untagged = vid == 1;
1131 int err;
1132
1133 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1134 if (err)
1135 return ERR_PTR(err);
1136
1137 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
1138 if (!mlxsw_sp_port_vlan) {
1139 err = -ENOMEM;
1140 goto err_port_vlan_alloc;
1141 }
1142
1143 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1144 mlxsw_sp_port_vlan->ref_count = 1;
1145 mlxsw_sp_port_vlan->vid = vid;
1146 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1147
1148 return mlxsw_sp_port_vlan;
1149
1150 err_port_vlan_alloc:
1151 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1152 return ERR_PTR(err);
1153 }
1154
1155 static void
mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan * mlxsw_sp_port_vlan)1156 mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1157 {
1158 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1159 u16 vid = mlxsw_sp_port_vlan->vid;
1160
1161 list_del(&mlxsw_sp_port_vlan->list);
1162 kfree(mlxsw_sp_port_vlan);
1163 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1164 }
1165
1166 struct mlxsw_sp_port_vlan *
mlxsw_sp_port_vlan_get(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid)1167 mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1168 {
1169 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1170
1171 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1172 if (mlxsw_sp_port_vlan) {
1173 mlxsw_sp_port_vlan->ref_count++;
1174 return mlxsw_sp_port_vlan;
1175 }
1176
1177 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1178 }
1179
mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan * mlxsw_sp_port_vlan)1180 void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1181 {
1182 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1183
1184 if (--mlxsw_sp_port_vlan->ref_count != 0)
1185 return;
1186
1187 if (mlxsw_sp_port_vlan->bridge_port)
1188 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
1189 else if (fid)
1190 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
1191
1192 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1193 }
1194
mlxsw_sp_port_add_vid(struct net_device * dev,__be16 __always_unused proto,u16 vid)1195 static int mlxsw_sp_port_add_vid(struct net_device *dev,
1196 __be16 __always_unused proto, u16 vid)
1197 {
1198 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1199
1200 /* VLAN 0 is added to HW filter when device goes up, but it is
1201 * reserved in our case, so simply return.
1202 */
1203 if (!vid)
1204 return 0;
1205
1206 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
1207 }
1208
mlxsw_sp_port_kill_vid(struct net_device * dev,__be16 __always_unused proto,u16 vid)1209 static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1210 __be16 __always_unused proto, u16 vid)
1211 {
1212 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1213 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1214
1215 /* VLAN 0 is removed from HW filter when device goes down, but
1216 * it is reserved in our case, so simply return.
1217 */
1218 if (!vid)
1219 return 0;
1220
1221 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1222 if (!mlxsw_sp_port_vlan)
1223 return 0;
1224 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
1225
1226 return 0;
1227 }
1228
mlxsw_sp_port_get_phys_port_name(struct net_device * dev,char * name,size_t len)1229 static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1230 size_t len)
1231 {
1232 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1233
1234 return mlxsw_core_port_get_phys_port_name(mlxsw_sp_port->mlxsw_sp->core,
1235 mlxsw_sp_port->local_port,
1236 name, len);
1237 }
1238
1239 static struct mlxsw_sp_port_mall_tc_entry *
mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port * port,unsigned long cookie)1240 mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1241 unsigned long cookie) {
1242 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1243
1244 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1245 if (mall_tc_entry->cookie == cookie)
1246 return mall_tc_entry;
1247
1248 return NULL;
1249 }
1250
1251 static int
mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port * mlxsw_sp_port,struct mlxsw_sp_port_mall_mirror_tc_entry * mirror,const struct tc_action * a,bool ingress)1252 mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1253 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
1254 const struct tc_action *a,
1255 bool ingress)
1256 {
1257 enum mlxsw_sp_span_type span_type;
1258 struct net_device *to_dev;
1259
1260 to_dev = tcf_mirred_dev(a);
1261 if (!to_dev) {
1262 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1263 return -EINVAL;
1264 }
1265
1266 mirror->ingress = ingress;
1267 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1268 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_dev, span_type,
1269 true, &mirror->span_id);
1270 }
1271
1272 static void
mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port * mlxsw_sp_port,struct mlxsw_sp_port_mall_mirror_tc_entry * mirror)1273 mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1274 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1275 {
1276 enum mlxsw_sp_span_type span_type;
1277
1278 span_type = mirror->ingress ?
1279 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1280 mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id,
1281 span_type, true);
1282 }
1283
1284 static int
mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port * mlxsw_sp_port,struct tc_cls_matchall_offload * cls,const struct tc_action * a,bool ingress)1285 mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1286 struct tc_cls_matchall_offload *cls,
1287 const struct tc_action *a,
1288 bool ingress)
1289 {
1290 int err;
1291
1292 if (!mlxsw_sp_port->sample)
1293 return -EOPNOTSUPP;
1294 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1295 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1296 return -EEXIST;
1297 }
1298 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1299 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1300 return -EOPNOTSUPP;
1301 }
1302
1303 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1304 tcf_sample_psample_group(a));
1305 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1306 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1307 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1308
1309 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1310 if (err)
1311 goto err_port_sample_set;
1312 return 0;
1313
1314 err_port_sample_set:
1315 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1316 return err;
1317 }
1318
1319 static void
mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port * mlxsw_sp_port)1320 mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1321 {
1322 if (!mlxsw_sp_port->sample)
1323 return;
1324
1325 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1326 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1327 }
1328
mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port * mlxsw_sp_port,struct tc_cls_matchall_offload * f,bool ingress)1329 static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1330 struct tc_cls_matchall_offload *f,
1331 bool ingress)
1332 {
1333 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1334 __be16 protocol = f->common.protocol;
1335 const struct tc_action *a;
1336 LIST_HEAD(actions);
1337 int err;
1338
1339 if (!tcf_exts_has_one_action(f->exts)) {
1340 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
1341 return -EOPNOTSUPP;
1342 }
1343
1344 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1345 if (!mall_tc_entry)
1346 return -ENOMEM;
1347 mall_tc_entry->cookie = f->cookie;
1348
1349 a = tcf_exts_first_action(f->exts);
1350
1351 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1352 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1353
1354 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1355 mirror = &mall_tc_entry->mirror;
1356 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1357 mirror, a, ingress);
1358 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1359 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
1360 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
1361 a, ingress);
1362 } else {
1363 err = -EOPNOTSUPP;
1364 }
1365
1366 if (err)
1367 goto err_add_action;
1368
1369 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
1370 return 0;
1371
1372 err_add_action:
1373 kfree(mall_tc_entry);
1374 return err;
1375 }
1376
mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port * mlxsw_sp_port,struct tc_cls_matchall_offload * f)1377 static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1378 struct tc_cls_matchall_offload *f)
1379 {
1380 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1381
1382 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
1383 f->cookie);
1384 if (!mall_tc_entry) {
1385 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1386 return;
1387 }
1388 list_del(&mall_tc_entry->list);
1389
1390 switch (mall_tc_entry->type) {
1391 case MLXSW_SP_PORT_MALL_MIRROR:
1392 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1393 &mall_tc_entry->mirror);
1394 break;
1395 case MLXSW_SP_PORT_MALL_SAMPLE:
1396 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1397 break;
1398 default:
1399 WARN_ON(1);
1400 }
1401
1402 kfree(mall_tc_entry);
1403 }
1404
mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port * mlxsw_sp_port,struct tc_cls_matchall_offload * f,bool ingress)1405 static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1406 struct tc_cls_matchall_offload *f,
1407 bool ingress)
1408 {
1409 switch (f->command) {
1410 case TC_CLSMATCHALL_REPLACE:
1411 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
1412 ingress);
1413 case TC_CLSMATCHALL_DESTROY:
1414 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1415 return 0;
1416 default:
1417 return -EOPNOTSUPP;
1418 }
1419 }
1420
1421 static int
mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block * acl_block,struct tc_cls_flower_offload * f)1422 mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1423 struct tc_cls_flower_offload *f)
1424 {
1425 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1426
1427 switch (f->command) {
1428 case TC_CLSFLOWER_REPLACE:
1429 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
1430 case TC_CLSFLOWER_DESTROY:
1431 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
1432 return 0;
1433 case TC_CLSFLOWER_STATS:
1434 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
1435 case TC_CLSFLOWER_TMPLT_CREATE:
1436 return mlxsw_sp_flower_tmplt_create(mlxsw_sp, acl_block, f);
1437 case TC_CLSFLOWER_TMPLT_DESTROY:
1438 mlxsw_sp_flower_tmplt_destroy(mlxsw_sp, acl_block, f);
1439 return 0;
1440 default:
1441 return -EOPNOTSUPP;
1442 }
1443 }
1444
mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,void * type_data,void * cb_priv,bool ingress)1445 static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1446 void *type_data,
1447 void *cb_priv, bool ingress)
1448 {
1449 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1450
1451 switch (type) {
1452 case TC_SETUP_CLSMATCHALL:
1453 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev,
1454 type_data))
1455 return -EOPNOTSUPP;
1456
1457 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1458 ingress);
1459 case TC_SETUP_CLSFLOWER:
1460 return 0;
1461 default:
1462 return -EOPNOTSUPP;
1463 }
1464 }
1465
mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,void * type_data,void * cb_priv)1466 static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1467 void *type_data,
1468 void *cb_priv)
1469 {
1470 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1471 cb_priv, true);
1472 }
1473
mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,void * type_data,void * cb_priv)1474 static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1475 void *type_data,
1476 void *cb_priv)
1477 {
1478 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1479 cb_priv, false);
1480 }
1481
mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,void * type_data,void * cb_priv)1482 static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1483 void *type_data, void *cb_priv)
1484 {
1485 struct mlxsw_sp_acl_block *acl_block = cb_priv;
1486
1487 switch (type) {
1488 case TC_SETUP_CLSMATCHALL:
1489 return 0;
1490 case TC_SETUP_CLSFLOWER:
1491 if (mlxsw_sp_acl_block_disabled(acl_block))
1492 return -EOPNOTSUPP;
1493
1494 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1495 default:
1496 return -EOPNOTSUPP;
1497 }
1498 }
1499
1500 static int
mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port * mlxsw_sp_port,struct tcf_block * block,bool ingress,struct netlink_ext_ack * extack)1501 mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
1502 struct tcf_block *block, bool ingress,
1503 struct netlink_ext_ack *extack)
1504 {
1505 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1506 struct mlxsw_sp_acl_block *acl_block;
1507 struct tcf_block_cb *block_cb;
1508 int err;
1509
1510 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1511 mlxsw_sp);
1512 if (!block_cb) {
1513 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net);
1514 if (!acl_block)
1515 return -ENOMEM;
1516 block_cb = __tcf_block_cb_register(block,
1517 mlxsw_sp_setup_tc_block_cb_flower,
1518 mlxsw_sp, acl_block, extack);
1519 if (IS_ERR(block_cb)) {
1520 err = PTR_ERR(block_cb);
1521 goto err_cb_register;
1522 }
1523 } else {
1524 acl_block = tcf_block_cb_priv(block_cb);
1525 }
1526 tcf_block_cb_incref(block_cb);
1527 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1528 mlxsw_sp_port, ingress);
1529 if (err)
1530 goto err_block_bind;
1531
1532 if (ingress)
1533 mlxsw_sp_port->ing_acl_block = acl_block;
1534 else
1535 mlxsw_sp_port->eg_acl_block = acl_block;
1536
1537 return 0;
1538
1539 err_block_bind:
1540 if (!tcf_block_cb_decref(block_cb)) {
1541 __tcf_block_cb_unregister(block, block_cb);
1542 err_cb_register:
1543 mlxsw_sp_acl_block_destroy(acl_block);
1544 }
1545 return err;
1546 }
1547
1548 static void
mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port * mlxsw_sp_port,struct tcf_block * block,bool ingress)1549 mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1550 struct tcf_block *block, bool ingress)
1551 {
1552 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1553 struct mlxsw_sp_acl_block *acl_block;
1554 struct tcf_block_cb *block_cb;
1555 int err;
1556
1557 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1558 mlxsw_sp);
1559 if (!block_cb)
1560 return;
1561
1562 if (ingress)
1563 mlxsw_sp_port->ing_acl_block = NULL;
1564 else
1565 mlxsw_sp_port->eg_acl_block = NULL;
1566
1567 acl_block = tcf_block_cb_priv(block_cb);
1568 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1569 mlxsw_sp_port, ingress);
1570 if (!err && !tcf_block_cb_decref(block_cb)) {
1571 __tcf_block_cb_unregister(block, block_cb);
1572 mlxsw_sp_acl_block_destroy(acl_block);
1573 }
1574 }
1575
mlxsw_sp_setup_tc_block(struct mlxsw_sp_port * mlxsw_sp_port,struct tc_block_offload * f)1576 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1577 struct tc_block_offload *f)
1578 {
1579 tc_setup_cb_t *cb;
1580 bool ingress;
1581 int err;
1582
1583 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1584 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1585 ingress = true;
1586 } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1587 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1588 ingress = false;
1589 } else {
1590 return -EOPNOTSUPP;
1591 }
1592
1593 switch (f->command) {
1594 case TC_BLOCK_BIND:
1595 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
1596 mlxsw_sp_port, f->extack);
1597 if (err)
1598 return err;
1599 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port,
1600 f->block, ingress,
1601 f->extack);
1602 if (err) {
1603 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1604 return err;
1605 }
1606 return 0;
1607 case TC_BLOCK_UNBIND:
1608 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1609 f->block, ingress);
1610 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1611 return 0;
1612 default:
1613 return -EOPNOTSUPP;
1614 }
1615 }
1616
mlxsw_sp_setup_tc(struct net_device * dev,enum tc_setup_type type,void * type_data)1617 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
1618 void *type_data)
1619 {
1620 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1621
1622 switch (type) {
1623 case TC_SETUP_BLOCK:
1624 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
1625 case TC_SETUP_QDISC_RED:
1626 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
1627 case TC_SETUP_QDISC_PRIO:
1628 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
1629 default:
1630 return -EOPNOTSUPP;
1631 }
1632 }
1633
1634
mlxsw_sp_feature_hw_tc(struct net_device * dev,bool enable)1635 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1636 {
1637 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1638
1639 if (!enable) {
1640 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1641 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1642 !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1643 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1644 return -EINVAL;
1645 }
1646 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1647 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1648 } else {
1649 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
1650 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
1651 }
1652 return 0;
1653 }
1654
1655 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1656
mlxsw_sp_handle_feature(struct net_device * dev,netdev_features_t wanted_features,netdev_features_t feature,mlxsw_sp_feature_handler feature_handler)1657 static int mlxsw_sp_handle_feature(struct net_device *dev,
1658 netdev_features_t wanted_features,
1659 netdev_features_t feature,
1660 mlxsw_sp_feature_handler feature_handler)
1661 {
1662 netdev_features_t changes = wanted_features ^ dev->features;
1663 bool enable = !!(wanted_features & feature);
1664 int err;
1665
1666 if (!(changes & feature))
1667 return 0;
1668
1669 err = feature_handler(dev, enable);
1670 if (err) {
1671 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1672 enable ? "Enable" : "Disable", &feature, err);
1673 return err;
1674 }
1675
1676 if (enable)
1677 dev->features |= feature;
1678 else
1679 dev->features &= ~feature;
1680
1681 return 0;
1682 }
mlxsw_sp_set_features(struct net_device * dev,netdev_features_t features)1683 static int mlxsw_sp_set_features(struct net_device *dev,
1684 netdev_features_t features)
1685 {
1686 return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1687 mlxsw_sp_feature_hw_tc);
1688 }
1689
1690 static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1691 .ndo_open = mlxsw_sp_port_open,
1692 .ndo_stop = mlxsw_sp_port_stop,
1693 .ndo_start_xmit = mlxsw_sp_port_xmit,
1694 .ndo_setup_tc = mlxsw_sp_setup_tc,
1695 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
1696 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1697 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1698 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
1699 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1700 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
1701 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1702 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
1703 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
1704 .ndo_set_features = mlxsw_sp_set_features,
1705 };
1706
mlxsw_sp_port_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * drvinfo)1707 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1708 struct ethtool_drvinfo *drvinfo)
1709 {
1710 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1711 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1712
1713 strlcpy(drvinfo->driver, mlxsw_sp->bus_info->device_kind,
1714 sizeof(drvinfo->driver));
1715 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1716 sizeof(drvinfo->version));
1717 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1718 "%d.%d.%d",
1719 mlxsw_sp->bus_info->fw_rev.major,
1720 mlxsw_sp->bus_info->fw_rev.minor,
1721 mlxsw_sp->bus_info->fw_rev.subminor);
1722 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1723 sizeof(drvinfo->bus_info));
1724 }
1725
mlxsw_sp_port_get_pauseparam(struct net_device * dev,struct ethtool_pauseparam * pause)1726 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1727 struct ethtool_pauseparam *pause)
1728 {
1729 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1730
1731 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1732 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1733 }
1734
mlxsw_sp_port_pause_set(struct mlxsw_sp_port * mlxsw_sp_port,struct ethtool_pauseparam * pause)1735 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1736 struct ethtool_pauseparam *pause)
1737 {
1738 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1739
1740 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1741 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1742 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1743
1744 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1745 pfcc_pl);
1746 }
1747
mlxsw_sp_port_set_pauseparam(struct net_device * dev,struct ethtool_pauseparam * pause)1748 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1749 struct ethtool_pauseparam *pause)
1750 {
1751 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1752 bool pause_en = pause->tx_pause || pause->rx_pause;
1753 int err;
1754
1755 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1756 netdev_err(dev, "PFC already enabled on port\n");
1757 return -EINVAL;
1758 }
1759
1760 if (pause->autoneg) {
1761 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1762 return -EINVAL;
1763 }
1764
1765 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1766 if (err) {
1767 netdev_err(dev, "Failed to configure port's headroom\n");
1768 return err;
1769 }
1770
1771 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1772 if (err) {
1773 netdev_err(dev, "Failed to set PAUSE parameters\n");
1774 goto err_port_pause_configure;
1775 }
1776
1777 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1778 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1779
1780 return 0;
1781
1782 err_port_pause_configure:
1783 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1784 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1785 return err;
1786 }
1787
1788 struct mlxsw_sp_port_hw_stats {
1789 char str[ETH_GSTRING_LEN];
1790 u64 (*getter)(const char *payload);
1791 bool cells_bytes;
1792 };
1793
1794 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
1795 {
1796 .str = "a_frames_transmitted_ok",
1797 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1798 },
1799 {
1800 .str = "a_frames_received_ok",
1801 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1802 },
1803 {
1804 .str = "a_frame_check_sequence_errors",
1805 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1806 },
1807 {
1808 .str = "a_alignment_errors",
1809 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1810 },
1811 {
1812 .str = "a_octets_transmitted_ok",
1813 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1814 },
1815 {
1816 .str = "a_octets_received_ok",
1817 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1818 },
1819 {
1820 .str = "a_multicast_frames_xmitted_ok",
1821 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1822 },
1823 {
1824 .str = "a_broadcast_frames_xmitted_ok",
1825 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1826 },
1827 {
1828 .str = "a_multicast_frames_received_ok",
1829 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1830 },
1831 {
1832 .str = "a_broadcast_frames_received_ok",
1833 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1834 },
1835 {
1836 .str = "a_in_range_length_errors",
1837 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1838 },
1839 {
1840 .str = "a_out_of_range_length_field",
1841 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1842 },
1843 {
1844 .str = "a_frame_too_long_errors",
1845 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1846 },
1847 {
1848 .str = "a_symbol_error_during_carrier",
1849 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1850 },
1851 {
1852 .str = "a_mac_control_frames_transmitted",
1853 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1854 },
1855 {
1856 .str = "a_mac_control_frames_received",
1857 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1858 },
1859 {
1860 .str = "a_unsupported_opcodes_received",
1861 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1862 },
1863 {
1864 .str = "a_pause_mac_ctrl_frames_received",
1865 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1866 },
1867 {
1868 .str = "a_pause_mac_ctrl_frames_xmitted",
1869 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1870 },
1871 };
1872
1873 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1874
1875 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2819_stats[] = {
1876 {
1877 .str = "ether_pkts64octets",
1878 .getter = mlxsw_reg_ppcnt_ether_stats_pkts64octets_get,
1879 },
1880 {
1881 .str = "ether_pkts65to127octets",
1882 .getter = mlxsw_reg_ppcnt_ether_stats_pkts65to127octets_get,
1883 },
1884 {
1885 .str = "ether_pkts128to255octets",
1886 .getter = mlxsw_reg_ppcnt_ether_stats_pkts128to255octets_get,
1887 },
1888 {
1889 .str = "ether_pkts256to511octets",
1890 .getter = mlxsw_reg_ppcnt_ether_stats_pkts256to511octets_get,
1891 },
1892 {
1893 .str = "ether_pkts512to1023octets",
1894 .getter = mlxsw_reg_ppcnt_ether_stats_pkts512to1023octets_get,
1895 },
1896 {
1897 .str = "ether_pkts1024to1518octets",
1898 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1024to1518octets_get,
1899 },
1900 {
1901 .str = "ether_pkts1519to2047octets",
1902 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1519to2047octets_get,
1903 },
1904 {
1905 .str = "ether_pkts2048to4095octets",
1906 .getter = mlxsw_reg_ppcnt_ether_stats_pkts2048to4095octets_get,
1907 },
1908 {
1909 .str = "ether_pkts4096to8191octets",
1910 .getter = mlxsw_reg_ppcnt_ether_stats_pkts4096to8191octets_get,
1911 },
1912 {
1913 .str = "ether_pkts8192to10239octets",
1914 .getter = mlxsw_reg_ppcnt_ether_stats_pkts8192to10239octets_get,
1915 },
1916 };
1917
1918 #define MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN \
1919 ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2819_stats)
1920
1921 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1922 {
1923 .str = "rx_octets_prio",
1924 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1925 },
1926 {
1927 .str = "rx_frames_prio",
1928 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1929 },
1930 {
1931 .str = "tx_octets_prio",
1932 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1933 },
1934 {
1935 .str = "tx_frames_prio",
1936 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1937 },
1938 {
1939 .str = "rx_pause_prio",
1940 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1941 },
1942 {
1943 .str = "rx_pause_duration_prio",
1944 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1945 },
1946 {
1947 .str = "tx_pause_prio",
1948 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1949 },
1950 {
1951 .str = "tx_pause_duration_prio",
1952 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1953 },
1954 };
1955
1956 #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1957
1958 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1959 {
1960 .str = "tc_transmit_queue_tc",
1961 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
1962 .cells_bytes = true,
1963 },
1964 {
1965 .str = "tc_no_buffer_discard_uc_tc",
1966 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1967 },
1968 };
1969
1970 #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1971
1972 #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
1973 MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN + \
1974 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN * \
1975 IEEE_8021QAZ_MAX_TCS) + \
1976 (MLXSW_SP_PORT_HW_TC_STATS_LEN * \
1977 TC_MAX_QUEUE))
1978
mlxsw_sp_port_get_prio_strings(u8 ** p,int prio)1979 static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1980 {
1981 int i;
1982
1983 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1984 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1985 mlxsw_sp_port_hw_prio_stats[i].str, prio);
1986 *p += ETH_GSTRING_LEN;
1987 }
1988 }
1989
mlxsw_sp_port_get_tc_strings(u8 ** p,int tc)1990 static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
1991 {
1992 int i;
1993
1994 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
1995 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1996 mlxsw_sp_port_hw_tc_stats[i].str, tc);
1997 *p += ETH_GSTRING_LEN;
1998 }
1999 }
2000
mlxsw_sp_port_get_strings(struct net_device * dev,u32 stringset,u8 * data)2001 static void mlxsw_sp_port_get_strings(struct net_device *dev,
2002 u32 stringset, u8 *data)
2003 {
2004 u8 *p = data;
2005 int i;
2006
2007 switch (stringset) {
2008 case ETH_SS_STATS:
2009 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2010 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2011 ETH_GSTRING_LEN);
2012 p += ETH_GSTRING_LEN;
2013 }
2014 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; i++) {
2015 memcpy(p, mlxsw_sp_port_hw_rfc_2819_stats[i].str,
2016 ETH_GSTRING_LEN);
2017 p += ETH_GSTRING_LEN;
2018 }
2019
2020 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2021 mlxsw_sp_port_get_prio_strings(&p, i);
2022
2023 for (i = 0; i < TC_MAX_QUEUE; i++)
2024 mlxsw_sp_port_get_tc_strings(&p, i);
2025
2026 break;
2027 }
2028 }
2029
mlxsw_sp_port_set_phys_id(struct net_device * dev,enum ethtool_phys_id_state state)2030 static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2031 enum ethtool_phys_id_state state)
2032 {
2033 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2034 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2035 char mlcr_pl[MLXSW_REG_MLCR_LEN];
2036 bool active;
2037
2038 switch (state) {
2039 case ETHTOOL_ID_ACTIVE:
2040 active = true;
2041 break;
2042 case ETHTOOL_ID_INACTIVE:
2043 active = false;
2044 break;
2045 default:
2046 return -EOPNOTSUPP;
2047 }
2048
2049 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2050 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2051 }
2052
2053 static int
mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats ** p_hw_stats,int * p_len,enum mlxsw_reg_ppcnt_grp grp)2054 mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2055 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2056 {
2057 switch (grp) {
2058 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2059 *p_hw_stats = mlxsw_sp_port_hw_stats;
2060 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2061 break;
2062 case MLXSW_REG_PPCNT_RFC_2819_CNT:
2063 *p_hw_stats = mlxsw_sp_port_hw_rfc_2819_stats;
2064 *p_len = MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2065 break;
2066 case MLXSW_REG_PPCNT_PRIO_CNT:
2067 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2068 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2069 break;
2070 case MLXSW_REG_PPCNT_TC_CNT:
2071 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2072 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2073 break;
2074 default:
2075 WARN_ON(1);
2076 return -EOPNOTSUPP;
2077 }
2078 return 0;
2079 }
2080
__mlxsw_sp_port_get_stats(struct net_device * dev,enum mlxsw_reg_ppcnt_grp grp,int prio,u64 * data,int data_index)2081 static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2082 enum mlxsw_reg_ppcnt_grp grp, int prio,
2083 u64 *data, int data_index)
2084 {
2085 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2086 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2087 struct mlxsw_sp_port_hw_stats *hw_stats;
2088 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
2089 int i, len;
2090 int err;
2091
2092 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2093 if (err)
2094 return;
2095 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
2096 for (i = 0; i < len; i++) {
2097 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
2098 if (!hw_stats[i].cells_bytes)
2099 continue;
2100 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2101 data[data_index + i]);
2102 }
2103 }
2104
mlxsw_sp_port_get_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)2105 static void mlxsw_sp_port_get_stats(struct net_device *dev,
2106 struct ethtool_stats *stats, u64 *data)
2107 {
2108 int i, data_index = 0;
2109
2110 /* IEEE 802.3 Counters */
2111 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2112 data, data_index);
2113 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2114
2115 /* RFC 2819 Counters */
2116 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2819_CNT, 0,
2117 data, data_index);
2118 data_index += MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2119
2120 /* Per-Priority Counters */
2121 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2122 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2123 data, data_index);
2124 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2125 }
2126
2127 /* Per-TC Counters */
2128 for (i = 0; i < TC_MAX_QUEUE; i++) {
2129 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2130 data, data_index);
2131 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2132 }
2133 }
2134
mlxsw_sp_port_get_sset_count(struct net_device * dev,int sset)2135 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2136 {
2137 switch (sset) {
2138 case ETH_SS_STATS:
2139 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
2140 default:
2141 return -EOPNOTSUPP;
2142 }
2143 }
2144
2145 struct mlxsw_sp_port_link_mode {
2146 enum ethtool_link_mode_bit_indices mask_ethtool;
2147 u32 mask;
2148 u32 speed;
2149 };
2150
2151 static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2152 {
2153 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
2154 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2155 .speed = SPEED_100,
2156 },
2157 {
2158 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2159 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
2160 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2161 .speed = SPEED_1000,
2162 },
2163 {
2164 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
2165 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2166 .speed = SPEED_10000,
2167 },
2168 {
2169 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2170 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
2171 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2172 .speed = SPEED_10000,
2173 },
2174 {
2175 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2176 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2177 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2178 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
2179 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2180 .speed = SPEED_10000,
2181 },
2182 {
2183 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
2184 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2185 .speed = SPEED_20000,
2186 },
2187 {
2188 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
2189 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2190 .speed = SPEED_40000,
2191 },
2192 {
2193 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
2194 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2195 .speed = SPEED_40000,
2196 },
2197 {
2198 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
2199 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2200 .speed = SPEED_40000,
2201 },
2202 {
2203 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
2204 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2205 .speed = SPEED_40000,
2206 },
2207 {
2208 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2209 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2210 .speed = SPEED_25000,
2211 },
2212 {
2213 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2214 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2215 .speed = SPEED_25000,
2216 },
2217 {
2218 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2219 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2220 .speed = SPEED_25000,
2221 },
2222 {
2223 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2224 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2225 .speed = SPEED_25000,
2226 },
2227 {
2228 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2229 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2230 .speed = SPEED_50000,
2231 },
2232 {
2233 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2234 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2235 .speed = SPEED_50000,
2236 },
2237 {
2238 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2239 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2240 .speed = SPEED_50000,
2241 },
2242 {
2243 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2244 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2245 .speed = SPEED_56000,
2246 },
2247 {
2248 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2249 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2250 .speed = SPEED_56000,
2251 },
2252 {
2253 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2254 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2255 .speed = SPEED_56000,
2256 },
2257 {
2258 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2259 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2260 .speed = SPEED_56000,
2261 },
2262 {
2263 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2264 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2265 .speed = SPEED_100000,
2266 },
2267 {
2268 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2269 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2270 .speed = SPEED_100000,
2271 },
2272 {
2273 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2274 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2275 .speed = SPEED_100000,
2276 },
2277 {
2278 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2279 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2280 .speed = SPEED_100000,
2281 },
2282 };
2283
2284 #define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2285
2286 static void
mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,struct ethtool_link_ksettings * cmd)2287 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2288 struct ethtool_link_ksettings *cmd)
2289 {
2290 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2291 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2292 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2293 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2294 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2295 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2296 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
2297
2298 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2299 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2300 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2301 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2302 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
2303 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
2304 }
2305
mlxsw_sp_from_ptys_link(u32 ptys_eth_proto,unsigned long * mode)2306 static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
2307 {
2308 int i;
2309
2310 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2311 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
2312 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2313 mode);
2314 }
2315 }
2316
mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok,u32 ptys_eth_proto,struct ethtool_link_ksettings * cmd)2317 static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
2318 struct ethtool_link_ksettings *cmd)
2319 {
2320 u32 speed = SPEED_UNKNOWN;
2321 u8 duplex = DUPLEX_UNKNOWN;
2322 int i;
2323
2324 if (!carrier_ok)
2325 goto out;
2326
2327 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2328 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2329 speed = mlxsw_sp_port_link_mode[i].speed;
2330 duplex = DUPLEX_FULL;
2331 break;
2332 }
2333 }
2334 out:
2335 cmd->base.speed = speed;
2336 cmd->base.duplex = duplex;
2337 }
2338
mlxsw_sp_port_connector_port(u32 ptys_eth_proto)2339 static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2340 {
2341 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2342 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2343 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2344 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2345 return PORT_FIBRE;
2346
2347 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2348 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2349 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2350 return PORT_DA;
2351
2352 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2353 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2354 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2355 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2356 return PORT_NONE;
2357
2358 return PORT_OTHER;
2359 }
2360
2361 static u32
mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings * cmd)2362 mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
2363 {
2364 u32 ptys_proto = 0;
2365 int i;
2366
2367 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2368 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2369 cmd->link_modes.advertising))
2370 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2371 }
2372 return ptys_proto;
2373 }
2374
mlxsw_sp_to_ptys_speed(u32 speed)2375 static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2376 {
2377 u32 ptys_proto = 0;
2378 int i;
2379
2380 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2381 if (speed == mlxsw_sp_port_link_mode[i].speed)
2382 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2383 }
2384 return ptys_proto;
2385 }
2386
mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)2387 static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2388 {
2389 u32 ptys_proto = 0;
2390 int i;
2391
2392 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2393 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2394 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2395 }
2396 return ptys_proto;
2397 }
2398
mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,struct ethtool_link_ksettings * cmd)2399 static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2400 struct ethtool_link_ksettings *cmd)
2401 {
2402 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2403 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2404 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2405
2406 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2407 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2408 }
2409
mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin,bool autoneg,struct ethtool_link_ksettings * cmd)2410 static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2411 struct ethtool_link_ksettings *cmd)
2412 {
2413 if (!autoneg)
2414 return;
2415
2416 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2417 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2418 }
2419
2420 static void
mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp,u8 autoneg_status,struct ethtool_link_ksettings * cmd)2421 mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2422 struct ethtool_link_ksettings *cmd)
2423 {
2424 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2425 return;
2426
2427 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2428 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2429 }
2430
mlxsw_sp_port_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * cmd)2431 static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2432 struct ethtool_link_ksettings *cmd)
2433 {
2434 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2435 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2436 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2437 char ptys_pl[MLXSW_REG_PTYS_LEN];
2438 u8 autoneg_status;
2439 bool autoneg;
2440 int err;
2441
2442 autoneg = mlxsw_sp_port->link.autoneg;
2443 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
2444 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2445 if (err)
2446 return err;
2447 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap, ð_proto_admin,
2448 ð_proto_oper);
2449
2450 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2451
2452 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2453
2454 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2455 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2456 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2457
2458 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2459 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2460 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2461 cmd);
2462
2463 return 0;
2464 }
2465
2466 static int
mlxsw_sp_port_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * cmd)2467 mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2468 const struct ethtool_link_ksettings *cmd)
2469 {
2470 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2471 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2472 char ptys_pl[MLXSW_REG_PTYS_LEN];
2473 u32 eth_proto_cap, eth_proto_new;
2474 bool autoneg;
2475 int err;
2476
2477 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
2478 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2479 if (err)
2480 return err;
2481 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap, NULL, NULL);
2482
2483 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2484 eth_proto_new = autoneg ?
2485 mlxsw_sp_to_ptys_advert_link(cmd) :
2486 mlxsw_sp_to_ptys_speed(cmd->base.speed);
2487
2488 eth_proto_new = eth_proto_new & eth_proto_cap;
2489 if (!eth_proto_new) {
2490 netdev_err(dev, "No supported speed requested\n");
2491 return -EINVAL;
2492 }
2493
2494 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2495 eth_proto_new, autoneg);
2496 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2497 if (err)
2498 return err;
2499
2500 if (!netif_running(dev))
2501 return 0;
2502
2503 mlxsw_sp_port->link.autoneg = autoneg;
2504
2505 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2506 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
2507
2508 return 0;
2509 }
2510
mlxsw_sp_flash_device(struct net_device * dev,struct ethtool_flash * flash)2511 static int mlxsw_sp_flash_device(struct net_device *dev,
2512 struct ethtool_flash *flash)
2513 {
2514 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2515 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2516 const struct firmware *firmware;
2517 int err;
2518
2519 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2520 return -EOPNOTSUPP;
2521
2522 dev_hold(dev);
2523 rtnl_unlock();
2524
2525 err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2526 if (err)
2527 goto out;
2528 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2529 release_firmware(firmware);
2530 out:
2531 rtnl_lock();
2532 dev_put(dev);
2533 return err;
2534 }
2535
2536 #define MLXSW_SP_I2C_ADDR_LOW 0x50
2537 #define MLXSW_SP_I2C_ADDR_HIGH 0x51
2538 #define MLXSW_SP_EEPROM_PAGE_LENGTH 256
2539
mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port * mlxsw_sp_port,u16 offset,u16 size,void * data,unsigned int * p_read_size)2540 static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2541 u16 offset, u16 size, void *data,
2542 unsigned int *p_read_size)
2543 {
2544 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2545 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2546 char mcia_pl[MLXSW_REG_MCIA_LEN];
2547 u16 i2c_addr;
2548 int status;
2549 int err;
2550
2551 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
2552
2553 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2554 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2555 /* Cross pages read, read until offset 256 in low page */
2556 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2557
2558 i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2559 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2560 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2561 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2562 }
2563
2564 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
2565 0, 0, offset, size, i2c_addr);
2566
2567 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2568 if (err)
2569 return err;
2570
2571 status = mlxsw_reg_mcia_status_get(mcia_pl);
2572 if (status)
2573 return -EIO;
2574
2575 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2576 memcpy(data, eeprom_tmp, size);
2577 *p_read_size = size;
2578
2579 return 0;
2580 }
2581
2582 enum mlxsw_sp_eeprom_module_info_rev_id {
2583 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
2584 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
2585 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
2586 };
2587
2588 enum mlxsw_sp_eeprom_module_info_id {
2589 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03,
2590 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
2591 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
2592 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
2593 };
2594
2595 enum mlxsw_sp_eeprom_module_info {
2596 MLXSW_SP_EEPROM_MODULE_INFO_ID,
2597 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2598 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2599 };
2600
mlxsw_sp_get_module_info(struct net_device * netdev,struct ethtool_modinfo * modinfo)2601 static int mlxsw_sp_get_module_info(struct net_device *netdev,
2602 struct ethtool_modinfo *modinfo)
2603 {
2604 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2605 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2606 u8 module_rev_id, module_id;
2607 unsigned int read_size;
2608 int err;
2609
2610 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2611 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2612 module_info, &read_size);
2613 if (err)
2614 return err;
2615
2616 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2617 return -EIO;
2618
2619 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2620 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2621
2622 switch (module_id) {
2623 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2624 modinfo->type = ETH_MODULE_SFF_8436;
2625 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2626 break;
2627 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2628 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2629 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2630 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2631 modinfo->type = ETH_MODULE_SFF_8636;
2632 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2633 } else {
2634 modinfo->type = ETH_MODULE_SFF_8436;
2635 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2636 }
2637 break;
2638 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2639 modinfo->type = ETH_MODULE_SFF_8472;
2640 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2641 break;
2642 default:
2643 return -EINVAL;
2644 }
2645
2646 return 0;
2647 }
2648
mlxsw_sp_get_module_eeprom(struct net_device * netdev,struct ethtool_eeprom * ee,u8 * data)2649 static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2650 struct ethtool_eeprom *ee,
2651 u8 *data)
2652 {
2653 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2654 int offset = ee->offset;
2655 unsigned int read_size;
2656 int i = 0;
2657 int err;
2658
2659 if (!ee->len)
2660 return -EINVAL;
2661
2662 memset(data, 0, ee->len);
2663
2664 while (i < ee->len) {
2665 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2666 ee->len - i, data + i,
2667 &read_size);
2668 if (err) {
2669 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2670 return err;
2671 }
2672
2673 i += read_size;
2674 offset += read_size;
2675 }
2676
2677 return 0;
2678 }
2679
2680 static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2681 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2682 .get_link = ethtool_op_get_link,
2683 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2684 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
2685 .get_strings = mlxsw_sp_port_get_strings,
2686 .set_phys_id = mlxsw_sp_port_set_phys_id,
2687 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2688 .get_sset_count = mlxsw_sp_port_get_sset_count,
2689 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2690 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
2691 .flash_device = mlxsw_sp_flash_device,
2692 .get_module_info = mlxsw_sp_get_module_info,
2693 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
2694 };
2695
2696 static int
mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port * mlxsw_sp_port,u8 width)2697 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2698 {
2699 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2700 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2701 char ptys_pl[MLXSW_REG_PTYS_LEN];
2702 u32 eth_proto_admin;
2703
2704 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
2705 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2706 eth_proto_admin, mlxsw_sp_port->link.autoneg);
2707 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2708 }
2709
mlxsw_sp_port_ets_set(struct mlxsw_sp_port * mlxsw_sp_port,enum mlxsw_reg_qeec_hr hr,u8 index,u8 next_index,bool dwrr,u8 dwrr_weight)2710 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2711 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2712 bool dwrr, u8 dwrr_weight)
2713 {
2714 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2715 char qeec_pl[MLXSW_REG_QEEC_LEN];
2716
2717 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2718 next_index);
2719 mlxsw_reg_qeec_de_set(qeec_pl, true);
2720 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2721 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2722 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2723 }
2724
mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port * mlxsw_sp_port,enum mlxsw_reg_qeec_hr hr,u8 index,u8 next_index,u32 maxrate)2725 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2726 enum mlxsw_reg_qeec_hr hr, u8 index,
2727 u8 next_index, u32 maxrate)
2728 {
2729 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2730 char qeec_pl[MLXSW_REG_QEEC_LEN];
2731
2732 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2733 next_index);
2734 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2735 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2736 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2737 }
2738
mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port * mlxsw_sp_port,u8 switch_prio,u8 tclass)2739 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2740 u8 switch_prio, u8 tclass)
2741 {
2742 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2743 char qtct_pl[MLXSW_REG_QTCT_LEN];
2744
2745 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2746 tclass);
2747 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2748 }
2749
mlxsw_sp_port_ets_init(struct mlxsw_sp_port * mlxsw_sp_port)2750 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2751 {
2752 int err, i;
2753
2754 /* Setup the elements hierarcy, so that each TC is linked to
2755 * one subgroup, which are all member in the same group.
2756 */
2757 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2758 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2759 0);
2760 if (err)
2761 return err;
2762 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2763 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2764 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2765 0, false, 0);
2766 if (err)
2767 return err;
2768 }
2769 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2770 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2771 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2772 false, 0);
2773 if (err)
2774 return err;
2775
2776 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2777 MLXSW_REG_QEEC_HIERARCY_TC,
2778 i + 8, i,
2779 false, 0);
2780 if (err)
2781 return err;
2782 }
2783
2784 /* Make sure the max shaper is disabled in all hierarchies that
2785 * support it.
2786 */
2787 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2788 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2789 MLXSW_REG_QEEC_MAS_DIS);
2790 if (err)
2791 return err;
2792 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2793 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2794 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2795 i, 0,
2796 MLXSW_REG_QEEC_MAS_DIS);
2797 if (err)
2798 return err;
2799 }
2800 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2801 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2802 MLXSW_REG_QEEC_HIERARCY_TC,
2803 i, i,
2804 MLXSW_REG_QEEC_MAS_DIS);
2805 if (err)
2806 return err;
2807 }
2808
2809 /* Map all priorities to traffic class 0. */
2810 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2811 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2812 if (err)
2813 return err;
2814 }
2815
2816 return 0;
2817 }
2818
mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port * mlxsw_sp_port,bool enable)2819 static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
2820 bool enable)
2821 {
2822 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2823 char qtctm_pl[MLXSW_REG_QTCTM_LEN];
2824
2825 mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable);
2826 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl);
2827 }
2828
mlxsw_sp_port_create(struct mlxsw_sp * mlxsw_sp,u8 local_port,bool split,u8 module,u8 width,u8 lane)2829 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2830 bool split, u8 module, u8 width, u8 lane)
2831 {
2832 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
2833 struct mlxsw_sp_port *mlxsw_sp_port;
2834 struct net_device *dev;
2835 int err;
2836
2837 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2838 if (err) {
2839 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2840 local_port);
2841 return err;
2842 }
2843
2844 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
2845 if (!dev) {
2846 err = -ENOMEM;
2847 goto err_alloc_etherdev;
2848 }
2849 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
2850 mlxsw_sp_port = netdev_priv(dev);
2851 mlxsw_sp_port->dev = dev;
2852 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2853 mlxsw_sp_port->local_port = local_port;
2854 mlxsw_sp_port->pvid = 1;
2855 mlxsw_sp_port->split = split;
2856 mlxsw_sp_port->mapping.module = module;
2857 mlxsw_sp_port->mapping.width = width;
2858 mlxsw_sp_port->mapping.lane = lane;
2859 mlxsw_sp_port->link.autoneg = 1;
2860 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
2861 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
2862
2863 mlxsw_sp_port->pcpu_stats =
2864 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2865 if (!mlxsw_sp_port->pcpu_stats) {
2866 err = -ENOMEM;
2867 goto err_alloc_stats;
2868 }
2869
2870 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2871 GFP_KERNEL);
2872 if (!mlxsw_sp_port->sample) {
2873 err = -ENOMEM;
2874 goto err_alloc_sample;
2875 }
2876
2877 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
2878 &update_stats_cache);
2879
2880 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2881 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2882
2883 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
2884 if (err) {
2885 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
2886 mlxsw_sp_port->local_port);
2887 goto err_port_module_map;
2888 }
2889
2890 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2891 if (err) {
2892 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2893 mlxsw_sp_port->local_port);
2894 goto err_port_swid_set;
2895 }
2896
2897 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2898 if (err) {
2899 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2900 mlxsw_sp_port->local_port);
2901 goto err_dev_addr_init;
2902 }
2903
2904 netif_carrier_off(dev);
2905
2906 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
2907 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2908 dev->hw_features |= NETIF_F_HW_TC;
2909
2910 dev->min_mtu = 0;
2911 dev->max_mtu = ETH_MAX_MTU;
2912
2913 /* Each packet needs to have a Tx header (metadata) on top all other
2914 * headers.
2915 */
2916 dev->needed_headroom = MLXSW_TXHDR_LEN;
2917
2918 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2919 if (err) {
2920 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2921 mlxsw_sp_port->local_port);
2922 goto err_port_system_port_mapping_set;
2923 }
2924
2925 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2926 if (err) {
2927 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2928 mlxsw_sp_port->local_port);
2929 goto err_port_speed_by_width_set;
2930 }
2931
2932 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2933 if (err) {
2934 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2935 mlxsw_sp_port->local_port);
2936 goto err_port_mtu_set;
2937 }
2938
2939 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2940 if (err)
2941 goto err_port_admin_status_set;
2942
2943 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2944 if (err) {
2945 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2946 mlxsw_sp_port->local_port);
2947 goto err_port_buffers_init;
2948 }
2949
2950 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2951 if (err) {
2952 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2953 mlxsw_sp_port->local_port);
2954 goto err_port_ets_init;
2955 }
2956
2957 err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true);
2958 if (err) {
2959 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n",
2960 mlxsw_sp_port->local_port);
2961 goto err_port_tc_mc_mode;
2962 }
2963
2964 /* ETS and buffers must be initialized before DCB. */
2965 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2966 if (err) {
2967 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2968 mlxsw_sp_port->local_port);
2969 goto err_port_dcb_init;
2970 }
2971
2972 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
2973 if (err) {
2974 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
2975 mlxsw_sp_port->local_port);
2976 goto err_port_fids_init;
2977 }
2978
2979 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
2980 if (err) {
2981 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
2982 mlxsw_sp_port->local_port);
2983 goto err_port_qdiscs_init;
2984 }
2985
2986 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
2987 if (IS_ERR(mlxsw_sp_port_vlan)) {
2988 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
2989 mlxsw_sp_port->local_port);
2990 err = PTR_ERR(mlxsw_sp_port_vlan);
2991 goto err_port_vlan_get;
2992 }
2993
2994 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
2995 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
2996 err = register_netdev(dev);
2997 if (err) {
2998 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
2999 mlxsw_sp_port->local_port);
3000 goto err_register_netdev;
3001 }
3002
3003 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
3004 mlxsw_sp_port, dev, module + 1,
3005 mlxsw_sp_port->split, lane / width);
3006 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
3007 return 0;
3008
3009 err_register_netdev:
3010 mlxsw_sp->ports[local_port] = NULL;
3011 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
3012 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
3013 err_port_vlan_get:
3014 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3015 err_port_qdiscs_init:
3016 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3017 err_port_fids_init:
3018 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3019 err_port_dcb_init:
3020 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
3021 err_port_tc_mc_mode:
3022 err_port_ets_init:
3023 err_port_buffers_init:
3024 err_port_admin_status_set:
3025 err_port_mtu_set:
3026 err_port_speed_by_width_set:
3027 err_port_system_port_mapping_set:
3028 err_dev_addr_init:
3029 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3030 err_port_swid_set:
3031 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
3032 err_port_module_map:
3033 kfree(mlxsw_sp_port->sample);
3034 err_alloc_sample:
3035 free_percpu(mlxsw_sp_port->pcpu_stats);
3036 err_alloc_stats:
3037 free_netdev(dev);
3038 err_alloc_etherdev:
3039 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3040 return err;
3041 }
3042
mlxsw_sp_port_remove(struct mlxsw_sp * mlxsw_sp,u8 local_port)3043 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3044 {
3045 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3046
3047 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
3048 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
3049 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
3050 mlxsw_sp->ports[local_port] = NULL;
3051 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
3052 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
3053 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3054 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3055 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3056 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
3057 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3058 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
3059 kfree(mlxsw_sp_port->sample);
3060 free_percpu(mlxsw_sp_port->pcpu_stats);
3061 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
3062 free_netdev(mlxsw_sp_port->dev);
3063 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3064 }
3065
mlxsw_sp_port_created(struct mlxsw_sp * mlxsw_sp,u8 local_port)3066 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3067 {
3068 return mlxsw_sp->ports[local_port] != NULL;
3069 }
3070
mlxsw_sp_ports_remove(struct mlxsw_sp * mlxsw_sp)3071 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
3072 {
3073 int i;
3074
3075 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
3076 if (mlxsw_sp_port_created(mlxsw_sp, i))
3077 mlxsw_sp_port_remove(mlxsw_sp, i);
3078 kfree(mlxsw_sp->port_to_module);
3079 kfree(mlxsw_sp->ports);
3080 }
3081
mlxsw_sp_ports_create(struct mlxsw_sp * mlxsw_sp)3082 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3083 {
3084 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
3085 u8 module, width, lane;
3086 size_t alloc_size;
3087 int i;
3088 int err;
3089
3090 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
3091 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3092 if (!mlxsw_sp->ports)
3093 return -ENOMEM;
3094
3095 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3096 GFP_KERNEL);
3097 if (!mlxsw_sp->port_to_module) {
3098 err = -ENOMEM;
3099 goto err_port_to_module_alloc;
3100 }
3101
3102 for (i = 1; i < max_ports; i++) {
3103 /* Mark as invalid */
3104 mlxsw_sp->port_to_module[i] = -1;
3105
3106 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
3107 &width, &lane);
3108 if (err)
3109 goto err_port_module_info_get;
3110 if (!width)
3111 continue;
3112 mlxsw_sp->port_to_module[i] = module;
3113 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3114 module, width, lane);
3115 if (err)
3116 goto err_port_create;
3117 }
3118 return 0;
3119
3120 err_port_create:
3121 err_port_module_info_get:
3122 for (i--; i >= 1; i--)
3123 if (mlxsw_sp_port_created(mlxsw_sp, i))
3124 mlxsw_sp_port_remove(mlxsw_sp, i);
3125 kfree(mlxsw_sp->port_to_module);
3126 err_port_to_module_alloc:
3127 kfree(mlxsw_sp->ports);
3128 return err;
3129 }
3130
mlxsw_sp_cluster_base_port_get(u8 local_port)3131 static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3132 {
3133 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3134
3135 return local_port - offset;
3136 }
3137
mlxsw_sp_port_split_create(struct mlxsw_sp * mlxsw_sp,u8 base_port,u8 module,unsigned int count)3138 static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3139 u8 module, unsigned int count)
3140 {
3141 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3142 int err, i;
3143
3144 for (i = 0; i < count; i++) {
3145 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
3146 module, width, i * width);
3147 if (err)
3148 goto err_port_create;
3149 }
3150
3151 return 0;
3152
3153 err_port_create:
3154 for (i--; i >= 0; i--)
3155 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3156 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
3157 return err;
3158 }
3159
mlxsw_sp_port_unsplit_create(struct mlxsw_sp * mlxsw_sp,u8 base_port,unsigned int count)3160 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3161 u8 base_port, unsigned int count)
3162 {
3163 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3164 int i;
3165
3166 /* Split by four means we need to re-create two ports, otherwise
3167 * only one.
3168 */
3169 count = count / 2;
3170
3171 for (i = 0; i < count; i++) {
3172 local_port = base_port + i * 2;
3173 if (mlxsw_sp->port_to_module[local_port] < 0)
3174 continue;
3175 module = mlxsw_sp->port_to_module[local_port];
3176
3177 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
3178 width, 0);
3179 }
3180 }
3181
mlxsw_sp_port_split(struct mlxsw_core * mlxsw_core,u8 local_port,unsigned int count,struct netlink_ext_ack * extack)3182 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3183 unsigned int count,
3184 struct netlink_ext_ack *extack)
3185 {
3186 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3187 struct mlxsw_sp_port *mlxsw_sp_port;
3188 u8 module, cur_width, base_port;
3189 int i;
3190 int err;
3191
3192 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3193 if (!mlxsw_sp_port) {
3194 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3195 local_port);
3196 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
3197 return -EINVAL;
3198 }
3199
3200 module = mlxsw_sp_port->mapping.module;
3201 cur_width = mlxsw_sp_port->mapping.width;
3202
3203 if (count != 2 && count != 4) {
3204 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3205 NL_SET_ERR_MSG_MOD(extack, "Port can only be split into 2 or 4 ports");
3206 return -EINVAL;
3207 }
3208
3209 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3210 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3211 NL_SET_ERR_MSG_MOD(extack, "Port cannot be split further");
3212 return -EINVAL;
3213 }
3214
3215 /* Make sure we have enough slave (even) ports for the split. */
3216 if (count == 2) {
3217 base_port = local_port;
3218 if (mlxsw_sp->ports[base_port + 1]) {
3219 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3220 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
3221 return -EINVAL;
3222 }
3223 } else {
3224 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3225 if (mlxsw_sp->ports[base_port + 1] ||
3226 mlxsw_sp->ports[base_port + 3]) {
3227 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3228 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
3229 return -EINVAL;
3230 }
3231 }
3232
3233 for (i = 0; i < count; i++)
3234 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3235 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
3236
3237 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3238 if (err) {
3239 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3240 goto err_port_split_create;
3241 }
3242
3243 return 0;
3244
3245 err_port_split_create:
3246 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
3247 return err;
3248 }
3249
mlxsw_sp_port_unsplit(struct mlxsw_core * mlxsw_core,u8 local_port,struct netlink_ext_ack * extack)3250 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port,
3251 struct netlink_ext_ack *extack)
3252 {
3253 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3254 struct mlxsw_sp_port *mlxsw_sp_port;
3255 u8 cur_width, base_port;
3256 unsigned int count;
3257 int i;
3258
3259 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3260 if (!mlxsw_sp_port) {
3261 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3262 local_port);
3263 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
3264 return -EINVAL;
3265 }
3266
3267 if (!mlxsw_sp_port->split) {
3268 netdev_err(mlxsw_sp_port->dev, "Port was not split\n");
3269 NL_SET_ERR_MSG_MOD(extack, "Port was not split");
3270 return -EINVAL;
3271 }
3272
3273 cur_width = mlxsw_sp_port->mapping.width;
3274 count = cur_width == 1 ? 4 : 2;
3275
3276 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3277
3278 /* Determine which ports to remove. */
3279 if (count == 2 && local_port >= base_port + 2)
3280 base_port = base_port + 2;
3281
3282 for (i = 0; i < count; i++)
3283 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3284 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
3285
3286 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
3287
3288 return 0;
3289 }
3290
mlxsw_sp_pude_event_func(const struct mlxsw_reg_info * reg,char * pude_pl,void * priv)3291 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3292 char *pude_pl, void *priv)
3293 {
3294 struct mlxsw_sp *mlxsw_sp = priv;
3295 struct mlxsw_sp_port *mlxsw_sp_port;
3296 enum mlxsw_reg_pude_oper_status status;
3297 u8 local_port;
3298
3299 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3300 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3301 if (!mlxsw_sp_port)
3302 return;
3303
3304 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3305 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3306 netdev_info(mlxsw_sp_port->dev, "link up\n");
3307 netif_carrier_on(mlxsw_sp_port->dev);
3308 } else {
3309 netdev_info(mlxsw_sp_port->dev, "link down\n");
3310 netif_carrier_off(mlxsw_sp_port->dev);
3311 }
3312 }
3313
mlxsw_sp_rx_listener_no_mark_func(struct sk_buff * skb,u8 local_port,void * priv)3314 static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3315 u8 local_port, void *priv)
3316 {
3317 struct mlxsw_sp *mlxsw_sp = priv;
3318 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3319 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3320
3321 if (unlikely(!mlxsw_sp_port)) {
3322 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3323 local_port);
3324 return;
3325 }
3326
3327 skb->dev = mlxsw_sp_port->dev;
3328
3329 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3330 u64_stats_update_begin(&pcpu_stats->syncp);
3331 pcpu_stats->rx_packets++;
3332 pcpu_stats->rx_bytes += skb->len;
3333 u64_stats_update_end(&pcpu_stats->syncp);
3334
3335 skb->protocol = eth_type_trans(skb, skb->dev);
3336 netif_receive_skb(skb);
3337 }
3338
mlxsw_sp_rx_listener_mark_func(struct sk_buff * skb,u8 local_port,void * priv)3339 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3340 void *priv)
3341 {
3342 skb->offload_fwd_mark = 1;
3343 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3344 }
3345
mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff * skb,u8 local_port,void * priv)3346 static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb,
3347 u8 local_port, void *priv)
3348 {
3349 skb->offload_mr_fwd_mark = 1;
3350 skb->offload_fwd_mark = 1;
3351 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3352 }
3353
mlxsw_sp_rx_listener_sample_func(struct sk_buff * skb,u8 local_port,void * priv)3354 static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3355 void *priv)
3356 {
3357 struct mlxsw_sp *mlxsw_sp = priv;
3358 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3359 struct psample_group *psample_group;
3360 u32 size;
3361
3362 if (unlikely(!mlxsw_sp_port)) {
3363 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3364 local_port);
3365 goto out;
3366 }
3367 if (unlikely(!mlxsw_sp_port->sample)) {
3368 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3369 local_port);
3370 goto out;
3371 }
3372
3373 size = mlxsw_sp_port->sample->truncate ?
3374 mlxsw_sp_port->sample->trunc_size : skb->len;
3375
3376 rcu_read_lock();
3377 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3378 if (!psample_group)
3379 goto out_unlock;
3380 psample_sample_packet(psample_group, skb, size,
3381 mlxsw_sp_port->dev->ifindex, 0,
3382 mlxsw_sp_port->sample->rate);
3383 out_unlock:
3384 rcu_read_unlock();
3385 out:
3386 consume_skb(skb);
3387 }
3388
3389 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3390 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
3391 _is_ctrl, SP_##_trap_group, DISCARD)
3392
3393 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3394 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
3395 _is_ctrl, SP_##_trap_group, DISCARD)
3396
3397 #define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3398 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \
3399 _is_ctrl, SP_##_trap_group, DISCARD)
3400
3401 #define MLXSW_SP_EVENTL(_func, _trap_id) \
3402 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
3403
3404 static const struct mlxsw_listener mlxsw_sp_listener[] = {
3405 /* Events */
3406 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
3407 /* L2 traps */
3408 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3409 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3410 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3411 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3412 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3413 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3414 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3415 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3416 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3417 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3418 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
3419 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
3420 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3421 false),
3422 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3423 false),
3424 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3425 false),
3426 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3427 false),
3428 /* L3 traps */
3429 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3430 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3431 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3432 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
3433 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3434 false),
3435 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3436 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3437 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3438 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3439 false),
3440 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3441 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3442 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
3443 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
3444 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3445 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3446 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3447 false),
3448 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3449 false),
3450 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3451 false),
3452 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3453 false),
3454 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3455 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3456 false),
3457 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3458 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
3459 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
3460 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
3461 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3462 MLXSW_SP_RXL_MARK(IPV4_VRRP, TRAP_TO_CPU, ROUTER_EXP, false),
3463 MLXSW_SP_RXL_MARK(IPV6_VRRP, TRAP_TO_CPU, ROUTER_EXP, false),
3464 /* PKT Sample trap */
3465 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
3466 false, SP_IP2ME, DISCARD),
3467 /* ACL trap */
3468 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
3469 /* Multicast Router Traps */
3470 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
3471 MLXSW_SP_RXL_MARK(IPV6_PIM, TRAP_TO_CPU, PIM, false),
3472 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
3473 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
3474 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
3475 };
3476
mlxsw_sp_cpu_policers_set(struct mlxsw_core * mlxsw_core)3477 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3478 {
3479 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3480 enum mlxsw_reg_qpcr_ir_units ir_units;
3481 int max_cpu_policers;
3482 bool is_bytes;
3483 u8 burst_size;
3484 u32 rate;
3485 int i, err;
3486
3487 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3488 return -EIO;
3489
3490 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3491
3492 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3493 for (i = 0; i < max_cpu_policers; i++) {
3494 is_bytes = false;
3495 switch (i) {
3496 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3497 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3498 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3499 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3500 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3501 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
3502 rate = 128;
3503 burst_size = 7;
3504 break;
3505 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3506 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
3507 rate = 16 * 1024;
3508 burst_size = 10;
3509 break;
3510 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
3511 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3512 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3513 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
3514 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3515 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3516 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
3517 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
3518 rate = 1024;
3519 burst_size = 7;
3520 break;
3521 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3522 is_bytes = true;
3523 rate = 4 * 1024;
3524 burst_size = 4;
3525 break;
3526 default:
3527 continue;
3528 }
3529
3530 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3531 burst_size);
3532 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3533 if (err)
3534 return err;
3535 }
3536
3537 return 0;
3538 }
3539
mlxsw_sp_trap_groups_set(struct mlxsw_core * mlxsw_core)3540 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
3541 {
3542 char htgt_pl[MLXSW_REG_HTGT_LEN];
3543 enum mlxsw_reg_htgt_trap_group i;
3544 int max_cpu_policers;
3545 int max_trap_groups;
3546 u8 priority, tc;
3547 u16 policer_id;
3548 int err;
3549
3550 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3551 return -EIO;
3552
3553 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
3554 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3555
3556 for (i = 0; i < max_trap_groups; i++) {
3557 policer_id = i;
3558 switch (i) {
3559 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3560 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3561 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3562 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3563 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3564 priority = 5;
3565 tc = 5;
3566 break;
3567 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
3568 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3569 priority = 4;
3570 tc = 4;
3571 break;
3572 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3573 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3574 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
3575 priority = 3;
3576 tc = 3;
3577 break;
3578 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3579 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
3580 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
3581 priority = 2;
3582 tc = 2;
3583 break;
3584 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
3585 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3586 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3587 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
3588 priority = 1;
3589 tc = 1;
3590 break;
3591 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
3592 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3593 tc = MLXSW_REG_HTGT_DEFAULT_TC;
3594 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
3595 break;
3596 default:
3597 continue;
3598 }
3599
3600 if (max_cpu_policers <= policer_id &&
3601 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3602 return -EIO;
3603
3604 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
3605 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3606 if (err)
3607 return err;
3608 }
3609
3610 return 0;
3611 }
3612
mlxsw_sp_traps_init(struct mlxsw_sp * mlxsw_sp)3613 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3614 {
3615 int i;
3616 int err;
3617
3618 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3619 if (err)
3620 return err;
3621
3622 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
3623 if (err)
3624 return err;
3625
3626 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
3627 err = mlxsw_core_trap_register(mlxsw_sp->core,
3628 &mlxsw_sp_listener[i],
3629 mlxsw_sp);
3630 if (err)
3631 goto err_listener_register;
3632
3633 }
3634 return 0;
3635
3636 err_listener_register:
3637 for (i--; i >= 0; i--) {
3638 mlxsw_core_trap_unregister(mlxsw_sp->core,
3639 &mlxsw_sp_listener[i],
3640 mlxsw_sp);
3641 }
3642 return err;
3643 }
3644
mlxsw_sp_traps_fini(struct mlxsw_sp * mlxsw_sp)3645 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3646 {
3647 int i;
3648
3649 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
3650 mlxsw_core_trap_unregister(mlxsw_sp->core,
3651 &mlxsw_sp_listener[i],
3652 mlxsw_sp);
3653 }
3654 }
3655
mlxsw_sp_lag_init(struct mlxsw_sp * mlxsw_sp)3656 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3657 {
3658 char slcr_pl[MLXSW_REG_SLCR_LEN];
3659 int err;
3660
3661 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3662 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3663 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3664 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3665 MLXSW_REG_SLCR_LAG_HASH_SIP |
3666 MLXSW_REG_SLCR_LAG_HASH_DIP |
3667 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3668 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3669 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
3670 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3671 if (err)
3672 return err;
3673
3674 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3675 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
3676 return -EIO;
3677
3678 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
3679 sizeof(struct mlxsw_sp_upper),
3680 GFP_KERNEL);
3681 if (!mlxsw_sp->lags)
3682 return -ENOMEM;
3683
3684 return 0;
3685 }
3686
mlxsw_sp_lag_fini(struct mlxsw_sp * mlxsw_sp)3687 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3688 {
3689 kfree(mlxsw_sp->lags);
3690 }
3691
mlxsw_sp_basic_trap_groups_set(struct mlxsw_core * mlxsw_core)3692 static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3693 {
3694 char htgt_pl[MLXSW_REG_HTGT_LEN];
3695
3696 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3697 MLXSW_REG_HTGT_INVALID_POLICER,
3698 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3699 MLXSW_REG_HTGT_DEFAULT_TC);
3700 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3701 }
3702
3703 static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3704 unsigned long event, void *ptr);
3705
mlxsw_sp_init(struct mlxsw_core * mlxsw_core,const struct mlxsw_bus_info * mlxsw_bus_info)3706 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
3707 const struct mlxsw_bus_info *mlxsw_bus_info)
3708 {
3709 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3710 int err;
3711
3712 mlxsw_sp->core = mlxsw_core;
3713 mlxsw_sp->bus_info = mlxsw_bus_info;
3714
3715 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3716 if (err)
3717 return err;
3718
3719 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3720 if (err) {
3721 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3722 return err;
3723 }
3724
3725 err = mlxsw_sp_kvdl_init(mlxsw_sp);
3726 if (err) {
3727 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3728 return err;
3729 }
3730
3731 err = mlxsw_sp_fids_init(mlxsw_sp);
3732 if (err) {
3733 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
3734 goto err_fids_init;
3735 }
3736
3737 err = mlxsw_sp_traps_init(mlxsw_sp);
3738 if (err) {
3739 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3740 goto err_traps_init;
3741 }
3742
3743 err = mlxsw_sp_buffers_init(mlxsw_sp);
3744 if (err) {
3745 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3746 goto err_buffers_init;
3747 }
3748
3749 err = mlxsw_sp_lag_init(mlxsw_sp);
3750 if (err) {
3751 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3752 goto err_lag_init;
3753 }
3754
3755 /* Initialize SPAN before router and switchdev, so that those components
3756 * can call mlxsw_sp_span_respin().
3757 */
3758 err = mlxsw_sp_span_init(mlxsw_sp);
3759 if (err) {
3760 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3761 goto err_span_init;
3762 }
3763
3764 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3765 if (err) {
3766 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3767 goto err_switchdev_init;
3768 }
3769
3770 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3771 if (err) {
3772 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3773 goto err_counter_pool_init;
3774 }
3775
3776 err = mlxsw_sp_afa_init(mlxsw_sp);
3777 if (err) {
3778 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3779 goto err_afa_init;
3780 }
3781
3782 err = mlxsw_sp_router_init(mlxsw_sp);
3783 if (err) {
3784 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3785 goto err_router_init;
3786 }
3787
3788 /* Initialize netdevice notifier after router and SPAN is initialized,
3789 * so that the event handler can use router structures and call SPAN
3790 * respin.
3791 */
3792 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
3793 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3794 if (err) {
3795 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
3796 goto err_netdev_notifier;
3797 }
3798
3799 err = mlxsw_sp_acl_init(mlxsw_sp);
3800 if (err) {
3801 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3802 goto err_acl_init;
3803 }
3804
3805 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3806 if (err) {
3807 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3808 goto err_dpipe_init;
3809 }
3810
3811 err = mlxsw_sp_ports_create(mlxsw_sp);
3812 if (err) {
3813 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3814 goto err_ports_create;
3815 }
3816
3817 return 0;
3818
3819 err_ports_create:
3820 mlxsw_sp_dpipe_fini(mlxsw_sp);
3821 err_dpipe_init:
3822 mlxsw_sp_acl_fini(mlxsw_sp);
3823 err_acl_init:
3824 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3825 err_netdev_notifier:
3826 mlxsw_sp_router_fini(mlxsw_sp);
3827 err_router_init:
3828 mlxsw_sp_afa_fini(mlxsw_sp);
3829 err_afa_init:
3830 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3831 err_counter_pool_init:
3832 mlxsw_sp_switchdev_fini(mlxsw_sp);
3833 err_switchdev_init:
3834 mlxsw_sp_span_fini(mlxsw_sp);
3835 err_span_init:
3836 mlxsw_sp_lag_fini(mlxsw_sp);
3837 err_lag_init:
3838 mlxsw_sp_buffers_fini(mlxsw_sp);
3839 err_buffers_init:
3840 mlxsw_sp_traps_fini(mlxsw_sp);
3841 err_traps_init:
3842 mlxsw_sp_fids_fini(mlxsw_sp);
3843 err_fids_init:
3844 mlxsw_sp_kvdl_fini(mlxsw_sp);
3845 return err;
3846 }
3847
mlxsw_sp1_init(struct mlxsw_core * mlxsw_core,const struct mlxsw_bus_info * mlxsw_bus_info)3848 static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core,
3849 const struct mlxsw_bus_info *mlxsw_bus_info)
3850 {
3851 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3852
3853 mlxsw_sp->req_rev = &mlxsw_sp1_fw_rev;
3854 mlxsw_sp->fw_filename = MLXSW_SP1_FW_FILENAME;
3855 mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops;
3856 mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops;
3857 mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops;
3858 mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops;
3859 mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops;
3860
3861 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info);
3862 }
3863
mlxsw_sp2_init(struct mlxsw_core * mlxsw_core,const struct mlxsw_bus_info * mlxsw_bus_info)3864 static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core,
3865 const struct mlxsw_bus_info *mlxsw_bus_info)
3866 {
3867 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3868
3869 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
3870 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
3871 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
3872 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
3873 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
3874
3875 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info);
3876 }
3877
mlxsw_sp_fini(struct mlxsw_core * mlxsw_core)3878 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
3879 {
3880 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3881
3882 mlxsw_sp_ports_remove(mlxsw_sp);
3883 mlxsw_sp_dpipe_fini(mlxsw_sp);
3884 mlxsw_sp_acl_fini(mlxsw_sp);
3885 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3886 mlxsw_sp_router_fini(mlxsw_sp);
3887 mlxsw_sp_afa_fini(mlxsw_sp);
3888 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3889 mlxsw_sp_switchdev_fini(mlxsw_sp);
3890 mlxsw_sp_span_fini(mlxsw_sp);
3891 mlxsw_sp_lag_fini(mlxsw_sp);
3892 mlxsw_sp_buffers_fini(mlxsw_sp);
3893 mlxsw_sp_traps_fini(mlxsw_sp);
3894 mlxsw_sp_fids_fini(mlxsw_sp);
3895 mlxsw_sp_kvdl_fini(mlxsw_sp);
3896 }
3897
3898 static const struct mlxsw_config_profile mlxsw_sp1_config_profile = {
3899 .used_max_mid = 1,
3900 .max_mid = MLXSW_SP_MID_MAX,
3901 .used_flood_tables = 1,
3902 .used_flood_mode = 1,
3903 .flood_mode = 3,
3904 .max_fid_offset_flood_tables = 3,
3905 .fid_offset_flood_table_size = VLAN_N_VID - 1,
3906 .max_fid_flood_tables = 3,
3907 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
3908 .used_max_ib_mc = 1,
3909 .max_ib_mc = 0,
3910 .used_max_pkey = 1,
3911 .max_pkey = 0,
3912 .used_kvd_sizes = 1,
3913 .kvd_hash_single_parts = 59,
3914 .kvd_hash_double_parts = 41,
3915 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
3916 .swid_config = {
3917 {
3918 .used_type = 1,
3919 .type = MLXSW_PORT_SWID_TYPE_ETH,
3920 }
3921 },
3922 };
3923
3924 static const struct mlxsw_config_profile mlxsw_sp2_config_profile = {
3925 .used_max_mid = 1,
3926 .max_mid = MLXSW_SP_MID_MAX,
3927 .used_flood_tables = 1,
3928 .used_flood_mode = 1,
3929 .flood_mode = 3,
3930 .max_fid_offset_flood_tables = 3,
3931 .fid_offset_flood_table_size = VLAN_N_VID - 1,
3932 .max_fid_flood_tables = 3,
3933 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
3934 .used_max_ib_mc = 1,
3935 .max_ib_mc = 0,
3936 .used_max_pkey = 1,
3937 .max_pkey = 0,
3938 .swid_config = {
3939 {
3940 .used_type = 1,
3941 .type = MLXSW_PORT_SWID_TYPE_ETH,
3942 }
3943 },
3944 };
3945
3946 static void
mlxsw_sp_resource_size_params_prepare(struct mlxsw_core * mlxsw_core,struct devlink_resource_size_params * kvd_size_params,struct devlink_resource_size_params * linear_size_params,struct devlink_resource_size_params * hash_double_size_params,struct devlink_resource_size_params * hash_single_size_params)3947 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
3948 struct devlink_resource_size_params *kvd_size_params,
3949 struct devlink_resource_size_params *linear_size_params,
3950 struct devlink_resource_size_params *hash_double_size_params,
3951 struct devlink_resource_size_params *hash_single_size_params)
3952 {
3953 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3954 KVD_SINGLE_MIN_SIZE);
3955 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3956 KVD_DOUBLE_MIN_SIZE);
3957 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3958 u32 linear_size_min = 0;
3959
3960 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size,
3961 MLXSW_SP_KVD_GRANULARITY,
3962 DEVLINK_RESOURCE_UNIT_ENTRY);
3963 devlink_resource_size_params_init(linear_size_params, linear_size_min,
3964 kvd_size - single_size_min -
3965 double_size_min,
3966 MLXSW_SP_KVD_GRANULARITY,
3967 DEVLINK_RESOURCE_UNIT_ENTRY);
3968 devlink_resource_size_params_init(hash_double_size_params,
3969 double_size_min,
3970 kvd_size - single_size_min -
3971 linear_size_min,
3972 MLXSW_SP_KVD_GRANULARITY,
3973 DEVLINK_RESOURCE_UNIT_ENTRY);
3974 devlink_resource_size_params_init(hash_single_size_params,
3975 single_size_min,
3976 kvd_size - double_size_min -
3977 linear_size_min,
3978 MLXSW_SP_KVD_GRANULARITY,
3979 DEVLINK_RESOURCE_UNIT_ENTRY);
3980 }
3981
mlxsw_sp1_resources_kvd_register(struct mlxsw_core * mlxsw_core)3982 static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core)
3983 {
3984 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3985 struct devlink_resource_size_params hash_single_size_params;
3986 struct devlink_resource_size_params hash_double_size_params;
3987 struct devlink_resource_size_params linear_size_params;
3988 struct devlink_resource_size_params kvd_size_params;
3989 u32 kvd_size, single_size, double_size, linear_size;
3990 const struct mlxsw_config_profile *profile;
3991 int err;
3992
3993 profile = &mlxsw_sp1_config_profile;
3994 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
3995 return -EIO;
3996
3997 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
3998 &linear_size_params,
3999 &hash_double_size_params,
4000 &hash_single_size_params);
4001
4002 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
4003 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
4004 kvd_size, MLXSW_SP_RESOURCE_KVD,
4005 DEVLINK_RESOURCE_ID_PARENT_TOP,
4006 &kvd_size_params);
4007 if (err)
4008 return err;
4009
4010 linear_size = profile->kvd_linear_size;
4011 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
4012 linear_size,
4013 MLXSW_SP_RESOURCE_KVD_LINEAR,
4014 MLXSW_SP_RESOURCE_KVD,
4015 &linear_size_params);
4016 if (err)
4017 return err;
4018
4019 err = mlxsw_sp1_kvdl_resources_register(mlxsw_core);
4020 if (err)
4021 return err;
4022
4023 double_size = kvd_size - linear_size;
4024 double_size *= profile->kvd_hash_double_parts;
4025 double_size /= profile->kvd_hash_double_parts +
4026 profile->kvd_hash_single_parts;
4027 double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY);
4028 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
4029 double_size,
4030 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
4031 MLXSW_SP_RESOURCE_KVD,
4032 &hash_double_size_params);
4033 if (err)
4034 return err;
4035
4036 single_size = kvd_size - double_size - linear_size;
4037 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
4038 single_size,
4039 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
4040 MLXSW_SP_RESOURCE_KVD,
4041 &hash_single_size_params);
4042 if (err)
4043 return err;
4044
4045 return 0;
4046 }
4047
mlxsw_sp1_resources_register(struct mlxsw_core * mlxsw_core)4048 static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core)
4049 {
4050 return mlxsw_sp1_resources_kvd_register(mlxsw_core);
4051 }
4052
mlxsw_sp2_resources_register(struct mlxsw_core * mlxsw_core)4053 static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core)
4054 {
4055 return 0;
4056 }
4057
mlxsw_sp_kvd_sizes_get(struct mlxsw_core * mlxsw_core,const struct mlxsw_config_profile * profile,u64 * p_single_size,u64 * p_double_size,u64 * p_linear_size)4058 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
4059 const struct mlxsw_config_profile *profile,
4060 u64 *p_single_size, u64 *p_double_size,
4061 u64 *p_linear_size)
4062 {
4063 struct devlink *devlink = priv_to_devlink(mlxsw_core);
4064 u32 double_size;
4065 int err;
4066
4067 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
4068 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE))
4069 return -EIO;
4070
4071 /* The hash part is what left of the kvd without the
4072 * linear part. It is split to the single size and
4073 * double size by the parts ratio from the profile.
4074 * Both sizes must be a multiplications of the
4075 * granularity from the profile. In case the user
4076 * provided the sizes they are obtained via devlink.
4077 */
4078 err = devlink_resource_size_get(devlink,
4079 MLXSW_SP_RESOURCE_KVD_LINEAR,
4080 p_linear_size);
4081 if (err)
4082 *p_linear_size = profile->kvd_linear_size;
4083
4084 err = devlink_resource_size_get(devlink,
4085 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
4086 p_double_size);
4087 if (err) {
4088 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
4089 *p_linear_size;
4090 double_size *= profile->kvd_hash_double_parts;
4091 double_size /= profile->kvd_hash_double_parts +
4092 profile->kvd_hash_single_parts;
4093 *p_double_size = rounddown(double_size,
4094 MLXSW_SP_KVD_GRANULARITY);
4095 }
4096
4097 err = devlink_resource_size_get(devlink,
4098 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
4099 p_single_size);
4100 if (err)
4101 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
4102 *p_double_size - *p_linear_size;
4103
4104 /* Check results are legal. */
4105 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
4106 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
4107 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
4108 return -EIO;
4109
4110 return 0;
4111 }
4112
4113 static struct mlxsw_driver mlxsw_sp1_driver = {
4114 .kind = mlxsw_sp1_driver_name,
4115 .priv_size = sizeof(struct mlxsw_sp),
4116 .init = mlxsw_sp1_init,
4117 .fini = mlxsw_sp_fini,
4118 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
4119 .port_split = mlxsw_sp_port_split,
4120 .port_unsplit = mlxsw_sp_port_unsplit,
4121 .sb_pool_get = mlxsw_sp_sb_pool_get,
4122 .sb_pool_set = mlxsw_sp_sb_pool_set,
4123 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
4124 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
4125 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
4126 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
4127 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
4128 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
4129 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
4130 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
4131 .txhdr_construct = mlxsw_sp_txhdr_construct,
4132 .resources_register = mlxsw_sp1_resources_register,
4133 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
4134 .txhdr_len = MLXSW_TXHDR_LEN,
4135 .profile = &mlxsw_sp1_config_profile,
4136 .res_query_enabled = true,
4137 };
4138
4139 static struct mlxsw_driver mlxsw_sp2_driver = {
4140 .kind = mlxsw_sp2_driver_name,
4141 .priv_size = sizeof(struct mlxsw_sp),
4142 .init = mlxsw_sp2_init,
4143 .fini = mlxsw_sp_fini,
4144 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
4145 .port_split = mlxsw_sp_port_split,
4146 .port_unsplit = mlxsw_sp_port_unsplit,
4147 .sb_pool_get = mlxsw_sp_sb_pool_get,
4148 .sb_pool_set = mlxsw_sp_sb_pool_set,
4149 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
4150 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
4151 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
4152 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
4153 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
4154 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
4155 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
4156 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
4157 .txhdr_construct = mlxsw_sp_txhdr_construct,
4158 .resources_register = mlxsw_sp2_resources_register,
4159 .txhdr_len = MLXSW_TXHDR_LEN,
4160 .profile = &mlxsw_sp2_config_profile,
4161 .res_query_enabled = true,
4162 };
4163
mlxsw_sp_port_dev_check(const struct net_device * dev)4164 bool mlxsw_sp_port_dev_check(const struct net_device *dev)
4165 {
4166 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
4167 }
4168
mlxsw_sp_lower_dev_walk(struct net_device * lower_dev,void * data)4169 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
4170 {
4171 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
4172 int ret = 0;
4173
4174 if (mlxsw_sp_port_dev_check(lower_dev)) {
4175 *p_mlxsw_sp_port = netdev_priv(lower_dev);
4176 ret = 1;
4177 }
4178
4179 return ret;
4180 }
4181
mlxsw_sp_port_dev_lower_find(struct net_device * dev)4182 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
4183 {
4184 struct mlxsw_sp_port *mlxsw_sp_port;
4185
4186 if (mlxsw_sp_port_dev_check(dev))
4187 return netdev_priv(dev);
4188
4189 mlxsw_sp_port = NULL;
4190 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
4191
4192 return mlxsw_sp_port;
4193 }
4194
mlxsw_sp_lower_get(struct net_device * dev)4195 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
4196 {
4197 struct mlxsw_sp_port *mlxsw_sp_port;
4198
4199 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
4200 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
4201 }
4202
mlxsw_sp_port_dev_lower_find_rcu(struct net_device * dev)4203 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
4204 {
4205 struct mlxsw_sp_port *mlxsw_sp_port;
4206
4207 if (mlxsw_sp_port_dev_check(dev))
4208 return netdev_priv(dev);
4209
4210 mlxsw_sp_port = NULL;
4211 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
4212 &mlxsw_sp_port);
4213
4214 return mlxsw_sp_port;
4215 }
4216
mlxsw_sp_port_lower_dev_hold(struct net_device * dev)4217 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
4218 {
4219 struct mlxsw_sp_port *mlxsw_sp_port;
4220
4221 rcu_read_lock();
4222 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
4223 if (mlxsw_sp_port)
4224 dev_hold(mlxsw_sp_port->dev);
4225 rcu_read_unlock();
4226 return mlxsw_sp_port;
4227 }
4228
mlxsw_sp_port_dev_put(struct mlxsw_sp_port * mlxsw_sp_port)4229 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
4230 {
4231 dev_put(mlxsw_sp_port->dev);
4232 }
4233
mlxsw_sp_lag_create(struct mlxsw_sp * mlxsw_sp,u16 lag_id)4234 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4235 {
4236 char sldr_pl[MLXSW_REG_SLDR_LEN];
4237
4238 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4239 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4240 }
4241
mlxsw_sp_lag_destroy(struct mlxsw_sp * mlxsw_sp,u16 lag_id)4242 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4243 {
4244 char sldr_pl[MLXSW_REG_SLDR_LEN];
4245
4246 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4247 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4248 }
4249
mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port * mlxsw_sp_port,u16 lag_id,u8 port_index)4250 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4251 u16 lag_id, u8 port_index)
4252 {
4253 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4254 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4255
4256 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4257 lag_id, port_index);
4258 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4259 }
4260
mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port * mlxsw_sp_port,u16 lag_id)4261 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4262 u16 lag_id)
4263 {
4264 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4265 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4266
4267 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4268 lag_id);
4269 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4270 }
4271
mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port * mlxsw_sp_port,u16 lag_id)4272 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4273 u16 lag_id)
4274 {
4275 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4276 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4277
4278 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4279 lag_id);
4280 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4281 }
4282
mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port * mlxsw_sp_port,u16 lag_id)4283 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4284 u16 lag_id)
4285 {
4286 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4287 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4288
4289 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4290 lag_id);
4291 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4292 }
4293
mlxsw_sp_lag_index_get(struct mlxsw_sp * mlxsw_sp,struct net_device * lag_dev,u16 * p_lag_id)4294 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4295 struct net_device *lag_dev,
4296 u16 *p_lag_id)
4297 {
4298 struct mlxsw_sp_upper *lag;
4299 int free_lag_id = -1;
4300 u64 max_lag;
4301 int i;
4302
4303 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4304 for (i = 0; i < max_lag; i++) {
4305 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4306 if (lag->ref_count) {
4307 if (lag->dev == lag_dev) {
4308 *p_lag_id = i;
4309 return 0;
4310 }
4311 } else if (free_lag_id < 0) {
4312 free_lag_id = i;
4313 }
4314 }
4315 if (free_lag_id < 0)
4316 return -EBUSY;
4317 *p_lag_id = free_lag_id;
4318 return 0;
4319 }
4320
4321 static bool
mlxsw_sp_master_lag_check(struct mlxsw_sp * mlxsw_sp,struct net_device * lag_dev,struct netdev_lag_upper_info * lag_upper_info,struct netlink_ext_ack * extack)4322 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4323 struct net_device *lag_dev,
4324 struct netdev_lag_upper_info *lag_upper_info,
4325 struct netlink_ext_ack *extack)
4326 {
4327 u16 lag_id;
4328
4329 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
4330 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices");
4331 return false;
4332 }
4333 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
4334 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
4335 return false;
4336 }
4337 return true;
4338 }
4339
mlxsw_sp_port_lag_index_get(struct mlxsw_sp * mlxsw_sp,u16 lag_id,u8 * p_port_index)4340 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4341 u16 lag_id, u8 *p_port_index)
4342 {
4343 u64 max_lag_members;
4344 int i;
4345
4346 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4347 MAX_LAG_MEMBERS);
4348 for (i = 0; i < max_lag_members; i++) {
4349 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4350 *p_port_index = i;
4351 return 0;
4352 }
4353 }
4354 return -EBUSY;
4355 }
4356
mlxsw_sp_port_lag_join(struct mlxsw_sp_port * mlxsw_sp_port,struct net_device * lag_dev)4357 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4358 struct net_device *lag_dev)
4359 {
4360 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4361 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
4362 struct mlxsw_sp_upper *lag;
4363 u16 lag_id;
4364 u8 port_index;
4365 int err;
4366
4367 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4368 if (err)
4369 return err;
4370 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4371 if (!lag->ref_count) {
4372 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4373 if (err)
4374 return err;
4375 lag->dev = lag_dev;
4376 }
4377
4378 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4379 if (err)
4380 return err;
4381 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4382 if (err)
4383 goto err_col_port_add;
4384 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4385 if (err)
4386 goto err_col_port_enable;
4387
4388 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4389 mlxsw_sp_port->local_port);
4390 mlxsw_sp_port->lag_id = lag_id;
4391 mlxsw_sp_port->lagged = 1;
4392 lag->ref_count++;
4393
4394 /* Port is no longer usable as a router interface */
4395 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4396 if (mlxsw_sp_port_vlan->fid)
4397 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
4398
4399 return 0;
4400
4401 err_col_port_enable:
4402 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
4403 err_col_port_add:
4404 if (!lag->ref_count)
4405 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
4406 return err;
4407 }
4408
mlxsw_sp_port_lag_leave(struct mlxsw_sp_port * mlxsw_sp_port,struct net_device * lag_dev)4409 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4410 struct net_device *lag_dev)
4411 {
4412 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4413 u16 lag_id = mlxsw_sp_port->lag_id;
4414 struct mlxsw_sp_upper *lag;
4415
4416 if (!mlxsw_sp_port->lagged)
4417 return;
4418 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4419 WARN_ON(lag->ref_count == 0);
4420
4421 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4422 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
4423
4424 /* Any VLANs configured on the port are no longer valid */
4425 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
4426
4427 if (lag->ref_count == 1)
4428 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
4429
4430 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4431 mlxsw_sp_port->local_port);
4432 mlxsw_sp_port->lagged = 0;
4433 lag->ref_count--;
4434
4435 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4436 /* Make sure untagged frames are allowed to ingress */
4437 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
4438 }
4439
mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port * mlxsw_sp_port,u16 lag_id)4440 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4441 u16 lag_id)
4442 {
4443 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4444 char sldr_pl[MLXSW_REG_SLDR_LEN];
4445
4446 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4447 mlxsw_sp_port->local_port);
4448 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4449 }
4450
mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port * mlxsw_sp_port,u16 lag_id)4451 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4452 u16 lag_id)
4453 {
4454 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4455 char sldr_pl[MLXSW_REG_SLDR_LEN];
4456
4457 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4458 mlxsw_sp_port->local_port);
4459 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4460 }
4461
mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port * mlxsw_sp_port,bool lag_tx_enabled)4462 static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4463 bool lag_tx_enabled)
4464 {
4465 if (lag_tx_enabled)
4466 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4467 mlxsw_sp_port->lag_id);
4468 else
4469 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4470 mlxsw_sp_port->lag_id);
4471 }
4472
mlxsw_sp_port_lag_changed(struct mlxsw_sp_port * mlxsw_sp_port,struct netdev_lag_lower_state_info * info)4473 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4474 struct netdev_lag_lower_state_info *info)
4475 {
4476 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4477 }
4478
mlxsw_sp_port_stp_set(struct mlxsw_sp_port * mlxsw_sp_port,bool enable)4479 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4480 bool enable)
4481 {
4482 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4483 enum mlxsw_reg_spms_state spms_state;
4484 char *spms_pl;
4485 u16 vid;
4486 int err;
4487
4488 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4489 MLXSW_REG_SPMS_STATE_DISCARDING;
4490
4491 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4492 if (!spms_pl)
4493 return -ENOMEM;
4494 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4495
4496 for (vid = 0; vid < VLAN_N_VID; vid++)
4497 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4498
4499 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4500 kfree(spms_pl);
4501 return err;
4502 }
4503
mlxsw_sp_port_ovs_join(struct mlxsw_sp_port * mlxsw_sp_port)4504 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4505 {
4506 u16 vid = 1;
4507 int err;
4508
4509 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
4510 if (err)
4511 return err;
4512 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4513 if (err)
4514 goto err_port_stp_set;
4515 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4516 true, false);
4517 if (err)
4518 goto err_port_vlan_set;
4519
4520 for (; vid <= VLAN_N_VID - 1; vid++) {
4521 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4522 vid, false);
4523 if (err)
4524 goto err_vid_learning_set;
4525 }
4526
4527 return 0;
4528
4529 err_vid_learning_set:
4530 for (vid--; vid >= 1; vid--)
4531 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
4532 err_port_vlan_set:
4533 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4534 err_port_stp_set:
4535 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
4536 return err;
4537 }
4538
mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port * mlxsw_sp_port)4539 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4540 {
4541 u16 vid;
4542
4543 for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
4544 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4545 vid, true);
4546
4547 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4548 false, false);
4549 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4550 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
4551 }
4552
mlxsw_sp_netdevice_port_upper_event(struct net_device * lower_dev,struct net_device * dev,unsigned long event,void * ptr)4553 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4554 struct net_device *dev,
4555 unsigned long event, void *ptr)
4556 {
4557 struct netdev_notifier_changeupper_info *info;
4558 struct mlxsw_sp_port *mlxsw_sp_port;
4559 struct netlink_ext_ack *extack;
4560 struct net_device *upper_dev;
4561 struct mlxsw_sp *mlxsw_sp;
4562 int err = 0;
4563
4564 mlxsw_sp_port = netdev_priv(dev);
4565 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4566 info = ptr;
4567 extack = netdev_notifier_info_to_extack(&info->info);
4568
4569 switch (event) {
4570 case NETDEV_PRECHANGEUPPER:
4571 upper_dev = info->upper_dev;
4572 if (!is_vlan_dev(upper_dev) &&
4573 !netif_is_lag_master(upper_dev) &&
4574 !netif_is_bridge_master(upper_dev) &&
4575 !netif_is_ovs_master(upper_dev) &&
4576 !netif_is_macvlan(upper_dev)) {
4577 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4578 return -EINVAL;
4579 }
4580 if (!info->linking)
4581 break;
4582 if (netdev_has_any_upper_dev(upper_dev) &&
4583 (!netif_is_bridge_master(upper_dev) ||
4584 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4585 upper_dev))) {
4586 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
4587 return -EINVAL;
4588 }
4589 if (netif_is_lag_master(upper_dev) &&
4590 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4591 info->upper_info, extack))
4592 return -EINVAL;
4593 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
4594 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
4595 return -EINVAL;
4596 }
4597 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
4598 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
4599 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
4600 return -EINVAL;
4601 }
4602 if (netif_is_macvlan(upper_dev) &&
4603 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, lower_dev)) {
4604 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
4605 return -EOPNOTSUPP;
4606 }
4607 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
4608 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
4609 return -EINVAL;
4610 }
4611 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
4612 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
4613 return -EINVAL;
4614 }
4615 if (is_vlan_dev(upper_dev) &&
4616 vlan_dev_vlan_id(upper_dev) == 1) {
4617 NL_SET_ERR_MSG_MOD(extack, "Creating a VLAN device with VID 1 is unsupported: VLAN 1 carries untagged traffic");
4618 return -EINVAL;
4619 }
4620 break;
4621 case NETDEV_CHANGEUPPER:
4622 upper_dev = info->upper_dev;
4623 if (netif_is_bridge_master(upper_dev)) {
4624 if (info->linking)
4625 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4626 lower_dev,
4627 upper_dev,
4628 extack);
4629 else
4630 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4631 lower_dev,
4632 upper_dev);
4633 } else if (netif_is_lag_master(upper_dev)) {
4634 if (info->linking)
4635 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4636 upper_dev);
4637 else
4638 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4639 upper_dev);
4640 } else if (netif_is_ovs_master(upper_dev)) {
4641 if (info->linking)
4642 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4643 else
4644 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
4645 } else if (netif_is_macvlan(upper_dev)) {
4646 if (!info->linking)
4647 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
4648 }
4649 break;
4650 }
4651
4652 return err;
4653 }
4654
mlxsw_sp_netdevice_port_lower_event(struct net_device * dev,unsigned long event,void * ptr)4655 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4656 unsigned long event, void *ptr)
4657 {
4658 struct netdev_notifier_changelowerstate_info *info;
4659 struct mlxsw_sp_port *mlxsw_sp_port;
4660 int err;
4661
4662 mlxsw_sp_port = netdev_priv(dev);
4663 info = ptr;
4664
4665 switch (event) {
4666 case NETDEV_CHANGELOWERSTATE:
4667 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4668 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4669 info->lower_state_info);
4670 if (err)
4671 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4672 }
4673 break;
4674 }
4675
4676 return 0;
4677 }
4678
mlxsw_sp_netdevice_port_event(struct net_device * lower_dev,struct net_device * port_dev,unsigned long event,void * ptr)4679 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4680 struct net_device *port_dev,
4681 unsigned long event, void *ptr)
4682 {
4683 switch (event) {
4684 case NETDEV_PRECHANGEUPPER:
4685 case NETDEV_CHANGEUPPER:
4686 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4687 event, ptr);
4688 case NETDEV_CHANGELOWERSTATE:
4689 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4690 ptr);
4691 }
4692
4693 return 0;
4694 }
4695
mlxsw_sp_netdevice_lag_event(struct net_device * lag_dev,unsigned long event,void * ptr)4696 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4697 unsigned long event, void *ptr)
4698 {
4699 struct net_device *dev;
4700 struct list_head *iter;
4701 int ret;
4702
4703 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4704 if (mlxsw_sp_port_dev_check(dev)) {
4705 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4706 ptr);
4707 if (ret)
4708 return ret;
4709 }
4710 }
4711
4712 return 0;
4713 }
4714
mlxsw_sp_netdevice_port_vlan_event(struct net_device * vlan_dev,struct net_device * dev,unsigned long event,void * ptr,u16 vid)4715 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4716 struct net_device *dev,
4717 unsigned long event, void *ptr,
4718 u16 vid)
4719 {
4720 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4721 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4722 struct netdev_notifier_changeupper_info *info = ptr;
4723 struct netlink_ext_ack *extack;
4724 struct net_device *upper_dev;
4725 int err = 0;
4726
4727 extack = netdev_notifier_info_to_extack(&info->info);
4728
4729 switch (event) {
4730 case NETDEV_PRECHANGEUPPER:
4731 upper_dev = info->upper_dev;
4732 if (!netif_is_bridge_master(upper_dev) &&
4733 !netif_is_macvlan(upper_dev)) {
4734 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4735 return -EINVAL;
4736 }
4737 if (!info->linking)
4738 break;
4739 if (netdev_has_any_upper_dev(upper_dev) &&
4740 (!netif_is_bridge_master(upper_dev) ||
4741 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4742 upper_dev))) {
4743 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
4744 return -EINVAL;
4745 }
4746 if (netif_is_macvlan(upper_dev) &&
4747 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, vlan_dev)) {
4748 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
4749 return -EOPNOTSUPP;
4750 }
4751 break;
4752 case NETDEV_CHANGEUPPER:
4753 upper_dev = info->upper_dev;
4754 if (netif_is_bridge_master(upper_dev)) {
4755 if (info->linking)
4756 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4757 vlan_dev,
4758 upper_dev,
4759 extack);
4760 else
4761 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4762 vlan_dev,
4763 upper_dev);
4764 } else if (netif_is_macvlan(upper_dev)) {
4765 if (!info->linking)
4766 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
4767 } else {
4768 err = -EINVAL;
4769 WARN_ON(1);
4770 }
4771 break;
4772 }
4773
4774 return err;
4775 }
4776
mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device * vlan_dev,struct net_device * lag_dev,unsigned long event,void * ptr,u16 vid)4777 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4778 struct net_device *lag_dev,
4779 unsigned long event,
4780 void *ptr, u16 vid)
4781 {
4782 struct net_device *dev;
4783 struct list_head *iter;
4784 int ret;
4785
4786 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4787 if (mlxsw_sp_port_dev_check(dev)) {
4788 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4789 event, ptr,
4790 vid);
4791 if (ret)
4792 return ret;
4793 }
4794 }
4795
4796 return 0;
4797 }
4798
mlxsw_sp_netdevice_vlan_event(struct net_device * vlan_dev,unsigned long event,void * ptr)4799 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4800 unsigned long event, void *ptr)
4801 {
4802 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4803 u16 vid = vlan_dev_vlan_id(vlan_dev);
4804
4805 if (mlxsw_sp_port_dev_check(real_dev))
4806 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
4807 event, ptr, vid);
4808 else if (netif_is_lag_master(real_dev))
4809 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
4810 real_dev, event,
4811 ptr, vid);
4812
4813 return 0;
4814 }
4815
mlxsw_sp_netdevice_bridge_event(struct net_device * br_dev,unsigned long event,void * ptr)4816 static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
4817 unsigned long event, void *ptr)
4818 {
4819 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(br_dev);
4820 struct netdev_notifier_changeupper_info *info = ptr;
4821 struct netlink_ext_ack *extack;
4822 struct net_device *upper_dev;
4823
4824 if (!mlxsw_sp)
4825 return 0;
4826
4827 extack = netdev_notifier_info_to_extack(&info->info);
4828
4829 switch (event) {
4830 case NETDEV_PRECHANGEUPPER:
4831 upper_dev = info->upper_dev;
4832 if (!is_vlan_dev(upper_dev) && !netif_is_macvlan(upper_dev)) {
4833 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4834 return -EOPNOTSUPP;
4835 }
4836 if (!info->linking)
4837 break;
4838 if (netif_is_macvlan(upper_dev) &&
4839 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, br_dev)) {
4840 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
4841 return -EOPNOTSUPP;
4842 }
4843 break;
4844 case NETDEV_CHANGEUPPER:
4845 upper_dev = info->upper_dev;
4846 if (info->linking)
4847 break;
4848 if (is_vlan_dev(upper_dev))
4849 mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev);
4850 if (netif_is_macvlan(upper_dev))
4851 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
4852 break;
4853 }
4854
4855 return 0;
4856 }
4857
mlxsw_sp_netdevice_macvlan_event(struct net_device * macvlan_dev,unsigned long event,void * ptr)4858 static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev,
4859 unsigned long event, void *ptr)
4860 {
4861 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev);
4862 struct netdev_notifier_changeupper_info *info = ptr;
4863 struct netlink_ext_ack *extack;
4864
4865 if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER)
4866 return 0;
4867
4868 extack = netdev_notifier_info_to_extack(&info->info);
4869
4870 /* VRF enslavement is handled in mlxsw_sp_netdevice_vrf_event() */
4871 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4872
4873 return -EOPNOTSUPP;
4874 }
4875
mlxsw_sp_is_vrf_event(unsigned long event,void * ptr)4876 static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4877 {
4878 struct netdev_notifier_changeupper_info *info = ptr;
4879
4880 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4881 return false;
4882 return netif_is_l3_master(info->upper_dev);
4883 }
4884
mlxsw_sp_netdevice_event(struct notifier_block * nb,unsigned long event,void * ptr)4885 static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
4886 unsigned long event, void *ptr)
4887 {
4888 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
4889 struct mlxsw_sp_span_entry *span_entry;
4890 struct mlxsw_sp *mlxsw_sp;
4891 int err = 0;
4892
4893 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
4894 if (event == NETDEV_UNREGISTER) {
4895 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
4896 if (span_entry)
4897 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
4898 }
4899 mlxsw_sp_span_respin(mlxsw_sp);
4900
4901 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
4902 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
4903 event, ptr);
4904 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
4905 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
4906 event, ptr);
4907 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
4908 err = mlxsw_sp_netdevice_router_port_event(dev);
4909 else if (mlxsw_sp_is_vrf_event(event, ptr))
4910 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
4911 else if (mlxsw_sp_port_dev_check(dev))
4912 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
4913 else if (netif_is_lag_master(dev))
4914 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
4915 else if (is_vlan_dev(dev))
4916 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
4917 else if (netif_is_bridge_master(dev))
4918 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
4919 else if (netif_is_macvlan(dev))
4920 err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr);
4921
4922 return notifier_from_errno(err);
4923 }
4924
4925 static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
4926 .notifier_call = mlxsw_sp_inetaddr_valid_event,
4927 };
4928
4929 static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4930 .notifier_call = mlxsw_sp_inetaddr_event,
4931 };
4932
4933 static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
4934 .notifier_call = mlxsw_sp_inet6addr_valid_event,
4935 };
4936
4937 static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
4938 .notifier_call = mlxsw_sp_inet6addr_event,
4939 };
4940
4941 static const struct pci_device_id mlxsw_sp1_pci_id_table[] = {
4942 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4943 {0, },
4944 };
4945
4946 static struct pci_driver mlxsw_sp1_pci_driver = {
4947 .name = mlxsw_sp1_driver_name,
4948 .id_table = mlxsw_sp1_pci_id_table,
4949 };
4950
4951 static const struct pci_device_id mlxsw_sp2_pci_id_table[] = {
4952 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0},
4953 {0, },
4954 };
4955
4956 static struct pci_driver mlxsw_sp2_pci_driver = {
4957 .name = mlxsw_sp2_driver_name,
4958 .id_table = mlxsw_sp2_pci_id_table,
4959 };
4960
mlxsw_sp_module_init(void)4961 static int __init mlxsw_sp_module_init(void)
4962 {
4963 int err;
4964
4965 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
4966 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
4967 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
4968 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
4969
4970 err = mlxsw_core_driver_register(&mlxsw_sp1_driver);
4971 if (err)
4972 goto err_sp1_core_driver_register;
4973
4974 err = mlxsw_core_driver_register(&mlxsw_sp2_driver);
4975 if (err)
4976 goto err_sp2_core_driver_register;
4977
4978 err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver);
4979 if (err)
4980 goto err_sp1_pci_driver_register;
4981
4982 err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver);
4983 if (err)
4984 goto err_sp2_pci_driver_register;
4985
4986 return 0;
4987
4988 err_sp2_pci_driver_register:
4989 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
4990 err_sp1_pci_driver_register:
4991 mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
4992 err_sp2_core_driver_register:
4993 mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
4994 err_sp1_core_driver_register:
4995 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
4996 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
4997 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
4998 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
4999 return err;
5000 }
5001
mlxsw_sp_module_exit(void)5002 static void __exit mlxsw_sp_module_exit(void)
5003 {
5004 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
5005 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
5006 mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
5007 mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
5008 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
5009 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
5010 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
5011 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
5012 }
5013
5014 module_init(mlxsw_sp_module_init);
5015 module_exit(mlxsw_sp_module_exit);
5016
5017 MODULE_LICENSE("Dual BSD/GPL");
5018 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
5019 MODULE_DESCRIPTION("Mellanox Spectrum driver");
5020 MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table);
5021 MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table);
5022 MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME);
5023
