1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2016-2018 Mellanox Technologies. All rights reserved */
3
4 #ifndef _MLXSW_RESOURCES_H
5 #define _MLXSW_RESOURCES_H
6
7 #include <linux/kernel.h>
8 #include <linux/types.h>
9
10 enum mlxsw_res_id {
11 MLXSW_RES_ID_KVD_SIZE,
12 MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE,
13 MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE,
14 MLXSW_RES_ID_MAX_KVD_LINEAR_RANGE,
15 MLXSW_RES_ID_MAX_KVD_ACTION_SETS,
16 MLXSW_RES_ID_MAX_TRAP_GROUPS,
17 MLXSW_RES_ID_CQE_V0,
18 MLXSW_RES_ID_CQE_V1,
19 MLXSW_RES_ID_CQE_V2,
20 MLXSW_RES_ID_COUNTER_POOL_SIZE,
21 MLXSW_RES_ID_MAX_SPAN,
22 MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES,
23 MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC,
24 MLXSW_RES_ID_MAX_SYSTEM_PORT,
25 MLXSW_RES_ID_MAX_LAG,
26 MLXSW_RES_ID_MAX_LAG_MEMBERS,
27 MLXSW_RES_ID_MAX_BUFFER_SIZE,
28 MLXSW_RES_ID_CELL_SIZE,
29 MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS,
30 MLXSW_RES_ID_ACL_MAX_TCAM_RULES,
31 MLXSW_RES_ID_ACL_MAX_REGIONS,
32 MLXSW_RES_ID_ACL_MAX_GROUPS,
33 MLXSW_RES_ID_ACL_MAX_GROUP_SIZE,
34 MLXSW_RES_ID_ACL_FLEX_KEYS,
35 MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE,
36 MLXSW_RES_ID_ACL_ACTIONS_PER_SET,
37 MLXSW_RES_ID_ACL_MAX_ERPT_BANKS,
38 MLXSW_RES_ID_ACL_MAX_ERPT_BANK_SIZE,
39 MLXSW_RES_ID_ACL_MAX_LARGE_KEY_ID,
40 MLXSW_RES_ID_ACL_ERPT_ENTRIES_2KB,
41 MLXSW_RES_ID_ACL_ERPT_ENTRIES_4KB,
42 MLXSW_RES_ID_ACL_ERPT_ENTRIES_8KB,
43 MLXSW_RES_ID_ACL_ERPT_ENTRIES_12KB,
44 MLXSW_RES_ID_MAX_CPU_POLICERS,
45 MLXSW_RES_ID_MAX_VRS,
46 MLXSW_RES_ID_MAX_RIFS,
47 MLXSW_RES_ID_MC_ERIF_LIST_ENTRIES,
48 MLXSW_RES_ID_MAX_LPM_TREES,
49
50 /* Internal resources.
51 * Determined by the SW, not queried from the HW.
52 */
53 MLXSW_RES_ID_KVD_SINGLE_SIZE,
54 MLXSW_RES_ID_KVD_DOUBLE_SIZE,
55 MLXSW_RES_ID_KVD_LINEAR_SIZE,
56
57 __MLXSW_RES_ID_MAX,
58 };
59
60 static u16 mlxsw_res_ids[] = {
61 [MLXSW_RES_ID_KVD_SIZE] = 0x1001,
62 [MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE] = 0x1002,
63 [MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE] = 0x1003,
64 [MLXSW_RES_ID_MAX_KVD_LINEAR_RANGE] = 0x1005,
65 [MLXSW_RES_ID_MAX_KVD_ACTION_SETS] = 0x1007,
66 [MLXSW_RES_ID_MAX_TRAP_GROUPS] = 0x2201,
67 [MLXSW_RES_ID_CQE_V0] = 0x2210,
68 [MLXSW_RES_ID_CQE_V1] = 0x2211,
69 [MLXSW_RES_ID_CQE_V2] = 0x2212,
70 [MLXSW_RES_ID_COUNTER_POOL_SIZE] = 0x2410,
71 [MLXSW_RES_ID_MAX_SPAN] = 0x2420,
72 [MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES] = 0x2443,
73 [MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC] = 0x2449,
74 [MLXSW_RES_ID_MAX_SYSTEM_PORT] = 0x2502,
75 [MLXSW_RES_ID_MAX_LAG] = 0x2520,
76 [MLXSW_RES_ID_MAX_LAG_MEMBERS] = 0x2521,
77 [MLXSW_RES_ID_MAX_BUFFER_SIZE] = 0x2802, /* Bytes */
78 [MLXSW_RES_ID_CELL_SIZE] = 0x2803, /* Bytes */
79 [MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS] = 0x2901,
80 [MLXSW_RES_ID_ACL_MAX_TCAM_RULES] = 0x2902,
81 [MLXSW_RES_ID_ACL_MAX_REGIONS] = 0x2903,
82 [MLXSW_RES_ID_ACL_MAX_GROUPS] = 0x2904,
83 [MLXSW_RES_ID_ACL_MAX_GROUP_SIZE] = 0x2905,
84 [MLXSW_RES_ID_ACL_FLEX_KEYS] = 0x2910,
85 [MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE] = 0x2911,
86 [MLXSW_RES_ID_ACL_ACTIONS_PER_SET] = 0x2912,
87 [MLXSW_RES_ID_ACL_MAX_ERPT_BANKS] = 0x2940,
88 [MLXSW_RES_ID_ACL_MAX_ERPT_BANK_SIZE] = 0x2941,
89 [MLXSW_RES_ID_ACL_MAX_LARGE_KEY_ID] = 0x2942,
90 [MLXSW_RES_ID_ACL_ERPT_ENTRIES_2KB] = 0x2950,
91 [MLXSW_RES_ID_ACL_ERPT_ENTRIES_4KB] = 0x2951,
92 [MLXSW_RES_ID_ACL_ERPT_ENTRIES_8KB] = 0x2952,
93 [MLXSW_RES_ID_ACL_ERPT_ENTRIES_12KB] = 0x2953,
94 [MLXSW_RES_ID_MAX_CPU_POLICERS] = 0x2A13,
95 [MLXSW_RES_ID_MAX_VRS] = 0x2C01,
96 [MLXSW_RES_ID_MAX_RIFS] = 0x2C02,
97 [MLXSW_RES_ID_MC_ERIF_LIST_ENTRIES] = 0x2C10,
98 [MLXSW_RES_ID_MAX_LPM_TREES] = 0x2C30,
99 };
100
101 struct mlxsw_res {
102 bool valid[__MLXSW_RES_ID_MAX];
103 u64 values[__MLXSW_RES_ID_MAX];
104 };
105
mlxsw_res_valid(struct mlxsw_res * res,enum mlxsw_res_id res_id)106 static inline bool mlxsw_res_valid(struct mlxsw_res *res,
107 enum mlxsw_res_id res_id)
108 {
109 return res->valid[res_id];
110 }
111
112 #define MLXSW_RES_VALID(res, short_res_id) \
113 mlxsw_res_valid(res, MLXSW_RES_ID_##short_res_id)
114
mlxsw_res_get(struct mlxsw_res * res,enum mlxsw_res_id res_id)115 static inline u64 mlxsw_res_get(struct mlxsw_res *res,
116 enum mlxsw_res_id res_id)
117 {
118 if (WARN_ON(!res->valid[res_id]))
119 return 0;
120 return res->values[res_id];
121 }
122
123 #define MLXSW_RES_GET(res, short_res_id) \
124 mlxsw_res_get(res, MLXSW_RES_ID_##short_res_id)
125
mlxsw_res_set(struct mlxsw_res * res,enum mlxsw_res_id res_id,u64 value)126 static inline void mlxsw_res_set(struct mlxsw_res *res,
127 enum mlxsw_res_id res_id, u64 value)
128 {
129 res->valid[res_id] = true;
130 res->values[res_id] = value;
131 }
132
133 #define MLXSW_RES_SET(res, short_res_id, value) \
134 mlxsw_res_set(res, MLXSW_RES_ID_##short_res_id, value)
135
mlxsw_res_parse(struct mlxsw_res * res,u16 id,u64 value)136 static inline void mlxsw_res_parse(struct mlxsw_res *res, u16 id, u64 value)
137 {
138 int i;
139
140 for (i = 0; i < ARRAY_SIZE(mlxsw_res_ids); i++) {
141 if (mlxsw_res_ids[i] == id) {
142 mlxsw_res_set(res, i, value);
143 return;
144 }
145 }
146 }
147
148 #endif
149
