1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/tcp.h>
34 #include <linux/if_vlan.h>
35 #include <net/dsfield.h>
36 #include "en.h"
37 #include "ipoib/ipoib.h"
38 #include "en_accel/en_accel.h"
39 #include "lib/clock.h"
40
41 #define MLX5E_SQ_NOPS_ROOM MLX5_SEND_WQE_MAX_WQEBBS
42
43 #ifndef CONFIG_MLX5_EN_TLS
44 #define MLX5E_SQ_STOP_ROOM (MLX5_SEND_WQE_MAX_WQEBBS +\
45 MLX5E_SQ_NOPS_ROOM)
46 #else
47 /* TLS offload requires MLX5E_SQ_STOP_ROOM to have
48 * enough room for a resync SKB, a normal SKB and a NOP
49 */
50 #define MLX5E_SQ_STOP_ROOM (2 * MLX5_SEND_WQE_MAX_WQEBBS +\
51 MLX5E_SQ_NOPS_ROOM)
52 #endif
53
mlx5e_tx_dma_unmap(struct device * pdev,struct mlx5e_sq_dma * dma)54 static inline void mlx5e_tx_dma_unmap(struct device *pdev,
55 struct mlx5e_sq_dma *dma)
56 {
57 switch (dma->type) {
58 case MLX5E_DMA_MAP_SINGLE:
59 dma_unmap_single(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
60 break;
61 case MLX5E_DMA_MAP_PAGE:
62 dma_unmap_page(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
63 break;
64 default:
65 WARN_ONCE(true, "mlx5e_tx_dma_unmap unknown DMA type!\n");
66 }
67 }
68
mlx5e_dma_get(struct mlx5e_txqsq * sq,u32 i)69 static inline struct mlx5e_sq_dma *mlx5e_dma_get(struct mlx5e_txqsq *sq, u32 i)
70 {
71 return &sq->db.dma_fifo[i & sq->dma_fifo_mask];
72 }
73
mlx5e_dma_push(struct mlx5e_txqsq * sq,dma_addr_t addr,u32 size,enum mlx5e_dma_map_type map_type)74 static inline void mlx5e_dma_push(struct mlx5e_txqsq *sq,
75 dma_addr_t addr,
76 u32 size,
77 enum mlx5e_dma_map_type map_type)
78 {
79 struct mlx5e_sq_dma *dma = mlx5e_dma_get(sq, sq->dma_fifo_pc++);
80
81 dma->addr = addr;
82 dma->size = size;
83 dma->type = map_type;
84 }
85
mlx5e_dma_unmap_wqe_err(struct mlx5e_txqsq * sq,u8 num_dma)86 static void mlx5e_dma_unmap_wqe_err(struct mlx5e_txqsq *sq, u8 num_dma)
87 {
88 int i;
89
90 for (i = 0; i < num_dma; i++) {
91 struct mlx5e_sq_dma *last_pushed_dma =
92 mlx5e_dma_get(sq, --sq->dma_fifo_pc);
93
94 mlx5e_tx_dma_unmap(sq->pdev, last_pushed_dma);
95 }
96 }
97
98 #ifdef CONFIG_MLX5_CORE_EN_DCB
mlx5e_get_dscp_up(struct mlx5e_priv * priv,struct sk_buff * skb)99 static inline int mlx5e_get_dscp_up(struct mlx5e_priv *priv, struct sk_buff *skb)
100 {
101 int dscp_cp = 0;
102
103 if (skb->protocol == htons(ETH_P_IP))
104 dscp_cp = ipv4_get_dsfield(ip_hdr(skb)) >> 2;
105 else if (skb->protocol == htons(ETH_P_IPV6))
106 dscp_cp = ipv6_get_dsfield(ipv6_hdr(skb)) >> 2;
107
108 return priv->dcbx_dp.dscp2prio[dscp_cp];
109 }
110 #endif
111
mlx5e_select_queue(struct net_device * dev,struct sk_buff * skb,struct net_device * sb_dev,select_queue_fallback_t fallback)112 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
113 struct net_device *sb_dev,
114 select_queue_fallback_t fallback)
115 {
116 struct mlx5e_priv *priv = netdev_priv(dev);
117 int channel_ix = fallback(dev, skb, NULL);
118 u16 num_channels;
119 int up = 0;
120
121 if (!netdev_get_num_tc(dev))
122 return channel_ix;
123
124 #ifdef CONFIG_MLX5_CORE_EN_DCB
125 if (priv->dcbx_dp.trust_state == MLX5_QPTS_TRUST_DSCP)
126 up = mlx5e_get_dscp_up(priv, skb);
127 else
128 #endif
129 if (skb_vlan_tag_present(skb))
130 up = skb->vlan_tci >> VLAN_PRIO_SHIFT;
131
132 /* channel_ix can be larger than num_channels since
133 * dev->num_real_tx_queues = num_channels * num_tc
134 */
135 num_channels = priv->channels.params.num_channels;
136 if (channel_ix >= num_channels)
137 channel_ix = reciprocal_scale(channel_ix, num_channels);
138
139 return priv->channel_tc2txq[channel_ix][up];
140 }
141
mlx5e_skb_l2_header_offset(struct sk_buff * skb)142 static inline int mlx5e_skb_l2_header_offset(struct sk_buff *skb)
143 {
144 #define MLX5E_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
145
146 return max(skb_network_offset(skb), MLX5E_MIN_INLINE);
147 }
148
mlx5e_skb_l3_header_offset(struct sk_buff * skb)149 static inline int mlx5e_skb_l3_header_offset(struct sk_buff *skb)
150 {
151 struct flow_keys keys;
152
153 if (skb_transport_header_was_set(skb))
154 return skb_transport_offset(skb);
155 else if (skb_flow_dissect_flow_keys(skb, &keys, 0))
156 return keys.control.thoff;
157 else
158 return mlx5e_skb_l2_header_offset(skb);
159 }
160
mlx5e_calc_min_inline(enum mlx5_inline_modes mode,struct sk_buff * skb)161 static inline u16 mlx5e_calc_min_inline(enum mlx5_inline_modes mode,
162 struct sk_buff *skb)
163 {
164 u16 hlen;
165
166 switch (mode) {
167 case MLX5_INLINE_MODE_NONE:
168 return 0;
169 case MLX5_INLINE_MODE_TCP_UDP:
170 hlen = eth_get_headlen(skb->data, skb_headlen(skb));
171 if (hlen == ETH_HLEN && !skb_vlan_tag_present(skb))
172 hlen += VLAN_HLEN;
173 break;
174 case MLX5_INLINE_MODE_IP:
175 /* When transport header is set to zero, it means no transport
176 * header. When transport header is set to 0xff's, it means
177 * transport header wasn't set.
178 */
179 if (skb_transport_offset(skb)) {
180 hlen = mlx5e_skb_l3_header_offset(skb);
181 break;
182 }
183 /* fall through */
184 case MLX5_INLINE_MODE_L2:
185 default:
186 hlen = mlx5e_skb_l2_header_offset(skb);
187 }
188 return min_t(u16, hlen, skb_headlen(skb));
189 }
190
mlx5e_insert_vlan(void * start,struct sk_buff * skb,u16 ihs)191 static inline void mlx5e_insert_vlan(void *start, struct sk_buff *skb, u16 ihs)
192 {
193 struct vlan_ethhdr *vhdr = (struct vlan_ethhdr *)start;
194 int cpy1_sz = 2 * ETH_ALEN;
195 int cpy2_sz = ihs - cpy1_sz;
196
197 memcpy(vhdr, skb->data, cpy1_sz);
198 vhdr->h_vlan_proto = skb->vlan_proto;
199 vhdr->h_vlan_TCI = cpu_to_be16(skb_vlan_tag_get(skb));
200 memcpy(&vhdr->h_vlan_encapsulated_proto, skb->data + cpy1_sz, cpy2_sz);
201 }
202
203 static inline void
mlx5e_txwqe_build_eseg_csum(struct mlx5e_txqsq * sq,struct sk_buff * skb,struct mlx5_wqe_eth_seg * eseg)204 mlx5e_txwqe_build_eseg_csum(struct mlx5e_txqsq *sq, struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg)
205 {
206 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
207 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM;
208 if (skb->encapsulation) {
209 eseg->cs_flags |= MLX5_ETH_WQE_L3_INNER_CSUM |
210 MLX5_ETH_WQE_L4_INNER_CSUM;
211 sq->stats->csum_partial_inner++;
212 } else {
213 eseg->cs_flags |= MLX5_ETH_WQE_L4_CSUM;
214 sq->stats->csum_partial++;
215 }
216 } else
217 sq->stats->csum_none++;
218 }
219
220 static inline u16
mlx5e_tx_get_gso_ihs(struct mlx5e_txqsq * sq,struct sk_buff * skb)221 mlx5e_tx_get_gso_ihs(struct mlx5e_txqsq *sq, struct sk_buff *skb)
222 {
223 struct mlx5e_sq_stats *stats = sq->stats;
224 u16 ihs;
225
226 if (skb->encapsulation) {
227 ihs = skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
228 stats->tso_inner_packets++;
229 stats->tso_inner_bytes += skb->len - ihs;
230 } else {
231 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4)
232 ihs = skb_transport_offset(skb) + sizeof(struct udphdr);
233 else
234 ihs = skb_transport_offset(skb) + tcp_hdrlen(skb);
235 stats->tso_packets++;
236 stats->tso_bytes += skb->len - ihs;
237 }
238
239 return ihs;
240 }
241
242 static inline int
mlx5e_txwqe_build_dsegs(struct mlx5e_txqsq * sq,struct sk_buff * skb,unsigned char * skb_data,u16 headlen,struct mlx5_wqe_data_seg * dseg)243 mlx5e_txwqe_build_dsegs(struct mlx5e_txqsq *sq, struct sk_buff *skb,
244 unsigned char *skb_data, u16 headlen,
245 struct mlx5_wqe_data_seg *dseg)
246 {
247 dma_addr_t dma_addr = 0;
248 u8 num_dma = 0;
249 int i;
250
251 if (headlen) {
252 dma_addr = dma_map_single(sq->pdev, skb_data, headlen,
253 DMA_TO_DEVICE);
254 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
255 goto dma_unmap_wqe_err;
256
257 dseg->addr = cpu_to_be64(dma_addr);
258 dseg->lkey = sq->mkey_be;
259 dseg->byte_count = cpu_to_be32(headlen);
260
261 mlx5e_dma_push(sq, dma_addr, headlen, MLX5E_DMA_MAP_SINGLE);
262 num_dma++;
263 dseg++;
264 }
265
266 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
267 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
268 int fsz = skb_frag_size(frag);
269
270 dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz,
271 DMA_TO_DEVICE);
272 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
273 goto dma_unmap_wqe_err;
274
275 dseg->addr = cpu_to_be64(dma_addr);
276 dseg->lkey = sq->mkey_be;
277 dseg->byte_count = cpu_to_be32(fsz);
278
279 mlx5e_dma_push(sq, dma_addr, fsz, MLX5E_DMA_MAP_PAGE);
280 num_dma++;
281 dseg++;
282 }
283
284 return num_dma;
285
286 dma_unmap_wqe_err:
287 mlx5e_dma_unmap_wqe_err(sq, num_dma);
288 return -ENOMEM;
289 }
290
mlx5e_fill_sq_frag_edge(struct mlx5e_txqsq * sq,struct mlx5_wq_cyc * wq,u16 pi,u16 nnops)291 static inline void mlx5e_fill_sq_frag_edge(struct mlx5e_txqsq *sq,
292 struct mlx5_wq_cyc *wq,
293 u16 pi, u16 nnops)
294 {
295 struct mlx5e_tx_wqe_info *edge_wi, *wi = &sq->db.wqe_info[pi];
296
297 edge_wi = wi + nnops;
298
299 /* fill sq frag edge with nops to avoid wqe wrapping two pages */
300 for (; wi < edge_wi; wi++) {
301 wi->skb = NULL;
302 wi->num_wqebbs = 1;
303 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
304 }
305 sq->stats->nop += nnops;
306 }
307
308 static inline void
mlx5e_txwqe_complete(struct mlx5e_txqsq * sq,struct sk_buff * skb,u8 opcode,u16 ds_cnt,u8 num_wqebbs,u32 num_bytes,u8 num_dma,struct mlx5e_tx_wqe_info * wi,struct mlx5_wqe_ctrl_seg * cseg)309 mlx5e_txwqe_complete(struct mlx5e_txqsq *sq, struct sk_buff *skb,
310 u8 opcode, u16 ds_cnt, u8 num_wqebbs, u32 num_bytes, u8 num_dma,
311 struct mlx5e_tx_wqe_info *wi, struct mlx5_wqe_ctrl_seg *cseg)
312 {
313 struct mlx5_wq_cyc *wq = &sq->wq;
314
315 wi->num_bytes = num_bytes;
316 wi->num_dma = num_dma;
317 wi->num_wqebbs = num_wqebbs;
318 wi->skb = skb;
319
320 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | opcode);
321 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
322
323 netdev_tx_sent_queue(sq->txq, num_bytes);
324
325 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
326 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
327
328 sq->pc += wi->num_wqebbs;
329 if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, MLX5E_SQ_STOP_ROOM))) {
330 netif_tx_stop_queue(sq->txq);
331 sq->stats->stopped++;
332 }
333
334 if (!skb->xmit_more || netif_xmit_stopped(sq->txq))
335 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, cseg);
336 }
337
338 #define INL_HDR_START_SZ (sizeof(((struct mlx5_wqe_eth_seg *)NULL)->inline_hdr.start))
339
mlx5e_sq_xmit(struct mlx5e_txqsq * sq,struct sk_buff * skb,struct mlx5e_tx_wqe * wqe,u16 pi)340 netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
341 struct mlx5e_tx_wqe *wqe, u16 pi)
342 {
343 struct mlx5_wq_cyc *wq = &sq->wq;
344 struct mlx5_wqe_ctrl_seg *cseg;
345 struct mlx5_wqe_eth_seg *eseg;
346 struct mlx5_wqe_data_seg *dseg;
347 struct mlx5e_tx_wqe_info *wi;
348
349 struct mlx5e_sq_stats *stats = sq->stats;
350 u16 headlen, ihs, contig_wqebbs_room;
351 u16 ds_cnt, ds_cnt_inl = 0;
352 u8 num_wqebbs, opcode;
353 u32 num_bytes;
354 int num_dma;
355 __be16 mss;
356
357 /* Calc ihs and ds cnt, no writes to wqe yet */
358 ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS;
359 if (skb_is_gso(skb)) {
360 opcode = MLX5_OPCODE_LSO;
361 mss = cpu_to_be16(skb_shinfo(skb)->gso_size);
362 ihs = mlx5e_tx_get_gso_ihs(sq, skb);
363 num_bytes = skb->len + (skb_shinfo(skb)->gso_segs - 1) * ihs;
364 stats->packets += skb_shinfo(skb)->gso_segs;
365 } else {
366 opcode = MLX5_OPCODE_SEND;
367 mss = 0;
368 ihs = mlx5e_calc_min_inline(sq->min_inline_mode, skb);
369 num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
370 stats->packets++;
371 }
372
373 stats->bytes += num_bytes;
374 stats->xmit_more += skb->xmit_more;
375
376 headlen = skb->len - ihs - skb->data_len;
377 ds_cnt += !!headlen;
378 ds_cnt += skb_shinfo(skb)->nr_frags;
379
380 if (ihs) {
381 ihs += !!skb_vlan_tag_present(skb) * VLAN_HLEN;
382
383 ds_cnt_inl = DIV_ROUND_UP(ihs - INL_HDR_START_SZ, MLX5_SEND_WQE_DS);
384 ds_cnt += ds_cnt_inl;
385 }
386
387 num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
388 contig_wqebbs_room = mlx5_wq_cyc_get_contig_wqebbs(wq, pi);
389 if (unlikely(contig_wqebbs_room < num_wqebbs)) {
390 mlx5e_fill_sq_frag_edge(sq, wq, pi, contig_wqebbs_room);
391 mlx5e_sq_fetch_wqe(sq, &wqe, &pi);
392 }
393
394 /* fill wqe */
395 wi = &sq->db.wqe_info[pi];
396 cseg = &wqe->ctrl;
397 eseg = &wqe->eth;
398 dseg = wqe->data;
399
400 mlx5e_txwqe_build_eseg_csum(sq, skb, eseg);
401
402 eseg->mss = mss;
403
404 if (ihs) {
405 eseg->inline_hdr.sz = cpu_to_be16(ihs);
406 if (skb_vlan_tag_present(skb)) {
407 ihs -= VLAN_HLEN;
408 mlx5e_insert_vlan(eseg->inline_hdr.start, skb, ihs);
409 stats->added_vlan_packets++;
410 } else {
411 memcpy(eseg->inline_hdr.start, skb->data, ihs);
412 }
413 dseg += ds_cnt_inl;
414 } else if (skb_vlan_tag_present(skb)) {
415 eseg->insert.type = cpu_to_be16(MLX5_ETH_WQE_INSERT_VLAN);
416 if (skb->vlan_proto == cpu_to_be16(ETH_P_8021AD))
417 eseg->insert.type |= cpu_to_be16(MLX5_ETH_WQE_SVLAN);
418 eseg->insert.vlan_tci = cpu_to_be16(skb_vlan_tag_get(skb));
419 stats->added_vlan_packets++;
420 }
421
422 num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb->data + ihs, headlen, dseg);
423 if (unlikely(num_dma < 0))
424 goto err_drop;
425
426 mlx5e_txwqe_complete(sq, skb, opcode, ds_cnt, num_wqebbs, num_bytes,
427 num_dma, wi, cseg);
428
429 return NETDEV_TX_OK;
430
431 err_drop:
432 stats->dropped++;
433 dev_kfree_skb_any(skb);
434
435 return NETDEV_TX_OK;
436 }
437
mlx5e_xmit(struct sk_buff * skb,struct net_device * dev)438 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev)
439 {
440 struct mlx5e_priv *priv = netdev_priv(dev);
441 struct mlx5e_tx_wqe *wqe;
442 struct mlx5e_txqsq *sq;
443 u16 pi;
444
445 sq = priv->txq2sq[skb_get_queue_mapping(skb)];
446 mlx5e_sq_fetch_wqe(sq, &wqe, &pi);
447
448 /* might send skbs and update wqe and pi */
449 skb = mlx5e_accel_handle_tx(skb, sq, dev, &wqe, &pi);
450 if (unlikely(!skb))
451 return NETDEV_TX_OK;
452
453 return mlx5e_sq_xmit(sq, skb, wqe, pi);
454 }
455
mlx5e_dump_error_cqe(struct mlx5e_txqsq * sq,struct mlx5_err_cqe * err_cqe)456 static void mlx5e_dump_error_cqe(struct mlx5e_txqsq *sq,
457 struct mlx5_err_cqe *err_cqe)
458 {
459 u32 ci = mlx5_cqwq_get_ci(&sq->cq.wq);
460
461 netdev_err(sq->channel->netdev,
462 "Error cqe on cqn 0x%x, ci 0x%x, sqn 0x%x, syndrome 0x%x, vendor syndrome 0x%x\n",
463 sq->cq.mcq.cqn, ci, sq->sqn, err_cqe->syndrome,
464 err_cqe->vendor_err_synd);
465 mlx5_dump_err_cqe(sq->cq.mdev, err_cqe);
466 }
467
mlx5e_poll_tx_cq(struct mlx5e_cq * cq,int napi_budget)468 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget)
469 {
470 struct mlx5e_sq_stats *stats;
471 struct mlx5e_txqsq *sq;
472 struct mlx5_cqe64 *cqe;
473 u32 dma_fifo_cc;
474 u32 nbytes;
475 u16 npkts;
476 u16 sqcc;
477 int i;
478
479 sq = container_of(cq, struct mlx5e_txqsq, cq);
480
481 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
482 return false;
483
484 cqe = mlx5_cqwq_get_cqe(&cq->wq);
485 if (!cqe)
486 return false;
487
488 stats = sq->stats;
489
490 npkts = 0;
491 nbytes = 0;
492
493 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
494 * otherwise a cq overrun may occur
495 */
496 sqcc = sq->cc;
497
498 /* avoid dirtying sq cache line every cqe */
499 dma_fifo_cc = sq->dma_fifo_cc;
500
501 i = 0;
502 do {
503 u16 wqe_counter;
504 bool last_wqe;
505
506 mlx5_cqwq_pop(&cq->wq);
507
508 wqe_counter = be16_to_cpu(cqe->wqe_counter);
509
510 if (unlikely(cqe->op_own >> 4 == MLX5_CQE_REQ_ERR)) {
511 if (!test_and_set_bit(MLX5E_SQ_STATE_RECOVERING,
512 &sq->state)) {
513 mlx5e_dump_error_cqe(sq,
514 (struct mlx5_err_cqe *)cqe);
515 queue_work(cq->channel->priv->wq,
516 &sq->recover.recover_work);
517 }
518 stats->cqe_err++;
519 }
520
521 do {
522 struct mlx5e_tx_wqe_info *wi;
523 struct sk_buff *skb;
524 u16 ci;
525 int j;
526
527 last_wqe = (sqcc == wqe_counter);
528
529 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
530 wi = &sq->db.wqe_info[ci];
531 skb = wi->skb;
532
533 if (unlikely(!skb)) { /* nop */
534 sqcc++;
535 continue;
536 }
537
538 if (unlikely(skb_shinfo(skb)->tx_flags &
539 SKBTX_HW_TSTAMP)) {
540 struct skb_shared_hwtstamps hwts = {};
541
542 hwts.hwtstamp =
543 mlx5_timecounter_cyc2time(sq->clock,
544 get_cqe_ts(cqe));
545 skb_tstamp_tx(skb, &hwts);
546 }
547
548 for (j = 0; j < wi->num_dma; j++) {
549 struct mlx5e_sq_dma *dma =
550 mlx5e_dma_get(sq, dma_fifo_cc++);
551
552 mlx5e_tx_dma_unmap(sq->pdev, dma);
553 }
554
555 npkts++;
556 nbytes += wi->num_bytes;
557 sqcc += wi->num_wqebbs;
558 napi_consume_skb(skb, napi_budget);
559 } while (!last_wqe);
560
561 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
562
563 stats->cqes += i;
564
565 mlx5_cqwq_update_db_record(&cq->wq);
566
567 /* ensure cq space is freed before enabling more cqes */
568 wmb();
569
570 sq->dma_fifo_cc = dma_fifo_cc;
571 sq->cc = sqcc;
572
573 netdev_tx_completed_queue(sq->txq, npkts, nbytes);
574
575 if (netif_tx_queue_stopped(sq->txq) &&
576 mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc,
577 MLX5E_SQ_STOP_ROOM) &&
578 !test_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state)) {
579 netif_tx_wake_queue(sq->txq);
580 stats->wake++;
581 }
582
583 return (i == MLX5E_TX_CQ_POLL_BUDGET);
584 }
585
mlx5e_free_txqsq_descs(struct mlx5e_txqsq * sq)586 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq)
587 {
588 struct mlx5e_tx_wqe_info *wi;
589 struct sk_buff *skb;
590 u16 ci;
591 int i;
592
593 while (sq->cc != sq->pc) {
594 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->cc);
595 wi = &sq->db.wqe_info[ci];
596 skb = wi->skb;
597
598 if (!skb) { /* nop */
599 sq->cc++;
600 continue;
601 }
602
603 for (i = 0; i < wi->num_dma; i++) {
604 struct mlx5e_sq_dma *dma =
605 mlx5e_dma_get(sq, sq->dma_fifo_cc++);
606
607 mlx5e_tx_dma_unmap(sq->pdev, dma);
608 }
609
610 dev_kfree_skb_any(skb);
611 sq->cc += wi->num_wqebbs;
612 }
613 }
614
615 #ifdef CONFIG_MLX5_CORE_IPOIB
616 static inline void
mlx5i_txwqe_build_datagram(struct mlx5_av * av,u32 dqpn,u32 dqkey,struct mlx5_wqe_datagram_seg * dseg)617 mlx5i_txwqe_build_datagram(struct mlx5_av *av, u32 dqpn, u32 dqkey,
618 struct mlx5_wqe_datagram_seg *dseg)
619 {
620 memcpy(&dseg->av, av, sizeof(struct mlx5_av));
621 dseg->av.dqp_dct = cpu_to_be32(dqpn | MLX5_EXTENDED_UD_AV);
622 dseg->av.key.qkey.qkey = cpu_to_be32(dqkey);
623 }
624
mlx5i_sq_xmit(struct mlx5e_txqsq * sq,struct sk_buff * skb,struct mlx5_av * av,u32 dqpn,u32 dqkey)625 netdev_tx_t mlx5i_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
626 struct mlx5_av *av, u32 dqpn, u32 dqkey)
627 {
628 struct mlx5_wq_cyc *wq = &sq->wq;
629 struct mlx5i_tx_wqe *wqe;
630
631 struct mlx5_wqe_datagram_seg *datagram;
632 struct mlx5_wqe_ctrl_seg *cseg;
633 struct mlx5_wqe_eth_seg *eseg;
634 struct mlx5_wqe_data_seg *dseg;
635 struct mlx5e_tx_wqe_info *wi;
636
637 struct mlx5e_sq_stats *stats = sq->stats;
638 u16 headlen, ihs, pi, contig_wqebbs_room;
639 u16 ds_cnt, ds_cnt_inl = 0;
640 u8 num_wqebbs, opcode;
641 u32 num_bytes;
642 int num_dma;
643 __be16 mss;
644
645 /* Calc ihs and ds cnt, no writes to wqe yet */
646 ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS;
647 if (skb_is_gso(skb)) {
648 opcode = MLX5_OPCODE_LSO;
649 mss = cpu_to_be16(skb_shinfo(skb)->gso_size);
650 ihs = mlx5e_tx_get_gso_ihs(sq, skb);
651 num_bytes = skb->len + (skb_shinfo(skb)->gso_segs - 1) * ihs;
652 stats->packets += skb_shinfo(skb)->gso_segs;
653 } else {
654 opcode = MLX5_OPCODE_SEND;
655 mss = 0;
656 ihs = mlx5e_calc_min_inline(sq->min_inline_mode, skb);
657 num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
658 stats->packets++;
659 }
660
661 stats->bytes += num_bytes;
662 stats->xmit_more += skb->xmit_more;
663
664 headlen = skb->len - ihs - skb->data_len;
665 ds_cnt += !!headlen;
666 ds_cnt += skb_shinfo(skb)->nr_frags;
667
668 if (ihs) {
669 ds_cnt_inl = DIV_ROUND_UP(ihs - INL_HDR_START_SZ, MLX5_SEND_WQE_DS);
670 ds_cnt += ds_cnt_inl;
671 }
672
673 num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
674 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
675 contig_wqebbs_room = mlx5_wq_cyc_get_contig_wqebbs(wq, pi);
676 if (unlikely(contig_wqebbs_room < num_wqebbs)) {
677 mlx5e_fill_sq_frag_edge(sq, wq, pi, contig_wqebbs_room);
678 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
679 }
680
681 mlx5i_sq_fetch_wqe(sq, &wqe, pi);
682
683 /* fill wqe */
684 wi = &sq->db.wqe_info[pi];
685 cseg = &wqe->ctrl;
686 datagram = &wqe->datagram;
687 eseg = &wqe->eth;
688 dseg = wqe->data;
689
690 mlx5i_txwqe_build_datagram(av, dqpn, dqkey, datagram);
691
692 mlx5e_txwqe_build_eseg_csum(sq, skb, eseg);
693
694 eseg->mss = mss;
695
696 if (ihs) {
697 memcpy(eseg->inline_hdr.start, skb->data, ihs);
698 eseg->inline_hdr.sz = cpu_to_be16(ihs);
699 dseg += ds_cnt_inl;
700 }
701
702 num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb->data + ihs, headlen, dseg);
703 if (unlikely(num_dma < 0))
704 goto err_drop;
705
706 mlx5e_txwqe_complete(sq, skb, opcode, ds_cnt, num_wqebbs, num_bytes,
707 num_dma, wi, cseg);
708
709 return NETDEV_TX_OK;
710
711 err_drop:
712 stats->dropped++;
713 dev_kfree_skb_any(skb);
714
715 return NETDEV_TX_OK;
716 }
717 #endif
718
