1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef __MLX5_EN_H__
33 #define __MLX5_EN_H__
34
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/crash_dump.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/mlx5/fs.h>
47 #include <linux/rhashtable.h>
48 #include <net/udp_tunnel.h>
49 #include <net/switchdev.h>
50 #include <net/xdp.h>
51 #include <linux/dim.h>
52 #include <linux/bits.h>
53 #include "wq.h"
54 #include "mlx5_core.h"
55 #include "en_stats.h"
56 #include "en/dcbnl.h"
57 #include "en/fs.h"
58 #include "en/qos.h"
59 #include "lib/hv_vhca.h"
60 #include "lib/clock.h"
61 #include "en/rx_res.h"
62
63 extern const struct net_device_ops mlx5e_netdev_ops;
64 struct page_pool;
65
66 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
67 #define MLX5E_METADATA_ETHER_LEN 8
68
69 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
70
71 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
72 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
73
74 #define MLX5E_MAX_NUM_TC 8
75 #define MLX5E_MAX_NUM_MQPRIO_CH_TC TC_QOPT_MAX_QUEUE
76
77 #define MLX5_RX_HEADROOM NET_SKB_PAD
78 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
79 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
80
81 #define MLX5E_RX_MAX_HEAD (256)
82
83 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
84 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
85 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
86 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
87 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \
88 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))
89
90 #define MLX5_MPWRQ_LOG_WQE_SZ 18
91 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
92 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
93 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
94
95 #define MLX5_ALIGN_MTTS(mtts) (ALIGN(mtts, 8))
96 #define MLX5_ALIGNED_MTTS_OCTW(mtts) ((mtts) / 2)
97 #define MLX5_MTT_OCTW(mtts) (MLX5_ALIGNED_MTTS_OCTW(MLX5_ALIGN_MTTS(mtts)))
98 /* Add another page to MLX5E_REQUIRED_WQE_MTTS as a buffer between
99 * WQEs, This page will absorb write overflow by the hardware, when
100 * receiving packets larger than MTU. These oversize packets are
101 * dropped by the driver at a later stage.
102 */
103 #define MLX5E_REQUIRED_WQE_MTTS (MLX5_ALIGN_MTTS(MLX5_MPWRQ_PAGES_PER_WQE + 1))
104 #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS)
105 #define MLX5E_MAX_RQ_NUM_MTTS \
106 ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */
107 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
108 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \
109 (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS))
110 #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \
111 (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \
112 (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU))
113
114 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
115 #define MLX5E_LOG_MAX_RX_WQE_BULK \
116 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
117
118 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
119 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
120 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
121
122 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
123 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
124 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \
125 MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW)
126
127 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
128
129 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
130 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
131
132 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
133 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
134 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
135 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
136 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
137 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
138 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
139 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
140
141 #define MLX5E_MIN_NUM_CHANNELS 0x1
142 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE / 2)
143 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
144 #define MLX5E_TX_CQ_POLL_BUDGET 128
145 #define MLX5E_TX_XSK_POLL_BUDGET 64
146 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
147
148 #define MLX5E_UMR_WQE_INLINE_SZ \
149 (sizeof(struct mlx5e_umr_wqe) + \
150 ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \
151 MLX5_UMR_MTT_ALIGNMENT))
152 #define MLX5E_UMR_WQEBBS \
153 (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB))
154
155 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK
156
157 #define mlx5e_dbg(mlevel, priv, format, ...) \
158 do { \
159 if (NETIF_MSG_##mlevel & (priv)->msglevel) \
160 netdev_warn(priv->netdev, format, \
161 ##__VA_ARGS__); \
162 } while (0)
163
164 #define mlx5e_state_dereference(priv, p) \
165 rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock))
166
167 enum mlx5e_rq_group {
168 MLX5E_RQ_GROUP_REGULAR,
169 MLX5E_RQ_GROUP_XSK,
170 #define MLX5E_NUM_RQ_GROUPS(g) (1 + MLX5E_RQ_GROUP_##g)
171 };
172
mlx5e_get_num_lag_ports(struct mlx5_core_dev * mdev)173 static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev)
174 {
175 if (mlx5_lag_is_lacp_owner(mdev))
176 return 1;
177
178 return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS);
179 }
180
mlx5_min_rx_wqes(int wq_type,u32 wq_size)181 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
182 {
183 switch (wq_type) {
184 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
185 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
186 wq_size / 2);
187 default:
188 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
189 wq_size / 2);
190 }
191 }
192
193 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */
mlx5e_get_max_num_channels(struct mlx5_core_dev * mdev)194 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
195 {
196 return is_kdump_kernel() ?
197 MLX5E_MIN_NUM_CHANNELS :
198 min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS);
199 }
200
201 struct mlx5e_tx_wqe {
202 struct mlx5_wqe_ctrl_seg ctrl;
203 struct mlx5_wqe_eth_seg eth;
204 struct mlx5_wqe_data_seg data[0];
205 };
206
207 struct mlx5e_rx_wqe_ll {
208 struct mlx5_wqe_srq_next_seg next;
209 struct mlx5_wqe_data_seg data[];
210 };
211
212 struct mlx5e_rx_wqe_cyc {
213 struct mlx5_wqe_data_seg data[0];
214 };
215
216 struct mlx5e_umr_wqe {
217 struct mlx5_wqe_ctrl_seg ctrl;
218 struct mlx5_wqe_umr_ctrl_seg uctrl;
219 struct mlx5_mkey_seg mkc;
220 struct mlx5_mtt inline_mtts[0];
221 };
222
223 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
224
225 enum mlx5e_priv_flag {
226 MLX5E_PFLAG_RX_CQE_BASED_MODER,
227 MLX5E_PFLAG_TX_CQE_BASED_MODER,
228 MLX5E_PFLAG_RX_CQE_COMPRESS,
229 MLX5E_PFLAG_RX_STRIDING_RQ,
230 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
231 MLX5E_PFLAG_XDP_TX_MPWQE,
232 MLX5E_PFLAG_SKB_TX_MPWQE,
233 MLX5E_PFLAG_TX_PORT_TS,
234 MLX5E_NUM_PFLAGS, /* Keep last */
235 };
236
237 #define MLX5E_SET_PFLAG(params, pflag, enable) \
238 do { \
239 if (enable) \
240 (params)->pflags |= BIT(pflag); \
241 else \
242 (params)->pflags &= ~(BIT(pflag)); \
243 } while (0)
244
245 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
246
247 struct mlx5e_params {
248 u8 log_sq_size;
249 u8 rq_wq_type;
250 u8 log_rq_mtu_frames;
251 u16 num_channels;
252 struct {
253 u16 mode;
254 u8 num_tc;
255 struct netdev_tc_txq tc_to_txq[TC_MAX_QUEUE];
256 } mqprio;
257 bool rx_cqe_compress_def;
258 bool tunneled_offload_en;
259 struct dim_cq_moder rx_cq_moderation;
260 struct dim_cq_moder tx_cq_moderation;
261 bool lro_en;
262 u8 tx_min_inline_mode;
263 bool vlan_strip_disable;
264 bool scatter_fcs_en;
265 bool rx_dim_enabled;
266 bool tx_dim_enabled;
267 u32 lro_timeout;
268 u32 pflags;
269 struct bpf_prog *xdp_prog;
270 struct mlx5e_xsk *xsk;
271 unsigned int sw_mtu;
272 int hard_mtu;
273 bool ptp_rx;
274 };
275
mlx5e_get_dcb_num_tc(struct mlx5e_params * params)276 static inline u8 mlx5e_get_dcb_num_tc(struct mlx5e_params *params)
277 {
278 return params->mqprio.mode == TC_MQPRIO_MODE_DCB ?
279 params->mqprio.num_tc : 1;
280 }
281
282 enum {
283 MLX5E_RQ_STATE_ENABLED,
284 MLX5E_RQ_STATE_RECOVERING,
285 MLX5E_RQ_STATE_AM,
286 MLX5E_RQ_STATE_NO_CSUM_COMPLETE,
287 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */
288 MLX5E_RQ_STATE_FPGA_TLS, /* FPGA TLS enabled */
289 MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX /* set when mini_cqe_resp_stride_index cap is used */
290 };
291
292 struct mlx5e_cq {
293 /* data path - accessed per cqe */
294 struct mlx5_cqwq wq;
295
296 /* data path - accessed per napi poll */
297 u16 event_ctr;
298 struct napi_struct *napi;
299 struct mlx5_core_cq mcq;
300 struct mlx5e_ch_stats *ch_stats;
301
302 /* control */
303 struct net_device *netdev;
304 struct mlx5_core_dev *mdev;
305 struct mlx5e_priv *priv;
306 struct mlx5_wq_ctrl wq_ctrl;
307 } ____cacheline_aligned_in_smp;
308
309 struct mlx5e_cq_decomp {
310 /* cqe decompression */
311 struct mlx5_cqe64 title;
312 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
313 u8 mini_arr_idx;
314 u16 left;
315 u16 wqe_counter;
316 } ____cacheline_aligned_in_smp;
317
318 enum mlx5e_dma_map_type {
319 MLX5E_DMA_MAP_SINGLE,
320 MLX5E_DMA_MAP_PAGE
321 };
322
323 struct mlx5e_sq_dma {
324 dma_addr_t addr;
325 u32 size;
326 enum mlx5e_dma_map_type type;
327 };
328
329 enum {
330 MLX5E_SQ_STATE_ENABLED,
331 MLX5E_SQ_STATE_MPWQE,
332 MLX5E_SQ_STATE_RECOVERING,
333 MLX5E_SQ_STATE_IPSEC,
334 MLX5E_SQ_STATE_AM,
335 MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE,
336 MLX5E_SQ_STATE_PENDING_XSK_TX,
337 MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC,
338 };
339
340 struct mlx5e_tx_mpwqe {
341 /* Current MPWQE session */
342 struct mlx5e_tx_wqe *wqe;
343 u32 bytes_count;
344 u8 ds_count;
345 u8 pkt_count;
346 u8 inline_on;
347 };
348
349 struct mlx5e_skb_fifo {
350 struct sk_buff **fifo;
351 u16 *pc;
352 u16 *cc;
353 u16 mask;
354 };
355
356 struct mlx5e_ptpsq;
357
358 struct mlx5e_txqsq {
359 /* data path */
360
361 /* dirtied @completion */
362 u16 cc;
363 u16 skb_fifo_cc;
364 u32 dma_fifo_cc;
365 struct dim dim; /* Adaptive Moderation */
366
367 /* dirtied @xmit */
368 u16 pc ____cacheline_aligned_in_smp;
369 u16 skb_fifo_pc;
370 u32 dma_fifo_pc;
371 struct mlx5e_tx_mpwqe mpwqe;
372
373 struct mlx5e_cq cq;
374
375 /* read only */
376 struct mlx5_wq_cyc wq;
377 u32 dma_fifo_mask;
378 struct mlx5e_sq_stats *stats;
379 struct {
380 struct mlx5e_sq_dma *dma_fifo;
381 struct mlx5e_skb_fifo skb_fifo;
382 struct mlx5e_tx_wqe_info *wqe_info;
383 } db;
384 void __iomem *uar_map;
385 struct netdev_queue *txq;
386 u32 sqn;
387 u16 stop_room;
388 u8 min_inline_mode;
389 struct device *pdev;
390 __be32 mkey_be;
391 unsigned long state;
392 unsigned int hw_mtu;
393 struct hwtstamp_config *tstamp;
394 struct mlx5_clock *clock;
395 struct net_device *netdev;
396 struct mlx5_core_dev *mdev;
397 struct mlx5e_priv *priv;
398
399 /* control path */
400 struct mlx5_wq_ctrl wq_ctrl;
401 int ch_ix;
402 int txq_ix;
403 u32 rate_limit;
404 struct work_struct recover_work;
405 struct mlx5e_ptpsq *ptpsq;
406 cqe_ts_to_ns ptp_cyc2time;
407 } ____cacheline_aligned_in_smp;
408
409 struct mlx5e_dma_info {
410 dma_addr_t addr;
411 union {
412 struct page *page;
413 struct xdp_buff *xsk;
414 };
415 };
416
417 /* XDP packets can be transmitted in different ways. On completion, we need to
418 * distinguish between them to clean up things in a proper way.
419 */
420 enum mlx5e_xdp_xmit_mode {
421 /* An xdp_frame was transmitted due to either XDP_REDIRECT from another
422 * device or XDP_TX from an XSK RQ. The frame has to be unmapped and
423 * returned.
424 */
425 MLX5E_XDP_XMIT_MODE_FRAME,
426
427 /* The xdp_frame was created in place as a result of XDP_TX from a
428 * regular RQ. No DMA remapping happened, and the page belongs to us.
429 */
430 MLX5E_XDP_XMIT_MODE_PAGE,
431
432 /* No xdp_frame was created at all, the transmit happened from a UMEM
433 * page. The UMEM Completion Ring producer pointer has to be increased.
434 */
435 MLX5E_XDP_XMIT_MODE_XSK,
436 };
437
438 struct mlx5e_xdp_info {
439 enum mlx5e_xdp_xmit_mode mode;
440 union {
441 struct {
442 struct xdp_frame *xdpf;
443 dma_addr_t dma_addr;
444 } frame;
445 struct {
446 struct mlx5e_rq *rq;
447 struct mlx5e_dma_info di;
448 } page;
449 };
450 };
451
452 struct mlx5e_xmit_data {
453 dma_addr_t dma_addr;
454 void *data;
455 u32 len;
456 };
457
458 struct mlx5e_xdp_info_fifo {
459 struct mlx5e_xdp_info *xi;
460 u32 *cc;
461 u32 *pc;
462 u32 mask;
463 };
464
465 struct mlx5e_xdpsq;
466 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *);
467 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *,
468 struct mlx5e_xmit_data *,
469 struct mlx5e_xdp_info *,
470 int);
471
472 struct mlx5e_xdpsq {
473 /* data path */
474
475 /* dirtied @completion */
476 u32 xdpi_fifo_cc;
477 u16 cc;
478
479 /* dirtied @xmit */
480 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp;
481 u16 pc;
482 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
483 struct mlx5e_tx_mpwqe mpwqe;
484
485 struct mlx5e_cq cq;
486
487 /* read only */
488 struct xsk_buff_pool *xsk_pool;
489 struct mlx5_wq_cyc wq;
490 struct mlx5e_xdpsq_stats *stats;
491 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check;
492 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame;
493 struct {
494 struct mlx5e_xdp_wqe_info *wqe_info;
495 struct mlx5e_xdp_info_fifo xdpi_fifo;
496 } db;
497 void __iomem *uar_map;
498 u32 sqn;
499 struct device *pdev;
500 __be32 mkey_be;
501 u8 min_inline_mode;
502 unsigned long state;
503 unsigned int hw_mtu;
504
505 /* control path */
506 struct mlx5_wq_ctrl wq_ctrl;
507 struct mlx5e_channel *channel;
508 } ____cacheline_aligned_in_smp;
509
510 struct mlx5e_ktls_resync_resp;
511
512 struct mlx5e_icosq {
513 /* data path */
514 u16 cc;
515 u16 pc;
516
517 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
518 struct mlx5e_cq cq;
519
520 /* write@xmit, read@completion */
521 struct {
522 struct mlx5e_icosq_wqe_info *wqe_info;
523 } db;
524
525 /* read only */
526 struct mlx5_wq_cyc wq;
527 void __iomem *uar_map;
528 u32 sqn;
529 u16 reserved_room;
530 unsigned long state;
531 struct mlx5e_ktls_resync_resp *ktls_resync;
532
533 /* control path */
534 struct mlx5_wq_ctrl wq_ctrl;
535 struct mlx5e_channel *channel;
536
537 struct work_struct recover_work;
538 } ____cacheline_aligned_in_smp;
539
540 struct mlx5e_wqe_frag_info {
541 struct mlx5e_dma_info *di;
542 u32 offset;
543 bool last_in_page;
544 };
545
546 struct mlx5e_umr_dma_info {
547 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
548 };
549
550 struct mlx5e_mpw_info {
551 struct mlx5e_umr_dma_info umr;
552 u16 consumed_strides;
553 DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
554 };
555
556 #define MLX5E_MAX_RX_FRAGS 4
557
558 /* a single cache unit is capable to serve one napi call (for non-striding rq)
559 * or a MPWQE (for striding rq).
560 */
561 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
562 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
563 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
564 struct mlx5e_page_cache {
565 u32 head;
566 u32 tail;
567 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
568 };
569
570 struct mlx5e_rq;
571 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
572 typedef struct sk_buff *
573 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
574 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
575 typedef struct sk_buff *
576 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
577 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
578 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
579 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
580
581 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk);
582 void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params);
583
584 enum mlx5e_rq_flag {
585 MLX5E_RQ_FLAG_XDP_XMIT,
586 MLX5E_RQ_FLAG_XDP_REDIRECT,
587 };
588
589 struct mlx5e_rq_frag_info {
590 int frag_size;
591 int frag_stride;
592 };
593
594 struct mlx5e_rq_frags_info {
595 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
596 u8 num_frags;
597 u8 log_num_frags;
598 u8 wqe_bulk;
599 };
600
601 struct mlx5e_rq {
602 /* data path */
603 union {
604 struct {
605 struct mlx5_wq_cyc wq;
606 struct mlx5e_wqe_frag_info *frags;
607 struct mlx5e_dma_info *di;
608 struct mlx5e_rq_frags_info info;
609 mlx5e_fp_skb_from_cqe skb_from_cqe;
610 } wqe;
611 struct {
612 struct mlx5_wq_ll wq;
613 struct mlx5e_umr_wqe umr_wqe;
614 struct mlx5e_mpw_info *info;
615 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
616 u16 num_strides;
617 u16 actual_wq_head;
618 u8 log_stride_sz;
619 u8 umr_in_progress;
620 u8 umr_last_bulk;
621 u8 umr_completed;
622 } mpwqe;
623 };
624 struct {
625 u16 headroom;
626 u32 frame0_sz;
627 u8 map_dir; /* dma map direction */
628 } buff;
629
630 struct device *pdev;
631 struct net_device *netdev;
632 struct mlx5e_rq_stats *stats;
633 struct mlx5e_cq cq;
634 struct mlx5e_cq_decomp cqd;
635 struct mlx5e_page_cache page_cache;
636 struct hwtstamp_config *tstamp;
637 struct mlx5_clock *clock;
638 struct mlx5e_icosq *icosq;
639 struct mlx5e_priv *priv;
640
641 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
642 mlx5e_fp_post_rx_wqes post_wqes;
643 mlx5e_fp_dealloc_wqe dealloc_wqe;
644
645 unsigned long state;
646 int ix;
647 unsigned int hw_mtu;
648
649 struct dim dim; /* Dynamic Interrupt Moderation */
650
651 /* XDP */
652 struct bpf_prog __rcu *xdp_prog;
653 struct mlx5e_xdpsq *xdpsq;
654 DECLARE_BITMAP(flags, 8);
655 struct page_pool *page_pool;
656
657 /* AF_XDP zero-copy */
658 struct xsk_buff_pool *xsk_pool;
659
660 struct work_struct recover_work;
661
662 /* control */
663 struct mlx5_wq_ctrl wq_ctrl;
664 __be32 mkey_be;
665 u8 wq_type;
666 u32 rqn;
667 struct mlx5_core_dev *mdev;
668 struct mlx5_core_mkey umr_mkey;
669 struct mlx5e_dma_info wqe_overflow;
670
671 /* XDP read-mostly */
672 struct xdp_rxq_info xdp_rxq;
673 cqe_ts_to_ns ptp_cyc2time;
674 } ____cacheline_aligned_in_smp;
675
676 enum mlx5e_channel_state {
677 MLX5E_CHANNEL_STATE_XSK,
678 MLX5E_CHANNEL_NUM_STATES
679 };
680
681 struct mlx5e_channel {
682 /* data path */
683 struct mlx5e_rq rq;
684 struct mlx5e_xdpsq rq_xdpsq;
685 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC];
686 struct mlx5e_icosq icosq; /* internal control operations */
687 struct mlx5e_txqsq __rcu * __rcu *qos_sqs;
688 bool xdp;
689 struct napi_struct napi;
690 struct device *pdev;
691 struct net_device *netdev;
692 __be32 mkey_be;
693 u16 qos_sqs_size;
694 u8 num_tc;
695 u8 lag_port;
696
697 /* XDP_REDIRECT */
698 struct mlx5e_xdpsq xdpsq;
699
700 /* AF_XDP zero-copy */
701 struct mlx5e_rq xskrq;
702 struct mlx5e_xdpsq xsksq;
703
704 /* Async ICOSQ */
705 struct mlx5e_icosq async_icosq;
706 /* async_icosq can be accessed from any CPU - the spinlock protects it. */
707 spinlock_t async_icosq_lock;
708
709 /* data path - accessed per napi poll */
710 const struct cpumask *aff_mask;
711 struct mlx5e_ch_stats *stats;
712
713 /* control */
714 struct mlx5e_priv *priv;
715 struct mlx5_core_dev *mdev;
716 struct hwtstamp_config *tstamp;
717 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES);
718 int ix;
719 int cpu;
720 };
721
722 struct mlx5e_ptp;
723
724 struct mlx5e_channels {
725 struct mlx5e_channel **c;
726 struct mlx5e_ptp *ptp;
727 unsigned int num;
728 struct mlx5e_params params;
729 };
730
731 struct mlx5e_channel_stats {
732 struct mlx5e_ch_stats ch;
733 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
734 struct mlx5e_rq_stats rq;
735 struct mlx5e_rq_stats xskrq;
736 struct mlx5e_xdpsq_stats rq_xdpsq;
737 struct mlx5e_xdpsq_stats xdpsq;
738 struct mlx5e_xdpsq_stats xsksq;
739 } ____cacheline_aligned_in_smp;
740
741 struct mlx5e_ptp_stats {
742 struct mlx5e_ch_stats ch;
743 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
744 struct mlx5e_ptp_cq_stats cq[MLX5E_MAX_NUM_TC];
745 struct mlx5e_rq_stats rq;
746 } ____cacheline_aligned_in_smp;
747
748 enum {
749 MLX5E_STATE_OPENED,
750 MLX5E_STATE_DESTROYING,
751 MLX5E_STATE_XDP_TX_ENABLED,
752 MLX5E_STATE_XDP_ACTIVE,
753 };
754
755 enum {
756 MLX5E_TC_PRIO = 0,
757 MLX5E_NIC_PRIO
758 };
759
760 struct mlx5e_modify_sq_param {
761 int curr_state;
762 int next_state;
763 int rl_update;
764 int rl_index;
765 bool qos_update;
766 u16 qos_queue_group_id;
767 };
768
769 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
770 struct mlx5e_hv_vhca_stats_agent {
771 struct mlx5_hv_vhca_agent *agent;
772 struct delayed_work work;
773 u16 delay;
774 void *buf;
775 };
776 #endif
777
778 struct mlx5e_xsk {
779 /* XSK buffer pools are stored separately from channels,
780 * because we don't want to lose them when channels are
781 * recreated. The kernel also stores buffer pool, but it doesn't
782 * distinguish between zero-copy and non-zero-copy UMEMs, so
783 * rely on our mechanism.
784 */
785 struct xsk_buff_pool **pools;
786 u16 refcnt;
787 bool ever_used;
788 };
789
790 /* Temporary storage for variables that are allocated when struct mlx5e_priv is
791 * initialized, and used where we can't allocate them because that functions
792 * must not fail. Use with care and make sure the same variable is not used
793 * simultaneously by multiple users.
794 */
795 struct mlx5e_scratchpad {
796 cpumask_var_t cpumask;
797 };
798
799 struct mlx5e_htb {
800 DECLARE_HASHTABLE(qos_tc2node, order_base_2(MLX5E_QOS_MAX_LEAF_NODES));
801 DECLARE_BITMAP(qos_used_qids, MLX5E_QOS_MAX_LEAF_NODES);
802 struct mlx5e_sq_stats **qos_sq_stats;
803 u16 max_qos_sqs;
804 u16 maj_id;
805 u16 defcls;
806 };
807
808 struct mlx5e_trap;
809
810 struct mlx5e_priv {
811 /* priv data path fields - start */
812 /* +1 for port ptp ts */
813 struct mlx5e_txqsq *txq2sq[(MLX5E_MAX_NUM_CHANNELS + 1) * MLX5E_MAX_NUM_TC +
814 MLX5E_QOS_MAX_LEAF_NODES];
815 int channel_tc2realtxq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
816 int port_ptp_tc2realtxq[MLX5E_MAX_NUM_TC];
817 #ifdef CONFIG_MLX5_CORE_EN_DCB
818 struct mlx5e_dcbx_dp dcbx_dp;
819 #endif
820 /* priv data path fields - end */
821
822 u32 msglevel;
823 unsigned long state;
824 struct mutex state_lock; /* Protects Interface state */
825 struct mlx5e_rq drop_rq;
826
827 struct mlx5e_channels channels;
828 u32 tisn[MLX5_MAX_PORTS][MLX5E_MAX_NUM_TC];
829 struct mlx5e_rx_res *rx_res;
830 u32 tx_rates[MLX5E_MAX_NUM_SQS];
831
832 struct mlx5e_flow_steering fs;
833
834 struct workqueue_struct *wq;
835 struct work_struct update_carrier_work;
836 struct work_struct set_rx_mode_work;
837 struct work_struct tx_timeout_work;
838 struct work_struct update_stats_work;
839 struct work_struct monitor_counters_work;
840 struct mlx5_nb monitor_counters_nb;
841
842 struct mlx5_core_dev *mdev;
843 struct net_device *netdev;
844 struct mlx5e_trap *en_trap;
845 struct mlx5e_stats stats;
846 struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS];
847 struct mlx5e_channel_stats trap_stats;
848 struct mlx5e_ptp_stats ptp_stats;
849 u16 stats_nch;
850 u16 max_nch;
851 u8 max_opened_tc;
852 bool tx_ptp_opened;
853 bool rx_ptp_opened;
854 struct hwtstamp_config tstamp;
855 u16 q_counter;
856 u16 drop_rq_q_counter;
857 struct notifier_block events_nb;
858 struct notifier_block blocking_events_nb;
859 int num_tc_x_num_ch;
860
861 struct udp_tunnel_nic_info nic_info;
862 #ifdef CONFIG_MLX5_CORE_EN_DCB
863 struct mlx5e_dcbx dcbx;
864 #endif
865
866 const struct mlx5e_profile *profile;
867 void *ppriv;
868 #ifdef CONFIG_MLX5_EN_IPSEC
869 struct mlx5e_ipsec *ipsec;
870 #endif
871 #ifdef CONFIG_MLX5_EN_TLS
872 struct mlx5e_tls *tls;
873 #endif
874 struct devlink_health_reporter *tx_reporter;
875 struct devlink_health_reporter *rx_reporter;
876 struct mlx5e_xsk xsk;
877 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
878 struct mlx5e_hv_vhca_stats_agent stats_agent;
879 #endif
880 struct mlx5e_scratchpad scratchpad;
881 struct mlx5e_htb htb;
882 };
883
884 struct mlx5e_rx_handlers {
885 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
886 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
887 };
888
889 extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic;
890
891 struct mlx5e_profile {
892 int (*init)(struct mlx5_core_dev *mdev,
893 struct net_device *netdev);
894 void (*cleanup)(struct mlx5e_priv *priv);
895 int (*init_rx)(struct mlx5e_priv *priv);
896 void (*cleanup_rx)(struct mlx5e_priv *priv);
897 int (*init_tx)(struct mlx5e_priv *priv);
898 void (*cleanup_tx)(struct mlx5e_priv *priv);
899 void (*enable)(struct mlx5e_priv *priv);
900 void (*disable)(struct mlx5e_priv *priv);
901 int (*update_rx)(struct mlx5e_priv *priv);
902 void (*update_stats)(struct mlx5e_priv *priv);
903 void (*update_carrier)(struct mlx5e_priv *priv);
904 unsigned int (*stats_grps_num)(struct mlx5e_priv *priv);
905 mlx5e_stats_grp_t *stats_grps;
906 const struct mlx5e_rx_handlers *rx_handlers;
907 int max_tc;
908 u8 rq_groups;
909 bool rx_ptp_support;
910 };
911
912 void mlx5e_build_ptys2ethtool_map(void);
913
914 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev);
915
916 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
917 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s);
918
919 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
920 int mlx5e_self_test_num(struct mlx5e_priv *priv);
921 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
922 u64 *buf);
923 void mlx5e_set_rx_mode_work(struct work_struct *work);
924
925 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
926 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
927 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val, bool rx_filter);
928
929 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
930 u16 vid);
931 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
932 u16 vid);
933 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
934
935 struct mlx5e_xsk_param;
936
937 struct mlx5e_rq_param;
938 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
939 struct mlx5e_xsk_param *xsk, int node,
940 struct mlx5e_rq *rq);
941 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time);
942 void mlx5e_close_rq(struct mlx5e_rq *rq);
943 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param);
944 void mlx5e_destroy_rq(struct mlx5e_rq *rq);
945
946 struct mlx5e_sq_param;
947 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
948 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq);
949 void mlx5e_close_icosq(struct mlx5e_icosq *sq);
950 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
951 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
952 struct mlx5e_xdpsq *sq, bool is_redirect);
953 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq);
954
955 struct mlx5e_create_cq_param {
956 struct napi_struct *napi;
957 struct mlx5e_ch_stats *ch_stats;
958 int node;
959 int ix;
960 };
961
962 struct mlx5e_cq_param;
963 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
964 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
965 struct mlx5e_cq *cq);
966 void mlx5e_close_cq(struct mlx5e_cq *cq);
967
968 int mlx5e_open_locked(struct net_device *netdev);
969 int mlx5e_close_locked(struct net_device *netdev);
970
971 int mlx5e_open_channels(struct mlx5e_priv *priv,
972 struct mlx5e_channels *chs);
973 void mlx5e_close_channels(struct mlx5e_channels *chs);
974
975 /* Function pointer to be used to modify HW or kernel settings while
976 * switching channels
977 */
978 typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context);
979 #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \
980 int fn##_ctx(struct mlx5e_priv *priv, void *context) \
981 { \
982 return fn(priv); \
983 }
984 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv);
985 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
986 struct mlx5e_params *new_params,
987 mlx5e_fp_preactivate preactivate,
988 void *context, bool reset);
989 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv);
990 int mlx5e_num_channels_changed(struct mlx5e_priv *priv);
991 int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context);
992 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
993 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
994 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx);
995
996 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state);
997 void mlx5e_activate_rq(struct mlx5e_rq *rq);
998 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
999 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq);
1000 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq);
1001
1002 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1003 struct mlx5e_modify_sq_param *p);
1004 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1005 struct mlx5e_params *params, struct mlx5e_sq_param *param,
1006 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, u16 qos_qid);
1007 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq);
1008 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq);
1009 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq);
1010 void mlx5e_tx_disable_queue(struct netdev_queue *txq);
1011 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa);
1012 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq);
1013 struct mlx5e_create_sq_param;
1014 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1015 struct mlx5e_sq_param *param,
1016 struct mlx5e_create_sq_param *csp,
1017 u16 qos_queue_group_id,
1018 u32 *sqn);
1019 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1020 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq);
1021
mlx5_tx_swp_supported(struct mlx5_core_dev * mdev)1022 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
1023 {
1024 return MLX5_CAP_ETH(mdev, swp) &&
1025 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
1026 }
1027
1028 extern const struct ethtool_ops mlx5e_ethtool_ops;
1029
1030 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
1031 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1032 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb,
1033 bool enable_mc_lb);
1034 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc);
1035
1036 /* common netdev helpers */
1037 void mlx5e_create_q_counters(struct mlx5e_priv *priv);
1038 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);
1039 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
1040 struct mlx5e_rq *drop_rq);
1041 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);
1042 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node);
1043 void mlx5e_free_di_list(struct mlx5e_rq *rq);
1044
1045 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn);
1046 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1047
1048 int mlx5e_create_tises(struct mlx5e_priv *priv);
1049 void mlx5e_destroy_tises(struct mlx5e_priv *priv);
1050 int mlx5e_update_nic_rx(struct mlx5e_priv *priv);
1051 void mlx5e_update_carrier(struct mlx5e_priv *priv);
1052 int mlx5e_close(struct net_device *netdev);
1053 int mlx5e_open(struct net_device *netdev);
1054
1055 void mlx5e_queue_update_stats(struct mlx5e_priv *priv);
1056
1057 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv);
1058 int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context);
1059 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
1060 mlx5e_fp_preactivate preactivate);
1061 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv);
1062
1063 /* ethtool helpers */
1064 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1065 struct ethtool_drvinfo *drvinfo);
1066 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1067 uint32_t stringset, uint8_t *data);
1068 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1069 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1070 struct ethtool_stats *stats, u64 *data);
1071 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1072 struct ethtool_ringparam *param);
1073 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1074 struct ethtool_ringparam *param);
1075 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1076 struct ethtool_channels *ch);
1077 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1078 struct ethtool_channels *ch);
1079 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1080 struct ethtool_coalesce *coal);
1081 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1082 struct ethtool_coalesce *coal);
1083 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
1084 struct ethtool_link_ksettings *link_ksettings);
1085 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1086 const struct ethtool_link_ksettings *link_ksettings);
1087 int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, u8 *hfunc);
1088 int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key,
1089 const u8 hfunc);
1090 int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
1091 u32 *rule_locs);
1092 int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd);
1093 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);
1094 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);
1095 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1096 struct ethtool_ts_info *info);
1097 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1098 struct ethtool_flash *flash);
1099 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1100 struct ethtool_pauseparam *pauseparam);
1101 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1102 struct ethtool_pauseparam *pauseparam);
1103
1104 /* mlx5e generic netdev management API */
1105 static inline bool
mlx5e_tx_mpwqe_supported(struct mlx5_core_dev * mdev)1106 mlx5e_tx_mpwqe_supported(struct mlx5_core_dev *mdev)
1107 {
1108 return !is_kdump_kernel() &&
1109 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe);
1110 }
1111
1112 int mlx5e_priv_init(struct mlx5e_priv *priv,
1113 const struct mlx5e_profile *profile,
1114 struct net_device *netdev,
1115 struct mlx5_core_dev *mdev);
1116 void mlx5e_priv_cleanup(struct mlx5e_priv *priv);
1117 struct net_device *
1118 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
1119 unsigned int txqs, unsigned int rxqs);
1120 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1121 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1122 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1123 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
1124 const struct mlx5e_profile *new_profile, void *new_ppriv);
1125 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv);
1126 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv);
1127 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu);
1128 void mlx5e_rx_dim_work(struct work_struct *work);
1129 void mlx5e_tx_dim_work(struct work_struct *work);
1130
1131 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
1132 struct net_device *netdev,
1133 netdev_features_t features);
1134 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features);
1135 #ifdef CONFIG_MLX5_ESWITCH
1136 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
1137 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate);
1138 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi);
1139 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats);
1140 #endif
1141 #endif /* __MLX5_EN_H__ */
1142
