1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /* Copyright (c) 2019 Mellanox Technologies. */
3
4 #include "dr_types.h"
5
mlx5dr_cmd_query_esw_vport_context(struct mlx5_core_dev * mdev,bool other_vport,u16 vport_number,u64 * icm_address_rx,u64 * icm_address_tx)6 int mlx5dr_cmd_query_esw_vport_context(struct mlx5_core_dev *mdev,
7 bool other_vport,
8 u16 vport_number,
9 u64 *icm_address_rx,
10 u64 *icm_address_tx)
11 {
12 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
13 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {};
14 int err;
15
16 MLX5_SET(query_esw_vport_context_in, in, opcode,
17 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
18 MLX5_SET(query_esw_vport_context_in, in, other_vport, other_vport);
19 MLX5_SET(query_esw_vport_context_in, in, vport_number, vport_number);
20
21 err = mlx5_cmd_exec_inout(mdev, query_esw_vport_context, in, out);
22 if (err)
23 return err;
24
25 *icm_address_rx =
26 MLX5_GET64(query_esw_vport_context_out, out,
27 esw_vport_context.sw_steering_vport_icm_address_rx);
28 *icm_address_tx =
29 MLX5_GET64(query_esw_vport_context_out, out,
30 esw_vport_context.sw_steering_vport_icm_address_tx);
31 return 0;
32 }
33
mlx5dr_cmd_query_gvmi(struct mlx5_core_dev * mdev,bool other_vport,u16 vport_number,u16 * gvmi)34 int mlx5dr_cmd_query_gvmi(struct mlx5_core_dev *mdev, bool other_vport,
35 u16 vport_number, u16 *gvmi)
36 {
37 u32 in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {};
38 int out_size;
39 void *out;
40 int err;
41
42 out_size = MLX5_ST_SZ_BYTES(query_hca_cap_out);
43 out = kzalloc(out_size, GFP_KERNEL);
44 if (!out)
45 return -ENOMEM;
46
47 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
48 MLX5_SET(query_hca_cap_in, in, other_function, other_vport);
49 MLX5_SET(query_hca_cap_in, in, function_id, vport_number);
50 MLX5_SET(query_hca_cap_in, in, op_mod,
51 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE << 1 |
52 HCA_CAP_OPMOD_GET_CUR);
53
54 err = mlx5_cmd_exec_inout(mdev, query_hca_cap, in, out);
55 if (err) {
56 kfree(out);
57 return err;
58 }
59
60 *gvmi = MLX5_GET(query_hca_cap_out, out, capability.cmd_hca_cap.vhca_id);
61
62 kfree(out);
63 return 0;
64 }
65
mlx5dr_cmd_query_esw_caps(struct mlx5_core_dev * mdev,struct mlx5dr_esw_caps * caps)66 int mlx5dr_cmd_query_esw_caps(struct mlx5_core_dev *mdev,
67 struct mlx5dr_esw_caps *caps)
68 {
69 caps->drop_icm_address_rx =
70 MLX5_CAP64_ESW_FLOWTABLE(mdev,
71 sw_steering_fdb_action_drop_icm_address_rx);
72 caps->drop_icm_address_tx =
73 MLX5_CAP64_ESW_FLOWTABLE(mdev,
74 sw_steering_fdb_action_drop_icm_address_tx);
75 caps->uplink_icm_address_rx =
76 MLX5_CAP64_ESW_FLOWTABLE(mdev,
77 sw_steering_uplink_icm_address_rx);
78 caps->uplink_icm_address_tx =
79 MLX5_CAP64_ESW_FLOWTABLE(mdev,
80 sw_steering_uplink_icm_address_tx);
81 caps->sw_owner_v2 = MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, sw_owner_v2);
82 if (!caps->sw_owner_v2)
83 caps->sw_owner = MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, sw_owner);
84
85 return 0;
86 }
87
dr_cmd_query_nic_vport_roce_en(struct mlx5_core_dev * mdev,u16 vport,bool * roce_en)88 static int dr_cmd_query_nic_vport_roce_en(struct mlx5_core_dev *mdev,
89 u16 vport, bool *roce_en)
90 {
91 u32 out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {};
92 u32 in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {};
93 int err;
94
95 MLX5_SET(query_nic_vport_context_in, in, opcode,
96 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
97 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
98 MLX5_SET(query_nic_vport_context_in, in, other_vport, !!vport);
99
100 err = mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out));
101 if (err)
102 return err;
103
104 *roce_en = MLX5_GET(query_nic_vport_context_out, out,
105 nic_vport_context.roce_en);
106 return 0;
107 }
108
mlx5dr_cmd_query_device(struct mlx5_core_dev * mdev,struct mlx5dr_cmd_caps * caps)109 int mlx5dr_cmd_query_device(struct mlx5_core_dev *mdev,
110 struct mlx5dr_cmd_caps *caps)
111 {
112 bool roce_en;
113 int err;
114
115 caps->prio_tag_required = MLX5_CAP_GEN(mdev, prio_tag_required);
116 caps->eswitch_manager = MLX5_CAP_GEN(mdev, eswitch_manager);
117 caps->gvmi = MLX5_CAP_GEN(mdev, vhca_id);
118 caps->flex_protocols = MLX5_CAP_GEN(mdev, flex_parser_protocols);
119 caps->sw_format_ver = MLX5_CAP_GEN(mdev, steering_format_version);
120
121 if (MLX5_CAP_GEN(mdev, roce)) {
122 err = dr_cmd_query_nic_vport_roce_en(mdev, 0, &roce_en);
123 if (err)
124 return err;
125
126 caps->roce_caps.roce_en = roce_en;
127 caps->roce_caps.fl_rc_qp_when_roce_disabled =
128 MLX5_CAP_ROCE(mdev, fl_rc_qp_when_roce_disabled);
129 caps->roce_caps.fl_rc_qp_when_roce_enabled =
130 MLX5_CAP_ROCE(mdev, fl_rc_qp_when_roce_enabled);
131 }
132
133 caps->isolate_vl_tc = MLX5_CAP_GEN(mdev, isolate_vl_tc_new);
134
135 if (caps->flex_protocols & MLX5_FLEX_PARSER_ICMP_V4_ENABLED) {
136 caps->flex_parser_id_icmp_dw0 = MLX5_CAP_GEN(mdev, flex_parser_id_icmp_dw0);
137 caps->flex_parser_id_icmp_dw1 = MLX5_CAP_GEN(mdev, flex_parser_id_icmp_dw1);
138 }
139
140 if (caps->flex_protocols & MLX5_FLEX_PARSER_ICMP_V6_ENABLED) {
141 caps->flex_parser_id_icmpv6_dw0 =
142 MLX5_CAP_GEN(mdev, flex_parser_id_icmpv6_dw0);
143 caps->flex_parser_id_icmpv6_dw1 =
144 MLX5_CAP_GEN(mdev, flex_parser_id_icmpv6_dw1);
145 }
146
147 if (caps->flex_protocols & MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED)
148 caps->flex_parser_id_geneve_tlv_option_0 =
149 MLX5_CAP_GEN(mdev, flex_parser_id_geneve_tlv_option_0);
150
151 if (caps->flex_protocols & MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED)
152 caps->flex_parser_id_mpls_over_gre =
153 MLX5_CAP_GEN(mdev, flex_parser_id_outer_first_mpls_over_gre);
154
155 if (caps->flex_protocols & mlx5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED)
156 caps->flex_parser_id_mpls_over_udp =
157 MLX5_CAP_GEN(mdev, flex_parser_id_outer_first_mpls_over_udp_label);
158
159 if (caps->flex_protocols & MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED)
160 caps->flex_parser_id_gtpu_dw_0 =
161 MLX5_CAP_GEN(mdev, flex_parser_id_gtpu_dw_0);
162
163 if (caps->flex_protocols & MLX5_FLEX_PARSER_GTPU_TEID_ENABLED)
164 caps->flex_parser_id_gtpu_teid =
165 MLX5_CAP_GEN(mdev, flex_parser_id_gtpu_teid);
166
167 if (caps->flex_protocols & MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED)
168 caps->flex_parser_id_gtpu_dw_2 =
169 MLX5_CAP_GEN(mdev, flex_parser_id_gtpu_dw_2);
170
171 if (caps->flex_protocols & MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED)
172 caps->flex_parser_id_gtpu_first_ext_dw_0 =
173 MLX5_CAP_GEN(mdev, flex_parser_id_gtpu_first_ext_dw_0);
174
175 caps->nic_rx_drop_address =
176 MLX5_CAP64_FLOWTABLE(mdev, sw_steering_nic_rx_action_drop_icm_address);
177 caps->nic_tx_drop_address =
178 MLX5_CAP64_FLOWTABLE(mdev, sw_steering_nic_tx_action_drop_icm_address);
179 caps->nic_tx_allow_address =
180 MLX5_CAP64_FLOWTABLE(mdev, sw_steering_nic_tx_action_allow_icm_address);
181
182 caps->rx_sw_owner_v2 = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, sw_owner_v2);
183 caps->tx_sw_owner_v2 = MLX5_CAP_FLOWTABLE_NIC_TX(mdev, sw_owner_v2);
184
185 if (!caps->rx_sw_owner_v2)
186 caps->rx_sw_owner = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, sw_owner);
187 if (!caps->tx_sw_owner_v2)
188 caps->tx_sw_owner = MLX5_CAP_FLOWTABLE_NIC_TX(mdev, sw_owner);
189
190 caps->max_ft_level = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_ft_level);
191
192 caps->log_icm_size = MLX5_CAP_DEV_MEM(mdev, log_steering_sw_icm_size);
193 caps->hdr_modify_icm_addr =
194 MLX5_CAP64_DEV_MEM(mdev, header_modify_sw_icm_start_address);
195
196 caps->roce_min_src_udp = MLX5_CAP_ROCE(mdev, r_roce_min_src_udp_port);
197
198 return 0;
199 }
200
mlx5dr_cmd_query_flow_table(struct mlx5_core_dev * dev,enum fs_flow_table_type type,u32 table_id,struct mlx5dr_cmd_query_flow_table_details * output)201 int mlx5dr_cmd_query_flow_table(struct mlx5_core_dev *dev,
202 enum fs_flow_table_type type,
203 u32 table_id,
204 struct mlx5dr_cmd_query_flow_table_details *output)
205 {
206 u32 out[MLX5_ST_SZ_DW(query_flow_table_out)] = {};
207 u32 in[MLX5_ST_SZ_DW(query_flow_table_in)] = {};
208 int err;
209
210 MLX5_SET(query_flow_table_in, in, opcode,
211 MLX5_CMD_OP_QUERY_FLOW_TABLE);
212
213 MLX5_SET(query_flow_table_in, in, table_type, type);
214 MLX5_SET(query_flow_table_in, in, table_id, table_id);
215
216 err = mlx5_cmd_exec_inout(dev, query_flow_table, in, out);
217 if (err)
218 return err;
219
220 output->status = MLX5_GET(query_flow_table_out, out, status);
221 output->level = MLX5_GET(query_flow_table_out, out, flow_table_context.level);
222
223 output->sw_owner_icm_root_1 = MLX5_GET64(query_flow_table_out, out,
224 flow_table_context.sw_owner_icm_root_1);
225 output->sw_owner_icm_root_0 = MLX5_GET64(query_flow_table_out, out,
226 flow_table_context.sw_owner_icm_root_0);
227
228 return 0;
229 }
230
mlx5dr_cmd_query_flow_sampler(struct mlx5_core_dev * dev,u32 sampler_id,u64 * rx_icm_addr,u64 * tx_icm_addr)231 int mlx5dr_cmd_query_flow_sampler(struct mlx5_core_dev *dev,
232 u32 sampler_id,
233 u64 *rx_icm_addr,
234 u64 *tx_icm_addr)
235 {
236 u32 out[MLX5_ST_SZ_DW(query_sampler_obj_out)] = {};
237 u32 in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {};
238 void *attr;
239 int ret;
240
241 MLX5_SET(general_obj_in_cmd_hdr, in, opcode,
242 MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
243 MLX5_SET(general_obj_in_cmd_hdr, in, obj_type,
244 MLX5_GENERAL_OBJECT_TYPES_SAMPLER);
245 MLX5_SET(general_obj_in_cmd_hdr, in, obj_id, sampler_id);
246
247 ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
248 if (ret)
249 return ret;
250
251 attr = MLX5_ADDR_OF(query_sampler_obj_out, out, sampler_object);
252
253 *rx_icm_addr = MLX5_GET64(sampler_obj, attr,
254 sw_steering_icm_address_rx);
255 *tx_icm_addr = MLX5_GET64(sampler_obj, attr,
256 sw_steering_icm_address_tx);
257
258 return 0;
259 }
260
mlx5dr_cmd_sync_steering(struct mlx5_core_dev * mdev)261 int mlx5dr_cmd_sync_steering(struct mlx5_core_dev *mdev)
262 {
263 u32 in[MLX5_ST_SZ_DW(sync_steering_in)] = {};
264
265 MLX5_SET(sync_steering_in, in, opcode, MLX5_CMD_OP_SYNC_STEERING);
266
267 return mlx5_cmd_exec_in(mdev, sync_steering, in);
268 }
269
mlx5dr_cmd_set_fte_modify_and_vport(struct mlx5_core_dev * mdev,u32 table_type,u32 table_id,u32 group_id,u32 modify_header_id,u32 vport_id)270 int mlx5dr_cmd_set_fte_modify_and_vport(struct mlx5_core_dev *mdev,
271 u32 table_type,
272 u32 table_id,
273 u32 group_id,
274 u32 modify_header_id,
275 u32 vport_id)
276 {
277 u32 out[MLX5_ST_SZ_DW(set_fte_out)] = {};
278 void *in_flow_context;
279 unsigned int inlen;
280 void *in_dests;
281 u32 *in;
282 int err;
283
284 inlen = MLX5_ST_SZ_BYTES(set_fte_in) +
285 1 * MLX5_ST_SZ_BYTES(dest_format_struct); /* One destination only */
286
287 in = kvzalloc(inlen, GFP_KERNEL);
288 if (!in)
289 return -ENOMEM;
290
291 MLX5_SET(set_fte_in, in, opcode, MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY);
292 MLX5_SET(set_fte_in, in, table_type, table_type);
293 MLX5_SET(set_fte_in, in, table_id, table_id);
294
295 in_flow_context = MLX5_ADDR_OF(set_fte_in, in, flow_context);
296 MLX5_SET(flow_context, in_flow_context, group_id, group_id);
297 MLX5_SET(flow_context, in_flow_context, modify_header_id, modify_header_id);
298 MLX5_SET(flow_context, in_flow_context, destination_list_size, 1);
299 MLX5_SET(flow_context, in_flow_context, action,
300 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
301 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR);
302
303 in_dests = MLX5_ADDR_OF(flow_context, in_flow_context, destination);
304 MLX5_SET(dest_format_struct, in_dests, destination_type,
305 MLX5_FLOW_DESTINATION_TYPE_VPORT);
306 MLX5_SET(dest_format_struct, in_dests, destination_id, vport_id);
307
308 err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
309 kvfree(in);
310
311 return err;
312 }
313
mlx5dr_cmd_del_flow_table_entry(struct mlx5_core_dev * mdev,u32 table_type,u32 table_id)314 int mlx5dr_cmd_del_flow_table_entry(struct mlx5_core_dev *mdev,
315 u32 table_type,
316 u32 table_id)
317 {
318 u32 in[MLX5_ST_SZ_DW(delete_fte_in)] = {};
319
320 MLX5_SET(delete_fte_in, in, opcode, MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY);
321 MLX5_SET(delete_fte_in, in, table_type, table_type);
322 MLX5_SET(delete_fte_in, in, table_id, table_id);
323
324 return mlx5_cmd_exec_in(mdev, delete_fte, in);
325 }
326
mlx5dr_cmd_alloc_modify_header(struct mlx5_core_dev * mdev,u32 table_type,u8 num_of_actions,u64 * actions,u32 * modify_header_id)327 int mlx5dr_cmd_alloc_modify_header(struct mlx5_core_dev *mdev,
328 u32 table_type,
329 u8 num_of_actions,
330 u64 *actions,
331 u32 *modify_header_id)
332 {
333 u32 out[MLX5_ST_SZ_DW(alloc_modify_header_context_out)] = {};
334 void *p_actions;
335 u32 inlen;
336 u32 *in;
337 int err;
338
339 inlen = MLX5_ST_SZ_BYTES(alloc_modify_header_context_in) +
340 num_of_actions * sizeof(u64);
341 in = kvzalloc(inlen, GFP_KERNEL);
342 if (!in)
343 return -ENOMEM;
344
345 MLX5_SET(alloc_modify_header_context_in, in, opcode,
346 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT);
347 MLX5_SET(alloc_modify_header_context_in, in, table_type, table_type);
348 MLX5_SET(alloc_modify_header_context_in, in, num_of_actions, num_of_actions);
349 p_actions = MLX5_ADDR_OF(alloc_modify_header_context_in, in, actions);
350 memcpy(p_actions, actions, num_of_actions * sizeof(u64));
351
352 err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
353 if (err)
354 goto out;
355
356 *modify_header_id = MLX5_GET(alloc_modify_header_context_out, out,
357 modify_header_id);
358 out:
359 kvfree(in);
360 return err;
361 }
362
mlx5dr_cmd_dealloc_modify_header(struct mlx5_core_dev * mdev,u32 modify_header_id)363 int mlx5dr_cmd_dealloc_modify_header(struct mlx5_core_dev *mdev,
364 u32 modify_header_id)
365 {
366 u32 in[MLX5_ST_SZ_DW(dealloc_modify_header_context_in)] = {};
367
368 MLX5_SET(dealloc_modify_header_context_in, in, opcode,
369 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT);
370 MLX5_SET(dealloc_modify_header_context_in, in, modify_header_id,
371 modify_header_id);
372
373 return mlx5_cmd_exec_in(mdev, dealloc_modify_header_context, in);
374 }
375
mlx5dr_cmd_create_empty_flow_group(struct mlx5_core_dev * mdev,u32 table_type,u32 table_id,u32 * group_id)376 int mlx5dr_cmd_create_empty_flow_group(struct mlx5_core_dev *mdev,
377 u32 table_type,
378 u32 table_id,
379 u32 *group_id)
380 {
381 u32 out[MLX5_ST_SZ_DW(create_flow_group_out)] = {};
382 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
383 u32 *in;
384 int err;
385
386 in = kvzalloc(inlen, GFP_KERNEL);
387 if (!in)
388 return -ENOMEM;
389
390 MLX5_SET(create_flow_group_in, in, opcode, MLX5_CMD_OP_CREATE_FLOW_GROUP);
391 MLX5_SET(create_flow_group_in, in, table_type, table_type);
392 MLX5_SET(create_flow_group_in, in, table_id, table_id);
393
394 err = mlx5_cmd_exec_inout(mdev, create_flow_group, in, out);
395 if (err)
396 goto out;
397
398 *group_id = MLX5_GET(create_flow_group_out, out, group_id);
399
400 out:
401 kvfree(in);
402 return err;
403 }
404
mlx5dr_cmd_destroy_flow_group(struct mlx5_core_dev * mdev,u32 table_type,u32 table_id,u32 group_id)405 int mlx5dr_cmd_destroy_flow_group(struct mlx5_core_dev *mdev,
406 u32 table_type,
407 u32 table_id,
408 u32 group_id)
409 {
410 u32 in[MLX5_ST_SZ_DW(destroy_flow_group_in)] = {};
411
412 MLX5_SET(destroy_flow_group_in, in, opcode,
413 MLX5_CMD_OP_DESTROY_FLOW_GROUP);
414 MLX5_SET(destroy_flow_group_in, in, table_type, table_type);
415 MLX5_SET(destroy_flow_group_in, in, table_id, table_id);
416 MLX5_SET(destroy_flow_group_in, in, group_id, group_id);
417
418 return mlx5_cmd_exec_in(mdev, destroy_flow_group, in);
419 }
420
mlx5dr_cmd_create_flow_table(struct mlx5_core_dev * mdev,struct mlx5dr_cmd_create_flow_table_attr * attr,u64 * fdb_rx_icm_addr,u32 * table_id)421 int mlx5dr_cmd_create_flow_table(struct mlx5_core_dev *mdev,
422 struct mlx5dr_cmd_create_flow_table_attr *attr,
423 u64 *fdb_rx_icm_addr,
424 u32 *table_id)
425 {
426 u32 out[MLX5_ST_SZ_DW(create_flow_table_out)] = {};
427 u32 in[MLX5_ST_SZ_DW(create_flow_table_in)] = {};
428 void *ft_mdev;
429 int err;
430
431 MLX5_SET(create_flow_table_in, in, opcode, MLX5_CMD_OP_CREATE_FLOW_TABLE);
432 MLX5_SET(create_flow_table_in, in, table_type, attr->table_type);
433
434 ft_mdev = MLX5_ADDR_OF(create_flow_table_in, in, flow_table_context);
435 MLX5_SET(flow_table_context, ft_mdev, termination_table, attr->term_tbl);
436 MLX5_SET(flow_table_context, ft_mdev, sw_owner, attr->sw_owner);
437 MLX5_SET(flow_table_context, ft_mdev, level, attr->level);
438
439 if (attr->sw_owner) {
440 /* icm_addr_0 used for FDB RX / NIC TX / NIC_RX
441 * icm_addr_1 used for FDB TX
442 */
443 if (attr->table_type == MLX5_FLOW_TABLE_TYPE_NIC_RX) {
444 MLX5_SET64(flow_table_context, ft_mdev,
445 sw_owner_icm_root_0, attr->icm_addr_rx);
446 } else if (attr->table_type == MLX5_FLOW_TABLE_TYPE_NIC_TX) {
447 MLX5_SET64(flow_table_context, ft_mdev,
448 sw_owner_icm_root_0, attr->icm_addr_tx);
449 } else if (attr->table_type == MLX5_FLOW_TABLE_TYPE_FDB) {
450 MLX5_SET64(flow_table_context, ft_mdev,
451 sw_owner_icm_root_0, attr->icm_addr_rx);
452 MLX5_SET64(flow_table_context, ft_mdev,
453 sw_owner_icm_root_1, attr->icm_addr_tx);
454 }
455 }
456
457 MLX5_SET(create_flow_table_in, in, flow_table_context.decap_en,
458 attr->decap_en);
459 MLX5_SET(create_flow_table_in, in, flow_table_context.reformat_en,
460 attr->reformat_en);
461
462 err = mlx5_cmd_exec_inout(mdev, create_flow_table, in, out);
463 if (err)
464 return err;
465
466 *table_id = MLX5_GET(create_flow_table_out, out, table_id);
467 if (!attr->sw_owner && attr->table_type == MLX5_FLOW_TABLE_TYPE_FDB &&
468 fdb_rx_icm_addr)
469 *fdb_rx_icm_addr =
470 (u64)MLX5_GET(create_flow_table_out, out, icm_address_31_0) |
471 (u64)MLX5_GET(create_flow_table_out, out, icm_address_39_32) << 32 |
472 (u64)MLX5_GET(create_flow_table_out, out, icm_address_63_40) << 40;
473
474 return 0;
475 }
476
mlx5dr_cmd_destroy_flow_table(struct mlx5_core_dev * mdev,u32 table_id,u32 table_type)477 int mlx5dr_cmd_destroy_flow_table(struct mlx5_core_dev *mdev,
478 u32 table_id,
479 u32 table_type)
480 {
481 u32 in[MLX5_ST_SZ_DW(destroy_flow_table_in)] = {};
482
483 MLX5_SET(destroy_flow_table_in, in, opcode,
484 MLX5_CMD_OP_DESTROY_FLOW_TABLE);
485 MLX5_SET(destroy_flow_table_in, in, table_type, table_type);
486 MLX5_SET(destroy_flow_table_in, in, table_id, table_id);
487
488 return mlx5_cmd_exec_in(mdev, destroy_flow_table, in);
489 }
490
mlx5dr_cmd_create_reformat_ctx(struct mlx5_core_dev * mdev,enum mlx5_reformat_ctx_type rt,u8 reformat_param_0,u8 reformat_param_1,size_t reformat_size,void * reformat_data,u32 * reformat_id)491 int mlx5dr_cmd_create_reformat_ctx(struct mlx5_core_dev *mdev,
492 enum mlx5_reformat_ctx_type rt,
493 u8 reformat_param_0,
494 u8 reformat_param_1,
495 size_t reformat_size,
496 void *reformat_data,
497 u32 *reformat_id)
498 {
499 u32 out[MLX5_ST_SZ_DW(alloc_packet_reformat_context_out)] = {};
500 size_t inlen, cmd_data_sz, cmd_total_sz;
501 void *prctx;
502 void *pdata;
503 void *in;
504 int err;
505
506 cmd_total_sz = MLX5_ST_SZ_BYTES(alloc_packet_reformat_context_in);
507 cmd_data_sz = MLX5_FLD_SZ_BYTES(alloc_packet_reformat_context_in,
508 packet_reformat_context.reformat_data);
509 inlen = ALIGN(cmd_total_sz + reformat_size - cmd_data_sz, 4);
510 in = kvzalloc(inlen, GFP_KERNEL);
511 if (!in)
512 return -ENOMEM;
513
514 MLX5_SET(alloc_packet_reformat_context_in, in, opcode,
515 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT);
516
517 prctx = MLX5_ADDR_OF(alloc_packet_reformat_context_in, in, packet_reformat_context);
518 pdata = MLX5_ADDR_OF(packet_reformat_context_in, prctx, reformat_data);
519
520 MLX5_SET(packet_reformat_context_in, prctx, reformat_type, rt);
521 MLX5_SET(packet_reformat_context_in, prctx, reformat_param_0, reformat_param_0);
522 MLX5_SET(packet_reformat_context_in, prctx, reformat_param_1, reformat_param_1);
523 MLX5_SET(packet_reformat_context_in, prctx, reformat_data_size, reformat_size);
524 if (reformat_data && reformat_size)
525 memcpy(pdata, reformat_data, reformat_size);
526
527 err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
528 if (err)
529 return err;
530
531 *reformat_id = MLX5_GET(alloc_packet_reformat_context_out, out, packet_reformat_id);
532 kvfree(in);
533
534 return err;
535 }
536
mlx5dr_cmd_destroy_reformat_ctx(struct mlx5_core_dev * mdev,u32 reformat_id)537 void mlx5dr_cmd_destroy_reformat_ctx(struct mlx5_core_dev *mdev,
538 u32 reformat_id)
539 {
540 u32 in[MLX5_ST_SZ_DW(dealloc_packet_reformat_context_in)] = {};
541
542 MLX5_SET(dealloc_packet_reformat_context_in, in, opcode,
543 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT);
544 MLX5_SET(dealloc_packet_reformat_context_in, in, packet_reformat_id,
545 reformat_id);
546
547 mlx5_cmd_exec_in(mdev, dealloc_packet_reformat_context, in);
548 }
549
mlx5dr_cmd_query_gid(struct mlx5_core_dev * mdev,u8 vhca_port_num,u16 index,struct mlx5dr_cmd_gid_attr * attr)550 int mlx5dr_cmd_query_gid(struct mlx5_core_dev *mdev, u8 vhca_port_num,
551 u16 index, struct mlx5dr_cmd_gid_attr *attr)
552 {
553 u32 out[MLX5_ST_SZ_DW(query_roce_address_out)] = {};
554 u32 in[MLX5_ST_SZ_DW(query_roce_address_in)] = {};
555 int err;
556
557 MLX5_SET(query_roce_address_in, in, opcode,
558 MLX5_CMD_OP_QUERY_ROCE_ADDRESS);
559
560 MLX5_SET(query_roce_address_in, in, roce_address_index, index);
561 MLX5_SET(query_roce_address_in, in, vhca_port_num, vhca_port_num);
562
563 err = mlx5_cmd_exec_inout(mdev, query_roce_address, in, out);
564 if (err)
565 return err;
566
567 memcpy(&attr->gid,
568 MLX5_ADDR_OF(query_roce_address_out,
569 out, roce_address.source_l3_address),
570 sizeof(attr->gid));
571 memcpy(attr->mac,
572 MLX5_ADDR_OF(query_roce_address_out, out,
573 roce_address.source_mac_47_32),
574 sizeof(attr->mac));
575
576 if (MLX5_GET(query_roce_address_out, out,
577 roce_address.roce_version) == MLX5_ROCE_VERSION_2)
578 attr->roce_ver = MLX5_ROCE_VERSION_2;
579 else
580 attr->roce_ver = MLX5_ROCE_VERSION_1;
581
582 return 0;
583 }
584
mlx5dr_cmd_set_extended_dest(struct mlx5_core_dev * dev,struct mlx5dr_cmd_fte_info * fte,bool * extended_dest)585 static int mlx5dr_cmd_set_extended_dest(struct mlx5_core_dev *dev,
586 struct mlx5dr_cmd_fte_info *fte,
587 bool *extended_dest)
588 {
589 int fw_log_max_fdb_encap_uplink = MLX5_CAP_ESW(dev, log_max_fdb_encap_uplink);
590 int num_fwd_destinations = 0;
591 int num_encap = 0;
592 int i;
593
594 *extended_dest = false;
595 if (!(fte->action.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST))
596 return 0;
597 for (i = 0; i < fte->dests_size; i++) {
598 if (fte->dest_arr[i].type == MLX5_FLOW_DESTINATION_TYPE_COUNTER)
599 continue;
600 if (fte->dest_arr[i].type == MLX5_FLOW_DESTINATION_TYPE_VPORT &&
601 fte->dest_arr[i].vport.flags & MLX5_FLOW_DEST_VPORT_REFORMAT_ID)
602 num_encap++;
603 num_fwd_destinations++;
604 }
605
606 if (num_fwd_destinations > 1 && num_encap > 0)
607 *extended_dest = true;
608
609 if (*extended_dest && !fw_log_max_fdb_encap_uplink) {
610 mlx5_core_warn(dev, "FW does not support extended destination");
611 return -EOPNOTSUPP;
612 }
613 if (num_encap > (1 << fw_log_max_fdb_encap_uplink)) {
614 mlx5_core_warn(dev, "FW does not support more than %d encaps",
615 1 << fw_log_max_fdb_encap_uplink);
616 return -EOPNOTSUPP;
617 }
618
619 return 0;
620 }
621
mlx5dr_cmd_set_fte(struct mlx5_core_dev * dev,int opmod,int modify_mask,struct mlx5dr_cmd_ft_info * ft,u32 group_id,struct mlx5dr_cmd_fte_info * fte)622 int mlx5dr_cmd_set_fte(struct mlx5_core_dev *dev,
623 int opmod, int modify_mask,
624 struct mlx5dr_cmd_ft_info *ft,
625 u32 group_id,
626 struct mlx5dr_cmd_fte_info *fte)
627 {
628 u32 out[MLX5_ST_SZ_DW(set_fte_out)] = {};
629 void *in_flow_context, *vlan;
630 bool extended_dest = false;
631 void *in_match_value;
632 unsigned int inlen;
633 int dst_cnt_size;
634 void *in_dests;
635 u32 *in;
636 int err;
637 int i;
638
639 if (mlx5dr_cmd_set_extended_dest(dev, fte, &extended_dest))
640 return -EOPNOTSUPP;
641
642 if (!extended_dest)
643 dst_cnt_size = MLX5_ST_SZ_BYTES(dest_format_struct);
644 else
645 dst_cnt_size = MLX5_ST_SZ_BYTES(extended_dest_format);
646
647 inlen = MLX5_ST_SZ_BYTES(set_fte_in) + fte->dests_size * dst_cnt_size;
648 in = kvzalloc(inlen, GFP_KERNEL);
649 if (!in)
650 return -ENOMEM;
651
652 MLX5_SET(set_fte_in, in, opcode, MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY);
653 MLX5_SET(set_fte_in, in, op_mod, opmod);
654 MLX5_SET(set_fte_in, in, modify_enable_mask, modify_mask);
655 MLX5_SET(set_fte_in, in, table_type, ft->type);
656 MLX5_SET(set_fte_in, in, table_id, ft->id);
657 MLX5_SET(set_fte_in, in, flow_index, fte->index);
658 MLX5_SET(set_fte_in, in, ignore_flow_level, fte->ignore_flow_level);
659 if (ft->vport) {
660 MLX5_SET(set_fte_in, in, vport_number, ft->vport);
661 MLX5_SET(set_fte_in, in, other_vport, 1);
662 }
663
664 in_flow_context = MLX5_ADDR_OF(set_fte_in, in, flow_context);
665 MLX5_SET(flow_context, in_flow_context, group_id, group_id);
666
667 MLX5_SET(flow_context, in_flow_context, flow_tag,
668 fte->flow_context.flow_tag);
669 MLX5_SET(flow_context, in_flow_context, flow_source,
670 fte->flow_context.flow_source);
671
672 MLX5_SET(flow_context, in_flow_context, extended_destination,
673 extended_dest);
674 if (extended_dest) {
675 u32 action;
676
677 action = fte->action.action &
678 ~MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
679 MLX5_SET(flow_context, in_flow_context, action, action);
680 } else {
681 MLX5_SET(flow_context, in_flow_context, action,
682 fte->action.action);
683 if (fte->action.pkt_reformat)
684 MLX5_SET(flow_context, in_flow_context, packet_reformat_id,
685 fte->action.pkt_reformat->id);
686 }
687 if (fte->action.modify_hdr)
688 MLX5_SET(flow_context, in_flow_context, modify_header_id,
689 fte->action.modify_hdr->id);
690
691 vlan = MLX5_ADDR_OF(flow_context, in_flow_context, push_vlan);
692
693 MLX5_SET(vlan, vlan, ethtype, fte->action.vlan[0].ethtype);
694 MLX5_SET(vlan, vlan, vid, fte->action.vlan[0].vid);
695 MLX5_SET(vlan, vlan, prio, fte->action.vlan[0].prio);
696
697 vlan = MLX5_ADDR_OF(flow_context, in_flow_context, push_vlan_2);
698
699 MLX5_SET(vlan, vlan, ethtype, fte->action.vlan[1].ethtype);
700 MLX5_SET(vlan, vlan, vid, fte->action.vlan[1].vid);
701 MLX5_SET(vlan, vlan, prio, fte->action.vlan[1].prio);
702
703 in_match_value = MLX5_ADDR_OF(flow_context, in_flow_context,
704 match_value);
705 memcpy(in_match_value, fte->val, sizeof(u32) * MLX5_ST_SZ_DW_MATCH_PARAM);
706
707 in_dests = MLX5_ADDR_OF(flow_context, in_flow_context, destination);
708 if (fte->action.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
709 int list_size = 0;
710
711 for (i = 0; i < fte->dests_size; i++) {
712 unsigned int id, type = fte->dest_arr[i].type;
713
714 if (type == MLX5_FLOW_DESTINATION_TYPE_COUNTER)
715 continue;
716
717 switch (type) {
718 case MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM:
719 id = fte->dest_arr[i].ft_num;
720 type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
721 break;
722 case MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE:
723 id = fte->dest_arr[i].ft_id;
724 break;
725 case MLX5_FLOW_DESTINATION_TYPE_VPORT:
726 id = fte->dest_arr[i].vport.num;
727 MLX5_SET(dest_format_struct, in_dests,
728 destination_eswitch_owner_vhca_id_valid,
729 !!(fte->dest_arr[i].vport.flags &
730 MLX5_FLOW_DEST_VPORT_VHCA_ID));
731 MLX5_SET(dest_format_struct, in_dests,
732 destination_eswitch_owner_vhca_id,
733 fte->dest_arr[i].vport.vhca_id);
734 if (extended_dest && (fte->dest_arr[i].vport.flags &
735 MLX5_FLOW_DEST_VPORT_REFORMAT_ID)) {
736 MLX5_SET(dest_format_struct, in_dests,
737 packet_reformat,
738 !!(fte->dest_arr[i].vport.flags &
739 MLX5_FLOW_DEST_VPORT_REFORMAT_ID));
740 MLX5_SET(extended_dest_format, in_dests,
741 packet_reformat_id,
742 fte->dest_arr[i].vport.reformat_id);
743 }
744 break;
745 case MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER:
746 id = fte->dest_arr[i].sampler_id;
747 break;
748 default:
749 id = fte->dest_arr[i].tir_num;
750 }
751
752 MLX5_SET(dest_format_struct, in_dests, destination_type,
753 type);
754 MLX5_SET(dest_format_struct, in_dests, destination_id, id);
755 in_dests += dst_cnt_size;
756 list_size++;
757 }
758
759 MLX5_SET(flow_context, in_flow_context, destination_list_size,
760 list_size);
761 }
762
763 if (fte->action.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
764 int max_list_size = BIT(MLX5_CAP_FLOWTABLE_TYPE(dev,
765 log_max_flow_counter,
766 ft->type));
767 int list_size = 0;
768
769 for (i = 0; i < fte->dests_size; i++) {
770 if (fte->dest_arr[i].type !=
771 MLX5_FLOW_DESTINATION_TYPE_COUNTER)
772 continue;
773
774 MLX5_SET(flow_counter_list, in_dests, flow_counter_id,
775 fte->dest_arr[i].counter_id);
776 in_dests += dst_cnt_size;
777 list_size++;
778 }
779 if (list_size > max_list_size) {
780 err = -EINVAL;
781 goto err_out;
782 }
783
784 MLX5_SET(flow_context, in_flow_context, flow_counter_list_size,
785 list_size);
786 }
787
788 err = mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
789 err_out:
790 kvfree(in);
791 return err;
792 }
793
