1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /* Copyright (c) 2019 Mellanox Technologies. */
3
4 #include "dr_types.h"
5 #include "dr_ste.h"
6
7 enum dr_action_domain {
8 DR_ACTION_DOMAIN_NIC_INGRESS,
9 DR_ACTION_DOMAIN_NIC_EGRESS,
10 DR_ACTION_DOMAIN_FDB_INGRESS,
11 DR_ACTION_DOMAIN_FDB_EGRESS,
12 DR_ACTION_DOMAIN_MAX,
13 };
14
15 enum dr_action_valid_state {
16 DR_ACTION_STATE_ERR,
17 DR_ACTION_STATE_NO_ACTION,
18 DR_ACTION_STATE_ENCAP,
19 DR_ACTION_STATE_DECAP,
20 DR_ACTION_STATE_MODIFY_HDR,
21 DR_ACTION_STATE_POP_VLAN,
22 DR_ACTION_STATE_PUSH_VLAN,
23 DR_ACTION_STATE_NON_TERM,
24 DR_ACTION_STATE_TERM,
25 DR_ACTION_STATE_ASO,
26 DR_ACTION_STATE_MAX,
27 };
28
29 static const char * const action_type_to_str[] = {
30 [DR_ACTION_TYP_TNL_L2_TO_L2] = "DR_ACTION_TYP_TNL_L2_TO_L2",
31 [DR_ACTION_TYP_L2_TO_TNL_L2] = "DR_ACTION_TYP_L2_TO_TNL_L2",
32 [DR_ACTION_TYP_TNL_L3_TO_L2] = "DR_ACTION_TYP_TNL_L3_TO_L2",
33 [DR_ACTION_TYP_L2_TO_TNL_L3] = "DR_ACTION_TYP_L2_TO_TNL_L3",
34 [DR_ACTION_TYP_DROP] = "DR_ACTION_TYP_DROP",
35 [DR_ACTION_TYP_QP] = "DR_ACTION_TYP_QP",
36 [DR_ACTION_TYP_FT] = "DR_ACTION_TYP_FT",
37 [DR_ACTION_TYP_CTR] = "DR_ACTION_TYP_CTR",
38 [DR_ACTION_TYP_TAG] = "DR_ACTION_TYP_TAG",
39 [DR_ACTION_TYP_MODIFY_HDR] = "DR_ACTION_TYP_MODIFY_HDR",
40 [DR_ACTION_TYP_VPORT] = "DR_ACTION_TYP_VPORT",
41 [DR_ACTION_TYP_POP_VLAN] = "DR_ACTION_TYP_POP_VLAN",
42 [DR_ACTION_TYP_PUSH_VLAN] = "DR_ACTION_TYP_PUSH_VLAN",
43 [DR_ACTION_TYP_SAMPLER] = "DR_ACTION_TYP_SAMPLER",
44 [DR_ACTION_TYP_INSERT_HDR] = "DR_ACTION_TYP_INSERT_HDR",
45 [DR_ACTION_TYP_REMOVE_HDR] = "DR_ACTION_TYP_REMOVE_HDR",
46 [DR_ACTION_TYP_ASO_FLOW_METER] = "DR_ACTION_TYP_ASO_FLOW_METER",
47 [DR_ACTION_TYP_RANGE] = "DR_ACTION_TYP_RANGE",
48 [DR_ACTION_TYP_MAX] = "DR_ACTION_UNKNOWN",
49 };
50
dr_action_id_to_str(enum mlx5dr_action_type action_id)51 static const char *dr_action_id_to_str(enum mlx5dr_action_type action_id)
52 {
53 if (action_id > DR_ACTION_TYP_MAX)
54 action_id = DR_ACTION_TYP_MAX;
55 return action_type_to_str[action_id];
56 }
57
58 static const enum dr_action_valid_state
59 next_action_state[DR_ACTION_DOMAIN_MAX][DR_ACTION_STATE_MAX][DR_ACTION_TYP_MAX] = {
60 [DR_ACTION_DOMAIN_NIC_INGRESS] = {
61 [DR_ACTION_STATE_NO_ACTION] = {
62 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
63 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
64 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
65 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
66 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
67 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_NON_TERM,
68 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
69 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP,
70 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP,
71 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
72 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
73 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
74 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP,
75 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
76 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
77 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
78 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
79 },
80 [DR_ACTION_STATE_DECAP] = {
81 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
82 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
83 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
84 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
85 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
86 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_DECAP,
87 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP,
88 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
89 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
90 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
91 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
92 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
93 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
94 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
95 },
96 [DR_ACTION_STATE_ENCAP] = {
97 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
98 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
99 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
100 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
101 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
102 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_ENCAP,
103 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP,
104 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
105 },
106 [DR_ACTION_STATE_MODIFY_HDR] = {
107 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
108 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
109 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
110 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
111 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
112 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_MODIFY_HDR,
113 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR,
114 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
115 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
116 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
117 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
118 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
119 },
120 [DR_ACTION_STATE_POP_VLAN] = {
121 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
122 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
123 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
124 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
125 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
126 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_POP_VLAN,
127 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN,
128 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
129 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
130 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
131 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
132 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
133 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
134 },
135 [DR_ACTION_STATE_PUSH_VLAN] = {
136 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
137 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
138 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
139 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
140 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_PUSH_VLAN,
141 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN,
142 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
143 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
144 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
145 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
146 },
147 [DR_ACTION_STATE_NON_TERM] = {
148 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
149 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
150 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
151 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
152 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
153 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_NON_TERM,
154 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
155 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP,
156 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP,
157 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
158 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
159 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
160 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP,
161 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
162 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
163 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
164 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
165 },
166 [DR_ACTION_STATE_ASO] = {
167 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
168 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
169 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
170 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
171 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ASO,
172 },
173 [DR_ACTION_STATE_TERM] = {
174 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM,
175 },
176 },
177 [DR_ACTION_DOMAIN_NIC_EGRESS] = {
178 [DR_ACTION_STATE_NO_ACTION] = {
179 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
180 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
181 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
182 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
183 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
184 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
185 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
186 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
187 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP,
188 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
189 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
190 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
191 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
192 },
193 [DR_ACTION_STATE_DECAP] = {
194 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
195 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
196 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
197 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
198 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP,
199 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
200 },
201 [DR_ACTION_STATE_ENCAP] = {
202 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
203 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
204 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
205 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
206 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP,
207 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
208 },
209 [DR_ACTION_STATE_MODIFY_HDR] = {
210 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
211 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
212 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
213 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
214 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR,
215 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
216 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
217 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
218 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
219 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
220 },
221 [DR_ACTION_STATE_POP_VLAN] = {
222 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
223 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
224 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
225 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN,
226 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
227 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
228 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
229 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
230 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
231 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
232 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
233 },
234 [DR_ACTION_STATE_PUSH_VLAN] = {
235 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
236 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
237 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
238 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
239 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN,
240 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
241 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
242 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
243 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
244 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
245 },
246 [DR_ACTION_STATE_NON_TERM] = {
247 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
248 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
249 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
250 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
251 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
252 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
253 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
254 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
255 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP,
256 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
257 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
258 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
259 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
260 },
261 [DR_ACTION_STATE_ASO] = {
262 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
263 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
264 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
265 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
266 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ASO,
267 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
268 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
269 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
270 },
271 [DR_ACTION_STATE_TERM] = {
272 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM,
273 },
274 },
275 [DR_ACTION_DOMAIN_FDB_INGRESS] = {
276 [DR_ACTION_STATE_NO_ACTION] = {
277 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
278 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
279 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
280 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
281 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
282 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP,
283 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP,
284 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
285 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
286 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
287 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP,
288 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
289 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
290 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
291 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
292 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
293 },
294 [DR_ACTION_STATE_DECAP] = {
295 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
296 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
297 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
298 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP,
299 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
300 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
301 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
302 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
303 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
304 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
305 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
306 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
307 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
308 },
309 [DR_ACTION_STATE_ENCAP] = {
310 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
311 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
312 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
313 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
314 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
315 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
316 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP,
317 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
318 },
319 [DR_ACTION_STATE_MODIFY_HDR] = {
320 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
321 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
322 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
323 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
324 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR,
325 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
326 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
327 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
328 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
329 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
330 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
331 },
332 [DR_ACTION_STATE_POP_VLAN] = {
333 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
334 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
335 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
336 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
337 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
338 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN,
339 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
340 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
341 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
342 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
343 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
344 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
345 },
346 [DR_ACTION_STATE_PUSH_VLAN] = {
347 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
348 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
349 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
350 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
351 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
352 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN,
353 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
354 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
355 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
356 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
357 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
358 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
359 },
360 [DR_ACTION_STATE_NON_TERM] = {
361 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
362 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
363 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
364 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
365 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
366 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP,
367 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP,
368 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
369 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
370 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
371 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP,
372 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
373 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
374 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
375 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
376 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
377 },
378 [DR_ACTION_STATE_ASO] = {
379 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
380 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
381 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
382 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
383 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ASO,
384 },
385 [DR_ACTION_STATE_TERM] = {
386 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM,
387 },
388 },
389 [DR_ACTION_DOMAIN_FDB_EGRESS] = {
390 [DR_ACTION_STATE_NO_ACTION] = {
391 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
392 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
393 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
394 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
395 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
396 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
397 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
398 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
399 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
400 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP,
401 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
402 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
403 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
404 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
405 },
406 [DR_ACTION_STATE_DECAP] = {
407 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
408 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
409 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
410 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP,
411 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
412 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
413 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
414 },
415 [DR_ACTION_STATE_ENCAP] = {
416 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
417 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
418 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
419 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP,
420 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
421 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
422 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
423 },
424 [DR_ACTION_STATE_MODIFY_HDR] = {
425 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
426 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
427 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
428 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
429 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR,
430 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
431 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
432 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
433 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
434 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
435 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
436 },
437 [DR_ACTION_STATE_POP_VLAN] = {
438 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
439 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
440 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
441 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN,
442 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
443 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
444 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
445 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
446 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
447 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
448 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
449 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
450 },
451 [DR_ACTION_STATE_PUSH_VLAN] = {
452 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
453 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
454 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
455 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
456 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
457 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN,
458 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
459 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
460 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
461 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
462 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
463 },
464 [DR_ACTION_STATE_NON_TERM] = {
465 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
466 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
467 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
468 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM,
469 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
470 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
471 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
472 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
473 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP,
474 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP,
475 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
476 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN,
477 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
478 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO,
479 },
480 [DR_ACTION_STATE_ASO] = {
481 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP,
482 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP,
483 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
484 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN,
485 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
486 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
487 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM,
488 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
489 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ASO,
490 },
491 [DR_ACTION_STATE_TERM] = {
492 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM,
493 },
494 },
495 };
496
497 static int
dr_action_reformat_to_action_type(enum mlx5dr_action_reformat_type reformat_type,enum mlx5dr_action_type * action_type)498 dr_action_reformat_to_action_type(enum mlx5dr_action_reformat_type reformat_type,
499 enum mlx5dr_action_type *action_type)
500 {
501 switch (reformat_type) {
502 case DR_ACTION_REFORMAT_TYP_TNL_L2_TO_L2:
503 *action_type = DR_ACTION_TYP_TNL_L2_TO_L2;
504 break;
505 case DR_ACTION_REFORMAT_TYP_L2_TO_TNL_L2:
506 *action_type = DR_ACTION_TYP_L2_TO_TNL_L2;
507 break;
508 case DR_ACTION_REFORMAT_TYP_TNL_L3_TO_L2:
509 *action_type = DR_ACTION_TYP_TNL_L3_TO_L2;
510 break;
511 case DR_ACTION_REFORMAT_TYP_L2_TO_TNL_L3:
512 *action_type = DR_ACTION_TYP_L2_TO_TNL_L3;
513 break;
514 case DR_ACTION_REFORMAT_TYP_INSERT_HDR:
515 *action_type = DR_ACTION_TYP_INSERT_HDR;
516 break;
517 case DR_ACTION_REFORMAT_TYP_REMOVE_HDR:
518 *action_type = DR_ACTION_TYP_REMOVE_HDR;
519 break;
520 default:
521 return -EINVAL;
522 }
523
524 return 0;
525 }
526
527 /* Apply the actions on the rule STE array starting from the last_ste.
528 * Actions might require more than one STE, new_num_stes will return
529 * the new size of the STEs array, rule with actions.
530 */
dr_actions_apply(struct mlx5dr_domain * dmn,enum mlx5dr_domain_nic_type nic_type,u8 * action_type_set,u8 * last_ste,struct mlx5dr_ste_actions_attr * attr,u32 * new_num_stes)531 static void dr_actions_apply(struct mlx5dr_domain *dmn,
532 enum mlx5dr_domain_nic_type nic_type,
533 u8 *action_type_set,
534 u8 *last_ste,
535 struct mlx5dr_ste_actions_attr *attr,
536 u32 *new_num_stes)
537 {
538 struct mlx5dr_ste_ctx *ste_ctx = dmn->ste_ctx;
539 u32 added_stes = 0;
540
541 if (nic_type == DR_DOMAIN_NIC_TYPE_RX)
542 mlx5dr_ste_set_actions_rx(ste_ctx, dmn, action_type_set,
543 last_ste, attr, &added_stes);
544 else
545 mlx5dr_ste_set_actions_tx(ste_ctx, dmn, action_type_set,
546 last_ste, attr, &added_stes);
547
548 *new_num_stes += added_stes;
549 }
550
551 static enum dr_action_domain
dr_action_get_action_domain(enum mlx5dr_domain_type domain,enum mlx5dr_domain_nic_type nic_type)552 dr_action_get_action_domain(enum mlx5dr_domain_type domain,
553 enum mlx5dr_domain_nic_type nic_type)
554 {
555 switch (domain) {
556 case MLX5DR_DOMAIN_TYPE_NIC_RX:
557 return DR_ACTION_DOMAIN_NIC_INGRESS;
558 case MLX5DR_DOMAIN_TYPE_NIC_TX:
559 return DR_ACTION_DOMAIN_NIC_EGRESS;
560 case MLX5DR_DOMAIN_TYPE_FDB:
561 if (nic_type == DR_DOMAIN_NIC_TYPE_RX)
562 return DR_ACTION_DOMAIN_FDB_INGRESS;
563 return DR_ACTION_DOMAIN_FDB_EGRESS;
564 default:
565 WARN_ON(true);
566 return DR_ACTION_DOMAIN_MAX;
567 }
568 }
569
570 static
dr_action_validate_and_get_next_state(enum dr_action_domain action_domain,u32 action_type,u32 * state)571 int dr_action_validate_and_get_next_state(enum dr_action_domain action_domain,
572 u32 action_type,
573 u32 *state)
574 {
575 u32 cur_state = *state;
576
577 /* Check action state machine is valid */
578 *state = next_action_state[action_domain][cur_state][action_type];
579
580 if (*state == DR_ACTION_STATE_ERR)
581 return -EOPNOTSUPP;
582
583 return 0;
584 }
585
dr_action_handle_cs_recalc(struct mlx5dr_domain * dmn,struct mlx5dr_action * dest_action,u64 * final_icm_addr)586 static int dr_action_handle_cs_recalc(struct mlx5dr_domain *dmn,
587 struct mlx5dr_action *dest_action,
588 u64 *final_icm_addr)
589 {
590 int ret;
591
592 switch (dest_action->action_type) {
593 case DR_ACTION_TYP_FT:
594 /* Allow destination flow table only if table is a terminating
595 * table, since there is an *assumption* that in such case FW
596 * will recalculate the CS.
597 */
598 if (dest_action->dest_tbl->is_fw_tbl) {
599 *final_icm_addr = dest_action->dest_tbl->fw_tbl.rx_icm_addr;
600 } else {
601 mlx5dr_dbg(dmn,
602 "Destination FT should be terminating when modify TTL is used\n");
603 return -EINVAL;
604 }
605 break;
606
607 case DR_ACTION_TYP_VPORT:
608 /* If destination is vport we will get the FW flow table
609 * that recalculates the CS and forwards to the vport.
610 */
611 ret = mlx5dr_domain_get_recalc_cs_ft_addr(dest_action->vport->dmn,
612 dest_action->vport->caps->num,
613 final_icm_addr);
614 if (ret) {
615 mlx5dr_err(dmn, "Failed to get FW cs recalc flow table\n");
616 return ret;
617 }
618 break;
619
620 default:
621 break;
622 }
623
624 return 0;
625 }
626
dr_action_modify_ttl_adjust(struct mlx5dr_domain * dmn,struct mlx5dr_ste_actions_attr * attr,bool rx_rule,bool * recalc_cs_required)627 static void dr_action_modify_ttl_adjust(struct mlx5dr_domain *dmn,
628 struct mlx5dr_ste_actions_attr *attr,
629 bool rx_rule,
630 bool *recalc_cs_required)
631 {
632 *recalc_cs_required = false;
633
634 /* if device supports csum recalculation - no adjustment needed */
635 if (mlx5dr_ste_supp_ttl_cs_recalc(&dmn->info.caps))
636 return;
637
638 /* no adjustment needed on TX rules */
639 if (!rx_rule)
640 return;
641
642 if (!MLX5_CAP_ESW_FLOWTABLE(dmn->mdev, fdb_ipv4_ttl_modify)) {
643 /* Ignore the modify TTL action.
644 * It is always kept as last HW action.
645 */
646 attr->modify_actions--;
647 return;
648 }
649
650 if (dmn->type == MLX5DR_DOMAIN_TYPE_FDB)
651 /* Due to a HW bug on some devices, modifying TTL on RX flows
652 * will cause an incorrect checksum calculation. In such cases
653 * we will use a FW table to recalculate the checksum.
654 */
655 *recalc_cs_required = true;
656 }
657
dr_action_print_sequence(struct mlx5dr_domain * dmn,struct mlx5dr_action * actions[],int last_idx)658 static void dr_action_print_sequence(struct mlx5dr_domain *dmn,
659 struct mlx5dr_action *actions[],
660 int last_idx)
661 {
662 int i;
663
664 for (i = 0; i <= last_idx; i++)
665 mlx5dr_err(dmn, "< %s (%d) > ",
666 dr_action_id_to_str(actions[i]->action_type),
667 actions[i]->action_type);
668 }
669
dr_action_get_dest_fw_tbl_addr(struct mlx5dr_matcher * matcher,struct mlx5dr_action_dest_tbl * dest_tbl,bool is_rx_rule,u64 * final_icm_addr)670 static int dr_action_get_dest_fw_tbl_addr(struct mlx5dr_matcher *matcher,
671 struct mlx5dr_action_dest_tbl *dest_tbl,
672 bool is_rx_rule,
673 u64 *final_icm_addr)
674 {
675 struct mlx5dr_cmd_query_flow_table_details output;
676 struct mlx5dr_domain *dmn = matcher->tbl->dmn;
677 int ret;
678
679 if (!dest_tbl->fw_tbl.rx_icm_addr) {
680 ret = mlx5dr_cmd_query_flow_table(dmn->mdev,
681 dest_tbl->fw_tbl.type,
682 dest_tbl->fw_tbl.id,
683 &output);
684 if (ret) {
685 mlx5dr_err(dmn,
686 "Failed mlx5_cmd_query_flow_table ret: %d\n",
687 ret);
688 return ret;
689 }
690
691 dest_tbl->fw_tbl.tx_icm_addr = output.sw_owner_icm_root_1;
692 dest_tbl->fw_tbl.rx_icm_addr = output.sw_owner_icm_root_0;
693 }
694
695 *final_icm_addr = is_rx_rule ? dest_tbl->fw_tbl.rx_icm_addr :
696 dest_tbl->fw_tbl.tx_icm_addr;
697 return 0;
698 }
699
dr_action_get_dest_sw_tbl_addr(struct mlx5dr_matcher * matcher,struct mlx5dr_action_dest_tbl * dest_tbl,bool is_rx_rule,u64 * final_icm_addr)700 static int dr_action_get_dest_sw_tbl_addr(struct mlx5dr_matcher *matcher,
701 struct mlx5dr_action_dest_tbl *dest_tbl,
702 bool is_rx_rule,
703 u64 *final_icm_addr)
704 {
705 struct mlx5dr_domain *dmn = matcher->tbl->dmn;
706 struct mlx5dr_icm_chunk *chunk;
707
708 if (dest_tbl->tbl->dmn != dmn) {
709 mlx5dr_err(dmn,
710 "Destination table belongs to a different domain\n");
711 return -EINVAL;
712 }
713
714 if (dest_tbl->tbl->level <= matcher->tbl->level) {
715 mlx5_core_dbg_once(dmn->mdev,
716 "Connecting table to a lower/same level destination table\n");
717 mlx5dr_dbg(dmn,
718 "Connecting table at level %d to a destination table at level %d\n",
719 matcher->tbl->level,
720 dest_tbl->tbl->level);
721 }
722
723 chunk = is_rx_rule ? dest_tbl->tbl->rx.s_anchor->chunk :
724 dest_tbl->tbl->tx.s_anchor->chunk;
725
726 *final_icm_addr = mlx5dr_icm_pool_get_chunk_icm_addr(chunk);
727 return 0;
728 }
729
dr_action_get_dest_tbl_addr(struct mlx5dr_matcher * matcher,struct mlx5dr_action_dest_tbl * dest_tbl,bool is_rx_rule,u64 * final_icm_addr)730 static int dr_action_get_dest_tbl_addr(struct mlx5dr_matcher *matcher,
731 struct mlx5dr_action_dest_tbl *dest_tbl,
732 bool is_rx_rule,
733 u64 *final_icm_addr)
734 {
735 if (dest_tbl->is_fw_tbl)
736 return dr_action_get_dest_fw_tbl_addr(matcher,
737 dest_tbl,
738 is_rx_rule,
739 final_icm_addr);
740
741 return dr_action_get_dest_sw_tbl_addr(matcher,
742 dest_tbl,
743 is_rx_rule,
744 final_icm_addr);
745 }
746
747 #define WITH_VLAN_NUM_HW_ACTIONS 6
748
mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher * matcher,struct mlx5dr_matcher_rx_tx * nic_matcher,struct mlx5dr_action * actions[],u32 num_actions,u8 * ste_arr,u32 * new_hw_ste_arr_sz)749 int mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher *matcher,
750 struct mlx5dr_matcher_rx_tx *nic_matcher,
751 struct mlx5dr_action *actions[],
752 u32 num_actions,
753 u8 *ste_arr,
754 u32 *new_hw_ste_arr_sz)
755 {
756 struct mlx5dr_domain_rx_tx *nic_dmn = nic_matcher->nic_tbl->nic_dmn;
757 bool rx_rule = nic_dmn->type == DR_DOMAIN_NIC_TYPE_RX;
758 struct mlx5dr_domain *dmn = matcher->tbl->dmn;
759 u8 action_type_set[DR_ACTION_TYP_MAX] = {};
760 struct mlx5dr_ste_actions_attr attr = {};
761 struct mlx5dr_action *dest_action = NULL;
762 u32 state = DR_ACTION_STATE_NO_ACTION;
763 enum dr_action_domain action_domain;
764 bool recalc_cs_required = false;
765 u8 *last_ste;
766 int i, ret;
767
768 attr.gvmi = dmn->info.caps.gvmi;
769 attr.hit_gvmi = dmn->info.caps.gvmi;
770 attr.final_icm_addr = nic_dmn->default_icm_addr;
771 action_domain = dr_action_get_action_domain(dmn->type, nic_dmn->type);
772
773 for (i = 0; i < num_actions; i++) {
774 struct mlx5dr_action *action;
775 int max_actions_type = 1;
776 u32 action_type;
777
778 action = actions[i];
779 action_type = action->action_type;
780
781 switch (action_type) {
782 case DR_ACTION_TYP_DROP:
783 attr.final_icm_addr = nic_dmn->drop_icm_addr;
784 break;
785 case DR_ACTION_TYP_FT:
786 dest_action = action;
787 ret = dr_action_get_dest_tbl_addr(matcher, action->dest_tbl,
788 rx_rule, &attr.final_icm_addr);
789 if (ret)
790 return ret;
791 break;
792 case DR_ACTION_TYP_RANGE:
793 ret = dr_action_get_dest_tbl_addr(matcher,
794 action->range->hit_tbl_action->dest_tbl,
795 rx_rule, &attr.final_icm_addr);
796 if (ret)
797 return ret;
798
799 ret = dr_action_get_dest_tbl_addr(matcher,
800 action->range->miss_tbl_action->dest_tbl,
801 rx_rule, &attr.range.miss_icm_addr);
802 if (ret)
803 return ret;
804
805 attr.range.definer_id = action->range->definer_id;
806 attr.range.min = action->range->min;
807 attr.range.max = action->range->max;
808 break;
809 case DR_ACTION_TYP_QP:
810 mlx5dr_info(dmn, "Domain doesn't support QP\n");
811 return -EOPNOTSUPP;
812 case DR_ACTION_TYP_CTR:
813 attr.ctr_id = action->ctr->ctr_id +
814 action->ctr->offset;
815 break;
816 case DR_ACTION_TYP_TAG:
817 attr.flow_tag = action->flow_tag->flow_tag;
818 break;
819 case DR_ACTION_TYP_TNL_L2_TO_L2:
820 break;
821 case DR_ACTION_TYP_TNL_L3_TO_L2:
822 if (action->rewrite->ptrn && action->rewrite->arg) {
823 attr.decap_index = mlx5dr_arg_get_obj_id(action->rewrite->arg);
824 attr.decap_actions = action->rewrite->ptrn->num_of_actions;
825 attr.decap_pat_idx = action->rewrite->ptrn->index;
826 } else {
827 attr.decap_index = action->rewrite->index;
828 attr.decap_actions = action->rewrite->num_of_actions;
829 attr.decap_with_vlan =
830 attr.decap_actions == WITH_VLAN_NUM_HW_ACTIONS;
831 attr.decap_pat_idx = MLX5DR_INVALID_PATTERN_INDEX;
832 }
833 break;
834 case DR_ACTION_TYP_MODIFY_HDR:
835 if (action->rewrite->single_action_opt) {
836 attr.modify_actions = action->rewrite->num_of_actions;
837 attr.single_modify_action = action->rewrite->data;
838 } else {
839 if (action->rewrite->ptrn && action->rewrite->arg) {
840 attr.modify_index =
841 mlx5dr_arg_get_obj_id(action->rewrite->arg);
842 attr.modify_actions = action->rewrite->ptrn->num_of_actions;
843 attr.modify_pat_idx = action->rewrite->ptrn->index;
844 } else {
845 attr.modify_index = action->rewrite->index;
846 attr.modify_actions = action->rewrite->num_of_actions;
847 attr.modify_pat_idx = MLX5DR_INVALID_PATTERN_INDEX;
848 }
849 }
850 if (action->rewrite->modify_ttl)
851 dr_action_modify_ttl_adjust(dmn, &attr, rx_rule,
852 &recalc_cs_required);
853 break;
854 case DR_ACTION_TYP_L2_TO_TNL_L2:
855 case DR_ACTION_TYP_L2_TO_TNL_L3:
856 if (rx_rule &&
857 !(dmn->ste_ctx->actions_caps & DR_STE_CTX_ACTION_CAP_RX_ENCAP)) {
858 mlx5dr_info(dmn, "Device doesn't support Encap on RX\n");
859 return -EOPNOTSUPP;
860 }
861 attr.reformat.size = action->reformat->size;
862 attr.reformat.id = action->reformat->id;
863 break;
864 case DR_ACTION_TYP_SAMPLER:
865 attr.final_icm_addr = rx_rule ? action->sampler->rx_icm_addr :
866 action->sampler->tx_icm_addr;
867 break;
868 case DR_ACTION_TYP_VPORT:
869 attr.hit_gvmi = action->vport->caps->vhca_gvmi;
870 dest_action = action;
871 attr.final_icm_addr = rx_rule ?
872 action->vport->caps->icm_address_rx :
873 action->vport->caps->icm_address_tx;
874 break;
875 case DR_ACTION_TYP_POP_VLAN:
876 if (!rx_rule && !(dmn->ste_ctx->actions_caps &
877 DR_STE_CTX_ACTION_CAP_TX_POP)) {
878 mlx5dr_dbg(dmn, "Device doesn't support POP VLAN action on TX\n");
879 return -EOPNOTSUPP;
880 }
881
882 max_actions_type = MLX5DR_MAX_VLANS;
883 attr.vlans.count++;
884 break;
885 case DR_ACTION_TYP_PUSH_VLAN:
886 if (rx_rule && !(dmn->ste_ctx->actions_caps &
887 DR_STE_CTX_ACTION_CAP_RX_PUSH)) {
888 mlx5dr_dbg(dmn, "Device doesn't support PUSH VLAN action on RX\n");
889 return -EOPNOTSUPP;
890 }
891
892 max_actions_type = MLX5DR_MAX_VLANS;
893 if (attr.vlans.count == MLX5DR_MAX_VLANS) {
894 mlx5dr_dbg(dmn, "Max VLAN push/pop count exceeded\n");
895 return -EINVAL;
896 }
897
898 attr.vlans.headers[attr.vlans.count++] = action->push_vlan->vlan_hdr;
899 break;
900 case DR_ACTION_TYP_INSERT_HDR:
901 case DR_ACTION_TYP_REMOVE_HDR:
902 attr.reformat.size = action->reformat->size;
903 attr.reformat.id = action->reformat->id;
904 attr.reformat.param_0 = action->reformat->param_0;
905 attr.reformat.param_1 = action->reformat->param_1;
906 break;
907 case DR_ACTION_TYP_ASO_FLOW_METER:
908 attr.aso_flow_meter.obj_id = action->aso->obj_id;
909 attr.aso_flow_meter.offset = action->aso->offset;
910 attr.aso_flow_meter.dest_reg_id = action->aso->dest_reg_id;
911 attr.aso_flow_meter.init_color = action->aso->init_color;
912 break;
913 default:
914 mlx5dr_err(dmn, "Unsupported action type %d\n", action_type);
915 return -EINVAL;
916 }
917
918 /* Check action duplication */
919 if (++action_type_set[action_type] > max_actions_type) {
920 mlx5dr_err(dmn, "Action type %d supports only max %d time(s)\n",
921 action_type, max_actions_type);
922 return -EINVAL;
923 }
924
925 /* Check action state machine is valid */
926 if (dr_action_validate_and_get_next_state(action_domain,
927 action_type,
928 &state)) {
929 mlx5dr_err(dmn, "Invalid action (gvmi: %d, is_rx: %d) sequence provided:",
930 attr.gvmi, rx_rule);
931 dr_action_print_sequence(dmn, actions, i);
932 return -EOPNOTSUPP;
933 }
934 }
935
936 *new_hw_ste_arr_sz = nic_matcher->num_of_builders;
937 last_ste = ste_arr + DR_STE_SIZE * (nic_matcher->num_of_builders - 1);
938
939 if (recalc_cs_required && dest_action) {
940 ret = dr_action_handle_cs_recalc(dmn, dest_action, &attr.final_icm_addr);
941 if (ret) {
942 mlx5dr_err(dmn,
943 "Failed to handle checksum recalculation err %d\n",
944 ret);
945 return ret;
946 }
947 }
948
949 dr_actions_apply(dmn,
950 nic_dmn->type,
951 action_type_set,
952 last_ste,
953 &attr,
954 new_hw_ste_arr_sz);
955
956 return 0;
957 }
958
959 static unsigned int action_size[DR_ACTION_TYP_MAX] = {
960 [DR_ACTION_TYP_TNL_L2_TO_L2] = sizeof(struct mlx5dr_action_reformat),
961 [DR_ACTION_TYP_L2_TO_TNL_L2] = sizeof(struct mlx5dr_action_reformat),
962 [DR_ACTION_TYP_TNL_L3_TO_L2] = sizeof(struct mlx5dr_action_rewrite),
963 [DR_ACTION_TYP_L2_TO_TNL_L3] = sizeof(struct mlx5dr_action_reformat),
964 [DR_ACTION_TYP_FT] = sizeof(struct mlx5dr_action_dest_tbl),
965 [DR_ACTION_TYP_CTR] = sizeof(struct mlx5dr_action_ctr),
966 [DR_ACTION_TYP_TAG] = sizeof(struct mlx5dr_action_flow_tag),
967 [DR_ACTION_TYP_MODIFY_HDR] = sizeof(struct mlx5dr_action_rewrite),
968 [DR_ACTION_TYP_VPORT] = sizeof(struct mlx5dr_action_vport),
969 [DR_ACTION_TYP_PUSH_VLAN] = sizeof(struct mlx5dr_action_push_vlan),
970 [DR_ACTION_TYP_INSERT_HDR] = sizeof(struct mlx5dr_action_reformat),
971 [DR_ACTION_TYP_REMOVE_HDR] = sizeof(struct mlx5dr_action_reformat),
972 [DR_ACTION_TYP_SAMPLER] = sizeof(struct mlx5dr_action_sampler),
973 [DR_ACTION_TYP_ASO_FLOW_METER] = sizeof(struct mlx5dr_action_aso_flow_meter),
974 [DR_ACTION_TYP_RANGE] = sizeof(struct mlx5dr_action_range),
975 };
976
977 static struct mlx5dr_action *
dr_action_create_generic(enum mlx5dr_action_type action_type)978 dr_action_create_generic(enum mlx5dr_action_type action_type)
979 {
980 struct mlx5dr_action *action;
981 int extra_size;
982
983 if (action_type < DR_ACTION_TYP_MAX)
984 extra_size = action_size[action_type];
985 else
986 return NULL;
987
988 action = kzalloc(sizeof(*action) + extra_size, GFP_KERNEL);
989 if (!action)
990 return NULL;
991
992 action->action_type = action_type;
993 refcount_set(&action->refcount, 1);
994 action->data = action + 1;
995
996 return action;
997 }
998
mlx5dr_action_create_drop(void)999 struct mlx5dr_action *mlx5dr_action_create_drop(void)
1000 {
1001 return dr_action_create_generic(DR_ACTION_TYP_DROP);
1002 }
1003
1004 struct mlx5dr_action *
mlx5dr_action_create_dest_table_num(struct mlx5dr_domain * dmn,u32 table_num)1005 mlx5dr_action_create_dest_table_num(struct mlx5dr_domain *dmn, u32 table_num)
1006 {
1007 struct mlx5dr_action *action;
1008
1009 action = dr_action_create_generic(DR_ACTION_TYP_FT);
1010 if (!action)
1011 return NULL;
1012
1013 action->dest_tbl->is_fw_tbl = true;
1014 action->dest_tbl->fw_tbl.dmn = dmn;
1015 action->dest_tbl->fw_tbl.id = table_num;
1016 action->dest_tbl->fw_tbl.type = FS_FT_FDB;
1017 refcount_inc(&dmn->refcount);
1018
1019 return action;
1020 }
1021
1022 struct mlx5dr_action *
mlx5dr_action_create_dest_table(struct mlx5dr_table * tbl)1023 mlx5dr_action_create_dest_table(struct mlx5dr_table *tbl)
1024 {
1025 struct mlx5dr_action *action;
1026
1027 refcount_inc(&tbl->refcount);
1028
1029 action = dr_action_create_generic(DR_ACTION_TYP_FT);
1030 if (!action)
1031 goto dec_ref;
1032
1033 action->dest_tbl->tbl = tbl;
1034
1035 return action;
1036
1037 dec_ref:
1038 refcount_dec(&tbl->refcount);
1039 return NULL;
1040 }
1041
dr_action_range_definer_fill(u16 * format_id,u8 * dw_selectors,u8 * byte_selectors,u8 * match_mask)1042 static void dr_action_range_definer_fill(u16 *format_id,
1043 u8 *dw_selectors,
1044 u8 *byte_selectors,
1045 u8 *match_mask)
1046 {
1047 int i;
1048
1049 *format_id = MLX5_IFC_DEFINER_FORMAT_ID_SELECT;
1050
1051 dw_selectors[0] = MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN / 4;
1052
1053 for (i = 1; i < MLX5_IFC_DEFINER_DW_SELECTORS_NUM; i++)
1054 dw_selectors[i] = MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED;
1055
1056 for (i = 0; i < MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM; i++)
1057 byte_selectors[i] = MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED;
1058
1059 MLX5_SET(match_definer_match_mask, match_mask,
1060 match_dw_0, 0xffffUL << 16);
1061 }
1062
dr_action_create_range_definer(struct mlx5dr_action * action)1063 static int dr_action_create_range_definer(struct mlx5dr_action *action)
1064 {
1065 u8 match_mask[MLX5_FLD_SZ_BYTES(match_definer, match_mask)] = {};
1066 u8 byte_selectors[MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM] = {};
1067 u8 dw_selectors[MLX5_IFC_DEFINER_DW_SELECTORS_NUM] = {};
1068 struct mlx5dr_domain *dmn = action->range->dmn;
1069 u32 definer_id;
1070 u16 format_id;
1071 int ret;
1072
1073 dr_action_range_definer_fill(&format_id,
1074 dw_selectors,
1075 byte_selectors,
1076 match_mask);
1077
1078 ret = mlx5dr_definer_get(dmn, format_id,
1079 dw_selectors, byte_selectors,
1080 match_mask, &definer_id);
1081 if (ret)
1082 return ret;
1083
1084 action->range->definer_id = definer_id;
1085 return 0;
1086 }
1087
dr_action_destroy_range_definer(struct mlx5dr_action * action)1088 static void dr_action_destroy_range_definer(struct mlx5dr_action *action)
1089 {
1090 mlx5dr_definer_put(action->range->dmn, action->range->definer_id);
1091 }
1092
1093 struct mlx5dr_action *
mlx5dr_action_create_dest_match_range(struct mlx5dr_domain * dmn,u32 field,struct mlx5_flow_table * hit_ft,struct mlx5_flow_table * miss_ft,u32 min,u32 max)1094 mlx5dr_action_create_dest_match_range(struct mlx5dr_domain *dmn,
1095 u32 field,
1096 struct mlx5_flow_table *hit_ft,
1097 struct mlx5_flow_table *miss_ft,
1098 u32 min,
1099 u32 max)
1100 {
1101 struct mlx5dr_action *action;
1102 int ret;
1103
1104 if (!mlx5dr_supp_match_ranges(dmn->mdev)) {
1105 mlx5dr_dbg(dmn, "SELECT definer support is needed for match range\n");
1106 return NULL;
1107 }
1108
1109 if (field != MLX5_FLOW_DEST_RANGE_FIELD_PKT_LEN ||
1110 min > 0xffff || max > 0xffff) {
1111 mlx5dr_err(dmn, "Invalid match range parameters\n");
1112 return NULL;
1113 }
1114
1115 action = dr_action_create_generic(DR_ACTION_TYP_RANGE);
1116 if (!action)
1117 return NULL;
1118
1119 action->range->hit_tbl_action =
1120 mlx5dr_is_fw_table(hit_ft) ?
1121 mlx5dr_action_create_dest_flow_fw_table(dmn, hit_ft) :
1122 mlx5dr_action_create_dest_table(hit_ft->fs_dr_table.dr_table);
1123
1124 if (!action->range->hit_tbl_action)
1125 goto free_action;
1126
1127 action->range->miss_tbl_action =
1128 mlx5dr_is_fw_table(miss_ft) ?
1129 mlx5dr_action_create_dest_flow_fw_table(dmn, miss_ft) :
1130 mlx5dr_action_create_dest_table(miss_ft->fs_dr_table.dr_table);
1131
1132 if (!action->range->miss_tbl_action)
1133 goto free_hit_tbl_action;
1134
1135 action->range->min = min;
1136 action->range->max = max;
1137 action->range->dmn = dmn;
1138
1139 ret = dr_action_create_range_definer(action);
1140 if (ret)
1141 goto free_miss_tbl_action;
1142
1143 /* No need to increase refcount on domain for this action,
1144 * the hit/miss table actions will do it internally.
1145 */
1146
1147 return action;
1148
1149 free_miss_tbl_action:
1150 mlx5dr_action_destroy(action->range->miss_tbl_action);
1151 free_hit_tbl_action:
1152 mlx5dr_action_destroy(action->range->hit_tbl_action);
1153 free_action:
1154 kfree(action);
1155
1156 return NULL;
1157 }
1158
1159 struct mlx5dr_action *
mlx5dr_action_create_mult_dest_tbl(struct mlx5dr_domain * dmn,struct mlx5dr_action_dest * dests,u32 num_of_dests,bool ignore_flow_level,u32 flow_source)1160 mlx5dr_action_create_mult_dest_tbl(struct mlx5dr_domain *dmn,
1161 struct mlx5dr_action_dest *dests,
1162 u32 num_of_dests,
1163 bool ignore_flow_level,
1164 u32 flow_source)
1165 {
1166 struct mlx5dr_cmd_flow_destination_hw_info *hw_dests;
1167 struct mlx5dr_action **ref_actions;
1168 struct mlx5dr_action *action;
1169 bool reformat_req = false;
1170 u32 num_of_ref = 0;
1171 u32 ref_act_cnt;
1172 int ret;
1173 int i;
1174
1175 if (dmn->type != MLX5DR_DOMAIN_TYPE_FDB) {
1176 mlx5dr_err(dmn, "Multiple destination support is for FDB only\n");
1177 return NULL;
1178 }
1179
1180 hw_dests = kcalloc(num_of_dests, sizeof(*hw_dests), GFP_KERNEL);
1181 if (!hw_dests)
1182 return NULL;
1183
1184 if (unlikely(check_mul_overflow(num_of_dests, 2u, &ref_act_cnt)))
1185 goto free_hw_dests;
1186
1187 ref_actions = kcalloc(ref_act_cnt, sizeof(*ref_actions), GFP_KERNEL);
1188 if (!ref_actions)
1189 goto free_hw_dests;
1190
1191 for (i = 0; i < num_of_dests; i++) {
1192 struct mlx5dr_action *reformat_action = dests[i].reformat;
1193 struct mlx5dr_action *dest_action = dests[i].dest;
1194
1195 ref_actions[num_of_ref++] = dest_action;
1196
1197 switch (dest_action->action_type) {
1198 case DR_ACTION_TYP_VPORT:
1199 hw_dests[i].vport.flags = MLX5_FLOW_DEST_VPORT_VHCA_ID;
1200 hw_dests[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1201 hw_dests[i].vport.num = dest_action->vport->caps->num;
1202 hw_dests[i].vport.vhca_id = dest_action->vport->caps->vhca_gvmi;
1203 if (reformat_action) {
1204 reformat_req = true;
1205 hw_dests[i].vport.reformat_id =
1206 reformat_action->reformat->id;
1207 ref_actions[num_of_ref++] = reformat_action;
1208 hw_dests[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
1209 }
1210 break;
1211
1212 case DR_ACTION_TYP_FT:
1213 hw_dests[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1214 if (dest_action->dest_tbl->is_fw_tbl)
1215 hw_dests[i].ft_id = dest_action->dest_tbl->fw_tbl.id;
1216 else
1217 hw_dests[i].ft_id = dest_action->dest_tbl->tbl->table_id;
1218 break;
1219
1220 default:
1221 mlx5dr_dbg(dmn, "Invalid multiple destinations action\n");
1222 goto free_ref_actions;
1223 }
1224 }
1225
1226 action = dr_action_create_generic(DR_ACTION_TYP_FT);
1227 if (!action)
1228 goto free_ref_actions;
1229
1230 ret = mlx5dr_fw_create_md_tbl(dmn,
1231 hw_dests,
1232 num_of_dests,
1233 reformat_req,
1234 &action->dest_tbl->fw_tbl.id,
1235 &action->dest_tbl->fw_tbl.group_id,
1236 ignore_flow_level,
1237 flow_source);
1238 if (ret)
1239 goto free_action;
1240
1241 refcount_inc(&dmn->refcount);
1242
1243 for (i = 0; i < num_of_ref; i++)
1244 refcount_inc(&ref_actions[i]->refcount);
1245
1246 action->dest_tbl->is_fw_tbl = true;
1247 action->dest_tbl->fw_tbl.dmn = dmn;
1248 action->dest_tbl->fw_tbl.type = FS_FT_FDB;
1249 action->dest_tbl->fw_tbl.ref_actions = ref_actions;
1250 action->dest_tbl->fw_tbl.num_of_ref_actions = num_of_ref;
1251
1252 kfree(hw_dests);
1253
1254 return action;
1255
1256 free_action:
1257 kfree(action);
1258 free_ref_actions:
1259 kfree(ref_actions);
1260 free_hw_dests:
1261 kfree(hw_dests);
1262 return NULL;
1263 }
1264
1265 struct mlx5dr_action *
mlx5dr_action_create_dest_flow_fw_table(struct mlx5dr_domain * dmn,struct mlx5_flow_table * ft)1266 mlx5dr_action_create_dest_flow_fw_table(struct mlx5dr_domain *dmn,
1267 struct mlx5_flow_table *ft)
1268 {
1269 struct mlx5dr_action *action;
1270
1271 action = dr_action_create_generic(DR_ACTION_TYP_FT);
1272 if (!action)
1273 return NULL;
1274
1275 action->dest_tbl->is_fw_tbl = 1;
1276 action->dest_tbl->fw_tbl.type = ft->type;
1277 action->dest_tbl->fw_tbl.id = ft->id;
1278 action->dest_tbl->fw_tbl.dmn = dmn;
1279
1280 refcount_inc(&dmn->refcount);
1281
1282 return action;
1283 }
1284
1285 struct mlx5dr_action *
mlx5dr_action_create_flow_counter(u32 counter_id)1286 mlx5dr_action_create_flow_counter(u32 counter_id)
1287 {
1288 struct mlx5dr_action *action;
1289
1290 action = dr_action_create_generic(DR_ACTION_TYP_CTR);
1291 if (!action)
1292 return NULL;
1293
1294 action->ctr->ctr_id = counter_id;
1295
1296 return action;
1297 }
1298
mlx5dr_action_create_tag(u32 tag_value)1299 struct mlx5dr_action *mlx5dr_action_create_tag(u32 tag_value)
1300 {
1301 struct mlx5dr_action *action;
1302
1303 action = dr_action_create_generic(DR_ACTION_TYP_TAG);
1304 if (!action)
1305 return NULL;
1306
1307 action->flow_tag->flow_tag = tag_value & 0xffffff;
1308
1309 return action;
1310 }
1311
1312 struct mlx5dr_action *
mlx5dr_action_create_flow_sampler(struct mlx5dr_domain * dmn,u32 sampler_id)1313 mlx5dr_action_create_flow_sampler(struct mlx5dr_domain *dmn, u32 sampler_id)
1314 {
1315 struct mlx5dr_action *action;
1316 u64 icm_rx, icm_tx;
1317 int ret;
1318
1319 ret = mlx5dr_cmd_query_flow_sampler(dmn->mdev, sampler_id,
1320 &icm_rx, &icm_tx);
1321 if (ret)
1322 return NULL;
1323
1324 action = dr_action_create_generic(DR_ACTION_TYP_SAMPLER);
1325 if (!action)
1326 return NULL;
1327
1328 action->sampler->dmn = dmn;
1329 action->sampler->sampler_id = sampler_id;
1330 action->sampler->rx_icm_addr = icm_rx;
1331 action->sampler->tx_icm_addr = icm_tx;
1332
1333 refcount_inc(&dmn->refcount);
1334 return action;
1335 }
1336
1337 static int
dr_action_verify_reformat_params(enum mlx5dr_action_type reformat_type,struct mlx5dr_domain * dmn,u8 reformat_param_0,u8 reformat_param_1,size_t data_sz,void * data)1338 dr_action_verify_reformat_params(enum mlx5dr_action_type reformat_type,
1339 struct mlx5dr_domain *dmn,
1340 u8 reformat_param_0,
1341 u8 reformat_param_1,
1342 size_t data_sz,
1343 void *data)
1344 {
1345 if (reformat_type == DR_ACTION_TYP_INSERT_HDR) {
1346 if ((!data && data_sz) || (data && !data_sz) ||
1347 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_insert_size) < data_sz ||
1348 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_insert_offset) < reformat_param_1) {
1349 mlx5dr_dbg(dmn, "Invalid reformat parameters for INSERT_HDR\n");
1350 goto out_err;
1351 }
1352 } else if (reformat_type == DR_ACTION_TYP_REMOVE_HDR) {
1353 if (data ||
1354 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_remove_size) < data_sz ||
1355 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_remove_offset) < reformat_param_1) {
1356 mlx5dr_dbg(dmn, "Invalid reformat parameters for REMOVE_HDR\n");
1357 goto out_err;
1358 }
1359 } else if (reformat_param_0 || reformat_param_1 ||
1360 reformat_type > DR_ACTION_TYP_REMOVE_HDR) {
1361 mlx5dr_dbg(dmn, "Invalid reformat parameters\n");
1362 goto out_err;
1363 }
1364
1365 if (dmn->type == MLX5DR_DOMAIN_TYPE_FDB)
1366 return 0;
1367
1368 if (dmn->type == MLX5DR_DOMAIN_TYPE_NIC_RX) {
1369 if (reformat_type != DR_ACTION_TYP_TNL_L2_TO_L2 &&
1370 reformat_type != DR_ACTION_TYP_TNL_L3_TO_L2) {
1371 mlx5dr_dbg(dmn, "Action reformat type not support on RX domain\n");
1372 goto out_err;
1373 }
1374 } else if (dmn->type == MLX5DR_DOMAIN_TYPE_NIC_TX) {
1375 if (reformat_type != DR_ACTION_TYP_L2_TO_TNL_L2 &&
1376 reformat_type != DR_ACTION_TYP_L2_TO_TNL_L3) {
1377 mlx5dr_dbg(dmn, "Action reformat type not support on TX domain\n");
1378 goto out_err;
1379 }
1380 }
1381
1382 return 0;
1383
1384 out_err:
1385 return -EINVAL;
1386 }
1387
1388 static int
dr_action_create_reformat_action(struct mlx5dr_domain * dmn,u8 reformat_param_0,u8 reformat_param_1,size_t data_sz,void * data,struct mlx5dr_action * action)1389 dr_action_create_reformat_action(struct mlx5dr_domain *dmn,
1390 u8 reformat_param_0, u8 reformat_param_1,
1391 size_t data_sz, void *data,
1392 struct mlx5dr_action *action)
1393 {
1394 u32 reformat_id;
1395 int ret;
1396
1397 switch (action->action_type) {
1398 case DR_ACTION_TYP_L2_TO_TNL_L2:
1399 case DR_ACTION_TYP_L2_TO_TNL_L3:
1400 {
1401 enum mlx5_reformat_ctx_type rt;
1402
1403 if (action->action_type == DR_ACTION_TYP_L2_TO_TNL_L2)
1404 rt = MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL;
1405 else
1406 rt = MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
1407
1408 ret = mlx5dr_cmd_create_reformat_ctx(dmn->mdev, rt, 0, 0,
1409 data_sz, data,
1410 &reformat_id);
1411 if (ret)
1412 return ret;
1413
1414 action->reformat->id = reformat_id;
1415 action->reformat->size = data_sz;
1416 return 0;
1417 }
1418 case DR_ACTION_TYP_TNL_L2_TO_L2:
1419 {
1420 return 0;
1421 }
1422 case DR_ACTION_TYP_TNL_L3_TO_L2:
1423 {
1424 u8 *hw_actions;
1425
1426 hw_actions = kzalloc(DR_ACTION_CACHE_LINE_SIZE, GFP_KERNEL);
1427 if (!hw_actions)
1428 return -ENOMEM;
1429
1430 ret = mlx5dr_ste_set_action_decap_l3_list(dmn->ste_ctx,
1431 data, data_sz,
1432 hw_actions,
1433 DR_ACTION_CACHE_LINE_SIZE,
1434 &action->rewrite->num_of_actions);
1435 if (ret) {
1436 mlx5dr_dbg(dmn, "Failed creating decap l3 action list\n");
1437 kfree(hw_actions);
1438 return ret;
1439 }
1440
1441 action->rewrite->data = hw_actions;
1442 action->rewrite->dmn = dmn;
1443
1444 ret = mlx5dr_ste_alloc_modify_hdr(action);
1445 if (ret) {
1446 mlx5dr_dbg(dmn, "Failed preparing reformat data\n");
1447 kfree(hw_actions);
1448 return ret;
1449 }
1450 return 0;
1451 }
1452 case DR_ACTION_TYP_INSERT_HDR:
1453 ret = mlx5dr_cmd_create_reformat_ctx(dmn->mdev,
1454 MLX5_REFORMAT_TYPE_INSERT_HDR,
1455 reformat_param_0,
1456 reformat_param_1,
1457 data_sz, data,
1458 &reformat_id);
1459 if (ret)
1460 return ret;
1461
1462 action->reformat->id = reformat_id;
1463 action->reformat->size = data_sz;
1464 action->reformat->param_0 = reformat_param_0;
1465 action->reformat->param_1 = reformat_param_1;
1466 return 0;
1467 case DR_ACTION_TYP_REMOVE_HDR:
1468 action->reformat->id = 0;
1469 action->reformat->size = data_sz;
1470 action->reformat->param_0 = reformat_param_0;
1471 action->reformat->param_1 = reformat_param_1;
1472 return 0;
1473 default:
1474 mlx5dr_info(dmn, "Reformat type is not supported %d\n", action->action_type);
1475 return -EINVAL;
1476 }
1477 }
1478
1479 #define CVLAN_ETHERTYPE 0x8100
1480 #define SVLAN_ETHERTYPE 0x88a8
1481
mlx5dr_action_create_pop_vlan(void)1482 struct mlx5dr_action *mlx5dr_action_create_pop_vlan(void)
1483 {
1484 return dr_action_create_generic(DR_ACTION_TYP_POP_VLAN);
1485 }
1486
mlx5dr_action_create_push_vlan(struct mlx5dr_domain * dmn,__be32 vlan_hdr)1487 struct mlx5dr_action *mlx5dr_action_create_push_vlan(struct mlx5dr_domain *dmn,
1488 __be32 vlan_hdr)
1489 {
1490 u32 vlan_hdr_h = ntohl(vlan_hdr);
1491 u16 ethertype = vlan_hdr_h >> 16;
1492 struct mlx5dr_action *action;
1493
1494 if (ethertype != SVLAN_ETHERTYPE && ethertype != CVLAN_ETHERTYPE) {
1495 mlx5dr_dbg(dmn, "Invalid vlan ethertype\n");
1496 return NULL;
1497 }
1498
1499 action = dr_action_create_generic(DR_ACTION_TYP_PUSH_VLAN);
1500 if (!action)
1501 return NULL;
1502
1503 action->push_vlan->vlan_hdr = vlan_hdr_h;
1504 return action;
1505 }
1506
1507 struct mlx5dr_action *
mlx5dr_action_create_packet_reformat(struct mlx5dr_domain * dmn,enum mlx5dr_action_reformat_type reformat_type,u8 reformat_param_0,u8 reformat_param_1,size_t data_sz,void * data)1508 mlx5dr_action_create_packet_reformat(struct mlx5dr_domain *dmn,
1509 enum mlx5dr_action_reformat_type reformat_type,
1510 u8 reformat_param_0,
1511 u8 reformat_param_1,
1512 size_t data_sz,
1513 void *data)
1514 {
1515 enum mlx5dr_action_type action_type;
1516 struct mlx5dr_action *action;
1517 int ret;
1518
1519 refcount_inc(&dmn->refcount);
1520
1521 /* General checks */
1522 ret = dr_action_reformat_to_action_type(reformat_type, &action_type);
1523 if (ret) {
1524 mlx5dr_dbg(dmn, "Invalid reformat_type provided\n");
1525 goto dec_ref;
1526 }
1527
1528 ret = dr_action_verify_reformat_params(action_type, dmn,
1529 reformat_param_0, reformat_param_1,
1530 data_sz, data);
1531 if (ret)
1532 goto dec_ref;
1533
1534 action = dr_action_create_generic(action_type);
1535 if (!action)
1536 goto dec_ref;
1537
1538 action->reformat->dmn = dmn;
1539
1540 ret = dr_action_create_reformat_action(dmn,
1541 reformat_param_0,
1542 reformat_param_1,
1543 data_sz,
1544 data,
1545 action);
1546 if (ret) {
1547 mlx5dr_dbg(dmn, "Failed creating reformat action %d\n", ret);
1548 goto free_action;
1549 }
1550
1551 return action;
1552
1553 free_action:
1554 kfree(action);
1555 dec_ref:
1556 refcount_dec(&dmn->refcount);
1557 return NULL;
1558 }
1559
1560 static int
dr_action_modify_sw_to_hw_add(struct mlx5dr_domain * dmn,__be64 * sw_action,__be64 * hw_action,const struct mlx5dr_ste_action_modify_field ** ret_hw_info)1561 dr_action_modify_sw_to_hw_add(struct mlx5dr_domain *dmn,
1562 __be64 *sw_action,
1563 __be64 *hw_action,
1564 const struct mlx5dr_ste_action_modify_field **ret_hw_info)
1565 {
1566 const struct mlx5dr_ste_action_modify_field *hw_action_info;
1567 u8 max_length;
1568 u16 sw_field;
1569 u32 data;
1570
1571 /* Get SW modify action data */
1572 sw_field = MLX5_GET(set_action_in, sw_action, field);
1573 data = MLX5_GET(set_action_in, sw_action, data);
1574
1575 /* Convert SW data to HW modify action format */
1576 hw_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, sw_field);
1577 if (!hw_action_info) {
1578 mlx5dr_dbg(dmn, "Modify add action invalid field given\n");
1579 return -EINVAL;
1580 }
1581
1582 max_length = hw_action_info->end - hw_action_info->start + 1;
1583
1584 mlx5dr_ste_set_action_add(dmn->ste_ctx,
1585 hw_action,
1586 hw_action_info->hw_field,
1587 hw_action_info->start,
1588 max_length,
1589 data);
1590
1591 *ret_hw_info = hw_action_info;
1592
1593 return 0;
1594 }
1595
1596 static int
dr_action_modify_sw_to_hw_set(struct mlx5dr_domain * dmn,__be64 * sw_action,__be64 * hw_action,const struct mlx5dr_ste_action_modify_field ** ret_hw_info)1597 dr_action_modify_sw_to_hw_set(struct mlx5dr_domain *dmn,
1598 __be64 *sw_action,
1599 __be64 *hw_action,
1600 const struct mlx5dr_ste_action_modify_field **ret_hw_info)
1601 {
1602 const struct mlx5dr_ste_action_modify_field *hw_action_info;
1603 u8 offset, length, max_length;
1604 u16 sw_field;
1605 u32 data;
1606
1607 /* Get SW modify action data */
1608 length = MLX5_GET(set_action_in, sw_action, length);
1609 offset = MLX5_GET(set_action_in, sw_action, offset);
1610 sw_field = MLX5_GET(set_action_in, sw_action, field);
1611 data = MLX5_GET(set_action_in, sw_action, data);
1612
1613 /* Convert SW data to HW modify action format */
1614 hw_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, sw_field);
1615 if (!hw_action_info) {
1616 mlx5dr_dbg(dmn, "Modify set action invalid field given\n");
1617 return -EINVAL;
1618 }
1619
1620 /* PRM defines that length zero specific length of 32bits */
1621 length = length ? length : 32;
1622
1623 max_length = hw_action_info->end - hw_action_info->start + 1;
1624
1625 if (length + offset > max_length) {
1626 mlx5dr_dbg(dmn, "Modify action length + offset exceeds limit\n");
1627 return -EINVAL;
1628 }
1629
1630 mlx5dr_ste_set_action_set(dmn->ste_ctx,
1631 hw_action,
1632 hw_action_info->hw_field,
1633 hw_action_info->start + offset,
1634 length,
1635 data);
1636
1637 *ret_hw_info = hw_action_info;
1638
1639 return 0;
1640 }
1641
1642 static int
dr_action_modify_sw_to_hw_copy(struct mlx5dr_domain * dmn,__be64 * sw_action,__be64 * hw_action,const struct mlx5dr_ste_action_modify_field ** ret_dst_hw_info,const struct mlx5dr_ste_action_modify_field ** ret_src_hw_info)1643 dr_action_modify_sw_to_hw_copy(struct mlx5dr_domain *dmn,
1644 __be64 *sw_action,
1645 __be64 *hw_action,
1646 const struct mlx5dr_ste_action_modify_field **ret_dst_hw_info,
1647 const struct mlx5dr_ste_action_modify_field **ret_src_hw_info)
1648 {
1649 u8 src_offset, dst_offset, src_max_length, dst_max_length, length;
1650 const struct mlx5dr_ste_action_modify_field *hw_dst_action_info;
1651 const struct mlx5dr_ste_action_modify_field *hw_src_action_info;
1652 u16 src_field, dst_field;
1653
1654 /* Get SW modify action data */
1655 src_field = MLX5_GET(copy_action_in, sw_action, src_field);
1656 dst_field = MLX5_GET(copy_action_in, sw_action, dst_field);
1657 src_offset = MLX5_GET(copy_action_in, sw_action, src_offset);
1658 dst_offset = MLX5_GET(copy_action_in, sw_action, dst_offset);
1659 length = MLX5_GET(copy_action_in, sw_action, length);
1660
1661 /* Convert SW data to HW modify action format */
1662 hw_src_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, src_field);
1663 hw_dst_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, dst_field);
1664 if (!hw_src_action_info || !hw_dst_action_info) {
1665 mlx5dr_dbg(dmn, "Modify copy action invalid field given\n");
1666 return -EINVAL;
1667 }
1668
1669 /* PRM defines that length zero specific length of 32bits */
1670 length = length ? length : 32;
1671
1672 src_max_length = hw_src_action_info->end -
1673 hw_src_action_info->start + 1;
1674 dst_max_length = hw_dst_action_info->end -
1675 hw_dst_action_info->start + 1;
1676
1677 if (length + src_offset > src_max_length ||
1678 length + dst_offset > dst_max_length) {
1679 mlx5dr_dbg(dmn, "Modify action length + offset exceeds limit\n");
1680 return -EINVAL;
1681 }
1682
1683 mlx5dr_ste_set_action_copy(dmn->ste_ctx,
1684 hw_action,
1685 hw_dst_action_info->hw_field,
1686 hw_dst_action_info->start + dst_offset,
1687 length,
1688 hw_src_action_info->hw_field,
1689 hw_src_action_info->start + src_offset);
1690
1691 *ret_dst_hw_info = hw_dst_action_info;
1692 *ret_src_hw_info = hw_src_action_info;
1693
1694 return 0;
1695 }
1696
1697 static int
dr_action_modify_sw_to_hw(struct mlx5dr_domain * dmn,__be64 * sw_action,__be64 * hw_action,const struct mlx5dr_ste_action_modify_field ** ret_dst_hw_info,const struct mlx5dr_ste_action_modify_field ** ret_src_hw_info)1698 dr_action_modify_sw_to_hw(struct mlx5dr_domain *dmn,
1699 __be64 *sw_action,
1700 __be64 *hw_action,
1701 const struct mlx5dr_ste_action_modify_field **ret_dst_hw_info,
1702 const struct mlx5dr_ste_action_modify_field **ret_src_hw_info)
1703 {
1704 u8 action;
1705 int ret;
1706
1707 *hw_action = 0;
1708 *ret_src_hw_info = NULL;
1709
1710 /* Get SW modify action type */
1711 action = MLX5_GET(set_action_in, sw_action, action_type);
1712
1713 switch (action) {
1714 case MLX5_ACTION_TYPE_SET:
1715 ret = dr_action_modify_sw_to_hw_set(dmn, sw_action,
1716 hw_action,
1717 ret_dst_hw_info);
1718 break;
1719
1720 case MLX5_ACTION_TYPE_ADD:
1721 ret = dr_action_modify_sw_to_hw_add(dmn, sw_action,
1722 hw_action,
1723 ret_dst_hw_info);
1724 break;
1725
1726 case MLX5_ACTION_TYPE_COPY:
1727 ret = dr_action_modify_sw_to_hw_copy(dmn, sw_action,
1728 hw_action,
1729 ret_dst_hw_info,
1730 ret_src_hw_info);
1731 break;
1732
1733 default:
1734 mlx5dr_info(dmn, "Unsupported action_type for modify action\n");
1735 ret = -EOPNOTSUPP;
1736 }
1737
1738 return ret;
1739 }
1740
1741 static int
dr_action_modify_check_set_field_limitation(struct mlx5dr_action * action,const __be64 * sw_action)1742 dr_action_modify_check_set_field_limitation(struct mlx5dr_action *action,
1743 const __be64 *sw_action)
1744 {
1745 u16 sw_field = MLX5_GET(set_action_in, sw_action, field);
1746 struct mlx5dr_domain *dmn = action->rewrite->dmn;
1747
1748 if (sw_field == MLX5_ACTION_IN_FIELD_METADATA_REG_A) {
1749 action->rewrite->allow_rx = 0;
1750 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_TX) {
1751 mlx5dr_dbg(dmn, "Unsupported field %d for RX/FDB set action\n",
1752 sw_field);
1753 return -EINVAL;
1754 }
1755 } else if (sw_field == MLX5_ACTION_IN_FIELD_METADATA_REG_B) {
1756 action->rewrite->allow_tx = 0;
1757 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_RX) {
1758 mlx5dr_dbg(dmn, "Unsupported field %d for TX/FDB set action\n",
1759 sw_field);
1760 return -EINVAL;
1761 }
1762 }
1763
1764 if (!action->rewrite->allow_rx && !action->rewrite->allow_tx) {
1765 mlx5dr_dbg(dmn, "Modify SET actions not supported on both RX and TX\n");
1766 return -EINVAL;
1767 }
1768
1769 return 0;
1770 }
1771
1772 static int
dr_action_modify_check_add_field_limitation(struct mlx5dr_action * action,const __be64 * sw_action)1773 dr_action_modify_check_add_field_limitation(struct mlx5dr_action *action,
1774 const __be64 *sw_action)
1775 {
1776 u16 sw_field = MLX5_GET(set_action_in, sw_action, field);
1777 struct mlx5dr_domain *dmn = action->rewrite->dmn;
1778
1779 if (sw_field != MLX5_ACTION_IN_FIELD_OUT_IP_TTL &&
1780 sw_field != MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT &&
1781 sw_field != MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM &&
1782 sw_field != MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM) {
1783 mlx5dr_dbg(dmn, "Unsupported field %d for add action\n",
1784 sw_field);
1785 return -EINVAL;
1786 }
1787
1788 return 0;
1789 }
1790
1791 static int
dr_action_modify_check_copy_field_limitation(struct mlx5dr_action * action,const __be64 * sw_action)1792 dr_action_modify_check_copy_field_limitation(struct mlx5dr_action *action,
1793 const __be64 *sw_action)
1794 {
1795 struct mlx5dr_domain *dmn = action->rewrite->dmn;
1796 u16 sw_fields[2];
1797 int i;
1798
1799 sw_fields[0] = MLX5_GET(copy_action_in, sw_action, src_field);
1800 sw_fields[1] = MLX5_GET(copy_action_in, sw_action, dst_field);
1801
1802 for (i = 0; i < 2; i++) {
1803 if (sw_fields[i] == MLX5_ACTION_IN_FIELD_METADATA_REG_A) {
1804 action->rewrite->allow_rx = 0;
1805 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_TX) {
1806 mlx5dr_dbg(dmn, "Unsupported field %d for RX/FDB set action\n",
1807 sw_fields[i]);
1808 return -EINVAL;
1809 }
1810 } else if (sw_fields[i] == MLX5_ACTION_IN_FIELD_METADATA_REG_B) {
1811 action->rewrite->allow_tx = 0;
1812 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_RX) {
1813 mlx5dr_dbg(dmn, "Unsupported field %d for TX/FDB set action\n",
1814 sw_fields[i]);
1815 return -EINVAL;
1816 }
1817 }
1818 }
1819
1820 if (!action->rewrite->allow_rx && !action->rewrite->allow_tx) {
1821 mlx5dr_dbg(dmn, "Modify copy actions not supported on both RX and TX\n");
1822 return -EINVAL;
1823 }
1824
1825 return 0;
1826 }
1827
1828 static int
dr_action_modify_check_field_limitation(struct mlx5dr_action * action,const __be64 * sw_action)1829 dr_action_modify_check_field_limitation(struct mlx5dr_action *action,
1830 const __be64 *sw_action)
1831 {
1832 struct mlx5dr_domain *dmn = action->rewrite->dmn;
1833 u8 action_type;
1834 int ret;
1835
1836 action_type = MLX5_GET(set_action_in, sw_action, action_type);
1837
1838 switch (action_type) {
1839 case MLX5_ACTION_TYPE_SET:
1840 ret = dr_action_modify_check_set_field_limitation(action,
1841 sw_action);
1842 break;
1843
1844 case MLX5_ACTION_TYPE_ADD:
1845 ret = dr_action_modify_check_add_field_limitation(action,
1846 sw_action);
1847 break;
1848
1849 case MLX5_ACTION_TYPE_COPY:
1850 ret = dr_action_modify_check_copy_field_limitation(action,
1851 sw_action);
1852 break;
1853
1854 default:
1855 mlx5dr_info(dmn, "Unsupported action %d modify action\n",
1856 action_type);
1857 ret = -EOPNOTSUPP;
1858 }
1859
1860 return ret;
1861 }
1862
1863 static bool
dr_action_modify_check_is_ttl_modify(const void * sw_action)1864 dr_action_modify_check_is_ttl_modify(const void *sw_action)
1865 {
1866 u16 sw_field = MLX5_GET(set_action_in, sw_action, field);
1867
1868 return sw_field == MLX5_ACTION_IN_FIELD_OUT_IP_TTL;
1869 }
1870
dr_actions_convert_modify_header(struct mlx5dr_action * action,u32 max_hw_actions,u32 num_sw_actions,__be64 sw_actions[],__be64 hw_actions[],u32 * num_hw_actions,bool * modify_ttl)1871 static int dr_actions_convert_modify_header(struct mlx5dr_action *action,
1872 u32 max_hw_actions,
1873 u32 num_sw_actions,
1874 __be64 sw_actions[],
1875 __be64 hw_actions[],
1876 u32 *num_hw_actions,
1877 bool *modify_ttl)
1878 {
1879 const struct mlx5dr_ste_action_modify_field *hw_dst_action_info;
1880 const struct mlx5dr_ste_action_modify_field *hw_src_action_info;
1881 struct mlx5dr_domain *dmn = action->rewrite->dmn;
1882 __be64 *modify_ttl_sw_action = NULL;
1883 int ret, i, hw_idx = 0;
1884 __be64 *sw_action;
1885 __be64 hw_action;
1886 u16 hw_field = 0;
1887 u32 l3_type = 0;
1888 u32 l4_type = 0;
1889
1890 *modify_ttl = false;
1891
1892 action->rewrite->allow_rx = 1;
1893 action->rewrite->allow_tx = 1;
1894
1895 for (i = 0; i < num_sw_actions || modify_ttl_sw_action; i++) {
1896 /* modify TTL is handled separately, as a last action */
1897 if (i == num_sw_actions) {
1898 sw_action = modify_ttl_sw_action;
1899 modify_ttl_sw_action = NULL;
1900 } else {
1901 sw_action = &sw_actions[i];
1902 }
1903
1904 ret = dr_action_modify_check_field_limitation(action,
1905 sw_action);
1906 if (ret)
1907 return ret;
1908
1909 if (!(*modify_ttl) &&
1910 dr_action_modify_check_is_ttl_modify(sw_action)) {
1911 modify_ttl_sw_action = sw_action;
1912 *modify_ttl = true;
1913 continue;
1914 }
1915
1916 /* Convert SW action to HW action */
1917 ret = dr_action_modify_sw_to_hw(dmn,
1918 sw_action,
1919 &hw_action,
1920 &hw_dst_action_info,
1921 &hw_src_action_info);
1922 if (ret)
1923 return ret;
1924
1925 /* Due to a HW limitation we cannot modify 2 different L3 types */
1926 if (l3_type && hw_dst_action_info->l3_type &&
1927 hw_dst_action_info->l3_type != l3_type) {
1928 mlx5dr_dbg(dmn, "Action list can't support two different L3 types\n");
1929 return -EINVAL;
1930 }
1931 if (hw_dst_action_info->l3_type)
1932 l3_type = hw_dst_action_info->l3_type;
1933
1934 /* Due to a HW limitation we cannot modify two different L4 types */
1935 if (l4_type && hw_dst_action_info->l4_type &&
1936 hw_dst_action_info->l4_type != l4_type) {
1937 mlx5dr_dbg(dmn, "Action list can't support two different L4 types\n");
1938 return -EINVAL;
1939 }
1940 if (hw_dst_action_info->l4_type)
1941 l4_type = hw_dst_action_info->l4_type;
1942
1943 /* HW reads and executes two actions at once this means we
1944 * need to create a gap if two actions access the same field
1945 */
1946 if ((hw_idx % 2) && (hw_field == hw_dst_action_info->hw_field ||
1947 (hw_src_action_info &&
1948 hw_field == hw_src_action_info->hw_field))) {
1949 /* Check if after gap insertion the total number of HW
1950 * modify actions doesn't exceeds the limit
1951 */
1952 hw_idx++;
1953 if (hw_idx >= max_hw_actions) {
1954 mlx5dr_dbg(dmn, "Modify header action number exceeds HW limit\n");
1955 return -EINVAL;
1956 }
1957 }
1958 hw_field = hw_dst_action_info->hw_field;
1959
1960 hw_actions[hw_idx] = hw_action;
1961 hw_idx++;
1962 }
1963
1964 /* if the resulting HW actions list is empty, add NOP action */
1965 if (!hw_idx)
1966 hw_idx++;
1967
1968 *num_hw_actions = hw_idx;
1969
1970 return 0;
1971 }
1972
dr_action_create_modify_action(struct mlx5dr_domain * dmn,size_t actions_sz,__be64 actions[],struct mlx5dr_action * action)1973 static int dr_action_create_modify_action(struct mlx5dr_domain *dmn,
1974 size_t actions_sz,
1975 __be64 actions[],
1976 struct mlx5dr_action *action)
1977 {
1978 u32 max_hw_actions;
1979 u32 num_hw_actions;
1980 u32 num_sw_actions;
1981 __be64 *hw_actions;
1982 bool modify_ttl;
1983 int ret;
1984
1985 num_sw_actions = actions_sz / DR_MODIFY_ACTION_SIZE;
1986 max_hw_actions = mlx5dr_icm_pool_chunk_size_to_entries(DR_CHUNK_SIZE_16);
1987
1988 if (num_sw_actions > max_hw_actions) {
1989 mlx5dr_dbg(dmn, "Max number of actions %d exceeds limit %d\n",
1990 num_sw_actions, max_hw_actions);
1991 return -EINVAL;
1992 }
1993
1994 hw_actions = kcalloc(1, max_hw_actions * DR_MODIFY_ACTION_SIZE, GFP_KERNEL);
1995 if (!hw_actions)
1996 return -ENOMEM;
1997
1998 ret = dr_actions_convert_modify_header(action,
1999 max_hw_actions,
2000 num_sw_actions,
2001 actions,
2002 hw_actions,
2003 &num_hw_actions,
2004 &modify_ttl);
2005 if (ret)
2006 goto free_hw_actions;
2007
2008 action->rewrite->modify_ttl = modify_ttl;
2009 action->rewrite->data = (u8 *)hw_actions;
2010 action->rewrite->num_of_actions = num_hw_actions;
2011
2012 if (num_hw_actions == 1 &&
2013 dmn->info.caps.sw_format_ver >= MLX5_STEERING_FORMAT_CONNECTX_6DX) {
2014 action->rewrite->single_action_opt = true;
2015 } else {
2016 action->rewrite->single_action_opt = false;
2017 ret = mlx5dr_ste_alloc_modify_hdr(action);
2018 if (ret)
2019 goto free_hw_actions;
2020 }
2021
2022 return 0;
2023
2024 free_hw_actions:
2025 kfree(hw_actions);
2026 return ret;
2027 }
2028
2029 struct mlx5dr_action *
mlx5dr_action_create_modify_header(struct mlx5dr_domain * dmn,u32 flags,size_t actions_sz,__be64 actions[])2030 mlx5dr_action_create_modify_header(struct mlx5dr_domain *dmn,
2031 u32 flags,
2032 size_t actions_sz,
2033 __be64 actions[])
2034 {
2035 struct mlx5dr_action *action;
2036 int ret = 0;
2037
2038 refcount_inc(&dmn->refcount);
2039
2040 if (actions_sz % DR_MODIFY_ACTION_SIZE) {
2041 mlx5dr_dbg(dmn, "Invalid modify actions size provided\n");
2042 goto dec_ref;
2043 }
2044
2045 action = dr_action_create_generic(DR_ACTION_TYP_MODIFY_HDR);
2046 if (!action)
2047 goto dec_ref;
2048
2049 action->rewrite->dmn = dmn;
2050
2051 ret = dr_action_create_modify_action(dmn,
2052 actions_sz,
2053 actions,
2054 action);
2055 if (ret) {
2056 mlx5dr_dbg(dmn, "Failed creating modify header action %d\n", ret);
2057 goto free_action;
2058 }
2059
2060 return action;
2061
2062 free_action:
2063 kfree(action);
2064 dec_ref:
2065 refcount_dec(&dmn->refcount);
2066 return NULL;
2067 }
2068
2069 struct mlx5dr_action *
mlx5dr_action_create_dest_vport(struct mlx5dr_domain * dmn,u16 vport,u8 vhca_id_valid,u16 vhca_id)2070 mlx5dr_action_create_dest_vport(struct mlx5dr_domain *dmn,
2071 u16 vport, u8 vhca_id_valid,
2072 u16 vhca_id)
2073 {
2074 struct mlx5dr_cmd_vport_cap *vport_cap;
2075 struct mlx5dr_domain *vport_dmn;
2076 struct mlx5dr_action *action;
2077 u8 peer_vport;
2078
2079 peer_vport = vhca_id_valid && mlx5_core_is_pf(dmn->mdev) &&
2080 (vhca_id != dmn->info.caps.gvmi);
2081 vport_dmn = peer_vport ? xa_load(&dmn->peer_dmn_xa, vhca_id) : dmn;
2082 if (!vport_dmn) {
2083 mlx5dr_dbg(dmn, "No peer vport domain for given vhca_id\n");
2084 return NULL;
2085 }
2086
2087 if (vport_dmn->type != MLX5DR_DOMAIN_TYPE_FDB) {
2088 mlx5dr_dbg(dmn, "Domain doesn't support vport actions\n");
2089 return NULL;
2090 }
2091
2092 vport_cap = mlx5dr_domain_get_vport_cap(vport_dmn, vport);
2093 if (!vport_cap) {
2094 mlx5dr_err(dmn,
2095 "Failed to get vport 0x%x caps - vport is disabled or invalid\n",
2096 vport);
2097 return NULL;
2098 }
2099
2100 action = dr_action_create_generic(DR_ACTION_TYP_VPORT);
2101 if (!action)
2102 return NULL;
2103
2104 action->vport->dmn = vport_dmn;
2105 action->vport->caps = vport_cap;
2106
2107 return action;
2108 }
2109
2110 struct mlx5dr_action *
mlx5dr_action_create_aso(struct mlx5dr_domain * dmn,u32 obj_id,u8 dest_reg_id,u8 aso_type,u8 init_color,u8 meter_id)2111 mlx5dr_action_create_aso(struct mlx5dr_domain *dmn, u32 obj_id,
2112 u8 dest_reg_id, u8 aso_type,
2113 u8 init_color, u8 meter_id)
2114 {
2115 struct mlx5dr_action *action;
2116
2117 if (aso_type != MLX5_EXE_ASO_FLOW_METER)
2118 return NULL;
2119
2120 if (init_color > MLX5_FLOW_METER_COLOR_UNDEFINED)
2121 return NULL;
2122
2123 action = dr_action_create_generic(DR_ACTION_TYP_ASO_FLOW_METER);
2124 if (!action)
2125 return NULL;
2126
2127 action->aso->obj_id = obj_id;
2128 action->aso->offset = meter_id;
2129 action->aso->dest_reg_id = dest_reg_id;
2130 action->aso->init_color = init_color;
2131 action->aso->dmn = dmn;
2132
2133 refcount_inc(&dmn->refcount);
2134
2135 return action;
2136 }
2137
mlx5dr_action_get_pkt_reformat_id(struct mlx5dr_action * action)2138 u32 mlx5dr_action_get_pkt_reformat_id(struct mlx5dr_action *action)
2139 {
2140 return action->reformat->id;
2141 }
2142
mlx5dr_action_destroy(struct mlx5dr_action * action)2143 int mlx5dr_action_destroy(struct mlx5dr_action *action)
2144 {
2145 if (WARN_ON_ONCE(refcount_read(&action->refcount) > 1))
2146 return -EBUSY;
2147
2148 switch (action->action_type) {
2149 case DR_ACTION_TYP_FT:
2150 if (action->dest_tbl->is_fw_tbl)
2151 refcount_dec(&action->dest_tbl->fw_tbl.dmn->refcount);
2152 else
2153 refcount_dec(&action->dest_tbl->tbl->refcount);
2154
2155 if (action->dest_tbl->is_fw_tbl &&
2156 action->dest_tbl->fw_tbl.num_of_ref_actions) {
2157 struct mlx5dr_action **ref_actions;
2158 int i;
2159
2160 ref_actions = action->dest_tbl->fw_tbl.ref_actions;
2161 for (i = 0; i < action->dest_tbl->fw_tbl.num_of_ref_actions; i++)
2162 refcount_dec(&ref_actions[i]->refcount);
2163
2164 kfree(ref_actions);
2165
2166 mlx5dr_fw_destroy_md_tbl(action->dest_tbl->fw_tbl.dmn,
2167 action->dest_tbl->fw_tbl.id,
2168 action->dest_tbl->fw_tbl.group_id);
2169 }
2170 break;
2171 case DR_ACTION_TYP_TNL_L2_TO_L2:
2172 case DR_ACTION_TYP_REMOVE_HDR:
2173 refcount_dec(&action->reformat->dmn->refcount);
2174 break;
2175 case DR_ACTION_TYP_TNL_L3_TO_L2:
2176 mlx5dr_ste_free_modify_hdr(action);
2177 kfree(action->rewrite->data);
2178 refcount_dec(&action->rewrite->dmn->refcount);
2179 break;
2180 case DR_ACTION_TYP_L2_TO_TNL_L2:
2181 case DR_ACTION_TYP_L2_TO_TNL_L3:
2182 case DR_ACTION_TYP_INSERT_HDR:
2183 mlx5dr_cmd_destroy_reformat_ctx((action->reformat->dmn)->mdev,
2184 action->reformat->id);
2185 refcount_dec(&action->reformat->dmn->refcount);
2186 break;
2187 case DR_ACTION_TYP_MODIFY_HDR:
2188 if (!action->rewrite->single_action_opt)
2189 mlx5dr_ste_free_modify_hdr(action);
2190 kfree(action->rewrite->data);
2191 refcount_dec(&action->rewrite->dmn->refcount);
2192 break;
2193 case DR_ACTION_TYP_SAMPLER:
2194 refcount_dec(&action->sampler->dmn->refcount);
2195 break;
2196 case DR_ACTION_TYP_ASO_FLOW_METER:
2197 refcount_dec(&action->aso->dmn->refcount);
2198 break;
2199 case DR_ACTION_TYP_RANGE:
2200 dr_action_destroy_range_definer(action);
2201 mlx5dr_action_destroy(action->range->miss_tbl_action);
2202 mlx5dr_action_destroy(action->range->hit_tbl_action);
2203 break;
2204 default:
2205 break;
2206 }
2207
2208 kfree(action);
2209 return 0;
2210 }
2211
