1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/random.h>
36 #include <linux/vmalloc.h>
37 #include <linux/hardirq.h>
38 #include <linux/mlx5/driver.h>
39 #include "mlx5_core.h"
40 #include "lib/eq.h"
41 #include "lib/mlx5.h"
42 #include "lib/pci_vsc.h"
43 #include "diag/fw_tracer.h"
44
45 enum {
46 MLX5_HEALTH_POLL_INTERVAL = 2 * HZ,
47 MAX_MISSES = 3,
48 };
49
50 enum {
51 MLX5_HEALTH_SYNDR_FW_ERR = 0x1,
52 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7,
53 MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8,
54 MLX5_HEALTH_SYNDR_CRC_ERR = 0x9,
55 MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa,
56 MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb,
57 MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc,
58 MLX5_HEALTH_SYNDR_EQ_ERR = 0xd,
59 MLX5_HEALTH_SYNDR_EQ_INV = 0xe,
60 MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf,
61 MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10
62 };
63
64 enum {
65 MLX5_DROP_NEW_HEALTH_WORK,
66 };
67
68 enum {
69 MLX5_SENSOR_NO_ERR = 0,
70 MLX5_SENSOR_PCI_COMM_ERR = 1,
71 MLX5_SENSOR_PCI_ERR = 2,
72 MLX5_SENSOR_NIC_DISABLED = 3,
73 MLX5_SENSOR_NIC_SW_RESET = 4,
74 MLX5_SENSOR_FW_SYND_RFR = 5,
75 };
76
mlx5_get_nic_state(struct mlx5_core_dev * dev)77 u8 mlx5_get_nic_state(struct mlx5_core_dev *dev)
78 {
79 return (ioread32be(&dev->iseg->cmdq_addr_l_sz) >> 8) & 7;
80 }
81
mlx5_set_nic_state(struct mlx5_core_dev * dev,u8 state)82 void mlx5_set_nic_state(struct mlx5_core_dev *dev, u8 state)
83 {
84 u32 cur_cmdq_addr_l_sz;
85
86 cur_cmdq_addr_l_sz = ioread32be(&dev->iseg->cmdq_addr_l_sz);
87 iowrite32be((cur_cmdq_addr_l_sz & 0xFFFFF000) |
88 state << MLX5_NIC_IFC_OFFSET,
89 &dev->iseg->cmdq_addr_l_sz);
90 }
91
sensor_pci_not_working(struct mlx5_core_dev * dev)92 static bool sensor_pci_not_working(struct mlx5_core_dev *dev)
93 {
94 struct mlx5_core_health *health = &dev->priv.health;
95 struct health_buffer __iomem *h = health->health;
96
97 /* Offline PCI reads return 0xffffffff */
98 return (ioread32be(&h->fw_ver) == 0xffffffff);
99 }
100
sensor_fw_synd_rfr(struct mlx5_core_dev * dev)101 static bool sensor_fw_synd_rfr(struct mlx5_core_dev *dev)
102 {
103 struct mlx5_core_health *health = &dev->priv.health;
104 struct health_buffer __iomem *h = health->health;
105 u32 rfr = ioread32be(&h->rfr) >> MLX5_RFR_OFFSET;
106 u8 synd = ioread8(&h->synd);
107
108 if (rfr && synd)
109 mlx5_core_dbg(dev, "FW requests reset, synd: %d\n", synd);
110 return rfr && synd;
111 }
112
mlx5_health_check_fatal_sensors(struct mlx5_core_dev * dev)113 u32 mlx5_health_check_fatal_sensors(struct mlx5_core_dev *dev)
114 {
115 if (sensor_pci_not_working(dev))
116 return MLX5_SENSOR_PCI_COMM_ERR;
117 if (pci_channel_offline(dev->pdev))
118 return MLX5_SENSOR_PCI_ERR;
119 if (mlx5_get_nic_state(dev) == MLX5_NIC_IFC_DISABLED)
120 return MLX5_SENSOR_NIC_DISABLED;
121 if (mlx5_get_nic_state(dev) == MLX5_NIC_IFC_SW_RESET)
122 return MLX5_SENSOR_NIC_SW_RESET;
123 if (sensor_fw_synd_rfr(dev))
124 return MLX5_SENSOR_FW_SYND_RFR;
125
126 return MLX5_SENSOR_NO_ERR;
127 }
128
lock_sem_sw_reset(struct mlx5_core_dev * dev,bool lock)129 static int lock_sem_sw_reset(struct mlx5_core_dev *dev, bool lock)
130 {
131 enum mlx5_vsc_state state;
132 int ret;
133
134 if (!mlx5_core_is_pf(dev))
135 return -EBUSY;
136
137 /* Try to lock GW access, this stage doesn't return
138 * EBUSY because locked GW does not mean that other PF
139 * already started the reset.
140 */
141 ret = mlx5_vsc_gw_lock(dev);
142 if (ret == -EBUSY)
143 return -EINVAL;
144 if (ret)
145 return ret;
146
147 state = lock ? MLX5_VSC_LOCK : MLX5_VSC_UNLOCK;
148 /* At this stage, if the return status == EBUSY, then we know
149 * for sure that another PF started the reset, so don't allow
150 * another reset.
151 */
152 ret = mlx5_vsc_sem_set_space(dev, MLX5_SEMAPHORE_SW_RESET, state);
153 if (ret)
154 mlx5_core_warn(dev, "Failed to lock SW reset semaphore\n");
155
156 /* Unlock GW access */
157 mlx5_vsc_gw_unlock(dev);
158
159 return ret;
160 }
161
reset_fw_if_needed(struct mlx5_core_dev * dev)162 static bool reset_fw_if_needed(struct mlx5_core_dev *dev)
163 {
164 bool supported = (ioread32be(&dev->iseg->initializing) >>
165 MLX5_FW_RESET_SUPPORTED_OFFSET) & 1;
166 u32 fatal_error;
167
168 if (!supported)
169 return false;
170
171 /* The reset only needs to be issued by one PF. The health buffer is
172 * shared between all functions, and will be cleared during a reset.
173 * Check again to avoid a redundant 2nd reset. If the fatal errors was
174 * PCI related a reset won't help.
175 */
176 fatal_error = mlx5_health_check_fatal_sensors(dev);
177 if (fatal_error == MLX5_SENSOR_PCI_COMM_ERR ||
178 fatal_error == MLX5_SENSOR_NIC_DISABLED ||
179 fatal_error == MLX5_SENSOR_NIC_SW_RESET) {
180 mlx5_core_warn(dev, "Not issuing FW reset. Either it's already done or won't help.");
181 return false;
182 }
183
184 mlx5_core_warn(dev, "Issuing FW Reset\n");
185 /* Write the NIC interface field to initiate the reset, the command
186 * interface address also resides here, don't overwrite it.
187 */
188 mlx5_set_nic_state(dev, MLX5_NIC_IFC_SW_RESET);
189
190 return true;
191 }
192
enter_error_state(struct mlx5_core_dev * dev,bool force)193 static void enter_error_state(struct mlx5_core_dev *dev, bool force)
194 {
195 if (mlx5_health_check_fatal_sensors(dev) || force) { /* protected state setting */
196 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
197 mlx5_cmd_flush(dev);
198 }
199
200 mlx5_notifier_call_chain(dev->priv.events, MLX5_DEV_EVENT_SYS_ERROR, (void *)1);
201 }
202
mlx5_enter_error_state(struct mlx5_core_dev * dev,bool force)203 void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force)
204 {
205 bool err_detected = false;
206
207 /* Mark the device as fatal in order to abort FW commands */
208 if ((mlx5_health_check_fatal_sensors(dev) || force) &&
209 dev->state == MLX5_DEVICE_STATE_UP) {
210 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
211 err_detected = true;
212 }
213 mutex_lock(&dev->intf_state_mutex);
214 if (!err_detected && dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
215 goto unlock;/* a previous error is still being handled */
216
217 enter_error_state(dev, force);
218 unlock:
219 mutex_unlock(&dev->intf_state_mutex);
220 }
221
222 #define MLX5_CRDUMP_WAIT_MS 60000
223 #define MLX5_FW_RESET_WAIT_MS 1000
mlx5_error_sw_reset(struct mlx5_core_dev * dev)224 void mlx5_error_sw_reset(struct mlx5_core_dev *dev)
225 {
226 unsigned long end, delay_ms = MLX5_FW_RESET_WAIT_MS;
227 int lock = -EBUSY;
228
229 mutex_lock(&dev->intf_state_mutex);
230 if (dev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR)
231 goto unlock;
232
233 mlx5_core_err(dev, "start\n");
234
235 if (mlx5_health_check_fatal_sensors(dev) == MLX5_SENSOR_FW_SYND_RFR) {
236 /* Get cr-dump and reset FW semaphore */
237 lock = lock_sem_sw_reset(dev, true);
238
239 if (lock == -EBUSY) {
240 delay_ms = MLX5_CRDUMP_WAIT_MS;
241 goto recover_from_sw_reset;
242 }
243 /* Execute SW reset */
244 reset_fw_if_needed(dev);
245 }
246
247 recover_from_sw_reset:
248 /* Recover from SW reset */
249 end = jiffies + msecs_to_jiffies(delay_ms);
250 do {
251 if (mlx5_get_nic_state(dev) == MLX5_NIC_IFC_DISABLED)
252 break;
253
254 msleep(20);
255 } while (!time_after(jiffies, end));
256
257 if (mlx5_get_nic_state(dev) != MLX5_NIC_IFC_DISABLED) {
258 dev_err(&dev->pdev->dev, "NIC IFC still %d after %lums.\n",
259 mlx5_get_nic_state(dev), delay_ms);
260 }
261
262 /* Release FW semaphore if you are the lock owner */
263 if (!lock)
264 lock_sem_sw_reset(dev, false);
265
266 mlx5_core_err(dev, "end\n");
267
268 unlock:
269 mutex_unlock(&dev->intf_state_mutex);
270 }
271
mlx5_handle_bad_state(struct mlx5_core_dev * dev)272 static void mlx5_handle_bad_state(struct mlx5_core_dev *dev)
273 {
274 u8 nic_interface = mlx5_get_nic_state(dev);
275
276 switch (nic_interface) {
277 case MLX5_NIC_IFC_FULL:
278 mlx5_core_warn(dev, "Expected to see disabled NIC but it is full driver\n");
279 break;
280
281 case MLX5_NIC_IFC_DISABLED:
282 mlx5_core_warn(dev, "starting teardown\n");
283 break;
284
285 case MLX5_NIC_IFC_NO_DRAM_NIC:
286 mlx5_core_warn(dev, "Expected to see disabled NIC but it is no dram nic\n");
287 break;
288
289 case MLX5_NIC_IFC_SW_RESET:
290 /* The IFC mode field is 3 bits, so it will read 0x7 in 2 cases:
291 * 1. PCI has been disabled (ie. PCI-AER, PF driver unloaded
292 * and this is a VF), this is not recoverable by SW reset.
293 * Logging of this is handled elsewhere.
294 * 2. FW reset has been issued by another function, driver can
295 * be reloaded to recover after the mode switches to
296 * MLX5_NIC_IFC_DISABLED.
297 */
298 if (dev->priv.health.fatal_error != MLX5_SENSOR_PCI_COMM_ERR)
299 mlx5_core_warn(dev, "NIC SW reset in progress\n");
300 break;
301
302 default:
303 mlx5_core_warn(dev, "Expected to see disabled NIC but it is has invalid value %d\n",
304 nic_interface);
305 }
306
307 mlx5_disable_device(dev);
308 }
309
310 /* How much time to wait until health resetting the driver (in msecs) */
311 #define MLX5_RECOVERY_WAIT_MSECS 60000
mlx5_health_wait_pci_up(struct mlx5_core_dev * dev)312 int mlx5_health_wait_pci_up(struct mlx5_core_dev *dev)
313 {
314 unsigned long end;
315
316 end = jiffies + msecs_to_jiffies(MLX5_RECOVERY_WAIT_MSECS);
317 while (sensor_pci_not_working(dev)) {
318 if (time_after(jiffies, end))
319 return -ETIMEDOUT;
320 msleep(100);
321 }
322 return 0;
323 }
324
mlx5_health_try_recover(struct mlx5_core_dev * dev)325 static int mlx5_health_try_recover(struct mlx5_core_dev *dev)
326 {
327 mlx5_core_warn(dev, "handling bad device here\n");
328 mlx5_handle_bad_state(dev);
329 if (mlx5_health_wait_pci_up(dev)) {
330 mlx5_core_err(dev, "health recovery flow aborted, PCI reads still not working\n");
331 return -EIO;
332 }
333 mlx5_core_err(dev, "starting health recovery flow\n");
334 if (mlx5_recover_device(dev) || mlx5_health_check_fatal_sensors(dev)) {
335 mlx5_core_err(dev, "health recovery failed\n");
336 return -EIO;
337 }
338
339 mlx5_core_info(dev, "health recovery succeeded\n");
340 return 0;
341 }
342
hsynd_str(u8 synd)343 static const char *hsynd_str(u8 synd)
344 {
345 switch (synd) {
346 case MLX5_HEALTH_SYNDR_FW_ERR:
347 return "firmware internal error";
348 case MLX5_HEALTH_SYNDR_IRISC_ERR:
349 return "irisc not responding";
350 case MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR:
351 return "unrecoverable hardware error";
352 case MLX5_HEALTH_SYNDR_CRC_ERR:
353 return "firmware CRC error";
354 case MLX5_HEALTH_SYNDR_FETCH_PCI_ERR:
355 return "ICM fetch PCI error";
356 case MLX5_HEALTH_SYNDR_HW_FTL_ERR:
357 return "HW fatal error\n";
358 case MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR:
359 return "async EQ buffer overrun";
360 case MLX5_HEALTH_SYNDR_EQ_ERR:
361 return "EQ error";
362 case MLX5_HEALTH_SYNDR_EQ_INV:
363 return "Invalid EQ referenced";
364 case MLX5_HEALTH_SYNDR_FFSER_ERR:
365 return "FFSER error";
366 case MLX5_HEALTH_SYNDR_HIGH_TEMP:
367 return "High temperature";
368 default:
369 return "unrecognized error";
370 }
371 }
372
print_health_info(struct mlx5_core_dev * dev)373 static void print_health_info(struct mlx5_core_dev *dev)
374 {
375 struct mlx5_core_health *health = &dev->priv.health;
376 struct health_buffer __iomem *h = health->health;
377 char fw_str[18];
378 u32 fw;
379 int i;
380
381 /* If the syndrome is 0, the device is OK and no need to print buffer */
382 if (!ioread8(&h->synd))
383 return;
384
385 for (i = 0; i < ARRAY_SIZE(h->assert_var); i++)
386 mlx5_core_err(dev, "assert_var[%d] 0x%08x\n", i,
387 ioread32be(h->assert_var + i));
388
389 mlx5_core_err(dev, "assert_exit_ptr 0x%08x\n",
390 ioread32be(&h->assert_exit_ptr));
391 mlx5_core_err(dev, "assert_callra 0x%08x\n",
392 ioread32be(&h->assert_callra));
393 sprintf(fw_str, "%d.%d.%d", fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev));
394 mlx5_core_err(dev, "fw_ver %s\n", fw_str);
395 mlx5_core_err(dev, "hw_id 0x%08x\n", ioread32be(&h->hw_id));
396 mlx5_core_err(dev, "irisc_index %d\n", ioread8(&h->irisc_index));
397 mlx5_core_err(dev, "synd 0x%x: %s\n", ioread8(&h->synd),
398 hsynd_str(ioread8(&h->synd)));
399 mlx5_core_err(dev, "ext_synd 0x%04x\n", ioread16be(&h->ext_synd));
400 fw = ioread32be(&h->fw_ver);
401 mlx5_core_err(dev, "raw fw_ver 0x%08x\n", fw);
402 }
403
404 static int
mlx5_fw_reporter_diagnose(struct devlink_health_reporter * reporter,struct devlink_fmsg * fmsg,struct netlink_ext_ack * extack)405 mlx5_fw_reporter_diagnose(struct devlink_health_reporter *reporter,
406 struct devlink_fmsg *fmsg,
407 struct netlink_ext_ack *extack)
408 {
409 struct mlx5_core_dev *dev = devlink_health_reporter_priv(reporter);
410 struct mlx5_core_health *health = &dev->priv.health;
411 struct health_buffer __iomem *h = health->health;
412 u8 synd;
413 int err;
414
415 synd = ioread8(&h->synd);
416 err = devlink_fmsg_u8_pair_put(fmsg, "Syndrome", synd);
417 if (err || !synd)
418 return err;
419 return devlink_fmsg_string_pair_put(fmsg, "Description", hsynd_str(synd));
420 }
421
422 struct mlx5_fw_reporter_ctx {
423 u8 err_synd;
424 int miss_counter;
425 };
426
427 static int
mlx5_fw_reporter_ctx_pairs_put(struct devlink_fmsg * fmsg,struct mlx5_fw_reporter_ctx * fw_reporter_ctx)428 mlx5_fw_reporter_ctx_pairs_put(struct devlink_fmsg *fmsg,
429 struct mlx5_fw_reporter_ctx *fw_reporter_ctx)
430 {
431 int err;
432
433 err = devlink_fmsg_u8_pair_put(fmsg, "syndrome",
434 fw_reporter_ctx->err_synd);
435 if (err)
436 return err;
437 err = devlink_fmsg_u32_pair_put(fmsg, "fw_miss_counter",
438 fw_reporter_ctx->miss_counter);
439 if (err)
440 return err;
441 return 0;
442 }
443
444 static int
mlx5_fw_reporter_heath_buffer_data_put(struct mlx5_core_dev * dev,struct devlink_fmsg * fmsg)445 mlx5_fw_reporter_heath_buffer_data_put(struct mlx5_core_dev *dev,
446 struct devlink_fmsg *fmsg)
447 {
448 struct mlx5_core_health *health = &dev->priv.health;
449 struct health_buffer __iomem *h = health->health;
450 int err;
451 int i;
452
453 if (!ioread8(&h->synd))
454 return 0;
455
456 err = devlink_fmsg_pair_nest_start(fmsg, "health buffer");
457 if (err)
458 return err;
459 err = devlink_fmsg_obj_nest_start(fmsg);
460 if (err)
461 return err;
462 err = devlink_fmsg_arr_pair_nest_start(fmsg, "assert_var");
463 if (err)
464 return err;
465
466 for (i = 0; i < ARRAY_SIZE(h->assert_var); i++) {
467 err = devlink_fmsg_u32_put(fmsg, ioread32be(h->assert_var + i));
468 if (err)
469 return err;
470 }
471 err = devlink_fmsg_arr_pair_nest_end(fmsg);
472 if (err)
473 return err;
474 err = devlink_fmsg_u32_pair_put(fmsg, "assert_exit_ptr",
475 ioread32be(&h->assert_exit_ptr));
476 if (err)
477 return err;
478 err = devlink_fmsg_u32_pair_put(fmsg, "assert_callra",
479 ioread32be(&h->assert_callra));
480 if (err)
481 return err;
482 err = devlink_fmsg_u32_pair_put(fmsg, "hw_id", ioread32be(&h->hw_id));
483 if (err)
484 return err;
485 err = devlink_fmsg_u8_pair_put(fmsg, "irisc_index",
486 ioread8(&h->irisc_index));
487 if (err)
488 return err;
489 err = devlink_fmsg_u8_pair_put(fmsg, "synd", ioread8(&h->synd));
490 if (err)
491 return err;
492 err = devlink_fmsg_u32_pair_put(fmsg, "ext_synd",
493 ioread16be(&h->ext_synd));
494 if (err)
495 return err;
496 err = devlink_fmsg_u32_pair_put(fmsg, "raw_fw_ver",
497 ioread32be(&h->fw_ver));
498 if (err)
499 return err;
500 err = devlink_fmsg_obj_nest_end(fmsg);
501 if (err)
502 return err;
503 return devlink_fmsg_pair_nest_end(fmsg);
504 }
505
506 static int
mlx5_fw_reporter_dump(struct devlink_health_reporter * reporter,struct devlink_fmsg * fmsg,void * priv_ctx,struct netlink_ext_ack * extack)507 mlx5_fw_reporter_dump(struct devlink_health_reporter *reporter,
508 struct devlink_fmsg *fmsg, void *priv_ctx,
509 struct netlink_ext_ack *extack)
510 {
511 struct mlx5_core_dev *dev = devlink_health_reporter_priv(reporter);
512 int err;
513
514 err = mlx5_fw_tracer_trigger_core_dump_general(dev);
515 if (err)
516 return err;
517
518 if (priv_ctx) {
519 struct mlx5_fw_reporter_ctx *fw_reporter_ctx = priv_ctx;
520
521 err = mlx5_fw_reporter_ctx_pairs_put(fmsg, fw_reporter_ctx);
522 if (err)
523 return err;
524 }
525
526 err = mlx5_fw_reporter_heath_buffer_data_put(dev, fmsg);
527 if (err)
528 return err;
529 return mlx5_fw_tracer_get_saved_traces_objects(dev->tracer, fmsg);
530 }
531
mlx5_fw_reporter_err_work(struct work_struct * work)532 static void mlx5_fw_reporter_err_work(struct work_struct *work)
533 {
534 struct mlx5_fw_reporter_ctx fw_reporter_ctx;
535 struct mlx5_core_health *health;
536
537 health = container_of(work, struct mlx5_core_health, report_work);
538
539 if (IS_ERR_OR_NULL(health->fw_reporter))
540 return;
541
542 fw_reporter_ctx.err_synd = health->synd;
543 fw_reporter_ctx.miss_counter = health->miss_counter;
544 if (fw_reporter_ctx.err_synd) {
545 devlink_health_report(health->fw_reporter,
546 "FW syndrom reported", &fw_reporter_ctx);
547 return;
548 }
549 if (fw_reporter_ctx.miss_counter)
550 devlink_health_report(health->fw_reporter,
551 "FW miss counter reported",
552 &fw_reporter_ctx);
553 }
554
555 static const struct devlink_health_reporter_ops mlx5_fw_reporter_ops = {
556 .name = "fw",
557 .diagnose = mlx5_fw_reporter_diagnose,
558 .dump = mlx5_fw_reporter_dump,
559 };
560
561 static int
mlx5_fw_fatal_reporter_recover(struct devlink_health_reporter * reporter,void * priv_ctx,struct netlink_ext_ack * extack)562 mlx5_fw_fatal_reporter_recover(struct devlink_health_reporter *reporter,
563 void *priv_ctx,
564 struct netlink_ext_ack *extack)
565 {
566 struct mlx5_core_dev *dev = devlink_health_reporter_priv(reporter);
567
568 return mlx5_health_try_recover(dev);
569 }
570
571 static int
mlx5_fw_fatal_reporter_dump(struct devlink_health_reporter * reporter,struct devlink_fmsg * fmsg,void * priv_ctx,struct netlink_ext_ack * extack)572 mlx5_fw_fatal_reporter_dump(struct devlink_health_reporter *reporter,
573 struct devlink_fmsg *fmsg, void *priv_ctx,
574 struct netlink_ext_ack *extack)
575 {
576 struct mlx5_core_dev *dev = devlink_health_reporter_priv(reporter);
577 u32 crdump_size = dev->priv.health.crdump_size;
578 u32 *cr_data;
579 int err;
580
581 if (!mlx5_core_is_pf(dev))
582 return -EPERM;
583
584 cr_data = kvmalloc(crdump_size, GFP_KERNEL);
585 if (!cr_data)
586 return -ENOMEM;
587 err = mlx5_crdump_collect(dev, cr_data);
588 if (err)
589 goto free_data;
590
591 if (priv_ctx) {
592 struct mlx5_fw_reporter_ctx *fw_reporter_ctx = priv_ctx;
593
594 err = mlx5_fw_reporter_ctx_pairs_put(fmsg, fw_reporter_ctx);
595 if (err)
596 goto free_data;
597 }
598
599 err = devlink_fmsg_binary_pair_put(fmsg, "crdump_data", cr_data, crdump_size);
600
601 free_data:
602 kvfree(cr_data);
603 return err;
604 }
605
mlx5_fw_fatal_reporter_err_work(struct work_struct * work)606 static void mlx5_fw_fatal_reporter_err_work(struct work_struct *work)
607 {
608 struct mlx5_fw_reporter_ctx fw_reporter_ctx;
609 struct mlx5_core_health *health;
610 struct mlx5_core_dev *dev;
611 struct mlx5_priv *priv;
612
613 health = container_of(work, struct mlx5_core_health, fatal_report_work);
614 priv = container_of(health, struct mlx5_priv, health);
615 dev = container_of(priv, struct mlx5_core_dev, priv);
616
617 enter_error_state(dev, false);
618 if (IS_ERR_OR_NULL(health->fw_fatal_reporter)) {
619 if (mlx5_health_try_recover(dev))
620 mlx5_core_err(dev, "health recovery failed\n");
621 return;
622 }
623 fw_reporter_ctx.err_synd = health->synd;
624 fw_reporter_ctx.miss_counter = health->miss_counter;
625 if (devlink_health_report(health->fw_fatal_reporter,
626 "FW fatal error reported", &fw_reporter_ctx) == -ECANCELED) {
627 /* If recovery wasn't performed, due to grace period,
628 * unload the driver. This ensures that the driver
629 * closes all its resources and it is not subjected to
630 * requests from the kernel.
631 */
632 mlx5_core_err(dev, "Driver is in error state. Unloading\n");
633 mlx5_unload_one(dev);
634 }
635 }
636
637 static const struct devlink_health_reporter_ops mlx5_fw_fatal_reporter_ops = {
638 .name = "fw_fatal",
639 .recover = mlx5_fw_fatal_reporter_recover,
640 .dump = mlx5_fw_fatal_reporter_dump,
641 };
642
643 #define MLX5_REPORTER_FW_GRACEFUL_PERIOD 1200000
mlx5_fw_reporters_create(struct mlx5_core_dev * dev)644 static void mlx5_fw_reporters_create(struct mlx5_core_dev *dev)
645 {
646 struct mlx5_core_health *health = &dev->priv.health;
647 struct devlink *devlink = priv_to_devlink(dev);
648
649 health->fw_reporter =
650 devlink_health_reporter_create(devlink, &mlx5_fw_reporter_ops,
651 0, dev);
652 if (IS_ERR(health->fw_reporter))
653 mlx5_core_warn(dev, "Failed to create fw reporter, err = %ld\n",
654 PTR_ERR(health->fw_reporter));
655
656 health->fw_fatal_reporter =
657 devlink_health_reporter_create(devlink,
658 &mlx5_fw_fatal_reporter_ops,
659 MLX5_REPORTER_FW_GRACEFUL_PERIOD,
660 dev);
661 if (IS_ERR(health->fw_fatal_reporter))
662 mlx5_core_warn(dev, "Failed to create fw fatal reporter, err = %ld\n",
663 PTR_ERR(health->fw_fatal_reporter));
664 }
665
mlx5_fw_reporters_destroy(struct mlx5_core_dev * dev)666 static void mlx5_fw_reporters_destroy(struct mlx5_core_dev *dev)
667 {
668 struct mlx5_core_health *health = &dev->priv.health;
669
670 if (!IS_ERR_OR_NULL(health->fw_reporter))
671 devlink_health_reporter_destroy(health->fw_reporter);
672
673 if (!IS_ERR_OR_NULL(health->fw_fatal_reporter))
674 devlink_health_reporter_destroy(health->fw_fatal_reporter);
675 }
676
get_next_poll_jiffies(void)677 static unsigned long get_next_poll_jiffies(void)
678 {
679 unsigned long next;
680
681 get_random_bytes(&next, sizeof(next));
682 next %= HZ;
683 next += jiffies + MLX5_HEALTH_POLL_INTERVAL;
684
685 return next;
686 }
687
mlx5_trigger_health_work(struct mlx5_core_dev * dev)688 void mlx5_trigger_health_work(struct mlx5_core_dev *dev)
689 {
690 struct mlx5_core_health *health = &dev->priv.health;
691 unsigned long flags;
692
693 spin_lock_irqsave(&health->wq_lock, flags);
694 if (!test_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags))
695 queue_work(health->wq, &health->fatal_report_work);
696 else
697 mlx5_core_err(dev, "new health works are not permitted at this stage\n");
698 spin_unlock_irqrestore(&health->wq_lock, flags);
699 }
700
poll_health(struct timer_list * t)701 static void poll_health(struct timer_list *t)
702 {
703 struct mlx5_core_dev *dev = from_timer(dev, t, priv.health.timer);
704 struct mlx5_core_health *health = &dev->priv.health;
705 struct health_buffer __iomem *h = health->health;
706 u32 fatal_error;
707 u8 prev_synd;
708 u32 count;
709
710 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
711 goto out;
712
713 fatal_error = mlx5_health_check_fatal_sensors(dev);
714
715 if (fatal_error && !health->fatal_error) {
716 mlx5_core_err(dev, "Fatal error %u detected\n", fatal_error);
717 dev->priv.health.fatal_error = fatal_error;
718 print_health_info(dev);
719 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
720 mlx5_trigger_health_work(dev);
721 return;
722 }
723
724 count = ioread32be(health->health_counter);
725 if (count == health->prev)
726 ++health->miss_counter;
727 else
728 health->miss_counter = 0;
729
730 health->prev = count;
731 if (health->miss_counter == MAX_MISSES) {
732 mlx5_core_err(dev, "device's health compromised - reached miss count\n");
733 print_health_info(dev);
734 queue_work(health->wq, &health->report_work);
735 }
736
737 prev_synd = health->synd;
738 health->synd = ioread8(&h->synd);
739 if (health->synd && health->synd != prev_synd)
740 queue_work(health->wq, &health->report_work);
741
742 out:
743 mod_timer(&health->timer, get_next_poll_jiffies());
744 }
745
mlx5_start_health_poll(struct mlx5_core_dev * dev)746 void mlx5_start_health_poll(struct mlx5_core_dev *dev)
747 {
748 struct mlx5_core_health *health = &dev->priv.health;
749
750 timer_setup(&health->timer, poll_health, 0);
751 health->fatal_error = MLX5_SENSOR_NO_ERR;
752 clear_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags);
753 health->health = &dev->iseg->health;
754 health->health_counter = &dev->iseg->health_counter;
755
756 health->timer.expires = round_jiffies(jiffies + MLX5_HEALTH_POLL_INTERVAL);
757 add_timer(&health->timer);
758 }
759
mlx5_stop_health_poll(struct mlx5_core_dev * dev,bool disable_health)760 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health)
761 {
762 struct mlx5_core_health *health = &dev->priv.health;
763 unsigned long flags;
764
765 if (disable_health) {
766 spin_lock_irqsave(&health->wq_lock, flags);
767 set_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags);
768 spin_unlock_irqrestore(&health->wq_lock, flags);
769 }
770
771 del_timer_sync(&health->timer);
772 }
773
mlx5_drain_health_wq(struct mlx5_core_dev * dev)774 void mlx5_drain_health_wq(struct mlx5_core_dev *dev)
775 {
776 struct mlx5_core_health *health = &dev->priv.health;
777 unsigned long flags;
778
779 spin_lock_irqsave(&health->wq_lock, flags);
780 set_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags);
781 spin_unlock_irqrestore(&health->wq_lock, flags);
782 cancel_work_sync(&health->report_work);
783 cancel_work_sync(&health->fatal_report_work);
784 }
785
mlx5_health_flush(struct mlx5_core_dev * dev)786 void mlx5_health_flush(struct mlx5_core_dev *dev)
787 {
788 struct mlx5_core_health *health = &dev->priv.health;
789
790 flush_workqueue(health->wq);
791 }
792
mlx5_health_cleanup(struct mlx5_core_dev * dev)793 void mlx5_health_cleanup(struct mlx5_core_dev *dev)
794 {
795 struct mlx5_core_health *health = &dev->priv.health;
796
797 destroy_workqueue(health->wq);
798 mlx5_fw_reporters_destroy(dev);
799 }
800
mlx5_health_init(struct mlx5_core_dev * dev)801 int mlx5_health_init(struct mlx5_core_dev *dev)
802 {
803 struct mlx5_core_health *health;
804 char *name;
805
806 mlx5_fw_reporters_create(dev);
807
808 health = &dev->priv.health;
809 name = kmalloc(64, GFP_KERNEL);
810 if (!name)
811 goto out_err;
812
813 strcpy(name, "mlx5_health");
814 strcat(name, dev_name(dev->device));
815 health->wq = create_singlethread_workqueue(name);
816 kfree(name);
817 if (!health->wq)
818 goto out_err;
819 spin_lock_init(&health->wq_lock);
820 INIT_WORK(&health->fatal_report_work, mlx5_fw_fatal_reporter_err_work);
821 INIT_WORK(&health->report_work, mlx5_fw_reporter_err_work);
822
823 return 0;
824
825 out_err:
826 mlx5_fw_reporters_destroy(dev);
827 return -ENOMEM;
828 }
829
