1 /*
2 * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef __MLX5_FPGA_CORE_H__
34 #define __MLX5_FPGA_CORE_H__
35
36 #ifdef CONFIG_MLX5_FPGA
37
38 #include <linux/mlx5/eq.h>
39
40 #include "mlx5_core.h"
41 #include "lib/eq.h"
42 #include "fpga/cmd.h"
43
44 /* Represents an Innova device */
45 struct mlx5_fpga_device {
46 struct mlx5_core_dev *mdev;
47 struct mlx5_nb fpga_err_nb;
48 struct mlx5_nb fpga_qp_err_nb;
49 spinlock_t state_lock; /* Protects state transitions */
50 enum mlx5_fpga_status state;
51 enum mlx5_fpga_image last_admin_image;
52 enum mlx5_fpga_image last_oper_image;
53
54 /* QP Connection resources */
55 struct {
56 u32 pdn;
57 struct mlx5_core_mkey mkey;
58 struct mlx5_uars_page *uar;
59 } conn_res;
60
61 struct mlx5_fpga_ipsec *ipsec;
62 struct mlx5_fpga_tls *tls;
63 };
64
65 #define mlx5_fpga_dbg(__adev, format, ...) \
66 mlx5_core_dbg((__adev)->mdev, "FPGA: %s:%d:(pid %d): " format, \
67 __func__, __LINE__, current->pid, ##__VA_ARGS__)
68
69 #define mlx5_fpga_err(__adev, format, ...) \
70 mlx5_core_err((__adev)->mdev, "FPGA: %s:%d:(pid %d): " format, \
71 __func__, __LINE__, current->pid, ##__VA_ARGS__)
72
73 #define mlx5_fpga_warn(__adev, format, ...) \
74 mlx5_core_warn((__adev)->mdev, "FPGA: %s:%d:(pid %d): " format, \
75 __func__, __LINE__, current->pid, ##__VA_ARGS__)
76
77 #define mlx5_fpga_warn_ratelimited(__adev, format, ...) \
78 mlx5_core_err_rl((__adev)->mdev, "FPGA: %s:%d: " \
79 format, __func__, __LINE__, ##__VA_ARGS__)
80
81 #define mlx5_fpga_notice(__adev, format, ...) \
82 mlx5_core_info((__adev)->mdev, "FPGA: " format, ##__VA_ARGS__)
83
84 #define mlx5_fpga_info(__adev, format, ...) \
85 mlx5_core_info((__adev)->mdev, "FPGA: " format, ##__VA_ARGS__)
86
87 int mlx5_fpga_init(struct mlx5_core_dev *mdev);
88 void mlx5_fpga_cleanup(struct mlx5_core_dev *mdev);
89 int mlx5_fpga_device_start(struct mlx5_core_dev *mdev);
90 void mlx5_fpga_device_stop(struct mlx5_core_dev *mdev);
91
92 #else
93
mlx5_fpga_init(struct mlx5_core_dev * mdev)94 static inline int mlx5_fpga_init(struct mlx5_core_dev *mdev)
95 {
96 return 0;
97 }
98
mlx5_fpga_cleanup(struct mlx5_core_dev * mdev)99 static inline void mlx5_fpga_cleanup(struct mlx5_core_dev *mdev)
100 {
101 }
102
mlx5_fpga_device_start(struct mlx5_core_dev * mdev)103 static inline int mlx5_fpga_device_start(struct mlx5_core_dev *mdev)
104 {
105 return 0;
106 }
107
mlx5_fpga_device_stop(struct mlx5_core_dev * mdev)108 static inline void mlx5_fpga_device_stop(struct mlx5_core_dev *mdev)
109 {
110 }
111
112 #endif
113
114 #endif /* __MLX5_FPGA_CORE_H__ */
115
