1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/mlx5/srq.h>
47 #include <linux/debugfs.h>
48 #include <linux/kmod.h>
49 #include <linux/mlx5/mlx5_ifc.h>
50 #include <linux/mlx5/vport.h>
51 #ifdef CONFIG_RFS_ACCEL
52 #include <linux/cpu_rmap.h>
53 #endif
54 #include <net/devlink.h>
55 #include "mlx5_core.h"
56 #include "fs_core.h"
57 #include "lib/mpfs.h"
58 #include "eswitch.h"
59 #include "lib/mlx5.h"
60 #include "fpga/core.h"
61 #include "fpga/ipsec.h"
62 #include "accel/ipsec.h"
63 #include "accel/tls.h"
64 #include "lib/clock.h"
65 #include "lib/vxlan.h"
66 #include "diag/fw_tracer.h"
67
68 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
69 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
70 MODULE_LICENSE("Dual BSD/GPL");
71 MODULE_VERSION(DRIVER_VERSION);
72
73 unsigned int mlx5_core_debug_mask;
74 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
75 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
76
77 #define MLX5_DEFAULT_PROF 2
78 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
79 module_param_named(prof_sel, prof_sel, uint, 0444);
80 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
81
82 static u32 sw_owner_id[4];
83
84 enum {
85 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
86 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
87 };
88
89 static struct mlx5_profile profile[] = {
90 [0] = {
91 .mask = 0,
92 },
93 [1] = {
94 .mask = MLX5_PROF_MASK_QP_SIZE,
95 .log_max_qp = 12,
96 },
97 [2] = {
98 .mask = MLX5_PROF_MASK_QP_SIZE |
99 MLX5_PROF_MASK_MR_CACHE,
100 .log_max_qp = 18,
101 .mr_cache[0] = {
102 .size = 500,
103 .limit = 250
104 },
105 .mr_cache[1] = {
106 .size = 500,
107 .limit = 250
108 },
109 .mr_cache[2] = {
110 .size = 500,
111 .limit = 250
112 },
113 .mr_cache[3] = {
114 .size = 500,
115 .limit = 250
116 },
117 .mr_cache[4] = {
118 .size = 500,
119 .limit = 250
120 },
121 .mr_cache[5] = {
122 .size = 500,
123 .limit = 250
124 },
125 .mr_cache[6] = {
126 .size = 500,
127 .limit = 250
128 },
129 .mr_cache[7] = {
130 .size = 500,
131 .limit = 250
132 },
133 .mr_cache[8] = {
134 .size = 500,
135 .limit = 250
136 },
137 .mr_cache[9] = {
138 .size = 500,
139 .limit = 250
140 },
141 .mr_cache[10] = {
142 .size = 500,
143 .limit = 250
144 },
145 .mr_cache[11] = {
146 .size = 500,
147 .limit = 250
148 },
149 .mr_cache[12] = {
150 .size = 64,
151 .limit = 32
152 },
153 .mr_cache[13] = {
154 .size = 32,
155 .limit = 16
156 },
157 .mr_cache[14] = {
158 .size = 16,
159 .limit = 8
160 },
161 .mr_cache[15] = {
162 .size = 8,
163 .limit = 4
164 },
165 .mr_cache[16] = {
166 .size = 8,
167 .limit = 4
168 },
169 .mr_cache[17] = {
170 .size = 8,
171 .limit = 4
172 },
173 .mr_cache[18] = {
174 .size = 8,
175 .limit = 4
176 },
177 .mr_cache[19] = {
178 .size = 4,
179 .limit = 2
180 },
181 .mr_cache[20] = {
182 .size = 4,
183 .limit = 2
184 },
185 },
186 };
187
188 #define FW_INIT_TIMEOUT_MILI 2000
189 #define FW_INIT_WAIT_MS 2
190 #define FW_PRE_INIT_TIMEOUT_MILI 10000
191
wait_fw_init(struct mlx5_core_dev * dev,u32 max_wait_mili)192 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
193 {
194 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
195 int err = 0;
196
197 while (fw_initializing(dev)) {
198 if (time_after(jiffies, end)) {
199 err = -EBUSY;
200 break;
201 }
202 msleep(FW_INIT_WAIT_MS);
203 }
204
205 return err;
206 }
207
mlx5_set_driver_version(struct mlx5_core_dev * dev)208 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
209 {
210 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
211 driver_version);
212 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0};
213 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0};
214 int remaining_size = driver_ver_sz;
215 char *string;
216
217 if (!MLX5_CAP_GEN(dev, driver_version))
218 return;
219
220 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
221
222 strncpy(string, "Linux", remaining_size);
223
224 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
225 strncat(string, ",", remaining_size);
226
227 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
228 strncat(string, DRIVER_NAME, remaining_size);
229
230 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
231 strncat(string, ",", remaining_size);
232
233 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
234 strncat(string, DRIVER_VERSION, remaining_size);
235
236 /*Send the command*/
237 MLX5_SET(set_driver_version_in, in, opcode,
238 MLX5_CMD_OP_SET_DRIVER_VERSION);
239
240 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
241 }
242
set_dma_caps(struct pci_dev * pdev)243 static int set_dma_caps(struct pci_dev *pdev)
244 {
245 int err;
246
247 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
248 if (err) {
249 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
250 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
251 if (err) {
252 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
253 return err;
254 }
255 }
256
257 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
258 if (err) {
259 dev_warn(&pdev->dev,
260 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
261 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
262 if (err) {
263 dev_err(&pdev->dev,
264 "Can't set consistent PCI DMA mask, aborting\n");
265 return err;
266 }
267 }
268
269 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
270 return err;
271 }
272
mlx5_pci_enable_device(struct mlx5_core_dev * dev)273 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
274 {
275 struct pci_dev *pdev = dev->pdev;
276 int err = 0;
277
278 mutex_lock(&dev->pci_status_mutex);
279 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
280 err = pci_enable_device(pdev);
281 if (!err)
282 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
283 }
284 mutex_unlock(&dev->pci_status_mutex);
285
286 return err;
287 }
288
mlx5_pci_disable_device(struct mlx5_core_dev * dev)289 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
290 {
291 struct pci_dev *pdev = dev->pdev;
292
293 mutex_lock(&dev->pci_status_mutex);
294 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
295 pci_disable_device(pdev);
296 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
297 }
298 mutex_unlock(&dev->pci_status_mutex);
299 }
300
request_bar(struct pci_dev * pdev)301 static int request_bar(struct pci_dev *pdev)
302 {
303 int err = 0;
304
305 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
306 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
307 return -ENODEV;
308 }
309
310 err = pci_request_regions(pdev, DRIVER_NAME);
311 if (err)
312 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
313
314 return err;
315 }
316
release_bar(struct pci_dev * pdev)317 static void release_bar(struct pci_dev *pdev)
318 {
319 pci_release_regions(pdev);
320 }
321
mlx5_alloc_irq_vectors(struct mlx5_core_dev * dev)322 static int mlx5_alloc_irq_vectors(struct mlx5_core_dev *dev)
323 {
324 struct mlx5_priv *priv = &dev->priv;
325 struct mlx5_eq_table *table = &priv->eq_table;
326 int num_eqs = MLX5_CAP_GEN(dev, max_num_eqs) ?
327 MLX5_CAP_GEN(dev, max_num_eqs) :
328 1 << MLX5_CAP_GEN(dev, log_max_eq);
329 int nvec;
330 int err;
331
332 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
333 MLX5_EQ_VEC_COMP_BASE;
334 nvec = min_t(int, nvec, num_eqs);
335 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
336 return -ENOMEM;
337
338 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
339 if (!priv->irq_info)
340 return -ENOMEM;
341
342 nvec = pci_alloc_irq_vectors(dev->pdev,
343 MLX5_EQ_VEC_COMP_BASE + 1, nvec,
344 PCI_IRQ_MSIX);
345 if (nvec < 0) {
346 err = nvec;
347 goto err_free_irq_info;
348 }
349
350 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
351
352 return 0;
353
354 err_free_irq_info:
355 kfree(priv->irq_info);
356 return err;
357 }
358
mlx5_free_irq_vectors(struct mlx5_core_dev * dev)359 static void mlx5_free_irq_vectors(struct mlx5_core_dev *dev)
360 {
361 struct mlx5_priv *priv = &dev->priv;
362
363 pci_free_irq_vectors(dev->pdev);
364 kfree(priv->irq_info);
365 }
366
367 struct mlx5_reg_host_endianness {
368 u8 he;
369 u8 rsvd[15];
370 };
371
372 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
373
374 enum {
375 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
376 MLX5_DEV_CAP_FLAG_DCT,
377 };
378
to_fw_pkey_sz(struct mlx5_core_dev * dev,u32 size)379 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
380 {
381 switch (size) {
382 case 128:
383 return 0;
384 case 256:
385 return 1;
386 case 512:
387 return 2;
388 case 1024:
389 return 3;
390 case 2048:
391 return 4;
392 case 4096:
393 return 5;
394 default:
395 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
396 return 0;
397 }
398 }
399
mlx5_core_get_caps_mode(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type,enum mlx5_cap_mode cap_mode)400 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
401 enum mlx5_cap_type cap_type,
402 enum mlx5_cap_mode cap_mode)
403 {
404 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
405 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
406 void *out, *hca_caps;
407 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
408 int err;
409
410 memset(in, 0, sizeof(in));
411 out = kzalloc(out_sz, GFP_KERNEL);
412 if (!out)
413 return -ENOMEM;
414
415 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
416 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
417 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
418 if (err) {
419 mlx5_core_warn(dev,
420 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
421 cap_type, cap_mode, err);
422 goto query_ex;
423 }
424
425 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
426
427 switch (cap_mode) {
428 case HCA_CAP_OPMOD_GET_MAX:
429 memcpy(dev->caps.hca_max[cap_type], hca_caps,
430 MLX5_UN_SZ_BYTES(hca_cap_union));
431 break;
432 case HCA_CAP_OPMOD_GET_CUR:
433 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
434 MLX5_UN_SZ_BYTES(hca_cap_union));
435 break;
436 default:
437 mlx5_core_warn(dev,
438 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
439 cap_type, cap_mode);
440 err = -EINVAL;
441 break;
442 }
443 query_ex:
444 kfree(out);
445 return err;
446 }
447
mlx5_core_get_caps(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type)448 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
449 {
450 int ret;
451
452 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
453 if (ret)
454 return ret;
455 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
456 }
457
set_caps(struct mlx5_core_dev * dev,void * in,int in_sz,int opmod)458 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
459 {
460 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
461
462 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
463 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
464 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
465 }
466
handle_hca_cap_atomic(struct mlx5_core_dev * dev)467 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
468 {
469 void *set_ctx;
470 void *set_hca_cap;
471 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
472 int req_endianness;
473 int err;
474
475 if (MLX5_CAP_GEN(dev, atomic)) {
476 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
477 if (err)
478 return err;
479 } else {
480 return 0;
481 }
482
483 req_endianness =
484 MLX5_CAP_ATOMIC(dev,
485 supported_atomic_req_8B_endianness_mode_1);
486
487 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
488 return 0;
489
490 set_ctx = kzalloc(set_sz, GFP_KERNEL);
491 if (!set_ctx)
492 return -ENOMEM;
493
494 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
495
496 /* Set requestor to host endianness */
497 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
498 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
499
500 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
501
502 kfree(set_ctx);
503 return err;
504 }
505
handle_hca_cap(struct mlx5_core_dev * dev)506 static int handle_hca_cap(struct mlx5_core_dev *dev)
507 {
508 void *set_ctx = NULL;
509 struct mlx5_profile *prof = dev->profile;
510 int err = -ENOMEM;
511 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
512 void *set_hca_cap;
513
514 set_ctx = kzalloc(set_sz, GFP_KERNEL);
515 if (!set_ctx)
516 goto query_ex;
517
518 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
519 if (err)
520 goto query_ex;
521
522 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
523 capability);
524 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
525 MLX5_ST_SZ_BYTES(cmd_hca_cap));
526
527 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
528 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
529 128);
530 /* we limit the size of the pkey table to 128 entries for now */
531 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
532 to_fw_pkey_sz(dev, 128));
533
534 /* Check log_max_qp from HCA caps to set in current profile */
535 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
536 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
537 profile[prof_sel].log_max_qp,
538 MLX5_CAP_GEN_MAX(dev, log_max_qp));
539 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
540 }
541 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
542 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
543 prof->log_max_qp);
544
545 /* disable cmdif checksum */
546 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
547
548 /* Enable 4K UAR only when HCA supports it and page size is bigger
549 * than 4K.
550 */
551 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
552 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
553
554 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
555
556 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
557 MLX5_SET(cmd_hca_cap,
558 set_hca_cap,
559 cache_line_128byte,
560 cache_line_size() >= 128 ? 1 : 0);
561
562 if (MLX5_CAP_GEN_MAX(dev, dct))
563 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
564
565 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
566 MLX5_SET(cmd_hca_cap,
567 set_hca_cap,
568 num_vhca_ports,
569 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
570
571 err = set_caps(dev, set_ctx, set_sz,
572 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
573
574 query_ex:
575 kfree(set_ctx);
576 return err;
577 }
578
set_hca_ctrl(struct mlx5_core_dev * dev)579 static int set_hca_ctrl(struct mlx5_core_dev *dev)
580 {
581 struct mlx5_reg_host_endianness he_in;
582 struct mlx5_reg_host_endianness he_out;
583 int err;
584
585 if (!mlx5_core_is_pf(dev))
586 return 0;
587
588 memset(&he_in, 0, sizeof(he_in));
589 he_in.he = MLX5_SET_HOST_ENDIANNESS;
590 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
591 &he_out, sizeof(he_out),
592 MLX5_REG_HOST_ENDIANNESS, 0, 1);
593 return err;
594 }
595
mlx5_core_set_hca_defaults(struct mlx5_core_dev * dev)596 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
597 {
598 int ret = 0;
599
600 /* Disable local_lb by default */
601 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
602 ret = mlx5_nic_vport_update_local_lb(dev, false);
603
604 return ret;
605 }
606
mlx5_core_enable_hca(struct mlx5_core_dev * dev,u16 func_id)607 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
608 {
609 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
610 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
611
612 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
613 MLX5_SET(enable_hca_in, in, function_id, func_id);
614 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
615 }
616
mlx5_core_disable_hca(struct mlx5_core_dev * dev,u16 func_id)617 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
618 {
619 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
620 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
621
622 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
623 MLX5_SET(disable_hca_in, in, function_id, func_id);
624 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
625 }
626
mlx5_read_internal_timer(struct mlx5_core_dev * dev)627 u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev)
628 {
629 u32 timer_h, timer_h1, timer_l;
630
631 timer_h = ioread32be(&dev->iseg->internal_timer_h);
632 timer_l = ioread32be(&dev->iseg->internal_timer_l);
633 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
634 if (timer_h != timer_h1) /* wrap around */
635 timer_l = ioread32be(&dev->iseg->internal_timer_l);
636
637 return (u64)timer_l | (u64)timer_h1 << 32;
638 }
639
mlx5_irq_set_affinity_hint(struct mlx5_core_dev * mdev,int i)640 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
641 {
642 struct mlx5_priv *priv = &mdev->priv;
643 int irq = pci_irq_vector(mdev->pdev, MLX5_EQ_VEC_COMP_BASE + i);
644
645 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
646 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
647 return -ENOMEM;
648 }
649
650 cpumask_set_cpu(cpumask_local_spread(i, priv->numa_node),
651 priv->irq_info[i].mask);
652
653 if (IS_ENABLED(CONFIG_SMP) &&
654 irq_set_affinity_hint(irq, priv->irq_info[i].mask))
655 mlx5_core_warn(mdev, "irq_set_affinity_hint failed, irq 0x%.4x", irq);
656
657 return 0;
658 }
659
mlx5_irq_clear_affinity_hint(struct mlx5_core_dev * mdev,int i)660 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
661 {
662 struct mlx5_priv *priv = &mdev->priv;
663 int irq = pci_irq_vector(mdev->pdev, MLX5_EQ_VEC_COMP_BASE + i);
664
665 irq_set_affinity_hint(irq, NULL);
666 free_cpumask_var(priv->irq_info[i].mask);
667 }
668
mlx5_irq_set_affinity_hints(struct mlx5_core_dev * mdev)669 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
670 {
671 int err;
672 int i;
673
674 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
675 err = mlx5_irq_set_affinity_hint(mdev, i);
676 if (err)
677 goto err_out;
678 }
679
680 return 0;
681
682 err_out:
683 for (i--; i >= 0; i--)
684 mlx5_irq_clear_affinity_hint(mdev, i);
685
686 return err;
687 }
688
mlx5_irq_clear_affinity_hints(struct mlx5_core_dev * mdev)689 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
690 {
691 int i;
692
693 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
694 mlx5_irq_clear_affinity_hint(mdev, i);
695 }
696
mlx5_vector2eqn(struct mlx5_core_dev * dev,int vector,int * eqn,unsigned int * irqn)697 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
698 unsigned int *irqn)
699 {
700 struct mlx5_eq_table *table = &dev->priv.eq_table;
701 struct mlx5_eq *eq, *n;
702 int err = -ENOENT;
703
704 spin_lock(&table->lock);
705 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
706 if (eq->index == vector) {
707 *eqn = eq->eqn;
708 *irqn = eq->irqn;
709 err = 0;
710 break;
711 }
712 }
713 spin_unlock(&table->lock);
714
715 return err;
716 }
717 EXPORT_SYMBOL(mlx5_vector2eqn);
718
mlx5_eqn2eq(struct mlx5_core_dev * dev,int eqn)719 struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn)
720 {
721 struct mlx5_eq_table *table = &dev->priv.eq_table;
722 struct mlx5_eq *eq;
723
724 spin_lock(&table->lock);
725 list_for_each_entry(eq, &table->comp_eqs_list, list)
726 if (eq->eqn == eqn) {
727 spin_unlock(&table->lock);
728 return eq;
729 }
730
731 spin_unlock(&table->lock);
732
733 return ERR_PTR(-ENOENT);
734 }
735
free_comp_eqs(struct mlx5_core_dev * dev)736 static void free_comp_eqs(struct mlx5_core_dev *dev)
737 {
738 struct mlx5_eq_table *table = &dev->priv.eq_table;
739 struct mlx5_eq *eq, *n;
740
741 #ifdef CONFIG_RFS_ACCEL
742 if (dev->rmap) {
743 free_irq_cpu_rmap(dev->rmap);
744 dev->rmap = NULL;
745 }
746 #endif
747 spin_lock(&table->lock);
748 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
749 list_del(&eq->list);
750 spin_unlock(&table->lock);
751 if (mlx5_destroy_unmap_eq(dev, eq))
752 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
753 eq->eqn);
754 kfree(eq);
755 spin_lock(&table->lock);
756 }
757 spin_unlock(&table->lock);
758 }
759
alloc_comp_eqs(struct mlx5_core_dev * dev)760 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
761 {
762 struct mlx5_eq_table *table = &dev->priv.eq_table;
763 char name[MLX5_MAX_IRQ_NAME];
764 struct mlx5_eq *eq;
765 int ncomp_vec;
766 int nent;
767 int err;
768 int i;
769
770 INIT_LIST_HEAD(&table->comp_eqs_list);
771 ncomp_vec = table->num_comp_vectors;
772 nent = MLX5_COMP_EQ_SIZE;
773 #ifdef CONFIG_RFS_ACCEL
774 dev->rmap = alloc_irq_cpu_rmap(ncomp_vec);
775 if (!dev->rmap)
776 return -ENOMEM;
777 #endif
778 for (i = 0; i < ncomp_vec; i++) {
779 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
780 if (!eq) {
781 err = -ENOMEM;
782 goto clean;
783 }
784
785 #ifdef CONFIG_RFS_ACCEL
786 irq_cpu_rmap_add(dev->rmap, pci_irq_vector(dev->pdev,
787 MLX5_EQ_VEC_COMP_BASE + i));
788 #endif
789 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
790 err = mlx5_create_map_eq(dev, eq,
791 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
792 name, MLX5_EQ_TYPE_COMP);
793 if (err) {
794 kfree(eq);
795 goto clean;
796 }
797 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
798 eq->index = i;
799 spin_lock(&table->lock);
800 list_add_tail(&eq->list, &table->comp_eqs_list);
801 spin_unlock(&table->lock);
802 }
803
804 return 0;
805
806 clean:
807 free_comp_eqs(dev);
808 return err;
809 }
810
mlx5_core_set_issi(struct mlx5_core_dev * dev)811 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
812 {
813 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
814 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
815 u32 sup_issi;
816 int err;
817
818 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
819 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in),
820 query_out, sizeof(query_out));
821 if (err) {
822 u32 syndrome;
823 u8 status;
824
825 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
826 if (!status || syndrome == MLX5_DRIVER_SYND) {
827 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
828 err, status, syndrome);
829 return err;
830 }
831
832 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
833 dev->issi = 0;
834 return 0;
835 }
836
837 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
838
839 if (sup_issi & (1 << 1)) {
840 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
841 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
842
843 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
844 MLX5_SET(set_issi_in, set_in, current_issi, 1);
845 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in),
846 set_out, sizeof(set_out));
847 if (err) {
848 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
849 err);
850 return err;
851 }
852
853 dev->issi = 1;
854
855 return 0;
856 } else if (sup_issi & (1 << 0) || !sup_issi) {
857 return 0;
858 }
859
860 return -EOPNOTSUPP;
861 }
862
mlx5_pci_init(struct mlx5_core_dev * dev,struct mlx5_priv * priv)863 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
864 {
865 struct pci_dev *pdev = dev->pdev;
866 int err = 0;
867
868 pci_set_drvdata(dev->pdev, dev);
869 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
870 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
871
872 mutex_init(&priv->pgdir_mutex);
873 INIT_LIST_HEAD(&priv->pgdir_list);
874 spin_lock_init(&priv->mkey_lock);
875
876 mutex_init(&priv->alloc_mutex);
877
878 priv->numa_node = dev_to_node(&dev->pdev->dev);
879
880 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
881 if (!priv->dbg_root) {
882 dev_err(&pdev->dev, "Cannot create debugfs dir, aborting\n");
883 return -ENOMEM;
884 }
885
886 err = mlx5_pci_enable_device(dev);
887 if (err) {
888 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
889 goto err_dbg;
890 }
891
892 err = request_bar(pdev);
893 if (err) {
894 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
895 goto err_disable;
896 }
897
898 pci_set_master(pdev);
899
900 err = set_dma_caps(pdev);
901 if (err) {
902 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
903 goto err_clr_master;
904 }
905
906 dev->iseg_base = pci_resource_start(dev->pdev, 0);
907 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
908 if (!dev->iseg) {
909 err = -ENOMEM;
910 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
911 goto err_clr_master;
912 }
913
914 return 0;
915
916 err_clr_master:
917 pci_clear_master(dev->pdev);
918 release_bar(dev->pdev);
919 err_disable:
920 mlx5_pci_disable_device(dev);
921
922 err_dbg:
923 debugfs_remove(priv->dbg_root);
924 return err;
925 }
926
mlx5_pci_close(struct mlx5_core_dev * dev,struct mlx5_priv * priv)927 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
928 {
929 iounmap(dev->iseg);
930 pci_clear_master(dev->pdev);
931 release_bar(dev->pdev);
932 mlx5_pci_disable_device(dev);
933 debugfs_remove_recursive(priv->dbg_root);
934 }
935
mlx5_init_once(struct mlx5_core_dev * dev,struct mlx5_priv * priv)936 static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
937 {
938 struct pci_dev *pdev = dev->pdev;
939 int err;
940
941 err = mlx5_query_board_id(dev);
942 if (err) {
943 dev_err(&pdev->dev, "query board id failed\n");
944 goto out;
945 }
946
947 err = mlx5_eq_init(dev);
948 if (err) {
949 dev_err(&pdev->dev, "failed to initialize eq\n");
950 goto out;
951 }
952
953 err = mlx5_cq_debugfs_init(dev);
954 if (err) {
955 dev_err(&pdev->dev, "failed to initialize cq debugfs\n");
956 goto err_eq_cleanup;
957 }
958
959 mlx5_init_qp_table(dev);
960
961 mlx5_init_srq_table(dev);
962
963 mlx5_init_mkey_table(dev);
964
965 mlx5_init_reserved_gids(dev);
966
967 mlx5_init_clock(dev);
968
969 dev->vxlan = mlx5_vxlan_create(dev);
970
971 err = mlx5_init_rl_table(dev);
972 if (err) {
973 dev_err(&pdev->dev, "Failed to init rate limiting\n");
974 goto err_tables_cleanup;
975 }
976
977 err = mlx5_mpfs_init(dev);
978 if (err) {
979 dev_err(&pdev->dev, "Failed to init l2 table %d\n", err);
980 goto err_rl_cleanup;
981 }
982
983 err = mlx5_eswitch_init(dev);
984 if (err) {
985 dev_err(&pdev->dev, "Failed to init eswitch %d\n", err);
986 goto err_mpfs_cleanup;
987 }
988
989 err = mlx5_sriov_init(dev);
990 if (err) {
991 dev_err(&pdev->dev, "Failed to init sriov %d\n", err);
992 goto err_eswitch_cleanup;
993 }
994
995 err = mlx5_fpga_init(dev);
996 if (err) {
997 dev_err(&pdev->dev, "Failed to init fpga device %d\n", err);
998 goto err_sriov_cleanup;
999 }
1000
1001 dev->tracer = mlx5_fw_tracer_create(dev);
1002
1003 return 0;
1004
1005 err_sriov_cleanup:
1006 mlx5_sriov_cleanup(dev);
1007 err_eswitch_cleanup:
1008 mlx5_eswitch_cleanup(dev->priv.eswitch);
1009 err_mpfs_cleanup:
1010 mlx5_mpfs_cleanup(dev);
1011 err_rl_cleanup:
1012 mlx5_cleanup_rl_table(dev);
1013 err_tables_cleanup:
1014 mlx5_vxlan_destroy(dev->vxlan);
1015 mlx5_cleanup_mkey_table(dev);
1016 mlx5_cleanup_srq_table(dev);
1017 mlx5_cleanup_qp_table(dev);
1018 mlx5_cq_debugfs_cleanup(dev);
1019
1020 err_eq_cleanup:
1021 mlx5_eq_cleanup(dev);
1022
1023 out:
1024 return err;
1025 }
1026
mlx5_cleanup_once(struct mlx5_core_dev * dev)1027 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
1028 {
1029 mlx5_fw_tracer_destroy(dev->tracer);
1030 mlx5_fpga_cleanup(dev);
1031 mlx5_sriov_cleanup(dev);
1032 mlx5_eswitch_cleanup(dev->priv.eswitch);
1033 mlx5_mpfs_cleanup(dev);
1034 mlx5_cleanup_rl_table(dev);
1035 mlx5_vxlan_destroy(dev->vxlan);
1036 mlx5_cleanup_clock(dev);
1037 mlx5_cleanup_reserved_gids(dev);
1038 mlx5_cleanup_mkey_table(dev);
1039 mlx5_cleanup_srq_table(dev);
1040 mlx5_cleanup_qp_table(dev);
1041 mlx5_cq_debugfs_cleanup(dev);
1042 mlx5_eq_cleanup(dev);
1043 }
1044
mlx5_load_one(struct mlx5_core_dev * dev,struct mlx5_priv * priv,bool boot)1045 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1046 bool boot)
1047 {
1048 struct pci_dev *pdev = dev->pdev;
1049 int err;
1050
1051 mutex_lock(&dev->intf_state_mutex);
1052 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1053 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
1054 __func__);
1055 goto out;
1056 }
1057
1058 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1059 fw_rev_min(dev), fw_rev_sub(dev));
1060
1061 /* Only PFs hold the relevant PCIe information for this query */
1062 if (mlx5_core_is_pf(dev))
1063 pcie_print_link_status(dev->pdev);
1064
1065 /* on load removing any previous indication of internal error, device is
1066 * up
1067 */
1068 dev->state = MLX5_DEVICE_STATE_UP;
1069
1070 /* wait for firmware to accept initialization segments configurations
1071 */
1072 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI);
1073 if (err) {
1074 dev_err(&dev->pdev->dev, "Firmware over %d MS in pre-initializing state, aborting\n",
1075 FW_PRE_INIT_TIMEOUT_MILI);
1076 goto out_err;
1077 }
1078
1079 err = mlx5_cmd_init(dev);
1080 if (err) {
1081 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
1082 goto out_err;
1083 }
1084
1085 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
1086 if (err) {
1087 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
1088 FW_INIT_TIMEOUT_MILI);
1089 goto err_cmd_cleanup;
1090 }
1091
1092 err = mlx5_core_enable_hca(dev, 0);
1093 if (err) {
1094 dev_err(&pdev->dev, "enable hca failed\n");
1095 goto err_cmd_cleanup;
1096 }
1097
1098 err = mlx5_core_set_issi(dev);
1099 if (err) {
1100 dev_err(&pdev->dev, "failed to set issi\n");
1101 goto err_disable_hca;
1102 }
1103
1104 err = mlx5_satisfy_startup_pages(dev, 1);
1105 if (err) {
1106 dev_err(&pdev->dev, "failed to allocate boot pages\n");
1107 goto err_disable_hca;
1108 }
1109
1110 err = set_hca_ctrl(dev);
1111 if (err) {
1112 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
1113 goto reclaim_boot_pages;
1114 }
1115
1116 err = handle_hca_cap(dev);
1117 if (err) {
1118 dev_err(&pdev->dev, "handle_hca_cap failed\n");
1119 goto reclaim_boot_pages;
1120 }
1121
1122 err = handle_hca_cap_atomic(dev);
1123 if (err) {
1124 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
1125 goto reclaim_boot_pages;
1126 }
1127
1128 err = mlx5_satisfy_startup_pages(dev, 0);
1129 if (err) {
1130 dev_err(&pdev->dev, "failed to allocate init pages\n");
1131 goto reclaim_boot_pages;
1132 }
1133
1134 err = mlx5_pagealloc_start(dev);
1135 if (err) {
1136 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
1137 goto reclaim_boot_pages;
1138 }
1139
1140 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1141 if (err) {
1142 dev_err(&pdev->dev, "init hca failed\n");
1143 goto err_pagealloc_stop;
1144 }
1145
1146 mlx5_set_driver_version(dev);
1147
1148 mlx5_start_health_poll(dev);
1149
1150 err = mlx5_query_hca_caps(dev);
1151 if (err) {
1152 dev_err(&pdev->dev, "query hca failed\n");
1153 goto err_stop_poll;
1154 }
1155
1156 if (boot) {
1157 err = mlx5_init_once(dev, priv);
1158 if (err) {
1159 dev_err(&pdev->dev, "sw objs init failed\n");
1160 goto err_stop_poll;
1161 }
1162 }
1163
1164 err = mlx5_alloc_irq_vectors(dev);
1165 if (err) {
1166 dev_err(&pdev->dev, "alloc irq vectors failed\n");
1167 goto err_cleanup_once;
1168 }
1169
1170 dev->priv.uar = mlx5_get_uars_page(dev);
1171 if (IS_ERR(dev->priv.uar)) {
1172 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
1173 err = PTR_ERR(dev->priv.uar);
1174 goto err_disable_msix;
1175 }
1176
1177 err = mlx5_start_eqs(dev);
1178 if (err) {
1179 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1180 goto err_put_uars;
1181 }
1182
1183 err = mlx5_fw_tracer_init(dev->tracer);
1184 if (err) {
1185 dev_err(&pdev->dev, "Failed to init FW tracer\n");
1186 goto err_fw_tracer;
1187 }
1188
1189 err = alloc_comp_eqs(dev);
1190 if (err) {
1191 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1192 goto err_comp_eqs;
1193 }
1194
1195 err = mlx5_irq_set_affinity_hints(dev);
1196 if (err) {
1197 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
1198 goto err_affinity_hints;
1199 }
1200
1201 err = mlx5_fpga_device_start(dev);
1202 if (err) {
1203 dev_err(&pdev->dev, "fpga device start failed %d\n", err);
1204 goto err_fpga_start;
1205 }
1206
1207 err = mlx5_accel_ipsec_init(dev);
1208 if (err) {
1209 dev_err(&pdev->dev, "IPSec device start failed %d\n", err);
1210 goto err_ipsec_start;
1211 }
1212
1213 err = mlx5_accel_tls_init(dev);
1214 if (err) {
1215 dev_err(&pdev->dev, "TLS device start failed %d\n", err);
1216 goto err_tls_start;
1217 }
1218
1219 err = mlx5_init_fs(dev);
1220 if (err) {
1221 dev_err(&pdev->dev, "Failed to init flow steering\n");
1222 goto err_fs;
1223 }
1224
1225 err = mlx5_core_set_hca_defaults(dev);
1226 if (err) {
1227 dev_err(&pdev->dev, "Failed to set hca defaults\n");
1228 goto err_fs;
1229 }
1230
1231 err = mlx5_sriov_attach(dev);
1232 if (err) {
1233 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1234 goto err_sriov;
1235 }
1236
1237 if (mlx5_device_registered(dev)) {
1238 mlx5_attach_device(dev);
1239 } else {
1240 err = mlx5_register_device(dev);
1241 if (err) {
1242 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1243 goto err_reg_dev;
1244 }
1245 }
1246
1247 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1248 out:
1249 mutex_unlock(&dev->intf_state_mutex);
1250
1251 return 0;
1252
1253 err_reg_dev:
1254 mlx5_sriov_detach(dev);
1255
1256 err_sriov:
1257 mlx5_cleanup_fs(dev);
1258
1259 err_fs:
1260 mlx5_accel_tls_cleanup(dev);
1261
1262 err_tls_start:
1263 mlx5_accel_ipsec_cleanup(dev);
1264
1265 err_ipsec_start:
1266 mlx5_fpga_device_stop(dev);
1267
1268 err_fpga_start:
1269 mlx5_irq_clear_affinity_hints(dev);
1270
1271 err_affinity_hints:
1272 free_comp_eqs(dev);
1273
1274 err_comp_eqs:
1275 mlx5_fw_tracer_cleanup(dev->tracer);
1276
1277 err_fw_tracer:
1278 mlx5_stop_eqs(dev);
1279
1280 err_put_uars:
1281 mlx5_put_uars_page(dev, priv->uar);
1282
1283 err_disable_msix:
1284 mlx5_free_irq_vectors(dev);
1285
1286 err_cleanup_once:
1287 if (boot)
1288 mlx5_cleanup_once(dev);
1289
1290 err_stop_poll:
1291 mlx5_stop_health_poll(dev, boot);
1292 if (mlx5_cmd_teardown_hca(dev)) {
1293 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1294 goto out_err;
1295 }
1296
1297 err_pagealloc_stop:
1298 mlx5_pagealloc_stop(dev);
1299
1300 reclaim_boot_pages:
1301 mlx5_reclaim_startup_pages(dev);
1302
1303 err_disable_hca:
1304 mlx5_core_disable_hca(dev, 0);
1305
1306 err_cmd_cleanup:
1307 mlx5_cmd_cleanup(dev);
1308
1309 out_err:
1310 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1311 mutex_unlock(&dev->intf_state_mutex);
1312
1313 return err;
1314 }
1315
mlx5_unload_one(struct mlx5_core_dev * dev,struct mlx5_priv * priv,bool cleanup)1316 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1317 bool cleanup)
1318 {
1319 int err = 0;
1320
1321 if (cleanup)
1322 mlx5_drain_health_recovery(dev);
1323
1324 mutex_lock(&dev->intf_state_mutex);
1325 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1326 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1327 __func__);
1328 if (cleanup)
1329 mlx5_cleanup_once(dev);
1330 goto out;
1331 }
1332
1333 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1334
1335 if (mlx5_device_registered(dev))
1336 mlx5_detach_device(dev);
1337
1338 mlx5_sriov_detach(dev);
1339 mlx5_cleanup_fs(dev);
1340 mlx5_accel_ipsec_cleanup(dev);
1341 mlx5_accel_tls_cleanup(dev);
1342 mlx5_fpga_device_stop(dev);
1343 mlx5_irq_clear_affinity_hints(dev);
1344 free_comp_eqs(dev);
1345 mlx5_fw_tracer_cleanup(dev->tracer);
1346 mlx5_stop_eqs(dev);
1347 mlx5_put_uars_page(dev, priv->uar);
1348 mlx5_free_irq_vectors(dev);
1349 if (cleanup)
1350 mlx5_cleanup_once(dev);
1351 mlx5_stop_health_poll(dev, cleanup);
1352 err = mlx5_cmd_teardown_hca(dev);
1353 if (err) {
1354 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1355 goto out;
1356 }
1357 mlx5_pagealloc_stop(dev);
1358 mlx5_reclaim_startup_pages(dev);
1359 mlx5_core_disable_hca(dev, 0);
1360 mlx5_cmd_cleanup(dev);
1361
1362 out:
1363 mutex_unlock(&dev->intf_state_mutex);
1364 return err;
1365 }
1366
1367 struct mlx5_core_event_handler {
1368 void (*event)(struct mlx5_core_dev *dev,
1369 enum mlx5_dev_event event,
1370 void *data);
1371 };
1372
1373 static const struct devlink_ops mlx5_devlink_ops = {
1374 #ifdef CONFIG_MLX5_ESWITCH
1375 .eswitch_mode_set = mlx5_devlink_eswitch_mode_set,
1376 .eswitch_mode_get = mlx5_devlink_eswitch_mode_get,
1377 .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set,
1378 .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get,
1379 .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set,
1380 .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get,
1381 #endif
1382 };
1383
1384 #define MLX5_IB_MOD "mlx5_ib"
init_one(struct pci_dev * pdev,const struct pci_device_id * id)1385 static int init_one(struct pci_dev *pdev,
1386 const struct pci_device_id *id)
1387 {
1388 struct mlx5_core_dev *dev;
1389 struct devlink *devlink;
1390 struct mlx5_priv *priv;
1391 int err;
1392
1393 devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev));
1394 if (!devlink) {
1395 dev_err(&pdev->dev, "kzalloc failed\n");
1396 return -ENOMEM;
1397 }
1398
1399 dev = devlink_priv(devlink);
1400 priv = &dev->priv;
1401 priv->pci_dev_data = id->driver_data;
1402
1403 pci_set_drvdata(pdev, dev);
1404
1405 dev->pdev = pdev;
1406 dev->event = mlx5_core_event;
1407 dev->profile = &profile[prof_sel];
1408
1409 INIT_LIST_HEAD(&priv->ctx_list);
1410 spin_lock_init(&priv->ctx_lock);
1411 mutex_init(&dev->pci_status_mutex);
1412 mutex_init(&dev->intf_state_mutex);
1413
1414 INIT_LIST_HEAD(&priv->waiting_events_list);
1415 priv->is_accum_events = false;
1416
1417 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1418 err = init_srcu_struct(&priv->pfault_srcu);
1419 if (err) {
1420 dev_err(&pdev->dev, "init_srcu_struct failed with error code %d\n",
1421 err);
1422 goto clean_dev;
1423 }
1424 #endif
1425 mutex_init(&priv->bfregs.reg_head.lock);
1426 mutex_init(&priv->bfregs.wc_head.lock);
1427 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1428 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1429
1430 err = mlx5_pci_init(dev, priv);
1431 if (err) {
1432 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1433 goto clean_srcu;
1434 }
1435
1436 err = mlx5_health_init(dev);
1437 if (err) {
1438 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1439 goto close_pci;
1440 }
1441
1442 mlx5_pagealloc_init(dev);
1443
1444 err = mlx5_load_one(dev, priv, true);
1445 if (err) {
1446 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
1447 goto clean_health;
1448 }
1449
1450 request_module_nowait(MLX5_IB_MOD);
1451
1452 err = devlink_register(devlink, &pdev->dev);
1453 if (err)
1454 goto clean_load;
1455
1456 pci_save_state(pdev);
1457 return 0;
1458
1459 clean_load:
1460 mlx5_unload_one(dev, priv, true);
1461 clean_health:
1462 mlx5_pagealloc_cleanup(dev);
1463 mlx5_health_cleanup(dev);
1464 close_pci:
1465 mlx5_pci_close(dev, priv);
1466 clean_srcu:
1467 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1468 cleanup_srcu_struct(&priv->pfault_srcu);
1469 clean_dev:
1470 #endif
1471 devlink_free(devlink);
1472
1473 return err;
1474 }
1475
remove_one(struct pci_dev * pdev)1476 static void remove_one(struct pci_dev *pdev)
1477 {
1478 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1479 struct devlink *devlink = priv_to_devlink(dev);
1480 struct mlx5_priv *priv = &dev->priv;
1481
1482 devlink_unregister(devlink);
1483 mlx5_unregister_device(dev);
1484
1485 if (mlx5_unload_one(dev, priv, true)) {
1486 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1487 mlx5_health_cleanup(dev);
1488 return;
1489 }
1490
1491 mlx5_pagealloc_cleanup(dev);
1492 mlx5_health_cleanup(dev);
1493 mlx5_pci_close(dev, priv);
1494 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1495 cleanup_srcu_struct(&priv->pfault_srcu);
1496 #endif
1497 devlink_free(devlink);
1498 }
1499
mlx5_pci_err_detected(struct pci_dev * pdev,pci_channel_state_t state)1500 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1501 pci_channel_state_t state)
1502 {
1503 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1504 struct mlx5_priv *priv = &dev->priv;
1505
1506 dev_info(&pdev->dev, "%s was called\n", __func__);
1507
1508 mlx5_enter_error_state(dev, false);
1509 mlx5_unload_one(dev, priv, false);
1510 /* In case of kernel call drain the health wq */
1511 if (state) {
1512 mlx5_drain_health_wq(dev);
1513 mlx5_pci_disable_device(dev);
1514 }
1515
1516 return state == pci_channel_io_perm_failure ?
1517 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1518 }
1519
1520 /* wait for the device to show vital signs by waiting
1521 * for the health counter to start counting.
1522 */
wait_vital(struct pci_dev * pdev)1523 static int wait_vital(struct pci_dev *pdev)
1524 {
1525 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1526 struct mlx5_core_health *health = &dev->priv.health;
1527 const int niter = 100;
1528 u32 last_count = 0;
1529 u32 count;
1530 int i;
1531
1532 for (i = 0; i < niter; i++) {
1533 count = ioread32be(health->health_counter);
1534 if (count && count != 0xffffffff) {
1535 if (last_count && last_count != count) {
1536 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1537 return 0;
1538 }
1539 last_count = count;
1540 }
1541 msleep(50);
1542 }
1543
1544 return -ETIMEDOUT;
1545 }
1546
mlx5_pci_slot_reset(struct pci_dev * pdev)1547 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1548 {
1549 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1550 int err;
1551
1552 dev_info(&pdev->dev, "%s was called\n", __func__);
1553
1554 err = mlx5_pci_enable_device(dev);
1555 if (err) {
1556 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1557 , __func__, err);
1558 return PCI_ERS_RESULT_DISCONNECT;
1559 }
1560
1561 pci_set_master(pdev);
1562 pci_restore_state(pdev);
1563 pci_save_state(pdev);
1564
1565 if (wait_vital(pdev)) {
1566 dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__);
1567 return PCI_ERS_RESULT_DISCONNECT;
1568 }
1569
1570 return PCI_ERS_RESULT_RECOVERED;
1571 }
1572
mlx5_pci_resume(struct pci_dev * pdev)1573 static void mlx5_pci_resume(struct pci_dev *pdev)
1574 {
1575 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1576 struct mlx5_priv *priv = &dev->priv;
1577 int err;
1578
1579 dev_info(&pdev->dev, "%s was called\n", __func__);
1580
1581 err = mlx5_load_one(dev, priv, false);
1582 if (err)
1583 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1584 , __func__, err);
1585 else
1586 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1587 }
1588
1589 static const struct pci_error_handlers mlx5_err_handler = {
1590 .error_detected = mlx5_pci_err_detected,
1591 .slot_reset = mlx5_pci_slot_reset,
1592 .resume = mlx5_pci_resume
1593 };
1594
mlx5_try_fast_unload(struct mlx5_core_dev * dev)1595 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1596 {
1597 int ret;
1598
1599 if (!MLX5_CAP_GEN(dev, force_teardown)) {
1600 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n");
1601 return -EOPNOTSUPP;
1602 }
1603
1604 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1605 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1606 return -EAGAIN;
1607 }
1608
1609 /* Panic tear down fw command will stop the PCI bus communication
1610 * with the HCA, so the health polll is no longer needed.
1611 */
1612 mlx5_drain_health_wq(dev);
1613 mlx5_stop_health_poll(dev, false);
1614
1615 ret = mlx5_cmd_force_teardown_hca(dev);
1616 if (ret) {
1617 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1618 mlx5_start_health_poll(dev);
1619 return ret;
1620 }
1621
1622 mlx5_enter_error_state(dev, true);
1623
1624 /* Some platforms requiring freeing the IRQ's in the shutdown
1625 * flow. If they aren't freed they can't be allocated after
1626 * kexec. There is no need to cleanup the mlx5_core software
1627 * contexts.
1628 */
1629 mlx5_irq_clear_affinity_hints(dev);
1630 mlx5_core_eq_free_irqs(dev);
1631
1632 return 0;
1633 }
1634
shutdown(struct pci_dev * pdev)1635 static void shutdown(struct pci_dev *pdev)
1636 {
1637 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1638 struct mlx5_priv *priv = &dev->priv;
1639 int err;
1640
1641 dev_info(&pdev->dev, "Shutdown was called\n");
1642 err = mlx5_try_fast_unload(dev);
1643 if (err)
1644 mlx5_unload_one(dev, priv, false);
1645 mlx5_pci_disable_device(dev);
1646 }
1647
1648 static const struct pci_device_id mlx5_core_pci_table[] = {
1649 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1650 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1651 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1652 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1653 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1654 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1655 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1656 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1657 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1658 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1659 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1660 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1661 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1662 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1663 { 0, }
1664 };
1665
1666 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1667
mlx5_disable_device(struct mlx5_core_dev * dev)1668 void mlx5_disable_device(struct mlx5_core_dev *dev)
1669 {
1670 mlx5_pci_err_detected(dev->pdev, 0);
1671 }
1672
mlx5_recover_device(struct mlx5_core_dev * dev)1673 void mlx5_recover_device(struct mlx5_core_dev *dev)
1674 {
1675 mlx5_pci_disable_device(dev);
1676 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1677 mlx5_pci_resume(dev->pdev);
1678 }
1679
1680 static struct pci_driver mlx5_core_driver = {
1681 .name = DRIVER_NAME,
1682 .id_table = mlx5_core_pci_table,
1683 .probe = init_one,
1684 .remove = remove_one,
1685 .shutdown = shutdown,
1686 .err_handler = &mlx5_err_handler,
1687 .sriov_configure = mlx5_core_sriov_configure,
1688 };
1689
mlx5_core_verify_params(void)1690 static void mlx5_core_verify_params(void)
1691 {
1692 if (prof_sel >= ARRAY_SIZE(profile)) {
1693 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1694 prof_sel,
1695 ARRAY_SIZE(profile) - 1,
1696 MLX5_DEFAULT_PROF);
1697 prof_sel = MLX5_DEFAULT_PROF;
1698 }
1699 }
1700
init(void)1701 static int __init init(void)
1702 {
1703 int err;
1704
1705 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1706
1707 mlx5_core_verify_params();
1708 mlx5_fpga_ipsec_build_fs_cmds();
1709 mlx5_register_debugfs();
1710
1711 err = pci_register_driver(&mlx5_core_driver);
1712 if (err)
1713 goto err_debug;
1714
1715 #ifdef CONFIG_MLX5_CORE_EN
1716 mlx5e_init();
1717 #endif
1718
1719 return 0;
1720
1721 err_debug:
1722 mlx5_unregister_debugfs();
1723 return err;
1724 }
1725
cleanup(void)1726 static void __exit cleanup(void)
1727 {
1728 #ifdef CONFIG_MLX5_CORE_EN
1729 mlx5e_cleanup();
1730 #endif
1731 pci_unregister_driver(&mlx5_core_driver);
1732 mlx5_unregister_debugfs();
1733 }
1734
1735 module_init(init);
1736 module_exit(cleanup);
1737
