1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include <linux/mlx5/vport.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
52 #endif
53 #include <net/devlink.h>
54 #include "mlx5_core.h"
55 #include "lib/eq.h"
56 #include "fs_core.h"
57 #include "lib/mpfs.h"
58 #include "eswitch.h"
59 #include "devlink.h"
60 #include "lib/mlx5.h"
61 #include "fpga/core.h"
62 #include "fpga/ipsec.h"
63 #include "accel/ipsec.h"
64 #include "accel/tls.h"
65 #include "lib/clock.h"
66 #include "lib/vxlan.h"
67 #include "lib/geneve.h"
68 #include "lib/devcom.h"
69 #include "lib/pci_vsc.h"
70 #include "diag/fw_tracer.h"
71 #include "ecpf.h"
72 #include "lib/hv_vhca.h"
73
74 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
75 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
76 MODULE_LICENSE("Dual BSD/GPL");
77 MODULE_VERSION(DRIVER_VERSION);
78
79 unsigned int mlx5_core_debug_mask;
80 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
81 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
82
83 #define MLX5_DEFAULT_PROF 2
84 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
85 module_param_named(prof_sel, prof_sel, uint, 0444);
86 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
87
88 static u32 sw_owner_id[4];
89
90 enum {
91 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
92 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
93 };
94
95 static struct mlx5_profile profile[] = {
96 [0] = {
97 .mask = 0,
98 },
99 [1] = {
100 .mask = MLX5_PROF_MASK_QP_SIZE,
101 .log_max_qp = 12,
102 },
103 [2] = {
104 .mask = MLX5_PROF_MASK_QP_SIZE |
105 MLX5_PROF_MASK_MR_CACHE,
106 .log_max_qp = 18,
107 .mr_cache[0] = {
108 .size = 500,
109 .limit = 250
110 },
111 .mr_cache[1] = {
112 .size = 500,
113 .limit = 250
114 },
115 .mr_cache[2] = {
116 .size = 500,
117 .limit = 250
118 },
119 .mr_cache[3] = {
120 .size = 500,
121 .limit = 250
122 },
123 .mr_cache[4] = {
124 .size = 500,
125 .limit = 250
126 },
127 .mr_cache[5] = {
128 .size = 500,
129 .limit = 250
130 },
131 .mr_cache[6] = {
132 .size = 500,
133 .limit = 250
134 },
135 .mr_cache[7] = {
136 .size = 500,
137 .limit = 250
138 },
139 .mr_cache[8] = {
140 .size = 500,
141 .limit = 250
142 },
143 .mr_cache[9] = {
144 .size = 500,
145 .limit = 250
146 },
147 .mr_cache[10] = {
148 .size = 500,
149 .limit = 250
150 },
151 .mr_cache[11] = {
152 .size = 500,
153 .limit = 250
154 },
155 .mr_cache[12] = {
156 .size = 64,
157 .limit = 32
158 },
159 .mr_cache[13] = {
160 .size = 32,
161 .limit = 16
162 },
163 .mr_cache[14] = {
164 .size = 16,
165 .limit = 8
166 },
167 .mr_cache[15] = {
168 .size = 8,
169 .limit = 4
170 },
171 },
172 };
173
174 #define FW_INIT_TIMEOUT_MILI 2000
175 #define FW_INIT_WAIT_MS 2
176 #define FW_PRE_INIT_TIMEOUT_MILI 120000
177 #define FW_INIT_WARN_MESSAGE_INTERVAL 20000
178
wait_fw_init(struct mlx5_core_dev * dev,u32 max_wait_mili,u32 warn_time_mili)179 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
180 u32 warn_time_mili)
181 {
182 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
183 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
184 int err = 0;
185
186 BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL);
187
188 while (fw_initializing(dev)) {
189 if (time_after(jiffies, end)) {
190 err = -EBUSY;
191 break;
192 }
193 if (warn_time_mili && time_after(jiffies, warn)) {
194 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n",
195 jiffies_to_msecs(end - warn) / 1000);
196 warn = jiffies + msecs_to_jiffies(warn_time_mili);
197 }
198 msleep(FW_INIT_WAIT_MS);
199 }
200
201 return err;
202 }
203
mlx5_set_driver_version(struct mlx5_core_dev * dev)204 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
205 {
206 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
207 driver_version);
208 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0};
209 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0};
210 int remaining_size = driver_ver_sz;
211 char *string;
212
213 if (!MLX5_CAP_GEN(dev, driver_version))
214 return;
215
216 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
217
218 strncpy(string, "Linux", remaining_size);
219
220 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
221 strncat(string, ",", remaining_size);
222
223 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
224 strncat(string, DRIVER_NAME, remaining_size);
225
226 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
227 strncat(string, ",", remaining_size);
228
229 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
230 strncat(string, DRIVER_VERSION, remaining_size);
231
232 /*Send the command*/
233 MLX5_SET(set_driver_version_in, in, opcode,
234 MLX5_CMD_OP_SET_DRIVER_VERSION);
235
236 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
237 }
238
set_dma_caps(struct pci_dev * pdev)239 static int set_dma_caps(struct pci_dev *pdev)
240 {
241 int err;
242
243 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
244 if (err) {
245 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
246 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
247 if (err) {
248 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
249 return err;
250 }
251 }
252
253 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
254 if (err) {
255 dev_warn(&pdev->dev,
256 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
257 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
258 if (err) {
259 dev_err(&pdev->dev,
260 "Can't set consistent PCI DMA mask, aborting\n");
261 return err;
262 }
263 }
264
265 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
266 return err;
267 }
268
mlx5_pci_enable_device(struct mlx5_core_dev * dev)269 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
270 {
271 struct pci_dev *pdev = dev->pdev;
272 int err = 0;
273
274 mutex_lock(&dev->pci_status_mutex);
275 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
276 err = pci_enable_device(pdev);
277 if (!err)
278 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
279 }
280 mutex_unlock(&dev->pci_status_mutex);
281
282 return err;
283 }
284
mlx5_pci_disable_device(struct mlx5_core_dev * dev)285 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
286 {
287 struct pci_dev *pdev = dev->pdev;
288
289 mutex_lock(&dev->pci_status_mutex);
290 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
291 pci_disable_device(pdev);
292 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
293 }
294 mutex_unlock(&dev->pci_status_mutex);
295 }
296
request_bar(struct pci_dev * pdev)297 static int request_bar(struct pci_dev *pdev)
298 {
299 int err = 0;
300
301 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
302 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
303 return -ENODEV;
304 }
305
306 err = pci_request_regions(pdev, DRIVER_NAME);
307 if (err)
308 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
309
310 return err;
311 }
312
release_bar(struct pci_dev * pdev)313 static void release_bar(struct pci_dev *pdev)
314 {
315 pci_release_regions(pdev);
316 }
317
318 struct mlx5_reg_host_endianness {
319 u8 he;
320 u8 rsvd[15];
321 };
322
323 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
324
325 enum {
326 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
327 MLX5_DEV_CAP_FLAG_DCT,
328 };
329
to_fw_pkey_sz(struct mlx5_core_dev * dev,u32 size)330 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
331 {
332 switch (size) {
333 case 128:
334 return 0;
335 case 256:
336 return 1;
337 case 512:
338 return 2;
339 case 1024:
340 return 3;
341 case 2048:
342 return 4;
343 case 4096:
344 return 5;
345 default:
346 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
347 return 0;
348 }
349 }
350
mlx5_core_get_caps_mode(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type,enum mlx5_cap_mode cap_mode)351 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
352 enum mlx5_cap_type cap_type,
353 enum mlx5_cap_mode cap_mode)
354 {
355 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
356 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
357 void *out, *hca_caps;
358 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
359 int err;
360
361 memset(in, 0, sizeof(in));
362 out = kzalloc(out_sz, GFP_KERNEL);
363 if (!out)
364 return -ENOMEM;
365
366 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
367 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
368 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
369 if (err) {
370 mlx5_core_warn(dev,
371 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
372 cap_type, cap_mode, err);
373 goto query_ex;
374 }
375
376 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
377
378 switch (cap_mode) {
379 case HCA_CAP_OPMOD_GET_MAX:
380 memcpy(dev->caps.hca_max[cap_type], hca_caps,
381 MLX5_UN_SZ_BYTES(hca_cap_union));
382 break;
383 case HCA_CAP_OPMOD_GET_CUR:
384 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
385 MLX5_UN_SZ_BYTES(hca_cap_union));
386 break;
387 default:
388 mlx5_core_warn(dev,
389 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
390 cap_type, cap_mode);
391 err = -EINVAL;
392 break;
393 }
394 query_ex:
395 kfree(out);
396 return err;
397 }
398
mlx5_core_get_caps(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type)399 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
400 {
401 int ret;
402
403 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
404 if (ret)
405 return ret;
406 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
407 }
408
set_caps(struct mlx5_core_dev * dev,void * in,int in_sz,int opmod)409 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
410 {
411 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
412
413 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
414 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
415 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
416 }
417
handle_hca_cap_atomic(struct mlx5_core_dev * dev)418 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
419 {
420 void *set_ctx;
421 void *set_hca_cap;
422 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
423 int req_endianness;
424 int err;
425
426 if (MLX5_CAP_GEN(dev, atomic)) {
427 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
428 if (err)
429 return err;
430 } else {
431 return 0;
432 }
433
434 req_endianness =
435 MLX5_CAP_ATOMIC(dev,
436 supported_atomic_req_8B_endianness_mode_1);
437
438 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
439 return 0;
440
441 set_ctx = kzalloc(set_sz, GFP_KERNEL);
442 if (!set_ctx)
443 return -ENOMEM;
444
445 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
446
447 /* Set requestor to host endianness */
448 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
449 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
450
451 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
452
453 kfree(set_ctx);
454 return err;
455 }
456
handle_hca_cap_odp(struct mlx5_core_dev * dev)457 static int handle_hca_cap_odp(struct mlx5_core_dev *dev)
458 {
459 void *set_hca_cap;
460 void *set_ctx;
461 int set_sz;
462 bool do_set = false;
463 int err;
464
465 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
466 !MLX5_CAP_GEN(dev, pg))
467 return 0;
468
469 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
470 if (err)
471 return err;
472
473 set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
474 set_ctx = kzalloc(set_sz, GFP_KERNEL);
475 if (!set_ctx)
476 return -ENOMEM;
477
478 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
479 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP],
480 MLX5_ST_SZ_BYTES(odp_cap));
481
482 #define ODP_CAP_SET_MAX(dev, field) \
483 do { \
484 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
485 if (_res) { \
486 do_set = true; \
487 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
488 } \
489 } while (0)
490
491 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
492 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
493 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
494 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
495 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
496 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
497 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
498 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
499 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive);
500 ODP_CAP_SET_MAX(dev, dc_odp_caps.send);
501 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive);
502 ODP_CAP_SET_MAX(dev, dc_odp_caps.write);
503 ODP_CAP_SET_MAX(dev, dc_odp_caps.read);
504 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic);
505
506 if (do_set)
507 err = set_caps(dev, set_ctx, set_sz,
508 MLX5_SET_HCA_CAP_OP_MOD_ODP);
509
510 kfree(set_ctx);
511
512 return err;
513 }
514
handle_hca_cap(struct mlx5_core_dev * dev)515 static int handle_hca_cap(struct mlx5_core_dev *dev)
516 {
517 void *set_ctx = NULL;
518 struct mlx5_profile *prof = dev->profile;
519 int err = -ENOMEM;
520 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
521 void *set_hca_cap;
522
523 set_ctx = kzalloc(set_sz, GFP_KERNEL);
524 if (!set_ctx)
525 goto query_ex;
526
527 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
528 if (err)
529 goto query_ex;
530
531 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
532 capability);
533 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
534 MLX5_ST_SZ_BYTES(cmd_hca_cap));
535
536 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
537 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
538 128);
539 /* we limit the size of the pkey table to 128 entries for now */
540 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
541 to_fw_pkey_sz(dev, 128));
542
543 /* Check log_max_qp from HCA caps to set in current profile */
544 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
545 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
546 profile[prof_sel].log_max_qp,
547 MLX5_CAP_GEN_MAX(dev, log_max_qp));
548 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
549 }
550 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
551 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
552 prof->log_max_qp);
553
554 /* disable cmdif checksum */
555 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
556
557 /* Enable 4K UAR only when HCA supports it and page size is bigger
558 * than 4K.
559 */
560 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
561 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
562
563 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
564
565 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
566 MLX5_SET(cmd_hca_cap,
567 set_hca_cap,
568 cache_line_128byte,
569 cache_line_size() >= 128 ? 1 : 0);
570
571 if (MLX5_CAP_GEN_MAX(dev, dct))
572 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
573
574 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
575 MLX5_SET(cmd_hca_cap,
576 set_hca_cap,
577 num_vhca_ports,
578 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
579
580 err = set_caps(dev, set_ctx, set_sz,
581 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
582
583 query_ex:
584 kfree(set_ctx);
585 return err;
586 }
587
set_hca_cap(struct mlx5_core_dev * dev)588 static int set_hca_cap(struct mlx5_core_dev *dev)
589 {
590 int err;
591
592 err = handle_hca_cap(dev);
593 if (err) {
594 mlx5_core_err(dev, "handle_hca_cap failed\n");
595 goto out;
596 }
597
598 err = handle_hca_cap_atomic(dev);
599 if (err) {
600 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
601 goto out;
602 }
603
604 err = handle_hca_cap_odp(dev);
605 if (err) {
606 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
607 goto out;
608 }
609
610 out:
611 return err;
612 }
613
set_hca_ctrl(struct mlx5_core_dev * dev)614 static int set_hca_ctrl(struct mlx5_core_dev *dev)
615 {
616 struct mlx5_reg_host_endianness he_in;
617 struct mlx5_reg_host_endianness he_out;
618 int err;
619
620 if (!mlx5_core_is_pf(dev))
621 return 0;
622
623 memset(&he_in, 0, sizeof(he_in));
624 he_in.he = MLX5_SET_HOST_ENDIANNESS;
625 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
626 &he_out, sizeof(he_out),
627 MLX5_REG_HOST_ENDIANNESS, 0, 1);
628 return err;
629 }
630
mlx5_core_set_hca_defaults(struct mlx5_core_dev * dev)631 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
632 {
633 int ret = 0;
634
635 /* Disable local_lb by default */
636 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
637 ret = mlx5_nic_vport_update_local_lb(dev, false);
638
639 return ret;
640 }
641
mlx5_core_enable_hca(struct mlx5_core_dev * dev,u16 func_id)642 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
643 {
644 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
645 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
646
647 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
648 MLX5_SET(enable_hca_in, in, function_id, func_id);
649 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
650 dev->caps.embedded_cpu);
651 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
652 }
653
mlx5_core_disable_hca(struct mlx5_core_dev * dev,u16 func_id)654 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
655 {
656 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
657 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
658
659 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
660 MLX5_SET(disable_hca_in, in, function_id, func_id);
661 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
662 dev->caps.embedded_cpu);
663 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
664 }
665
mlx5_read_internal_timer(struct mlx5_core_dev * dev,struct ptp_system_timestamp * sts)666 u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev,
667 struct ptp_system_timestamp *sts)
668 {
669 u32 timer_h, timer_h1, timer_l;
670
671 timer_h = ioread32be(&dev->iseg->internal_timer_h);
672 ptp_read_system_prets(sts);
673 timer_l = ioread32be(&dev->iseg->internal_timer_l);
674 ptp_read_system_postts(sts);
675 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
676 if (timer_h != timer_h1) {
677 /* wrap around */
678 ptp_read_system_prets(sts);
679 timer_l = ioread32be(&dev->iseg->internal_timer_l);
680 ptp_read_system_postts(sts);
681 }
682
683 return (u64)timer_l | (u64)timer_h1 << 32;
684 }
685
mlx5_core_set_issi(struct mlx5_core_dev * dev)686 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
687 {
688 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
689 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
690 u32 sup_issi;
691 int err;
692
693 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
694 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in),
695 query_out, sizeof(query_out));
696 if (err) {
697 u32 syndrome;
698 u8 status;
699
700 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
701 if (!status || syndrome == MLX5_DRIVER_SYND) {
702 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
703 err, status, syndrome);
704 return err;
705 }
706
707 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
708 dev->issi = 0;
709 return 0;
710 }
711
712 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
713
714 if (sup_issi & (1 << 1)) {
715 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
716 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
717
718 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
719 MLX5_SET(set_issi_in, set_in, current_issi, 1);
720 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in),
721 set_out, sizeof(set_out));
722 if (err) {
723 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
724 err);
725 return err;
726 }
727
728 dev->issi = 1;
729
730 return 0;
731 } else if (sup_issi & (1 << 0) || !sup_issi) {
732 return 0;
733 }
734
735 return -EOPNOTSUPP;
736 }
737
mlx5_pci_init(struct mlx5_core_dev * dev,struct pci_dev * pdev,const struct pci_device_id * id)738 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
739 const struct pci_device_id *id)
740 {
741 struct mlx5_priv *priv = &dev->priv;
742 int err = 0;
743
744 mutex_init(&dev->pci_status_mutex);
745 pci_set_drvdata(dev->pdev, dev);
746
747 dev->bar_addr = pci_resource_start(pdev, 0);
748 priv->numa_node = dev_to_node(&dev->pdev->dev);
749
750 err = mlx5_pci_enable_device(dev);
751 if (err) {
752 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
753 return err;
754 }
755
756 err = request_bar(pdev);
757 if (err) {
758 mlx5_core_err(dev, "error requesting BARs, aborting\n");
759 goto err_disable;
760 }
761
762 pci_set_master(pdev);
763
764 err = set_dma_caps(pdev);
765 if (err) {
766 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
767 goto err_clr_master;
768 }
769
770 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
771 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
772 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
773 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
774
775 dev->iseg_base = dev->bar_addr;
776 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
777 if (!dev->iseg) {
778 err = -ENOMEM;
779 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
780 goto err_clr_master;
781 }
782
783 mlx5_pci_vsc_init(dev);
784
785 return 0;
786
787 err_clr_master:
788 pci_clear_master(dev->pdev);
789 release_bar(dev->pdev);
790 err_disable:
791 mlx5_pci_disable_device(dev);
792 return err;
793 }
794
mlx5_pci_close(struct mlx5_core_dev * dev)795 static void mlx5_pci_close(struct mlx5_core_dev *dev)
796 {
797 iounmap(dev->iseg);
798 pci_clear_master(dev->pdev);
799 release_bar(dev->pdev);
800 mlx5_pci_disable_device(dev);
801 }
802
mlx5_init_once(struct mlx5_core_dev * dev)803 static int mlx5_init_once(struct mlx5_core_dev *dev)
804 {
805 int err;
806
807 dev->priv.devcom = mlx5_devcom_register_device(dev);
808 if (IS_ERR(dev->priv.devcom))
809 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n",
810 dev->priv.devcom);
811
812 err = mlx5_query_board_id(dev);
813 if (err) {
814 mlx5_core_err(dev, "query board id failed\n");
815 goto err_devcom;
816 }
817
818 err = mlx5_irq_table_init(dev);
819 if (err) {
820 mlx5_core_err(dev, "failed to initialize irq table\n");
821 goto err_devcom;
822 }
823
824 err = mlx5_eq_table_init(dev);
825 if (err) {
826 mlx5_core_err(dev, "failed to initialize eq\n");
827 goto err_irq_cleanup;
828 }
829
830 err = mlx5_events_init(dev);
831 if (err) {
832 mlx5_core_err(dev, "failed to initialize events\n");
833 goto err_eq_cleanup;
834 }
835
836 mlx5_cq_debugfs_init(dev);
837
838 mlx5_init_qp_table(dev);
839
840 mlx5_init_mkey_table(dev);
841
842 mlx5_init_reserved_gids(dev);
843
844 mlx5_init_clock(dev);
845
846 dev->vxlan = mlx5_vxlan_create(dev);
847 dev->geneve = mlx5_geneve_create(dev);
848
849 err = mlx5_init_rl_table(dev);
850 if (err) {
851 mlx5_core_err(dev, "Failed to init rate limiting\n");
852 goto err_tables_cleanup;
853 }
854
855 err = mlx5_mpfs_init(dev);
856 if (err) {
857 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
858 goto err_rl_cleanup;
859 }
860
861 err = mlx5_sriov_init(dev);
862 if (err) {
863 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
864 goto err_mpfs_cleanup;
865 }
866
867 err = mlx5_eswitch_init(dev);
868 if (err) {
869 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
870 goto err_sriov_cleanup;
871 }
872
873 err = mlx5_fpga_init(dev);
874 if (err) {
875 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
876 goto err_eswitch_cleanup;
877 }
878
879 dev->dm = mlx5_dm_create(dev);
880 if (IS_ERR(dev->dm))
881 mlx5_core_warn(dev, "Failed to init device memory%d\n", err);
882
883 dev->tracer = mlx5_fw_tracer_create(dev);
884 dev->hv_vhca = mlx5_hv_vhca_create(dev);
885
886 return 0;
887
888 err_eswitch_cleanup:
889 mlx5_eswitch_cleanup(dev->priv.eswitch);
890 err_sriov_cleanup:
891 mlx5_sriov_cleanup(dev);
892 err_mpfs_cleanup:
893 mlx5_mpfs_cleanup(dev);
894 err_rl_cleanup:
895 mlx5_cleanup_rl_table(dev);
896 err_tables_cleanup:
897 mlx5_geneve_destroy(dev->geneve);
898 mlx5_vxlan_destroy(dev->vxlan);
899 mlx5_cleanup_mkey_table(dev);
900 mlx5_cleanup_qp_table(dev);
901 mlx5_cq_debugfs_cleanup(dev);
902 mlx5_events_cleanup(dev);
903 err_eq_cleanup:
904 mlx5_eq_table_cleanup(dev);
905 err_irq_cleanup:
906 mlx5_irq_table_cleanup(dev);
907 err_devcom:
908 mlx5_devcom_unregister_device(dev->priv.devcom);
909
910 return err;
911 }
912
mlx5_cleanup_once(struct mlx5_core_dev * dev)913 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
914 {
915 mlx5_hv_vhca_destroy(dev->hv_vhca);
916 mlx5_fw_tracer_destroy(dev->tracer);
917 mlx5_dm_cleanup(dev);
918 mlx5_fpga_cleanup(dev);
919 mlx5_eswitch_cleanup(dev->priv.eswitch);
920 mlx5_sriov_cleanup(dev);
921 mlx5_mpfs_cleanup(dev);
922 mlx5_cleanup_rl_table(dev);
923 mlx5_geneve_destroy(dev->geneve);
924 mlx5_vxlan_destroy(dev->vxlan);
925 mlx5_cleanup_clock(dev);
926 mlx5_cleanup_reserved_gids(dev);
927 mlx5_cleanup_mkey_table(dev);
928 mlx5_cleanup_qp_table(dev);
929 mlx5_cq_debugfs_cleanup(dev);
930 mlx5_events_cleanup(dev);
931 mlx5_eq_table_cleanup(dev);
932 mlx5_irq_table_cleanup(dev);
933 mlx5_devcom_unregister_device(dev->priv.devcom);
934 }
935
mlx5_function_setup(struct mlx5_core_dev * dev,bool boot)936 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot)
937 {
938 int err;
939
940 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
941 fw_rev_min(dev), fw_rev_sub(dev));
942
943 /* Only PFs hold the relevant PCIe information for this query */
944 if (mlx5_core_is_pf(dev))
945 pcie_print_link_status(dev->pdev);
946
947 /* wait for firmware to accept initialization segments configurations
948 */
949 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL);
950 if (err) {
951 mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n",
952 FW_PRE_INIT_TIMEOUT_MILI);
953 return err;
954 }
955
956 err = mlx5_cmd_init(dev);
957 if (err) {
958 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
959 return err;
960 }
961
962 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0);
963 if (err) {
964 mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n",
965 FW_INIT_TIMEOUT_MILI);
966 goto err_cmd_cleanup;
967 }
968
969 err = mlx5_core_enable_hca(dev, 0);
970 if (err) {
971 mlx5_core_err(dev, "enable hca failed\n");
972 goto err_cmd_cleanup;
973 }
974
975 err = mlx5_core_set_issi(dev);
976 if (err) {
977 mlx5_core_err(dev, "failed to set issi\n");
978 goto err_disable_hca;
979 }
980
981 err = mlx5_satisfy_startup_pages(dev, 1);
982 if (err) {
983 mlx5_core_err(dev, "failed to allocate boot pages\n");
984 goto err_disable_hca;
985 }
986
987 err = set_hca_ctrl(dev);
988 if (err) {
989 mlx5_core_err(dev, "set_hca_ctrl failed\n");
990 goto reclaim_boot_pages;
991 }
992
993 err = set_hca_cap(dev);
994 if (err) {
995 mlx5_core_err(dev, "set_hca_cap failed\n");
996 goto reclaim_boot_pages;
997 }
998
999 err = mlx5_satisfy_startup_pages(dev, 0);
1000 if (err) {
1001 mlx5_core_err(dev, "failed to allocate init pages\n");
1002 goto reclaim_boot_pages;
1003 }
1004
1005 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1006 if (err) {
1007 mlx5_core_err(dev, "init hca failed\n");
1008 goto reclaim_boot_pages;
1009 }
1010
1011 mlx5_set_driver_version(dev);
1012
1013 mlx5_start_health_poll(dev);
1014
1015 err = mlx5_query_hca_caps(dev);
1016 if (err) {
1017 mlx5_core_err(dev, "query hca failed\n");
1018 goto stop_health;
1019 }
1020
1021 return 0;
1022
1023 stop_health:
1024 mlx5_stop_health_poll(dev, boot);
1025 reclaim_boot_pages:
1026 mlx5_reclaim_startup_pages(dev);
1027 err_disable_hca:
1028 mlx5_core_disable_hca(dev, 0);
1029 err_cmd_cleanup:
1030 mlx5_cmd_cleanup(dev);
1031
1032 return err;
1033 }
1034
mlx5_function_teardown(struct mlx5_core_dev * dev,bool boot)1035 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1036 {
1037 int err;
1038
1039 mlx5_stop_health_poll(dev, boot);
1040 err = mlx5_cmd_teardown_hca(dev);
1041 if (err) {
1042 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1043 return err;
1044 }
1045 mlx5_reclaim_startup_pages(dev);
1046 mlx5_core_disable_hca(dev, 0);
1047 mlx5_cmd_cleanup(dev);
1048
1049 return 0;
1050 }
1051
mlx5_load(struct mlx5_core_dev * dev)1052 static int mlx5_load(struct mlx5_core_dev *dev)
1053 {
1054 int err;
1055
1056 dev->priv.uar = mlx5_get_uars_page(dev);
1057 if (IS_ERR(dev->priv.uar)) {
1058 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1059 err = PTR_ERR(dev->priv.uar);
1060 return err;
1061 }
1062
1063 mlx5_events_start(dev);
1064 mlx5_pagealloc_start(dev);
1065
1066 err = mlx5_irq_table_create(dev);
1067 if (err) {
1068 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1069 goto err_irq_table;
1070 }
1071
1072 err = mlx5_eq_table_create(dev);
1073 if (err) {
1074 mlx5_core_err(dev, "Failed to create EQs\n");
1075 goto err_eq_table;
1076 }
1077
1078 err = mlx5_fw_tracer_init(dev->tracer);
1079 if (err) {
1080 mlx5_core_err(dev, "Failed to init FW tracer\n");
1081 goto err_fw_tracer;
1082 }
1083
1084 mlx5_hv_vhca_init(dev->hv_vhca);
1085
1086 err = mlx5_fpga_device_start(dev);
1087 if (err) {
1088 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1089 goto err_fpga_start;
1090 }
1091
1092 err = mlx5_accel_ipsec_init(dev);
1093 if (err) {
1094 mlx5_core_err(dev, "IPSec device start failed %d\n", err);
1095 goto err_ipsec_start;
1096 }
1097
1098 err = mlx5_accel_tls_init(dev);
1099 if (err) {
1100 mlx5_core_err(dev, "TLS device start failed %d\n", err);
1101 goto err_tls_start;
1102 }
1103
1104 err = mlx5_init_fs(dev);
1105 if (err) {
1106 mlx5_core_err(dev, "Failed to init flow steering\n");
1107 goto err_fs;
1108 }
1109
1110 err = mlx5_core_set_hca_defaults(dev);
1111 if (err) {
1112 mlx5_core_err(dev, "Failed to set hca defaults\n");
1113 goto err_sriov;
1114 }
1115
1116 err = mlx5_sriov_attach(dev);
1117 if (err) {
1118 mlx5_core_err(dev, "sriov init failed %d\n", err);
1119 goto err_sriov;
1120 }
1121
1122 err = mlx5_ec_init(dev);
1123 if (err) {
1124 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1125 goto err_ec;
1126 }
1127
1128 return 0;
1129
1130 err_ec:
1131 mlx5_sriov_detach(dev);
1132 err_sriov:
1133 mlx5_cleanup_fs(dev);
1134 err_fs:
1135 mlx5_accel_tls_cleanup(dev);
1136 err_tls_start:
1137 mlx5_accel_ipsec_cleanup(dev);
1138 err_ipsec_start:
1139 mlx5_fpga_device_stop(dev);
1140 err_fpga_start:
1141 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1142 mlx5_fw_tracer_cleanup(dev->tracer);
1143 err_fw_tracer:
1144 mlx5_eq_table_destroy(dev);
1145 err_eq_table:
1146 mlx5_irq_table_destroy(dev);
1147 err_irq_table:
1148 mlx5_pagealloc_stop(dev);
1149 mlx5_events_stop(dev);
1150 mlx5_put_uars_page(dev, dev->priv.uar);
1151 return err;
1152 }
1153
mlx5_unload(struct mlx5_core_dev * dev)1154 static void mlx5_unload(struct mlx5_core_dev *dev)
1155 {
1156 mlx5_ec_cleanup(dev);
1157 mlx5_sriov_detach(dev);
1158 mlx5_cleanup_fs(dev);
1159 mlx5_accel_ipsec_cleanup(dev);
1160 mlx5_accel_tls_cleanup(dev);
1161 mlx5_fpga_device_stop(dev);
1162 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1163 mlx5_fw_tracer_cleanup(dev->tracer);
1164 mlx5_eq_table_destroy(dev);
1165 mlx5_irq_table_destroy(dev);
1166 mlx5_pagealloc_stop(dev);
1167 mlx5_events_stop(dev);
1168 mlx5_put_uars_page(dev, dev->priv.uar);
1169 }
1170
mlx5_load_one(struct mlx5_core_dev * dev,bool boot)1171 static int mlx5_load_one(struct mlx5_core_dev *dev, bool boot)
1172 {
1173 int err = 0;
1174
1175 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
1176 mutex_lock(&dev->intf_state_mutex);
1177 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1178 mlx5_core_warn(dev, "interface is up, NOP\n");
1179 goto out;
1180 }
1181 /* remove any previous indication of internal error */
1182 dev->state = MLX5_DEVICE_STATE_UP;
1183
1184 err = mlx5_function_setup(dev, boot);
1185 if (err)
1186 goto out;
1187
1188 if (boot) {
1189 err = mlx5_init_once(dev);
1190 if (err) {
1191 mlx5_core_err(dev, "sw objs init failed\n");
1192 goto function_teardown;
1193 }
1194 }
1195
1196 err = mlx5_load(dev);
1197 if (err)
1198 goto err_load;
1199
1200 if (mlx5_device_registered(dev)) {
1201 mlx5_attach_device(dev);
1202 } else {
1203 err = mlx5_register_device(dev);
1204 if (err) {
1205 mlx5_core_err(dev, "register device failed %d\n", err);
1206 goto err_reg_dev;
1207 }
1208 }
1209
1210 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1211 out:
1212 mutex_unlock(&dev->intf_state_mutex);
1213
1214 return err;
1215
1216 err_reg_dev:
1217 mlx5_unload(dev);
1218 err_load:
1219 if (boot)
1220 mlx5_cleanup_once(dev);
1221 function_teardown:
1222 mlx5_function_teardown(dev, boot);
1223 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1224 mutex_unlock(&dev->intf_state_mutex);
1225
1226 return err;
1227 }
1228
mlx5_unload_one(struct mlx5_core_dev * dev,bool cleanup)1229 static int mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup)
1230 {
1231 int err = 0;
1232
1233 if (cleanup) {
1234 mlx5_unregister_device(dev);
1235 mlx5_drain_health_wq(dev);
1236 }
1237
1238 mutex_lock(&dev->intf_state_mutex);
1239 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1240 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1241 __func__);
1242 if (cleanup)
1243 mlx5_cleanup_once(dev);
1244 goto out;
1245 }
1246
1247 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1248
1249 if (mlx5_device_registered(dev))
1250 mlx5_detach_device(dev);
1251
1252 mlx5_unload(dev);
1253
1254 if (cleanup)
1255 mlx5_cleanup_once(dev);
1256
1257 mlx5_function_teardown(dev, cleanup);
1258 out:
1259 mutex_unlock(&dev->intf_state_mutex);
1260 return err;
1261 }
1262
mlx5_mdev_init(struct mlx5_core_dev * dev,int profile_idx)1263 static int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1264 {
1265 struct mlx5_priv *priv = &dev->priv;
1266 int err;
1267
1268 dev->profile = &profile[profile_idx];
1269
1270 INIT_LIST_HEAD(&priv->ctx_list);
1271 spin_lock_init(&priv->ctx_lock);
1272 mutex_init(&dev->intf_state_mutex);
1273
1274 mutex_init(&priv->bfregs.reg_head.lock);
1275 mutex_init(&priv->bfregs.wc_head.lock);
1276 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1277 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1278
1279 mutex_init(&priv->alloc_mutex);
1280 mutex_init(&priv->pgdir_mutex);
1281 INIT_LIST_HEAD(&priv->pgdir_list);
1282 spin_lock_init(&priv->mkey_lock);
1283
1284 priv->dbg_root = debugfs_create_dir(dev_name(dev->device),
1285 mlx5_debugfs_root);
1286 if (!priv->dbg_root) {
1287 dev_err(dev->device, "mlx5_core: error, Cannot create debugfs dir, aborting\n");
1288 return -ENOMEM;
1289 }
1290
1291 err = mlx5_health_init(dev);
1292 if (err)
1293 goto err_health_init;
1294
1295 err = mlx5_pagealloc_init(dev);
1296 if (err)
1297 goto err_pagealloc_init;
1298
1299 return 0;
1300
1301 err_pagealloc_init:
1302 mlx5_health_cleanup(dev);
1303 err_health_init:
1304 debugfs_remove(dev->priv.dbg_root);
1305
1306 return err;
1307 }
1308
mlx5_mdev_uninit(struct mlx5_core_dev * dev)1309 static void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1310 {
1311 mlx5_pagealloc_cleanup(dev);
1312 mlx5_health_cleanup(dev);
1313 debugfs_remove_recursive(dev->priv.dbg_root);
1314 }
1315
1316 #define MLX5_IB_MOD "mlx5_ib"
init_one(struct pci_dev * pdev,const struct pci_device_id * id)1317 static int init_one(struct pci_dev *pdev, const struct pci_device_id *id)
1318 {
1319 struct mlx5_core_dev *dev;
1320 struct devlink *devlink;
1321 int err;
1322
1323 devlink = mlx5_devlink_alloc();
1324 if (!devlink) {
1325 dev_err(&pdev->dev, "devlink alloc failed\n");
1326 return -ENOMEM;
1327 }
1328
1329 dev = devlink_priv(devlink);
1330 dev->device = &pdev->dev;
1331 dev->pdev = pdev;
1332
1333 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1334 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1335
1336 err = mlx5_mdev_init(dev, prof_sel);
1337 if (err)
1338 goto mdev_init_err;
1339
1340 err = mlx5_pci_init(dev, pdev, id);
1341 if (err) {
1342 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1343 err);
1344 goto pci_init_err;
1345 }
1346
1347 err = mlx5_load_one(dev, true);
1348 if (err) {
1349 mlx5_core_err(dev, "mlx5_load_one failed with error code %d\n",
1350 err);
1351 goto err_load_one;
1352 }
1353
1354 request_module_nowait(MLX5_IB_MOD);
1355
1356 err = mlx5_devlink_register(devlink, &pdev->dev);
1357 if (err)
1358 goto clean_load;
1359
1360 err = mlx5_crdump_enable(dev);
1361 if (err)
1362 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err);
1363
1364 pci_save_state(pdev);
1365 return 0;
1366
1367 clean_load:
1368 mlx5_unload_one(dev, true);
1369
1370 err_load_one:
1371 mlx5_pci_close(dev);
1372 pci_init_err:
1373 mlx5_mdev_uninit(dev);
1374 mdev_init_err:
1375 mlx5_devlink_free(devlink);
1376
1377 return err;
1378 }
1379
remove_one(struct pci_dev * pdev)1380 static void remove_one(struct pci_dev *pdev)
1381 {
1382 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1383 struct devlink *devlink = priv_to_devlink(dev);
1384
1385 mlx5_crdump_disable(dev);
1386 mlx5_devlink_unregister(devlink);
1387
1388 if (mlx5_unload_one(dev, true)) {
1389 mlx5_core_err(dev, "mlx5_unload_one failed\n");
1390 mlx5_health_flush(dev);
1391 return;
1392 }
1393
1394 mlx5_pci_close(dev);
1395 mlx5_mdev_uninit(dev);
1396 mlx5_devlink_free(devlink);
1397 }
1398
mlx5_pci_err_detected(struct pci_dev * pdev,pci_channel_state_t state)1399 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1400 pci_channel_state_t state)
1401 {
1402 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1403
1404 mlx5_core_info(dev, "%s was called\n", __func__);
1405
1406 mlx5_enter_error_state(dev, false);
1407 mlx5_error_sw_reset(dev);
1408 mlx5_unload_one(dev, false);
1409 mlx5_drain_health_wq(dev);
1410 mlx5_pci_disable_device(dev);
1411
1412 return state == pci_channel_io_perm_failure ?
1413 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1414 }
1415
1416 /* wait for the device to show vital signs by waiting
1417 * for the health counter to start counting.
1418 */
wait_vital(struct pci_dev * pdev)1419 static int wait_vital(struct pci_dev *pdev)
1420 {
1421 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1422 struct mlx5_core_health *health = &dev->priv.health;
1423 const int niter = 100;
1424 u32 last_count = 0;
1425 u32 count;
1426 int i;
1427
1428 for (i = 0; i < niter; i++) {
1429 count = ioread32be(health->health_counter);
1430 if (count && count != 0xffffffff) {
1431 if (last_count && last_count != count) {
1432 mlx5_core_info(dev,
1433 "wait vital counter value 0x%x after %d iterations\n",
1434 count, i);
1435 return 0;
1436 }
1437 last_count = count;
1438 }
1439 msleep(50);
1440 }
1441
1442 return -ETIMEDOUT;
1443 }
1444
mlx5_pci_slot_reset(struct pci_dev * pdev)1445 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1446 {
1447 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1448 int err;
1449
1450 mlx5_core_info(dev, "%s was called\n", __func__);
1451
1452 err = mlx5_pci_enable_device(dev);
1453 if (err) {
1454 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
1455 __func__, err);
1456 return PCI_ERS_RESULT_DISCONNECT;
1457 }
1458
1459 pci_set_master(pdev);
1460 pci_restore_state(pdev);
1461 pci_save_state(pdev);
1462
1463 if (wait_vital(pdev)) {
1464 mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__);
1465 return PCI_ERS_RESULT_DISCONNECT;
1466 }
1467
1468 return PCI_ERS_RESULT_RECOVERED;
1469 }
1470
mlx5_pci_resume(struct pci_dev * pdev)1471 static void mlx5_pci_resume(struct pci_dev *pdev)
1472 {
1473 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1474 int err;
1475
1476 mlx5_core_info(dev, "%s was called\n", __func__);
1477
1478 err = mlx5_load_one(dev, false);
1479 if (err)
1480 mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n",
1481 __func__, err);
1482 else
1483 mlx5_core_info(dev, "%s: device recovered\n", __func__);
1484 }
1485
1486 static const struct pci_error_handlers mlx5_err_handler = {
1487 .error_detected = mlx5_pci_err_detected,
1488 .slot_reset = mlx5_pci_slot_reset,
1489 .resume = mlx5_pci_resume
1490 };
1491
mlx5_try_fast_unload(struct mlx5_core_dev * dev)1492 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1493 {
1494 bool fast_teardown = false, force_teardown = false;
1495 int ret = 1;
1496
1497 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1498 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1499
1500 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1501 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1502
1503 if (!fast_teardown && !force_teardown)
1504 return -EOPNOTSUPP;
1505
1506 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1507 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1508 return -EAGAIN;
1509 }
1510
1511 /* Panic tear down fw command will stop the PCI bus communication
1512 * with the HCA, so the health polll is no longer needed.
1513 */
1514 mlx5_drain_health_wq(dev);
1515 mlx5_stop_health_poll(dev, false);
1516
1517 ret = mlx5_cmd_fast_teardown_hca(dev);
1518 if (!ret)
1519 goto succeed;
1520
1521 ret = mlx5_cmd_force_teardown_hca(dev);
1522 if (!ret)
1523 goto succeed;
1524
1525 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1526 mlx5_start_health_poll(dev);
1527 return ret;
1528
1529 succeed:
1530 mlx5_enter_error_state(dev, true);
1531
1532 /* Some platforms requiring freeing the IRQ's in the shutdown
1533 * flow. If they aren't freed they can't be allocated after
1534 * kexec. There is no need to cleanup the mlx5_core software
1535 * contexts.
1536 */
1537 mlx5_core_eq_free_irqs(dev);
1538
1539 return 0;
1540 }
1541
shutdown(struct pci_dev * pdev)1542 static void shutdown(struct pci_dev *pdev)
1543 {
1544 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1545 int err;
1546
1547 mlx5_core_info(dev, "Shutdown was called\n");
1548 err = mlx5_try_fast_unload(dev);
1549 if (err)
1550 mlx5_unload_one(dev, false);
1551 mlx5_pci_disable_device(dev);
1552 }
1553
1554 static const struct pci_device_id mlx5_core_pci_table[] = {
1555 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1556 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1557 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1558 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1559 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1560 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1561 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1562 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1563 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1564 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1565 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1566 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1567 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
1568 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
1569 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
1570 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1571 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1572 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
1573 { 0, }
1574 };
1575
1576 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1577
mlx5_disable_device(struct mlx5_core_dev * dev)1578 void mlx5_disable_device(struct mlx5_core_dev *dev)
1579 {
1580 mlx5_error_sw_reset(dev);
1581 mlx5_unload_one(dev, false);
1582 }
1583
mlx5_recover_device(struct mlx5_core_dev * dev)1584 void mlx5_recover_device(struct mlx5_core_dev *dev)
1585 {
1586 mlx5_pci_disable_device(dev);
1587 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1588 mlx5_pci_resume(dev->pdev);
1589 }
1590
1591 static struct pci_driver mlx5_core_driver = {
1592 .name = DRIVER_NAME,
1593 .id_table = mlx5_core_pci_table,
1594 .probe = init_one,
1595 .remove = remove_one,
1596 .shutdown = shutdown,
1597 .err_handler = &mlx5_err_handler,
1598 .sriov_configure = mlx5_core_sriov_configure,
1599 };
1600
mlx5_core_verify_params(void)1601 static void mlx5_core_verify_params(void)
1602 {
1603 if (prof_sel >= ARRAY_SIZE(profile)) {
1604 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1605 prof_sel,
1606 ARRAY_SIZE(profile) - 1,
1607 MLX5_DEFAULT_PROF);
1608 prof_sel = MLX5_DEFAULT_PROF;
1609 }
1610 }
1611
init(void)1612 static int __init init(void)
1613 {
1614 int err;
1615
1616 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1617
1618 mlx5_core_verify_params();
1619 mlx5_accel_ipsec_build_fs_cmds();
1620 mlx5_register_debugfs();
1621
1622 err = pci_register_driver(&mlx5_core_driver);
1623 if (err)
1624 goto err_debug;
1625
1626 #ifdef CONFIG_MLX5_CORE_EN
1627 mlx5e_init();
1628 #endif
1629
1630 return 0;
1631
1632 err_debug:
1633 mlx5_unregister_debugfs();
1634 return err;
1635 }
1636
cleanup(void)1637 static void __exit cleanup(void)
1638 {
1639 #ifdef CONFIG_MLX5_CORE_EN
1640 mlx5e_cleanup();
1641 #endif
1642 pci_unregister_driver(&mlx5_core_driver);
1643 mlx5_unregister_debugfs();
1644 }
1645
1646 module_init(init);
1647 module_exit(cleanup);
1648
