1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include <linux/mlx5/vport.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
52 #endif
53 #include <linux/version.h>
54 #include <net/devlink.h>
55 #include "mlx5_core.h"
56 #include "lib/eq.h"
57 #include "fs_core.h"
58 #include "lib/mpfs.h"
59 #include "eswitch.h"
60 #include "devlink.h"
61 #include "fw_reset.h"
62 #include "lib/mlx5.h"
63 #include "lib/tout.h"
64 #include "fpga/core.h"
65 #include "en_accel/ipsec.h"
66 #include "lib/clock.h"
67 #include "lib/vxlan.h"
68 #include "lib/geneve.h"
69 #include "lib/devcom.h"
70 #include "lib/pci_vsc.h"
71 #include "diag/fw_tracer.h"
72 #include "ecpf.h"
73 #include "lib/hv_vhca.h"
74 #include "diag/rsc_dump.h"
75 #include "sf/vhca_event.h"
76 #include "sf/dev/dev.h"
77 #include "sf/sf.h"
78 #include "mlx5_irq.h"
79
80 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
81 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
82 MODULE_LICENSE("Dual BSD/GPL");
83
84 unsigned int mlx5_core_debug_mask;
85 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
86 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
87
88 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
89 module_param_named(prof_sel, prof_sel, uint, 0444);
90 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
91
92 static u32 sw_owner_id[4];
93 #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1)
94 static DEFINE_IDA(sw_vhca_ida);
95
96 enum {
97 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
98 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
99 };
100
101 #define LOG_MAX_SUPPORTED_QPS 0xff
102
103 static struct mlx5_profile profile[] = {
104 [0] = {
105 .mask = 0,
106 },
107 [1] = {
108 .mask = MLX5_PROF_MASK_QP_SIZE,
109 .log_max_qp = 12,
110 },
111 [2] = {
112 .mask = MLX5_PROF_MASK_QP_SIZE |
113 MLX5_PROF_MASK_MR_CACHE,
114 .log_max_qp = LOG_MAX_SUPPORTED_QPS,
115 .mr_cache[0] = {
116 .size = 500,
117 .limit = 250
118 },
119 .mr_cache[1] = {
120 .size = 500,
121 .limit = 250
122 },
123 .mr_cache[2] = {
124 .size = 500,
125 .limit = 250
126 },
127 .mr_cache[3] = {
128 .size = 500,
129 .limit = 250
130 },
131 .mr_cache[4] = {
132 .size = 500,
133 .limit = 250
134 },
135 .mr_cache[5] = {
136 .size = 500,
137 .limit = 250
138 },
139 .mr_cache[6] = {
140 .size = 500,
141 .limit = 250
142 },
143 .mr_cache[7] = {
144 .size = 500,
145 .limit = 250
146 },
147 .mr_cache[8] = {
148 .size = 500,
149 .limit = 250
150 },
151 .mr_cache[9] = {
152 .size = 500,
153 .limit = 250
154 },
155 .mr_cache[10] = {
156 .size = 500,
157 .limit = 250
158 },
159 .mr_cache[11] = {
160 .size = 500,
161 .limit = 250
162 },
163 .mr_cache[12] = {
164 .size = 64,
165 .limit = 32
166 },
167 .mr_cache[13] = {
168 .size = 32,
169 .limit = 16
170 },
171 .mr_cache[14] = {
172 .size = 16,
173 .limit = 8
174 },
175 .mr_cache[15] = {
176 .size = 8,
177 .limit = 4
178 },
179 },
180 };
181
wait_fw_init(struct mlx5_core_dev * dev,u32 max_wait_mili,u32 warn_time_mili)182 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
183 u32 warn_time_mili)
184 {
185 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
186 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
187 u32 fw_initializing;
188 int err = 0;
189
190 do {
191 fw_initializing = ioread32be(&dev->iseg->initializing);
192 if (!(fw_initializing >> 31))
193 break;
194 if (time_after(jiffies, end) ||
195 test_and_clear_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) {
196 err = -EBUSY;
197 break;
198 }
199 if (warn_time_mili && time_after(jiffies, warn)) {
200 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds (0x%x)\n",
201 jiffies_to_msecs(end - warn) / 1000, fw_initializing);
202 warn = jiffies + msecs_to_jiffies(warn_time_mili);
203 }
204 msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT));
205 } while (true);
206
207 return err;
208 }
209
mlx5_set_driver_version(struct mlx5_core_dev * dev)210 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
211 {
212 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
213 driver_version);
214 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
215 int remaining_size = driver_ver_sz;
216 char *string;
217
218 if (!MLX5_CAP_GEN(dev, driver_version))
219 return;
220
221 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
222
223 strncpy(string, "Linux", remaining_size);
224
225 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
226 strncat(string, ",", remaining_size);
227
228 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
229 strncat(string, KBUILD_MODNAME, remaining_size);
230
231 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
232 strncat(string, ",", remaining_size);
233
234 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
235
236 snprintf(string + strlen(string), remaining_size, "%u.%u.%u",
237 LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL,
238 LINUX_VERSION_SUBLEVEL);
239
240 /*Send the command*/
241 MLX5_SET(set_driver_version_in, in, opcode,
242 MLX5_CMD_OP_SET_DRIVER_VERSION);
243
244 mlx5_cmd_exec_in(dev, set_driver_version, in);
245 }
246
set_dma_caps(struct pci_dev * pdev)247 static int set_dma_caps(struct pci_dev *pdev)
248 {
249 int err;
250
251 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
252 if (err) {
253 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
254 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
255 if (err) {
256 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
257 return err;
258 }
259 }
260
261 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
262 return err;
263 }
264
mlx5_pci_enable_device(struct mlx5_core_dev * dev)265 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
266 {
267 struct pci_dev *pdev = dev->pdev;
268 int err = 0;
269
270 mutex_lock(&dev->pci_status_mutex);
271 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
272 err = pci_enable_device(pdev);
273 if (!err)
274 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
275 }
276 mutex_unlock(&dev->pci_status_mutex);
277
278 return err;
279 }
280
mlx5_pci_disable_device(struct mlx5_core_dev * dev)281 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
282 {
283 struct pci_dev *pdev = dev->pdev;
284
285 mutex_lock(&dev->pci_status_mutex);
286 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
287 pci_disable_device(pdev);
288 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
289 }
290 mutex_unlock(&dev->pci_status_mutex);
291 }
292
request_bar(struct pci_dev * pdev)293 static int request_bar(struct pci_dev *pdev)
294 {
295 int err = 0;
296
297 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
298 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
299 return -ENODEV;
300 }
301
302 err = pci_request_regions(pdev, KBUILD_MODNAME);
303 if (err)
304 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
305
306 return err;
307 }
308
release_bar(struct pci_dev * pdev)309 static void release_bar(struct pci_dev *pdev)
310 {
311 pci_release_regions(pdev);
312 }
313
314 struct mlx5_reg_host_endianness {
315 u8 he;
316 u8 rsvd[15];
317 };
318
to_fw_pkey_sz(struct mlx5_core_dev * dev,u32 size)319 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
320 {
321 switch (size) {
322 case 128:
323 return 0;
324 case 256:
325 return 1;
326 case 512:
327 return 2;
328 case 1024:
329 return 3;
330 case 2048:
331 return 4;
332 case 4096:
333 return 5;
334 default:
335 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
336 return 0;
337 }
338 }
339
mlx5_core_get_caps_mode(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type,enum mlx5_cap_mode cap_mode)340 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
341 enum mlx5_cap_type cap_type,
342 enum mlx5_cap_mode cap_mode)
343 {
344 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
345 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
346 void *out, *hca_caps;
347 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
348 int err;
349
350 memset(in, 0, sizeof(in));
351 out = kzalloc(out_sz, GFP_KERNEL);
352 if (!out)
353 return -ENOMEM;
354
355 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
356 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
357 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out);
358 if (err) {
359 mlx5_core_warn(dev,
360 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
361 cap_type, cap_mode, err);
362 goto query_ex;
363 }
364
365 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
366
367 switch (cap_mode) {
368 case HCA_CAP_OPMOD_GET_MAX:
369 memcpy(dev->caps.hca[cap_type]->max, hca_caps,
370 MLX5_UN_SZ_BYTES(hca_cap_union));
371 break;
372 case HCA_CAP_OPMOD_GET_CUR:
373 memcpy(dev->caps.hca[cap_type]->cur, hca_caps,
374 MLX5_UN_SZ_BYTES(hca_cap_union));
375 break;
376 default:
377 mlx5_core_warn(dev,
378 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
379 cap_type, cap_mode);
380 err = -EINVAL;
381 break;
382 }
383 query_ex:
384 kfree(out);
385 return err;
386 }
387
mlx5_core_get_caps(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type)388 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
389 {
390 int ret;
391
392 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
393 if (ret)
394 return ret;
395 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
396 }
397
set_caps(struct mlx5_core_dev * dev,void * in,int opmod)398 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod)
399 {
400 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
401 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
402 return mlx5_cmd_exec_in(dev, set_hca_cap, in);
403 }
404
handle_hca_cap_atomic(struct mlx5_core_dev * dev,void * set_ctx)405 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx)
406 {
407 void *set_hca_cap;
408 int req_endianness;
409 int err;
410
411 if (!MLX5_CAP_GEN(dev, atomic))
412 return 0;
413
414 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
415 if (err)
416 return err;
417
418 req_endianness =
419 MLX5_CAP_ATOMIC(dev,
420 supported_atomic_req_8B_endianness_mode_1);
421
422 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
423 return 0;
424
425 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
426
427 /* Set requestor to host endianness */
428 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
429 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
430
431 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
432 }
433
handle_hca_cap_odp(struct mlx5_core_dev * dev,void * set_ctx)434 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx)
435 {
436 void *set_hca_cap;
437 bool do_set = false;
438 int err;
439
440 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
441 !MLX5_CAP_GEN(dev, pg))
442 return 0;
443
444 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
445 if (err)
446 return err;
447
448 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
449 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur,
450 MLX5_ST_SZ_BYTES(odp_cap));
451
452 #define ODP_CAP_SET_MAX(dev, field) \
453 do { \
454 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
455 if (_res) { \
456 do_set = true; \
457 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
458 } \
459 } while (0)
460
461 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
462 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
463 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
464 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
465 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
466 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
467 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
468 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
469 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive);
470 ODP_CAP_SET_MAX(dev, dc_odp_caps.send);
471 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive);
472 ODP_CAP_SET_MAX(dev, dc_odp_caps.write);
473 ODP_CAP_SET_MAX(dev, dc_odp_caps.read);
474 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic);
475
476 if (!do_set)
477 return 0;
478
479 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP);
480 }
481
max_uc_list_get_devlink_param(struct mlx5_core_dev * dev)482 static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev)
483 {
484 struct devlink *devlink = priv_to_devlink(dev);
485 union devlink_param_value val;
486 int err;
487
488 err = devlink_param_driverinit_value_get(devlink,
489 DEVLINK_PARAM_GENERIC_ID_MAX_MACS,
490 &val);
491 if (!err)
492 return val.vu32;
493 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
494 return err;
495 }
496
mlx5_is_roce_on(struct mlx5_core_dev * dev)497 bool mlx5_is_roce_on(struct mlx5_core_dev *dev)
498 {
499 struct devlink *devlink = priv_to_devlink(dev);
500 union devlink_param_value val;
501 int err;
502
503 err = devlink_param_driverinit_value_get(devlink,
504 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
505 &val);
506
507 if (!err)
508 return val.vbool;
509
510 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
511 return MLX5_CAP_GEN(dev, roce);
512 }
513 EXPORT_SYMBOL(mlx5_is_roce_on);
514
handle_hca_cap_2(struct mlx5_core_dev * dev,void * set_ctx)515 static int handle_hca_cap_2(struct mlx5_core_dev *dev, void *set_ctx)
516 {
517 void *set_hca_cap;
518 int err;
519
520 if (!MLX5_CAP_GEN_MAX(dev, hca_cap_2))
521 return 0;
522
523 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2);
524 if (err)
525 return err;
526
527 if (!MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) ||
528 !(dev->priv.sw_vhca_id > 0))
529 return 0;
530
531 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
532 capability);
533 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur,
534 MLX5_ST_SZ_BYTES(cmd_hca_cap_2));
535 MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1);
536
537 return set_caps(dev, set_ctx, MLX5_CAP_GENERAL_2);
538 }
539
handle_hca_cap(struct mlx5_core_dev * dev,void * set_ctx)540 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
541 {
542 struct mlx5_profile *prof = &dev->profile;
543 void *set_hca_cap;
544 int max_uc_list;
545 int err;
546
547 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
548 if (err)
549 return err;
550
551 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
552 capability);
553 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur,
554 MLX5_ST_SZ_BYTES(cmd_hca_cap));
555
556 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
557 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
558 128);
559 /* we limit the size of the pkey table to 128 entries for now */
560 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
561 to_fw_pkey_sz(dev, 128));
562
563 /* Check log_max_qp from HCA caps to set in current profile */
564 if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) {
565 prof->log_max_qp = min_t(u8, 18, MLX5_CAP_GEN_MAX(dev, log_max_qp));
566 } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) {
567 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
568 prof->log_max_qp,
569 MLX5_CAP_GEN_MAX(dev, log_max_qp));
570 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
571 }
572 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
573 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
574 prof->log_max_qp);
575
576 /* disable cmdif checksum */
577 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
578
579 /* Enable 4K UAR only when HCA supports it and page size is bigger
580 * than 4K.
581 */
582 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
583 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
584
585 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
586
587 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
588 MLX5_SET(cmd_hca_cap,
589 set_hca_cap,
590 cache_line_128byte,
591 cache_line_size() >= 128 ? 1 : 0);
592
593 if (MLX5_CAP_GEN_MAX(dev, dct))
594 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
595
596 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event))
597 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
598
599 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
600 MLX5_SET(cmd_hca_cap,
601 set_hca_cap,
602 num_vhca_ports,
603 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
604
605 if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
606 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
607
608 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name))
609 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
610
611 mlx5_vhca_state_cap_handle(dev, set_hca_cap);
612
613 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix))
614 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix,
615 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix));
616
617 if (MLX5_CAP_GEN(dev, roce_rw_supported))
618 MLX5_SET(cmd_hca_cap, set_hca_cap, roce,
619 mlx5_is_roce_on(dev));
620
621 max_uc_list = max_uc_list_get_devlink_param(dev);
622 if (max_uc_list > 0)
623 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list,
624 ilog2(max_uc_list));
625
626 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
627 }
628
629 /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the
630 * boot process.
631 * In case RoCE cap is writable in FW and user/devlink requested to change the
632 * cap, we are yet to query the final state of the above cap.
633 * Hence, the need for this function.
634 *
635 * Returns
636 * True:
637 * 1) RoCE cap is read only in FW and already disabled
638 * OR:
639 * 2) RoCE cap is writable in FW and user/devlink requested it off.
640 *
641 * In any other case, return False.
642 */
is_roce_fw_disabled(struct mlx5_core_dev * dev)643 static bool is_roce_fw_disabled(struct mlx5_core_dev *dev)
644 {
645 return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_on(dev)) ||
646 (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce));
647 }
648
handle_hca_cap_roce(struct mlx5_core_dev * dev,void * set_ctx)649 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx)
650 {
651 void *set_hca_cap;
652 int err;
653
654 if (is_roce_fw_disabled(dev))
655 return 0;
656
657 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
658 if (err)
659 return err;
660
661 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) ||
662 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port))
663 return 0;
664
665 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
666 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur,
667 MLX5_ST_SZ_BYTES(roce_cap));
668 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
669
670 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE);
671 return err;
672 }
673
handle_hca_cap_port_selection(struct mlx5_core_dev * dev,void * set_ctx)674 static int handle_hca_cap_port_selection(struct mlx5_core_dev *dev,
675 void *set_ctx)
676 {
677 void *set_hca_cap;
678 int err;
679
680 if (!MLX5_CAP_GEN(dev, port_selection_cap))
681 return 0;
682
683 err = mlx5_core_get_caps(dev, MLX5_CAP_PORT_SELECTION);
684 if (err)
685 return err;
686
687 if (MLX5_CAP_PORT_SELECTION(dev, port_select_flow_table_bypass) ||
688 !MLX5_CAP_PORT_SELECTION_MAX(dev, port_select_flow_table_bypass))
689 return 0;
690
691 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
692 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur,
693 MLX5_ST_SZ_BYTES(port_selection_cap));
694 MLX5_SET(port_selection_cap, set_hca_cap, port_select_flow_table_bypass, 1);
695
696 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MODE_PORT_SELECTION);
697
698 return err;
699 }
700
set_hca_cap(struct mlx5_core_dev * dev)701 static int set_hca_cap(struct mlx5_core_dev *dev)
702 {
703 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
704 void *set_ctx;
705 int err;
706
707 set_ctx = kzalloc(set_sz, GFP_KERNEL);
708 if (!set_ctx)
709 return -ENOMEM;
710
711 err = handle_hca_cap(dev, set_ctx);
712 if (err) {
713 mlx5_core_err(dev, "handle_hca_cap failed\n");
714 goto out;
715 }
716
717 memset(set_ctx, 0, set_sz);
718 err = handle_hca_cap_atomic(dev, set_ctx);
719 if (err) {
720 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
721 goto out;
722 }
723
724 memset(set_ctx, 0, set_sz);
725 err = handle_hca_cap_odp(dev, set_ctx);
726 if (err) {
727 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
728 goto out;
729 }
730
731 memset(set_ctx, 0, set_sz);
732 err = handle_hca_cap_roce(dev, set_ctx);
733 if (err) {
734 mlx5_core_err(dev, "handle_hca_cap_roce failed\n");
735 goto out;
736 }
737
738 memset(set_ctx, 0, set_sz);
739 err = handle_hca_cap_2(dev, set_ctx);
740 if (err) {
741 mlx5_core_err(dev, "handle_hca_cap_2 failed\n");
742 goto out;
743 }
744
745 memset(set_ctx, 0, set_sz);
746 err = handle_hca_cap_port_selection(dev, set_ctx);
747 if (err) {
748 mlx5_core_err(dev, "handle_hca_cap_port_selection failed\n");
749 goto out;
750 }
751
752 out:
753 kfree(set_ctx);
754 return err;
755 }
756
set_hca_ctrl(struct mlx5_core_dev * dev)757 static int set_hca_ctrl(struct mlx5_core_dev *dev)
758 {
759 struct mlx5_reg_host_endianness he_in;
760 struct mlx5_reg_host_endianness he_out;
761 int err;
762
763 if (!mlx5_core_is_pf(dev))
764 return 0;
765
766 memset(&he_in, 0, sizeof(he_in));
767 he_in.he = MLX5_SET_HOST_ENDIANNESS;
768 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
769 &he_out, sizeof(he_out),
770 MLX5_REG_HOST_ENDIANNESS, 0, 1);
771 return err;
772 }
773
mlx5_core_set_hca_defaults(struct mlx5_core_dev * dev)774 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
775 {
776 int ret = 0;
777
778 /* Disable local_lb by default */
779 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
780 ret = mlx5_nic_vport_update_local_lb(dev, false);
781
782 return ret;
783 }
784
mlx5_core_enable_hca(struct mlx5_core_dev * dev,u16 func_id)785 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
786 {
787 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
788
789 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
790 MLX5_SET(enable_hca_in, in, function_id, func_id);
791 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
792 dev->caps.embedded_cpu);
793 return mlx5_cmd_exec_in(dev, enable_hca, in);
794 }
795
mlx5_core_disable_hca(struct mlx5_core_dev * dev,u16 func_id)796 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
797 {
798 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
799
800 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
801 MLX5_SET(disable_hca_in, in, function_id, func_id);
802 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
803 dev->caps.embedded_cpu);
804 return mlx5_cmd_exec_in(dev, disable_hca, in);
805 }
806
mlx5_core_set_issi(struct mlx5_core_dev * dev)807 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
808 {
809 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {};
810 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {};
811 u32 sup_issi;
812 int err;
813
814 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
815 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out);
816 if (err) {
817 u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome);
818 u8 status = MLX5_GET(query_issi_out, query_out, status);
819
820 if (!status || syndrome == MLX5_DRIVER_SYND) {
821 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
822 err, status, syndrome);
823 return err;
824 }
825
826 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
827 dev->issi = 0;
828 return 0;
829 }
830
831 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
832
833 if (sup_issi & (1 << 1)) {
834 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {};
835
836 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
837 MLX5_SET(set_issi_in, set_in, current_issi, 1);
838 err = mlx5_cmd_exec_in(dev, set_issi, set_in);
839 if (err) {
840 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
841 err);
842 return err;
843 }
844
845 dev->issi = 1;
846
847 return 0;
848 } else if (sup_issi & (1 << 0) || !sup_issi) {
849 return 0;
850 }
851
852 return -EOPNOTSUPP;
853 }
854
mlx5_pci_init(struct mlx5_core_dev * dev,struct pci_dev * pdev,const struct pci_device_id * id)855 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
856 const struct pci_device_id *id)
857 {
858 int err = 0;
859
860 mutex_init(&dev->pci_status_mutex);
861 pci_set_drvdata(dev->pdev, dev);
862
863 dev->bar_addr = pci_resource_start(pdev, 0);
864
865 err = mlx5_pci_enable_device(dev);
866 if (err) {
867 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
868 return err;
869 }
870
871 err = request_bar(pdev);
872 if (err) {
873 mlx5_core_err(dev, "error requesting BARs, aborting\n");
874 goto err_disable;
875 }
876
877 pci_set_master(pdev);
878
879 err = set_dma_caps(pdev);
880 if (err) {
881 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
882 goto err_clr_master;
883 }
884
885 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
886 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
887 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
888 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
889
890 dev->iseg_base = dev->bar_addr;
891 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
892 if (!dev->iseg) {
893 err = -ENOMEM;
894 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
895 goto err_clr_master;
896 }
897
898 mlx5_pci_vsc_init(dev);
899 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
900 return 0;
901
902 err_clr_master:
903 pci_clear_master(dev->pdev);
904 release_bar(dev->pdev);
905 err_disable:
906 mlx5_pci_disable_device(dev);
907 return err;
908 }
909
mlx5_pci_close(struct mlx5_core_dev * dev)910 static void mlx5_pci_close(struct mlx5_core_dev *dev)
911 {
912 /* health work might still be active, and it needs pci bar in
913 * order to know the NIC state. Therefore, drain the health WQ
914 * before removing the pci bars
915 */
916 mlx5_drain_health_wq(dev);
917 iounmap(dev->iseg);
918 pci_clear_master(dev->pdev);
919 release_bar(dev->pdev);
920 mlx5_pci_disable_device(dev);
921 }
922
mlx5_init_once(struct mlx5_core_dev * dev)923 static int mlx5_init_once(struct mlx5_core_dev *dev)
924 {
925 int err;
926
927 dev->priv.devcom = mlx5_devcom_register_device(dev);
928 if (IS_ERR(dev->priv.devcom))
929 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n",
930 dev->priv.devcom);
931
932 err = mlx5_query_board_id(dev);
933 if (err) {
934 mlx5_core_err(dev, "query board id failed\n");
935 goto err_devcom;
936 }
937
938 err = mlx5_irq_table_init(dev);
939 if (err) {
940 mlx5_core_err(dev, "failed to initialize irq table\n");
941 goto err_devcom;
942 }
943
944 err = mlx5_eq_table_init(dev);
945 if (err) {
946 mlx5_core_err(dev, "failed to initialize eq\n");
947 goto err_irq_cleanup;
948 }
949
950 err = mlx5_events_init(dev);
951 if (err) {
952 mlx5_core_err(dev, "failed to initialize events\n");
953 goto err_eq_cleanup;
954 }
955
956 err = mlx5_fw_reset_init(dev);
957 if (err) {
958 mlx5_core_err(dev, "failed to initialize fw reset events\n");
959 goto err_events_cleanup;
960 }
961
962 mlx5_cq_debugfs_init(dev);
963
964 mlx5_init_reserved_gids(dev);
965
966 mlx5_init_clock(dev);
967
968 dev->vxlan = mlx5_vxlan_create(dev);
969 dev->geneve = mlx5_geneve_create(dev);
970
971 err = mlx5_init_rl_table(dev);
972 if (err) {
973 mlx5_core_err(dev, "Failed to init rate limiting\n");
974 goto err_tables_cleanup;
975 }
976
977 err = mlx5_mpfs_init(dev);
978 if (err) {
979 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
980 goto err_rl_cleanup;
981 }
982
983 err = mlx5_sriov_init(dev);
984 if (err) {
985 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
986 goto err_mpfs_cleanup;
987 }
988
989 err = mlx5_eswitch_init(dev);
990 if (err) {
991 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
992 goto err_sriov_cleanup;
993 }
994
995 err = mlx5_fpga_init(dev);
996 if (err) {
997 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
998 goto err_eswitch_cleanup;
999 }
1000
1001 err = mlx5_vhca_event_init(dev);
1002 if (err) {
1003 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err);
1004 goto err_fpga_cleanup;
1005 }
1006
1007 err = mlx5_sf_hw_table_init(dev);
1008 if (err) {
1009 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err);
1010 goto err_sf_hw_table_cleanup;
1011 }
1012
1013 err = mlx5_sf_table_init(dev);
1014 if (err) {
1015 mlx5_core_err(dev, "Failed to init SF table %d\n", err);
1016 goto err_sf_table_cleanup;
1017 }
1018
1019 err = mlx5_fs_core_alloc(dev);
1020 if (err) {
1021 mlx5_core_err(dev, "Failed to alloc flow steering\n");
1022 goto err_fs;
1023 }
1024
1025 dev->dm = mlx5_dm_create(dev);
1026 if (IS_ERR(dev->dm))
1027 mlx5_core_warn(dev, "Failed to init device memory%d\n", err);
1028
1029 dev->tracer = mlx5_fw_tracer_create(dev);
1030 dev->hv_vhca = mlx5_hv_vhca_create(dev);
1031 dev->rsc_dump = mlx5_rsc_dump_create(dev);
1032
1033 return 0;
1034
1035 err_fs:
1036 mlx5_sf_table_cleanup(dev);
1037 err_sf_table_cleanup:
1038 mlx5_sf_hw_table_cleanup(dev);
1039 err_sf_hw_table_cleanup:
1040 mlx5_vhca_event_cleanup(dev);
1041 err_fpga_cleanup:
1042 mlx5_fpga_cleanup(dev);
1043 err_eswitch_cleanup:
1044 mlx5_eswitch_cleanup(dev->priv.eswitch);
1045 err_sriov_cleanup:
1046 mlx5_sriov_cleanup(dev);
1047 err_mpfs_cleanup:
1048 mlx5_mpfs_cleanup(dev);
1049 err_rl_cleanup:
1050 mlx5_cleanup_rl_table(dev);
1051 err_tables_cleanup:
1052 mlx5_geneve_destroy(dev->geneve);
1053 mlx5_vxlan_destroy(dev->vxlan);
1054 mlx5_cq_debugfs_cleanup(dev);
1055 mlx5_fw_reset_cleanup(dev);
1056 err_events_cleanup:
1057 mlx5_events_cleanup(dev);
1058 err_eq_cleanup:
1059 mlx5_eq_table_cleanup(dev);
1060 err_irq_cleanup:
1061 mlx5_irq_table_cleanup(dev);
1062 err_devcom:
1063 mlx5_devcom_unregister_device(dev->priv.devcom);
1064
1065 return err;
1066 }
1067
mlx5_cleanup_once(struct mlx5_core_dev * dev)1068 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
1069 {
1070 mlx5_rsc_dump_destroy(dev);
1071 mlx5_hv_vhca_destroy(dev->hv_vhca);
1072 mlx5_fw_tracer_destroy(dev->tracer);
1073 mlx5_dm_cleanup(dev);
1074 mlx5_fs_core_free(dev);
1075 mlx5_sf_table_cleanup(dev);
1076 mlx5_sf_hw_table_cleanup(dev);
1077 mlx5_vhca_event_cleanup(dev);
1078 mlx5_fpga_cleanup(dev);
1079 mlx5_eswitch_cleanup(dev->priv.eswitch);
1080 mlx5_sriov_cleanup(dev);
1081 mlx5_mpfs_cleanup(dev);
1082 mlx5_cleanup_rl_table(dev);
1083 mlx5_geneve_destroy(dev->geneve);
1084 mlx5_vxlan_destroy(dev->vxlan);
1085 mlx5_cleanup_clock(dev);
1086 mlx5_cleanup_reserved_gids(dev);
1087 mlx5_cq_debugfs_cleanup(dev);
1088 mlx5_fw_reset_cleanup(dev);
1089 mlx5_events_cleanup(dev);
1090 mlx5_eq_table_cleanup(dev);
1091 mlx5_irq_table_cleanup(dev);
1092 mlx5_devcom_unregister_device(dev->priv.devcom);
1093 }
1094
mlx5_function_setup(struct mlx5_core_dev * dev,bool boot,u64 timeout)1095 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot, u64 timeout)
1096 {
1097 int err;
1098
1099 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1100 fw_rev_min(dev), fw_rev_sub(dev));
1101
1102 /* Only PFs hold the relevant PCIe information for this query */
1103 if (mlx5_core_is_pf(dev))
1104 pcie_print_link_status(dev->pdev);
1105
1106 /* wait for firmware to accept initialization segments configurations
1107 */
1108 err = wait_fw_init(dev, timeout,
1109 mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL));
1110 if (err) {
1111 mlx5_core_err(dev, "Firmware over %llu MS in pre-initializing state, aborting\n",
1112 timeout);
1113 return err;
1114 }
1115
1116 err = mlx5_cmd_init(dev);
1117 if (err) {
1118 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
1119 return err;
1120 }
1121
1122 mlx5_tout_query_iseg(dev);
1123
1124 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0);
1125 if (err) {
1126 mlx5_core_err(dev, "Firmware over %llu MS in initializing state, aborting\n",
1127 mlx5_tout_ms(dev, FW_INIT));
1128 goto err_cmd_cleanup;
1129 }
1130
1131 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP);
1132
1133 mlx5_start_health_poll(dev);
1134
1135 err = mlx5_core_enable_hca(dev, 0);
1136 if (err) {
1137 mlx5_core_err(dev, "enable hca failed\n");
1138 goto stop_health_poll;
1139 }
1140
1141 err = mlx5_core_set_issi(dev);
1142 if (err) {
1143 mlx5_core_err(dev, "failed to set issi\n");
1144 goto err_disable_hca;
1145 }
1146
1147 err = mlx5_satisfy_startup_pages(dev, 1);
1148 if (err) {
1149 mlx5_core_err(dev, "failed to allocate boot pages\n");
1150 goto err_disable_hca;
1151 }
1152
1153 err = mlx5_tout_query_dtor(dev);
1154 if (err) {
1155 mlx5_core_err(dev, "failed to read dtor\n");
1156 goto reclaim_boot_pages;
1157 }
1158
1159 err = set_hca_ctrl(dev);
1160 if (err) {
1161 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1162 goto reclaim_boot_pages;
1163 }
1164
1165 err = set_hca_cap(dev);
1166 if (err) {
1167 mlx5_core_err(dev, "set_hca_cap failed\n");
1168 goto reclaim_boot_pages;
1169 }
1170
1171 err = mlx5_satisfy_startup_pages(dev, 0);
1172 if (err) {
1173 mlx5_core_err(dev, "failed to allocate init pages\n");
1174 goto reclaim_boot_pages;
1175 }
1176
1177 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1178 if (err) {
1179 mlx5_core_err(dev, "init hca failed\n");
1180 goto reclaim_boot_pages;
1181 }
1182
1183 mlx5_set_driver_version(dev);
1184
1185 err = mlx5_query_hca_caps(dev);
1186 if (err) {
1187 mlx5_core_err(dev, "query hca failed\n");
1188 goto reclaim_boot_pages;
1189 }
1190 mlx5_start_health_fw_log_up(dev);
1191
1192 return 0;
1193
1194 reclaim_boot_pages:
1195 mlx5_reclaim_startup_pages(dev);
1196 err_disable_hca:
1197 mlx5_core_disable_hca(dev, 0);
1198 stop_health_poll:
1199 mlx5_stop_health_poll(dev, boot);
1200 err_cmd_cleanup:
1201 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1202 mlx5_cmd_cleanup(dev);
1203
1204 return err;
1205 }
1206
mlx5_function_teardown(struct mlx5_core_dev * dev,bool boot)1207 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1208 {
1209 int err;
1210
1211 err = mlx5_cmd_teardown_hca(dev);
1212 if (err) {
1213 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1214 return err;
1215 }
1216 mlx5_reclaim_startup_pages(dev);
1217 mlx5_core_disable_hca(dev, 0);
1218 mlx5_stop_health_poll(dev, boot);
1219 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1220 mlx5_cmd_cleanup(dev);
1221
1222 return 0;
1223 }
1224
mlx5_load(struct mlx5_core_dev * dev)1225 static int mlx5_load(struct mlx5_core_dev *dev)
1226 {
1227 int err;
1228
1229 dev->priv.uar = mlx5_get_uars_page(dev);
1230 if (IS_ERR(dev->priv.uar)) {
1231 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1232 err = PTR_ERR(dev->priv.uar);
1233 return err;
1234 }
1235
1236 mlx5_events_start(dev);
1237 mlx5_pagealloc_start(dev);
1238
1239 err = mlx5_irq_table_create(dev);
1240 if (err) {
1241 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1242 goto err_irq_table;
1243 }
1244
1245 err = mlx5_eq_table_create(dev);
1246 if (err) {
1247 mlx5_core_err(dev, "Failed to create EQs\n");
1248 goto err_eq_table;
1249 }
1250
1251 err = mlx5_fw_tracer_init(dev->tracer);
1252 if (err) {
1253 mlx5_core_err(dev, "Failed to init FW tracer %d\n", err);
1254 mlx5_fw_tracer_destroy(dev->tracer);
1255 dev->tracer = NULL;
1256 }
1257
1258 mlx5_fw_reset_events_start(dev);
1259 mlx5_hv_vhca_init(dev->hv_vhca);
1260
1261 err = mlx5_rsc_dump_init(dev);
1262 if (err) {
1263 mlx5_core_err(dev, "Failed to init Resource dump %d\n", err);
1264 mlx5_rsc_dump_destroy(dev);
1265 dev->rsc_dump = NULL;
1266 }
1267
1268 err = mlx5_fpga_device_start(dev);
1269 if (err) {
1270 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1271 goto err_fpga_start;
1272 }
1273
1274 err = mlx5_fs_core_init(dev);
1275 if (err) {
1276 mlx5_core_err(dev, "Failed to init flow steering\n");
1277 goto err_fs;
1278 }
1279
1280 err = mlx5_core_set_hca_defaults(dev);
1281 if (err) {
1282 mlx5_core_err(dev, "Failed to set hca defaults\n");
1283 goto err_set_hca;
1284 }
1285
1286 mlx5_vhca_event_start(dev);
1287
1288 err = mlx5_sf_hw_table_create(dev);
1289 if (err) {
1290 mlx5_core_err(dev, "sf table create failed %d\n", err);
1291 goto err_vhca;
1292 }
1293
1294 err = mlx5_ec_init(dev);
1295 if (err) {
1296 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1297 goto err_ec;
1298 }
1299
1300 mlx5_lag_add_mdev(dev);
1301 err = mlx5_sriov_attach(dev);
1302 if (err) {
1303 mlx5_core_err(dev, "sriov init failed %d\n", err);
1304 goto err_sriov;
1305 }
1306
1307 mlx5_sf_dev_table_create(dev);
1308
1309 return 0;
1310
1311 err_sriov:
1312 mlx5_lag_remove_mdev(dev);
1313 mlx5_ec_cleanup(dev);
1314 err_ec:
1315 mlx5_sf_hw_table_destroy(dev);
1316 err_vhca:
1317 mlx5_vhca_event_stop(dev);
1318 err_set_hca:
1319 mlx5_fs_core_cleanup(dev);
1320 err_fs:
1321 mlx5_fpga_device_stop(dev);
1322 err_fpga_start:
1323 mlx5_rsc_dump_cleanup(dev);
1324 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1325 mlx5_fw_reset_events_stop(dev);
1326 mlx5_fw_tracer_cleanup(dev->tracer);
1327 mlx5_eq_table_destroy(dev);
1328 err_eq_table:
1329 mlx5_irq_table_destroy(dev);
1330 err_irq_table:
1331 mlx5_pagealloc_stop(dev);
1332 mlx5_events_stop(dev);
1333 mlx5_put_uars_page(dev, dev->priv.uar);
1334 return err;
1335 }
1336
mlx5_unload(struct mlx5_core_dev * dev)1337 static void mlx5_unload(struct mlx5_core_dev *dev)
1338 {
1339 mlx5_sf_dev_table_destroy(dev);
1340 mlx5_sriov_detach(dev);
1341 mlx5_eswitch_disable(dev->priv.eswitch);
1342 mlx5_lag_remove_mdev(dev);
1343 mlx5_ec_cleanup(dev);
1344 mlx5_sf_hw_table_destroy(dev);
1345 mlx5_vhca_event_stop(dev);
1346 mlx5_fs_core_cleanup(dev);
1347 mlx5_fpga_device_stop(dev);
1348 mlx5_rsc_dump_cleanup(dev);
1349 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1350 mlx5_fw_reset_events_stop(dev);
1351 mlx5_fw_tracer_cleanup(dev->tracer);
1352 mlx5_eq_table_destroy(dev);
1353 mlx5_irq_table_destroy(dev);
1354 mlx5_pagealloc_stop(dev);
1355 mlx5_events_stop(dev);
1356 mlx5_put_uars_page(dev, dev->priv.uar);
1357 }
1358
mlx5_init_one(struct mlx5_core_dev * dev)1359 int mlx5_init_one(struct mlx5_core_dev *dev)
1360 {
1361 struct devlink *devlink = priv_to_devlink(dev);
1362 int err = 0;
1363
1364 devl_lock(devlink);
1365 mutex_lock(&dev->intf_state_mutex);
1366 dev->state = MLX5_DEVICE_STATE_UP;
1367
1368 err = mlx5_function_setup(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT));
1369 if (err)
1370 goto err_function;
1371
1372 err = mlx5_init_once(dev);
1373 if (err) {
1374 mlx5_core_err(dev, "sw objs init failed\n");
1375 goto function_teardown;
1376 }
1377
1378 err = mlx5_load(dev);
1379 if (err)
1380 goto err_load;
1381
1382 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1383
1384 err = mlx5_devlink_register(priv_to_devlink(dev));
1385 if (err)
1386 goto err_devlink_reg;
1387
1388 err = mlx5_register_device(dev);
1389 if (err)
1390 goto err_register;
1391
1392 mutex_unlock(&dev->intf_state_mutex);
1393 devl_unlock(devlink);
1394 return 0;
1395
1396 err_register:
1397 mlx5_devlink_unregister(priv_to_devlink(dev));
1398 err_devlink_reg:
1399 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1400 mlx5_unload(dev);
1401 err_load:
1402 mlx5_cleanup_once(dev);
1403 function_teardown:
1404 mlx5_function_teardown(dev, true);
1405 err_function:
1406 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1407 mutex_unlock(&dev->intf_state_mutex);
1408 devl_unlock(devlink);
1409 return err;
1410 }
1411
mlx5_uninit_one(struct mlx5_core_dev * dev)1412 void mlx5_uninit_one(struct mlx5_core_dev *dev)
1413 {
1414 struct devlink *devlink = priv_to_devlink(dev);
1415
1416 devl_lock(devlink);
1417 mutex_lock(&dev->intf_state_mutex);
1418
1419 mlx5_unregister_device(dev);
1420 mlx5_devlink_unregister(priv_to_devlink(dev));
1421
1422 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1423 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1424 __func__);
1425 mlx5_cleanup_once(dev);
1426 goto out;
1427 }
1428
1429 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1430 mlx5_unload(dev);
1431 mlx5_cleanup_once(dev);
1432 mlx5_function_teardown(dev, true);
1433 out:
1434 mutex_unlock(&dev->intf_state_mutex);
1435 devl_unlock(devlink);
1436 }
1437
mlx5_load_one_devl_locked(struct mlx5_core_dev * dev,bool recovery)1438 int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery)
1439 {
1440 int err = 0;
1441 u64 timeout;
1442
1443 devl_assert_locked(priv_to_devlink(dev));
1444 mutex_lock(&dev->intf_state_mutex);
1445 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1446 mlx5_core_warn(dev, "interface is up, NOP\n");
1447 goto out;
1448 }
1449 /* remove any previous indication of internal error */
1450 dev->state = MLX5_DEVICE_STATE_UP;
1451
1452 if (recovery)
1453 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_ON_RECOVERY_TIMEOUT);
1454 else
1455 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT);
1456 err = mlx5_function_setup(dev, false, timeout);
1457 if (err)
1458 goto err_function;
1459
1460 err = mlx5_load(dev);
1461 if (err)
1462 goto err_load;
1463
1464 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1465
1466 err = mlx5_attach_device(dev);
1467 if (err)
1468 goto err_attach;
1469
1470 mutex_unlock(&dev->intf_state_mutex);
1471 return 0;
1472
1473 err_attach:
1474 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1475 mlx5_unload(dev);
1476 err_load:
1477 mlx5_function_teardown(dev, false);
1478 err_function:
1479 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1480 out:
1481 mutex_unlock(&dev->intf_state_mutex);
1482 return err;
1483 }
1484
mlx5_load_one(struct mlx5_core_dev * dev,bool recovery)1485 int mlx5_load_one(struct mlx5_core_dev *dev, bool recovery)
1486 {
1487 struct devlink *devlink = priv_to_devlink(dev);
1488 int ret;
1489
1490 devl_lock(devlink);
1491 ret = mlx5_load_one_devl_locked(dev, recovery);
1492 devl_unlock(devlink);
1493 return ret;
1494 }
1495
mlx5_unload_one_devl_locked(struct mlx5_core_dev * dev)1496 void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev)
1497 {
1498 devl_assert_locked(priv_to_devlink(dev));
1499 mutex_lock(&dev->intf_state_mutex);
1500
1501 mlx5_detach_device(dev);
1502
1503 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1504 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1505 __func__);
1506 goto out;
1507 }
1508
1509 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1510 mlx5_unload(dev);
1511 mlx5_function_teardown(dev, false);
1512 out:
1513 mutex_unlock(&dev->intf_state_mutex);
1514 }
1515
mlx5_unload_one(struct mlx5_core_dev * dev)1516 void mlx5_unload_one(struct mlx5_core_dev *dev)
1517 {
1518 struct devlink *devlink = priv_to_devlink(dev);
1519
1520 devl_lock(devlink);
1521 mlx5_unload_one_devl_locked(dev);
1522 devl_unlock(devlink);
1523 }
1524
1525 static const int types[] = {
1526 MLX5_CAP_GENERAL,
1527 MLX5_CAP_GENERAL_2,
1528 MLX5_CAP_ETHERNET_OFFLOADS,
1529 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1530 MLX5_CAP_ODP,
1531 MLX5_CAP_ATOMIC,
1532 MLX5_CAP_ROCE,
1533 MLX5_CAP_IPOIB_OFFLOADS,
1534 MLX5_CAP_FLOW_TABLE,
1535 MLX5_CAP_ESWITCH_FLOW_TABLE,
1536 MLX5_CAP_ESWITCH,
1537 MLX5_CAP_VECTOR_CALC,
1538 MLX5_CAP_QOS,
1539 MLX5_CAP_DEBUG,
1540 MLX5_CAP_DEV_MEM,
1541 MLX5_CAP_DEV_EVENT,
1542 MLX5_CAP_TLS,
1543 MLX5_CAP_VDPA_EMULATION,
1544 MLX5_CAP_IPSEC,
1545 MLX5_CAP_PORT_SELECTION,
1546 MLX5_CAP_DEV_SHAMPO,
1547 MLX5_CAP_MACSEC,
1548 MLX5_CAP_ADV_VIRTUALIZATION,
1549 };
1550
mlx5_hca_caps_free(struct mlx5_core_dev * dev)1551 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev)
1552 {
1553 int type;
1554 int i;
1555
1556 for (i = 0; i < ARRAY_SIZE(types); i++) {
1557 type = types[i];
1558 kfree(dev->caps.hca[type]);
1559 }
1560 }
1561
mlx5_hca_caps_alloc(struct mlx5_core_dev * dev)1562 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev)
1563 {
1564 struct mlx5_hca_cap *cap;
1565 int type;
1566 int i;
1567
1568 for (i = 0; i < ARRAY_SIZE(types); i++) {
1569 cap = kzalloc(sizeof(*cap), GFP_KERNEL);
1570 if (!cap)
1571 goto err;
1572 type = types[i];
1573 dev->caps.hca[type] = cap;
1574 }
1575
1576 return 0;
1577
1578 err:
1579 mlx5_hca_caps_free(dev);
1580 return -ENOMEM;
1581 }
1582
mlx5_mdev_init(struct mlx5_core_dev * dev,int profile_idx)1583 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1584 {
1585 struct mlx5_priv *priv = &dev->priv;
1586 int err;
1587
1588 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile));
1589 INIT_LIST_HEAD(&priv->ctx_list);
1590 spin_lock_init(&priv->ctx_lock);
1591 lockdep_register_key(&dev->lock_key);
1592 mutex_init(&dev->intf_state_mutex);
1593 lockdep_set_class(&dev->intf_state_mutex, &dev->lock_key);
1594
1595 mutex_init(&priv->bfregs.reg_head.lock);
1596 mutex_init(&priv->bfregs.wc_head.lock);
1597 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1598 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1599
1600 mutex_init(&priv->alloc_mutex);
1601 mutex_init(&priv->pgdir_mutex);
1602 INIT_LIST_HEAD(&priv->pgdir_list);
1603
1604 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev));
1605 priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device),
1606 mlx5_debugfs_root);
1607 INIT_LIST_HEAD(&priv->traps);
1608
1609 err = mlx5_tout_init(dev);
1610 if (err) {
1611 mlx5_core_err(dev, "Failed initializing timeouts, aborting\n");
1612 goto err_timeout_init;
1613 }
1614
1615 err = mlx5_health_init(dev);
1616 if (err)
1617 goto err_health_init;
1618
1619 err = mlx5_pagealloc_init(dev);
1620 if (err)
1621 goto err_pagealloc_init;
1622
1623 err = mlx5_adev_init(dev);
1624 if (err)
1625 goto err_adev_init;
1626
1627 err = mlx5_hca_caps_alloc(dev);
1628 if (err)
1629 goto err_hca_caps;
1630
1631 /* The conjunction of sw_vhca_id with sw_owner_id will be a global
1632 * unique id per function which uses mlx5_core.
1633 * Those values are supplied to FW as part of the init HCA command to
1634 * be used by both driver and FW when it's applicable.
1635 */
1636 dev->priv.sw_vhca_id = ida_alloc_range(&sw_vhca_ida, 1,
1637 MAX_SW_VHCA_ID,
1638 GFP_KERNEL);
1639 if (dev->priv.sw_vhca_id < 0)
1640 mlx5_core_err(dev, "failed to allocate sw_vhca_id, err=%d\n",
1641 dev->priv.sw_vhca_id);
1642
1643 return 0;
1644
1645 err_hca_caps:
1646 mlx5_adev_cleanup(dev);
1647 err_adev_init:
1648 mlx5_pagealloc_cleanup(dev);
1649 err_pagealloc_init:
1650 mlx5_health_cleanup(dev);
1651 err_health_init:
1652 mlx5_tout_cleanup(dev);
1653 err_timeout_init:
1654 debugfs_remove(dev->priv.dbg.dbg_root);
1655 mutex_destroy(&priv->pgdir_mutex);
1656 mutex_destroy(&priv->alloc_mutex);
1657 mutex_destroy(&priv->bfregs.wc_head.lock);
1658 mutex_destroy(&priv->bfregs.reg_head.lock);
1659 mutex_destroy(&dev->intf_state_mutex);
1660 lockdep_unregister_key(&dev->lock_key);
1661 return err;
1662 }
1663
mlx5_mdev_uninit(struct mlx5_core_dev * dev)1664 void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1665 {
1666 struct mlx5_priv *priv = &dev->priv;
1667
1668 if (priv->sw_vhca_id > 0)
1669 ida_free(&sw_vhca_ida, dev->priv.sw_vhca_id);
1670
1671 mlx5_hca_caps_free(dev);
1672 mlx5_adev_cleanup(dev);
1673 mlx5_pagealloc_cleanup(dev);
1674 mlx5_health_cleanup(dev);
1675 mlx5_tout_cleanup(dev);
1676 debugfs_remove_recursive(dev->priv.dbg.dbg_root);
1677 mutex_destroy(&priv->pgdir_mutex);
1678 mutex_destroy(&priv->alloc_mutex);
1679 mutex_destroy(&priv->bfregs.wc_head.lock);
1680 mutex_destroy(&priv->bfregs.reg_head.lock);
1681 mutex_destroy(&dev->intf_state_mutex);
1682 lockdep_unregister_key(&dev->lock_key);
1683 }
1684
probe_one(struct pci_dev * pdev,const struct pci_device_id * id)1685 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1686 {
1687 struct mlx5_core_dev *dev;
1688 struct devlink *devlink;
1689 int err;
1690
1691 devlink = mlx5_devlink_alloc(&pdev->dev);
1692 if (!devlink) {
1693 dev_err(&pdev->dev, "devlink alloc failed\n");
1694 return -ENOMEM;
1695 }
1696
1697 dev = devlink_priv(devlink);
1698 dev->device = &pdev->dev;
1699 dev->pdev = pdev;
1700
1701 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1702 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1703
1704 dev->priv.adev_idx = mlx5_adev_idx_alloc();
1705 if (dev->priv.adev_idx < 0) {
1706 err = dev->priv.adev_idx;
1707 goto adev_init_err;
1708 }
1709
1710 err = mlx5_mdev_init(dev, prof_sel);
1711 if (err)
1712 goto mdev_init_err;
1713
1714 err = mlx5_pci_init(dev, pdev, id);
1715 if (err) {
1716 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1717 err);
1718 goto pci_init_err;
1719 }
1720
1721 err = mlx5_init_one(dev);
1722 if (err) {
1723 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n",
1724 err);
1725 goto err_init_one;
1726 }
1727
1728 err = mlx5_crdump_enable(dev);
1729 if (err)
1730 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err);
1731
1732 pci_save_state(pdev);
1733 devlink_register(devlink);
1734 return 0;
1735
1736 err_init_one:
1737 mlx5_pci_close(dev);
1738 pci_init_err:
1739 mlx5_mdev_uninit(dev);
1740 mdev_init_err:
1741 mlx5_adev_idx_free(dev->priv.adev_idx);
1742 adev_init_err:
1743 mlx5_devlink_free(devlink);
1744
1745 return err;
1746 }
1747
remove_one(struct pci_dev * pdev)1748 static void remove_one(struct pci_dev *pdev)
1749 {
1750 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1751 struct devlink *devlink = priv_to_devlink(dev);
1752
1753 /* mlx5_drain_fw_reset() is using devlink APIs. Hence, we must drain
1754 * fw_reset before unregistering the devlink.
1755 */
1756 mlx5_drain_fw_reset(dev);
1757 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state);
1758 devlink_unregister(devlink);
1759 mlx5_sriov_disable(pdev);
1760 mlx5_crdump_disable(dev);
1761 mlx5_drain_health_wq(dev);
1762 mlx5_uninit_one(dev);
1763 mlx5_pci_close(dev);
1764 mlx5_mdev_uninit(dev);
1765 mlx5_adev_idx_free(dev->priv.adev_idx);
1766 mlx5_devlink_free(devlink);
1767 }
1768
1769 #define mlx5_pci_trace(dev, fmt, ...) ({ \
1770 struct mlx5_core_dev *__dev = (dev); \
1771 mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \
1772 __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \
1773 __dev->pci_status, ##__VA_ARGS__); \
1774 })
1775
result2str(enum pci_ers_result result)1776 static const char *result2str(enum pci_ers_result result)
1777 {
1778 return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" :
1779 result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" :
1780 result == PCI_ERS_RESULT_RECOVERED ? "recovered" :
1781 "unknown";
1782 }
1783
mlx5_pci_err_detected(struct pci_dev * pdev,pci_channel_state_t state)1784 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1785 pci_channel_state_t state)
1786 {
1787 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1788 enum pci_ers_result res;
1789
1790 mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state);
1791
1792 mlx5_enter_error_state(dev, false);
1793 mlx5_error_sw_reset(dev);
1794 mlx5_unload_one(dev);
1795 mlx5_drain_health_wq(dev);
1796 mlx5_pci_disable_device(dev);
1797
1798 res = state == pci_channel_io_perm_failure ?
1799 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1800
1801 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, result = %d, %s\n",
1802 __func__, dev->state, dev->pci_status, res, result2str(res));
1803 return res;
1804 }
1805
1806 /* wait for the device to show vital signs by waiting
1807 * for the health counter to start counting.
1808 */
wait_vital(struct pci_dev * pdev)1809 static int wait_vital(struct pci_dev *pdev)
1810 {
1811 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1812 struct mlx5_core_health *health = &dev->priv.health;
1813 const int niter = 100;
1814 u32 last_count = 0;
1815 u32 count;
1816 int i;
1817
1818 for (i = 0; i < niter; i++) {
1819 count = ioread32be(health->health_counter);
1820 if (count && count != 0xffffffff) {
1821 if (last_count && last_count != count) {
1822 mlx5_core_info(dev,
1823 "wait vital counter value 0x%x after %d iterations\n",
1824 count, i);
1825 return 0;
1826 }
1827 last_count = count;
1828 }
1829 msleep(50);
1830 }
1831
1832 return -ETIMEDOUT;
1833 }
1834
mlx5_pci_slot_reset(struct pci_dev * pdev)1835 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1836 {
1837 enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT;
1838 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1839 int err;
1840
1841 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Enter\n",
1842 __func__, dev->state, dev->pci_status);
1843
1844 err = mlx5_pci_enable_device(dev);
1845 if (err) {
1846 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
1847 __func__, err);
1848 goto out;
1849 }
1850
1851 pci_set_master(pdev);
1852 pci_restore_state(pdev);
1853 pci_save_state(pdev);
1854
1855 err = wait_vital(pdev);
1856 if (err) {
1857 mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n",
1858 __func__, err);
1859 goto out;
1860 }
1861
1862 res = PCI_ERS_RESULT_RECOVERED;
1863 out:
1864 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, err = %d, result = %d, %s\n",
1865 __func__, dev->state, dev->pci_status, err, res, result2str(res));
1866 return res;
1867 }
1868
mlx5_pci_resume(struct pci_dev * pdev)1869 static void mlx5_pci_resume(struct pci_dev *pdev)
1870 {
1871 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1872 int err;
1873
1874 mlx5_pci_trace(dev, "Enter, loading driver..\n");
1875
1876 err = mlx5_load_one(dev, false);
1877
1878 if (!err)
1879 devlink_health_reporter_state_update(dev->priv.health.fw_fatal_reporter,
1880 DEVLINK_HEALTH_REPORTER_STATE_HEALTHY);
1881
1882 mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err,
1883 !err ? "recovered" : "Failed");
1884 }
1885
1886 static const struct pci_error_handlers mlx5_err_handler = {
1887 .error_detected = mlx5_pci_err_detected,
1888 .slot_reset = mlx5_pci_slot_reset,
1889 .resume = mlx5_pci_resume
1890 };
1891
mlx5_try_fast_unload(struct mlx5_core_dev * dev)1892 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1893 {
1894 bool fast_teardown = false, force_teardown = false;
1895 int ret = 1;
1896
1897 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1898 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1899
1900 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1901 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1902
1903 if (!fast_teardown && !force_teardown)
1904 return -EOPNOTSUPP;
1905
1906 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1907 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1908 return -EAGAIN;
1909 }
1910
1911 /* Panic tear down fw command will stop the PCI bus communication
1912 * with the HCA, so the health poll is no longer needed.
1913 */
1914 mlx5_drain_health_wq(dev);
1915 mlx5_stop_health_poll(dev, false);
1916
1917 ret = mlx5_cmd_fast_teardown_hca(dev);
1918 if (!ret)
1919 goto succeed;
1920
1921 ret = mlx5_cmd_force_teardown_hca(dev);
1922 if (!ret)
1923 goto succeed;
1924
1925 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1926 mlx5_start_health_poll(dev);
1927 return ret;
1928
1929 succeed:
1930 mlx5_enter_error_state(dev, true);
1931
1932 /* Some platforms requiring freeing the IRQ's in the shutdown
1933 * flow. If they aren't freed they can't be allocated after
1934 * kexec. There is no need to cleanup the mlx5_core software
1935 * contexts.
1936 */
1937 mlx5_core_eq_free_irqs(dev);
1938
1939 return 0;
1940 }
1941
shutdown(struct pci_dev * pdev)1942 static void shutdown(struct pci_dev *pdev)
1943 {
1944 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1945 int err;
1946
1947 mlx5_core_info(dev, "Shutdown was called\n");
1948 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state);
1949 err = mlx5_try_fast_unload(dev);
1950 if (err)
1951 mlx5_unload_one(dev);
1952 mlx5_pci_disable_device(dev);
1953 }
1954
mlx5_suspend(struct pci_dev * pdev,pm_message_t state)1955 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state)
1956 {
1957 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1958
1959 mlx5_unload_one(dev);
1960
1961 return 0;
1962 }
1963
mlx5_resume(struct pci_dev * pdev)1964 static int mlx5_resume(struct pci_dev *pdev)
1965 {
1966 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1967
1968 return mlx5_load_one(dev, false);
1969 }
1970
1971 static const struct pci_device_id mlx5_core_pci_table[] = {
1972 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1973 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1974 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1975 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1976 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1977 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1978 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1979 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1980 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1981 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1982 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1983 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1984 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
1985 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
1986 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
1987 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
1988 { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */
1989 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1990 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1991 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
1992 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */
1993 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */
1994 { 0, }
1995 };
1996
1997 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1998
mlx5_disable_device(struct mlx5_core_dev * dev)1999 void mlx5_disable_device(struct mlx5_core_dev *dev)
2000 {
2001 mlx5_error_sw_reset(dev);
2002 mlx5_unload_one_devl_locked(dev);
2003 }
2004
mlx5_recover_device(struct mlx5_core_dev * dev)2005 int mlx5_recover_device(struct mlx5_core_dev *dev)
2006 {
2007 if (!mlx5_core_is_sf(dev)) {
2008 mlx5_pci_disable_device(dev);
2009 if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED)
2010 return -EIO;
2011 }
2012
2013 return mlx5_load_one_devl_locked(dev, true);
2014 }
2015
2016 static struct pci_driver mlx5_core_driver = {
2017 .name = KBUILD_MODNAME,
2018 .id_table = mlx5_core_pci_table,
2019 .probe = probe_one,
2020 .remove = remove_one,
2021 .suspend = mlx5_suspend,
2022 .resume = mlx5_resume,
2023 .shutdown = shutdown,
2024 .err_handler = &mlx5_err_handler,
2025 .sriov_configure = mlx5_core_sriov_configure,
2026 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix,
2027 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count,
2028 };
2029
2030 /**
2031 * mlx5_vf_get_core_dev - Get the mlx5 core device from a given VF PCI device if
2032 * mlx5_core is its driver.
2033 * @pdev: The associated PCI device.
2034 *
2035 * Upon return the interface state lock stay held to let caller uses it safely.
2036 * Caller must ensure to use the returned mlx5 device for a narrow window
2037 * and put it back with mlx5_vf_put_core_dev() immediately once usage was over.
2038 *
2039 * Return: Pointer to the associated mlx5_core_dev or NULL.
2040 */
mlx5_vf_get_core_dev(struct pci_dev * pdev)2041 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev)
2042 {
2043 struct mlx5_core_dev *mdev;
2044
2045 mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver);
2046 if (IS_ERR(mdev))
2047 return NULL;
2048
2049 mutex_lock(&mdev->intf_state_mutex);
2050 if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) {
2051 mutex_unlock(&mdev->intf_state_mutex);
2052 return NULL;
2053 }
2054
2055 return mdev;
2056 }
2057 EXPORT_SYMBOL(mlx5_vf_get_core_dev);
2058
2059 /**
2060 * mlx5_vf_put_core_dev - Put the mlx5 core device back.
2061 * @mdev: The mlx5 core device.
2062 *
2063 * Upon return the interface state lock is unlocked and caller should not
2064 * access the mdev any more.
2065 */
mlx5_vf_put_core_dev(struct mlx5_core_dev * mdev)2066 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev)
2067 {
2068 mutex_unlock(&mdev->intf_state_mutex);
2069 }
2070 EXPORT_SYMBOL(mlx5_vf_put_core_dev);
2071
mlx5_core_verify_params(void)2072 static void mlx5_core_verify_params(void)
2073 {
2074 if (prof_sel >= ARRAY_SIZE(profile)) {
2075 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
2076 prof_sel,
2077 ARRAY_SIZE(profile) - 1,
2078 MLX5_DEFAULT_PROF);
2079 prof_sel = MLX5_DEFAULT_PROF;
2080 }
2081 }
2082
init(void)2083 static int __init init(void)
2084 {
2085 int err;
2086
2087 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME),
2088 "mlx5_core name not in sync with kernel module name");
2089
2090 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
2091
2092 mlx5_core_verify_params();
2093 mlx5_register_debugfs();
2094
2095 err = pci_register_driver(&mlx5_core_driver);
2096 if (err)
2097 goto err_debug;
2098
2099 err = mlx5_sf_driver_register();
2100 if (err)
2101 goto err_sf;
2102
2103 err = mlx5e_init();
2104 if (err)
2105 goto err_en;
2106
2107 return 0;
2108
2109 err_en:
2110 mlx5_sf_driver_unregister();
2111 err_sf:
2112 pci_unregister_driver(&mlx5_core_driver);
2113 err_debug:
2114 mlx5_unregister_debugfs();
2115 return err;
2116 }
2117
cleanup(void)2118 static void __exit cleanup(void)
2119 {
2120 mlx5e_cleanup();
2121 mlx5_sf_driver_unregister();
2122 pci_unregister_driver(&mlx5_core_driver);
2123 mlx5_unregister_debugfs();
2124 }
2125
2126 module_init(init);
2127 module_exit(cleanup);
2128
