1 /*
2 * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/errno.h>
36 #include <linux/pci.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/slab.h>
39 #include <linux/delay.h>
40 #include <linux/random.h>
41 #include <linux/io-mapping.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/debugfs.h>
44
45 #include "mlx5_core.h"
46
47 enum {
48 CMD_IF_REV = 5,
49 };
50
51 enum {
52 CMD_MODE_POLLING,
53 CMD_MODE_EVENTS
54 };
55
56 enum {
57 MLX5_CMD_DELIVERY_STAT_OK = 0x0,
58 MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR = 0x1,
59 MLX5_CMD_DELIVERY_STAT_TOK_ERR = 0x2,
60 MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR = 0x3,
61 MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR = 0x4,
62 MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR = 0x5,
63 MLX5_CMD_DELIVERY_STAT_FW_ERR = 0x6,
64 MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR = 0x7,
65 MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR = 0x8,
66 MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR = 0x9,
67 MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR = 0x10,
68 };
69
alloc_cmd(struct mlx5_cmd * cmd,struct mlx5_cmd_msg * in,struct mlx5_cmd_msg * out,void * uout,int uout_size,mlx5_cmd_cbk_t cbk,void * context,int page_queue)70 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
71 struct mlx5_cmd_msg *in,
72 struct mlx5_cmd_msg *out,
73 void *uout, int uout_size,
74 mlx5_cmd_cbk_t cbk,
75 void *context, int page_queue)
76 {
77 gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
78 struct mlx5_cmd_work_ent *ent;
79
80 ent = kzalloc(sizeof(*ent), alloc_flags);
81 if (!ent)
82 return ERR_PTR(-ENOMEM);
83
84 ent->in = in;
85 ent->out = out;
86 ent->uout = uout;
87 ent->uout_size = uout_size;
88 ent->callback = cbk;
89 ent->context = context;
90 ent->cmd = cmd;
91 ent->page_queue = page_queue;
92
93 return ent;
94 }
95
alloc_token(struct mlx5_cmd * cmd)96 static u8 alloc_token(struct mlx5_cmd *cmd)
97 {
98 u8 token;
99
100 spin_lock(&cmd->token_lock);
101 cmd->token++;
102 if (cmd->token == 0)
103 cmd->token++;
104 token = cmd->token;
105 spin_unlock(&cmd->token_lock);
106
107 return token;
108 }
109
alloc_ent(struct mlx5_cmd * cmd)110 static int alloc_ent(struct mlx5_cmd *cmd)
111 {
112 unsigned long flags;
113 int ret;
114
115 spin_lock_irqsave(&cmd->alloc_lock, flags);
116 ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
117 if (ret < cmd->max_reg_cmds)
118 clear_bit(ret, &cmd->bitmask);
119 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
120
121 return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
122 }
123
free_ent(struct mlx5_cmd * cmd,int idx)124 static void free_ent(struct mlx5_cmd *cmd, int idx)
125 {
126 unsigned long flags;
127
128 spin_lock_irqsave(&cmd->alloc_lock, flags);
129 set_bit(idx, &cmd->bitmask);
130 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
131 }
132
get_inst(struct mlx5_cmd * cmd,int idx)133 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
134 {
135 return cmd->cmd_buf + (idx << cmd->log_stride);
136 }
137
mlx5_calc_cmd_blocks(struct mlx5_cmd_msg * msg)138 static int mlx5_calc_cmd_blocks(struct mlx5_cmd_msg *msg)
139 {
140 int size = msg->len;
141 int blen = size - min_t(int, sizeof(msg->first.data), size);
142
143 return DIV_ROUND_UP(blen, MLX5_CMD_DATA_BLOCK_SIZE);
144 }
145
xor8_buf(void * buf,size_t offset,int len)146 static u8 xor8_buf(void *buf, size_t offset, int len)
147 {
148 u8 *ptr = buf;
149 u8 sum = 0;
150 int i;
151 int end = len + offset;
152
153 for (i = offset; i < end; i++)
154 sum ^= ptr[i];
155
156 return sum;
157 }
158
verify_block_sig(struct mlx5_cmd_prot_block * block)159 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
160 {
161 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
162 int xor_len = sizeof(*block) - sizeof(block->data) - 1;
163
164 if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
165 return -EINVAL;
166
167 if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
168 return -EINVAL;
169
170 return 0;
171 }
172
calc_block_sig(struct mlx5_cmd_prot_block * block)173 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
174 {
175 int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
176 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
177
178 block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
179 block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
180 }
181
calc_chain_sig(struct mlx5_cmd_msg * msg)182 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
183 {
184 struct mlx5_cmd_mailbox *next = msg->next;
185 int n = mlx5_calc_cmd_blocks(msg);
186 int i = 0;
187
188 for (i = 0; i < n && next; i++) {
189 calc_block_sig(next->buf);
190 next = next->next;
191 }
192 }
193
set_signature(struct mlx5_cmd_work_ent * ent,int csum)194 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
195 {
196 ent->lay->sig = ~xor8_buf(ent->lay, 0, sizeof(*ent->lay));
197 if (csum) {
198 calc_chain_sig(ent->in);
199 calc_chain_sig(ent->out);
200 }
201 }
202
poll_timeout(struct mlx5_cmd_work_ent * ent)203 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
204 {
205 unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
206 u8 own;
207
208 do {
209 own = READ_ONCE(ent->lay->status_own);
210 if (!(own & CMD_OWNER_HW)) {
211 ent->ret = 0;
212 return;
213 }
214 cond_resched();
215 } while (time_before(jiffies, poll_end));
216
217 ent->ret = -ETIMEDOUT;
218 }
219
free_cmd(struct mlx5_cmd_work_ent * ent)220 static void free_cmd(struct mlx5_cmd_work_ent *ent)
221 {
222 kfree(ent);
223 }
224
verify_signature(struct mlx5_cmd_work_ent * ent)225 static int verify_signature(struct mlx5_cmd_work_ent *ent)
226 {
227 struct mlx5_cmd_mailbox *next = ent->out->next;
228 int n = mlx5_calc_cmd_blocks(ent->out);
229 int err;
230 u8 sig;
231 int i = 0;
232
233 sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
234 if (sig != 0xff)
235 return -EINVAL;
236
237 for (i = 0; i < n && next; i++) {
238 err = verify_block_sig(next->buf);
239 if (err)
240 return err;
241
242 next = next->next;
243 }
244
245 return 0;
246 }
247
dump_buf(void * buf,int size,int data_only,int offset)248 static void dump_buf(void *buf, int size, int data_only, int offset)
249 {
250 __be32 *p = buf;
251 int i;
252
253 for (i = 0; i < size; i += 16) {
254 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
255 be32_to_cpu(p[1]), be32_to_cpu(p[2]),
256 be32_to_cpu(p[3]));
257 p += 4;
258 offset += 16;
259 }
260 if (!data_only)
261 pr_debug("\n");
262 }
263
mlx5_internal_err_ret_value(struct mlx5_core_dev * dev,u16 op,u32 * synd,u8 * status)264 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
265 u32 *synd, u8 *status)
266 {
267 *synd = 0;
268 *status = 0;
269
270 switch (op) {
271 case MLX5_CMD_OP_TEARDOWN_HCA:
272 case MLX5_CMD_OP_DISABLE_HCA:
273 case MLX5_CMD_OP_MANAGE_PAGES:
274 case MLX5_CMD_OP_DESTROY_MKEY:
275 case MLX5_CMD_OP_DESTROY_EQ:
276 case MLX5_CMD_OP_DESTROY_CQ:
277 case MLX5_CMD_OP_DESTROY_QP:
278 case MLX5_CMD_OP_DESTROY_PSV:
279 case MLX5_CMD_OP_DESTROY_SRQ:
280 case MLX5_CMD_OP_DESTROY_XRC_SRQ:
281 case MLX5_CMD_OP_DESTROY_XRQ:
282 case MLX5_CMD_OP_DESTROY_DCT:
283 case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
284 case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
285 case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
286 case MLX5_CMD_OP_DEALLOC_PD:
287 case MLX5_CMD_OP_DEALLOC_UAR:
288 case MLX5_CMD_OP_DETACH_FROM_MCG:
289 case MLX5_CMD_OP_DEALLOC_XRCD:
290 case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
291 case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
292 case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
293 case MLX5_CMD_OP_DESTROY_LAG:
294 case MLX5_CMD_OP_DESTROY_VPORT_LAG:
295 case MLX5_CMD_OP_DESTROY_TIR:
296 case MLX5_CMD_OP_DESTROY_SQ:
297 case MLX5_CMD_OP_DESTROY_RQ:
298 case MLX5_CMD_OP_DESTROY_RMP:
299 case MLX5_CMD_OP_DESTROY_TIS:
300 case MLX5_CMD_OP_DESTROY_RQT:
301 case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
302 case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
303 case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
304 case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
305 case MLX5_CMD_OP_2ERR_QP:
306 case MLX5_CMD_OP_2RST_QP:
307 case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
308 case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
309 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
310 case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
311 case MLX5_CMD_OP_DEALLOC_ENCAP_HEADER:
312 case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
313 case MLX5_CMD_OP_FPGA_DESTROY_QP:
314 case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT:
315 return MLX5_CMD_STAT_OK;
316
317 case MLX5_CMD_OP_QUERY_HCA_CAP:
318 case MLX5_CMD_OP_QUERY_ADAPTER:
319 case MLX5_CMD_OP_INIT_HCA:
320 case MLX5_CMD_OP_ENABLE_HCA:
321 case MLX5_CMD_OP_QUERY_PAGES:
322 case MLX5_CMD_OP_SET_HCA_CAP:
323 case MLX5_CMD_OP_QUERY_ISSI:
324 case MLX5_CMD_OP_SET_ISSI:
325 case MLX5_CMD_OP_CREATE_MKEY:
326 case MLX5_CMD_OP_QUERY_MKEY:
327 case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
328 case MLX5_CMD_OP_PAGE_FAULT_RESUME:
329 case MLX5_CMD_OP_CREATE_EQ:
330 case MLX5_CMD_OP_QUERY_EQ:
331 case MLX5_CMD_OP_GEN_EQE:
332 case MLX5_CMD_OP_CREATE_CQ:
333 case MLX5_CMD_OP_QUERY_CQ:
334 case MLX5_CMD_OP_MODIFY_CQ:
335 case MLX5_CMD_OP_CREATE_QP:
336 case MLX5_CMD_OP_RST2INIT_QP:
337 case MLX5_CMD_OP_INIT2RTR_QP:
338 case MLX5_CMD_OP_RTR2RTS_QP:
339 case MLX5_CMD_OP_RTS2RTS_QP:
340 case MLX5_CMD_OP_SQERR2RTS_QP:
341 case MLX5_CMD_OP_QUERY_QP:
342 case MLX5_CMD_OP_SQD_RTS_QP:
343 case MLX5_CMD_OP_INIT2INIT_QP:
344 case MLX5_CMD_OP_CREATE_PSV:
345 case MLX5_CMD_OP_CREATE_SRQ:
346 case MLX5_CMD_OP_QUERY_SRQ:
347 case MLX5_CMD_OP_ARM_RQ:
348 case MLX5_CMD_OP_CREATE_XRC_SRQ:
349 case MLX5_CMD_OP_QUERY_XRC_SRQ:
350 case MLX5_CMD_OP_ARM_XRC_SRQ:
351 case MLX5_CMD_OP_CREATE_XRQ:
352 case MLX5_CMD_OP_QUERY_XRQ:
353 case MLX5_CMD_OP_ARM_XRQ:
354 case MLX5_CMD_OP_CREATE_DCT:
355 case MLX5_CMD_OP_DRAIN_DCT:
356 case MLX5_CMD_OP_QUERY_DCT:
357 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
358 case MLX5_CMD_OP_QUERY_VPORT_STATE:
359 case MLX5_CMD_OP_MODIFY_VPORT_STATE:
360 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
361 case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
362 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
363 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
364 case MLX5_CMD_OP_SET_ROCE_ADDRESS:
365 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
366 case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
367 case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
368 case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
369 case MLX5_CMD_OP_QUERY_VNIC_ENV:
370 case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
371 case MLX5_CMD_OP_ALLOC_Q_COUNTER:
372 case MLX5_CMD_OP_QUERY_Q_COUNTER:
373 case MLX5_CMD_OP_SET_PP_RATE_LIMIT:
374 case MLX5_CMD_OP_QUERY_RATE_LIMIT:
375 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
376 case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
377 case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
378 case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
379 case MLX5_CMD_OP_ALLOC_PD:
380 case MLX5_CMD_OP_ALLOC_UAR:
381 case MLX5_CMD_OP_CONFIG_INT_MODERATION:
382 case MLX5_CMD_OP_ACCESS_REG:
383 case MLX5_CMD_OP_ATTACH_TO_MCG:
384 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
385 case MLX5_CMD_OP_MAD_IFC:
386 case MLX5_CMD_OP_QUERY_MAD_DEMUX:
387 case MLX5_CMD_OP_SET_MAD_DEMUX:
388 case MLX5_CMD_OP_NOP:
389 case MLX5_CMD_OP_ALLOC_XRCD:
390 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
391 case MLX5_CMD_OP_QUERY_CONG_STATUS:
392 case MLX5_CMD_OP_MODIFY_CONG_STATUS:
393 case MLX5_CMD_OP_QUERY_CONG_PARAMS:
394 case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
395 case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
396 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
397 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
398 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
399 case MLX5_CMD_OP_CREATE_LAG:
400 case MLX5_CMD_OP_MODIFY_LAG:
401 case MLX5_CMD_OP_QUERY_LAG:
402 case MLX5_CMD_OP_CREATE_VPORT_LAG:
403 case MLX5_CMD_OP_CREATE_TIR:
404 case MLX5_CMD_OP_MODIFY_TIR:
405 case MLX5_CMD_OP_QUERY_TIR:
406 case MLX5_CMD_OP_CREATE_SQ:
407 case MLX5_CMD_OP_MODIFY_SQ:
408 case MLX5_CMD_OP_QUERY_SQ:
409 case MLX5_CMD_OP_CREATE_RQ:
410 case MLX5_CMD_OP_MODIFY_RQ:
411 case MLX5_CMD_OP_QUERY_RQ:
412 case MLX5_CMD_OP_CREATE_RMP:
413 case MLX5_CMD_OP_MODIFY_RMP:
414 case MLX5_CMD_OP_QUERY_RMP:
415 case MLX5_CMD_OP_CREATE_TIS:
416 case MLX5_CMD_OP_MODIFY_TIS:
417 case MLX5_CMD_OP_QUERY_TIS:
418 case MLX5_CMD_OP_CREATE_RQT:
419 case MLX5_CMD_OP_MODIFY_RQT:
420 case MLX5_CMD_OP_QUERY_RQT:
421
422 case MLX5_CMD_OP_CREATE_FLOW_TABLE:
423 case MLX5_CMD_OP_QUERY_FLOW_TABLE:
424 case MLX5_CMD_OP_CREATE_FLOW_GROUP:
425 case MLX5_CMD_OP_QUERY_FLOW_GROUP:
426 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
427 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
428 case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
429 case MLX5_CMD_OP_ALLOC_ENCAP_HEADER:
430 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
431 case MLX5_CMD_OP_FPGA_CREATE_QP:
432 case MLX5_CMD_OP_FPGA_MODIFY_QP:
433 case MLX5_CMD_OP_FPGA_QUERY_QP:
434 case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
435 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
436 case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT:
437 case MLX5_CMD_OP_QUERY_GENERAL_OBJECT:
438 *status = MLX5_DRIVER_STATUS_ABORTED;
439 *synd = MLX5_DRIVER_SYND;
440 return -EIO;
441 default:
442 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
443 return -EINVAL;
444 }
445 }
446
mlx5_command_str(int command)447 const char *mlx5_command_str(int command)
448 {
449 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
450
451 switch (command) {
452 MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
453 MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
454 MLX5_COMMAND_STR_CASE(INIT_HCA);
455 MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
456 MLX5_COMMAND_STR_CASE(ENABLE_HCA);
457 MLX5_COMMAND_STR_CASE(DISABLE_HCA);
458 MLX5_COMMAND_STR_CASE(QUERY_PAGES);
459 MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
460 MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
461 MLX5_COMMAND_STR_CASE(QUERY_ISSI);
462 MLX5_COMMAND_STR_CASE(SET_ISSI);
463 MLX5_COMMAND_STR_CASE(SET_DRIVER_VERSION);
464 MLX5_COMMAND_STR_CASE(CREATE_MKEY);
465 MLX5_COMMAND_STR_CASE(QUERY_MKEY);
466 MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
467 MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
468 MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
469 MLX5_COMMAND_STR_CASE(CREATE_EQ);
470 MLX5_COMMAND_STR_CASE(DESTROY_EQ);
471 MLX5_COMMAND_STR_CASE(QUERY_EQ);
472 MLX5_COMMAND_STR_CASE(GEN_EQE);
473 MLX5_COMMAND_STR_CASE(CREATE_CQ);
474 MLX5_COMMAND_STR_CASE(DESTROY_CQ);
475 MLX5_COMMAND_STR_CASE(QUERY_CQ);
476 MLX5_COMMAND_STR_CASE(MODIFY_CQ);
477 MLX5_COMMAND_STR_CASE(CREATE_QP);
478 MLX5_COMMAND_STR_CASE(DESTROY_QP);
479 MLX5_COMMAND_STR_CASE(RST2INIT_QP);
480 MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
481 MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
482 MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
483 MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
484 MLX5_COMMAND_STR_CASE(2ERR_QP);
485 MLX5_COMMAND_STR_CASE(2RST_QP);
486 MLX5_COMMAND_STR_CASE(QUERY_QP);
487 MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
488 MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
489 MLX5_COMMAND_STR_CASE(CREATE_PSV);
490 MLX5_COMMAND_STR_CASE(DESTROY_PSV);
491 MLX5_COMMAND_STR_CASE(CREATE_SRQ);
492 MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
493 MLX5_COMMAND_STR_CASE(QUERY_SRQ);
494 MLX5_COMMAND_STR_CASE(ARM_RQ);
495 MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
496 MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
497 MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
498 MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
499 MLX5_COMMAND_STR_CASE(CREATE_DCT);
500 MLX5_COMMAND_STR_CASE(DESTROY_DCT);
501 MLX5_COMMAND_STR_CASE(DRAIN_DCT);
502 MLX5_COMMAND_STR_CASE(QUERY_DCT);
503 MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
504 MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
505 MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
506 MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
507 MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
508 MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
509 MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
510 MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
511 MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
512 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
513 MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
514 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
515 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
516 MLX5_COMMAND_STR_CASE(QUERY_VNIC_ENV);
517 MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
518 MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
519 MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
520 MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
521 MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT);
522 MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
523 MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
524 MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
525 MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
526 MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
527 MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
528 MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
529 MLX5_COMMAND_STR_CASE(ALLOC_PD);
530 MLX5_COMMAND_STR_CASE(DEALLOC_PD);
531 MLX5_COMMAND_STR_CASE(ALLOC_UAR);
532 MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
533 MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
534 MLX5_COMMAND_STR_CASE(ACCESS_REG);
535 MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
536 MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
537 MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
538 MLX5_COMMAND_STR_CASE(MAD_IFC);
539 MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
540 MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
541 MLX5_COMMAND_STR_CASE(NOP);
542 MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
543 MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
544 MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
545 MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
546 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
547 MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
548 MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
549 MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
550 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
551 MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
552 MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
553 MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
554 MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
555 MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
556 MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
557 MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
558 MLX5_COMMAND_STR_CASE(CREATE_LAG);
559 MLX5_COMMAND_STR_CASE(MODIFY_LAG);
560 MLX5_COMMAND_STR_CASE(QUERY_LAG);
561 MLX5_COMMAND_STR_CASE(DESTROY_LAG);
562 MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
563 MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
564 MLX5_COMMAND_STR_CASE(CREATE_TIR);
565 MLX5_COMMAND_STR_CASE(MODIFY_TIR);
566 MLX5_COMMAND_STR_CASE(DESTROY_TIR);
567 MLX5_COMMAND_STR_CASE(QUERY_TIR);
568 MLX5_COMMAND_STR_CASE(CREATE_SQ);
569 MLX5_COMMAND_STR_CASE(MODIFY_SQ);
570 MLX5_COMMAND_STR_CASE(DESTROY_SQ);
571 MLX5_COMMAND_STR_CASE(QUERY_SQ);
572 MLX5_COMMAND_STR_CASE(CREATE_RQ);
573 MLX5_COMMAND_STR_CASE(MODIFY_RQ);
574 MLX5_COMMAND_STR_CASE(DESTROY_RQ);
575 MLX5_COMMAND_STR_CASE(QUERY_RQ);
576 MLX5_COMMAND_STR_CASE(CREATE_RMP);
577 MLX5_COMMAND_STR_CASE(MODIFY_RMP);
578 MLX5_COMMAND_STR_CASE(DESTROY_RMP);
579 MLX5_COMMAND_STR_CASE(QUERY_RMP);
580 MLX5_COMMAND_STR_CASE(CREATE_TIS);
581 MLX5_COMMAND_STR_CASE(MODIFY_TIS);
582 MLX5_COMMAND_STR_CASE(DESTROY_TIS);
583 MLX5_COMMAND_STR_CASE(QUERY_TIS);
584 MLX5_COMMAND_STR_CASE(CREATE_RQT);
585 MLX5_COMMAND_STR_CASE(MODIFY_RQT);
586 MLX5_COMMAND_STR_CASE(DESTROY_RQT);
587 MLX5_COMMAND_STR_CASE(QUERY_RQT);
588 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
589 MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
590 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
591 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
592 MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
593 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
594 MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
595 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
596 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
597 MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
598 MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
599 MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
600 MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
601 MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
602 MLX5_COMMAND_STR_CASE(ALLOC_ENCAP_HEADER);
603 MLX5_COMMAND_STR_CASE(DEALLOC_ENCAP_HEADER);
604 MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
605 MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
606 MLX5_COMMAND_STR_CASE(FPGA_CREATE_QP);
607 MLX5_COMMAND_STR_CASE(FPGA_MODIFY_QP);
608 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
609 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
610 MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
611 MLX5_COMMAND_STR_CASE(CREATE_XRQ);
612 MLX5_COMMAND_STR_CASE(DESTROY_XRQ);
613 MLX5_COMMAND_STR_CASE(QUERY_XRQ);
614 MLX5_COMMAND_STR_CASE(ARM_XRQ);
615 MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT);
616 MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT);
617 MLX5_COMMAND_STR_CASE(MODIFY_GENERAL_OBJECT);
618 MLX5_COMMAND_STR_CASE(QUERY_GENERAL_OBJECT);
619 MLX5_COMMAND_STR_CASE(QUERY_MODIFY_HEADER_CONTEXT);
620 default: return "unknown command opcode";
621 }
622 }
623
cmd_status_str(u8 status)624 static const char *cmd_status_str(u8 status)
625 {
626 switch (status) {
627 case MLX5_CMD_STAT_OK:
628 return "OK";
629 case MLX5_CMD_STAT_INT_ERR:
630 return "internal error";
631 case MLX5_CMD_STAT_BAD_OP_ERR:
632 return "bad operation";
633 case MLX5_CMD_STAT_BAD_PARAM_ERR:
634 return "bad parameter";
635 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
636 return "bad system state";
637 case MLX5_CMD_STAT_BAD_RES_ERR:
638 return "bad resource";
639 case MLX5_CMD_STAT_RES_BUSY:
640 return "resource busy";
641 case MLX5_CMD_STAT_LIM_ERR:
642 return "limits exceeded";
643 case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
644 return "bad resource state";
645 case MLX5_CMD_STAT_IX_ERR:
646 return "bad index";
647 case MLX5_CMD_STAT_NO_RES_ERR:
648 return "no resources";
649 case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
650 return "bad input length";
651 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
652 return "bad output length";
653 case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
654 return "bad QP state";
655 case MLX5_CMD_STAT_BAD_PKT_ERR:
656 return "bad packet (discarded)";
657 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
658 return "bad size too many outstanding CQEs";
659 default:
660 return "unknown status";
661 }
662 }
663
cmd_status_to_err(u8 status)664 static int cmd_status_to_err(u8 status)
665 {
666 switch (status) {
667 case MLX5_CMD_STAT_OK: return 0;
668 case MLX5_CMD_STAT_INT_ERR: return -EIO;
669 case MLX5_CMD_STAT_BAD_OP_ERR: return -EINVAL;
670 case MLX5_CMD_STAT_BAD_PARAM_ERR: return -EINVAL;
671 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: return -EIO;
672 case MLX5_CMD_STAT_BAD_RES_ERR: return -EINVAL;
673 case MLX5_CMD_STAT_RES_BUSY: return -EBUSY;
674 case MLX5_CMD_STAT_LIM_ERR: return -ENOMEM;
675 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: return -EINVAL;
676 case MLX5_CMD_STAT_IX_ERR: return -EINVAL;
677 case MLX5_CMD_STAT_NO_RES_ERR: return -EAGAIN;
678 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: return -EIO;
679 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: return -EIO;
680 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: return -EINVAL;
681 case MLX5_CMD_STAT_BAD_PKT_ERR: return -EINVAL;
682 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: return -EINVAL;
683 default: return -EIO;
684 }
685 }
686
687 struct mlx5_ifc_mbox_out_bits {
688 u8 status[0x8];
689 u8 reserved_at_8[0x18];
690
691 u8 syndrome[0x20];
692
693 u8 reserved_at_40[0x40];
694 };
695
696 struct mlx5_ifc_mbox_in_bits {
697 u8 opcode[0x10];
698 u8 uid[0x10];
699
700 u8 reserved_at_20[0x10];
701 u8 op_mod[0x10];
702
703 u8 reserved_at_40[0x40];
704 };
705
mlx5_cmd_mbox_status(void * out,u8 * status,u32 * syndrome)706 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
707 {
708 *status = MLX5_GET(mbox_out, out, status);
709 *syndrome = MLX5_GET(mbox_out, out, syndrome);
710 }
711
mlx5_cmd_check(struct mlx5_core_dev * dev,void * in,void * out)712 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
713 {
714 u32 syndrome;
715 u8 status;
716 u16 opcode;
717 u16 op_mod;
718 u16 uid;
719
720 mlx5_cmd_mbox_status(out, &status, &syndrome);
721 if (!status)
722 return 0;
723
724 opcode = MLX5_GET(mbox_in, in, opcode);
725 op_mod = MLX5_GET(mbox_in, in, op_mod);
726 uid = MLX5_GET(mbox_in, in, uid);
727
728 if (!uid && opcode != MLX5_CMD_OP_DESTROY_MKEY)
729 mlx5_core_err_rl(dev,
730 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
731 mlx5_command_str(opcode), opcode, op_mod,
732 cmd_status_str(status), status, syndrome);
733 else
734 mlx5_core_dbg(dev,
735 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
736 mlx5_command_str(opcode),
737 opcode, op_mod,
738 cmd_status_str(status),
739 status,
740 syndrome);
741
742 return cmd_status_to_err(status);
743 }
744
dump_command(struct mlx5_core_dev * dev,struct mlx5_cmd_work_ent * ent,int input)745 static void dump_command(struct mlx5_core_dev *dev,
746 struct mlx5_cmd_work_ent *ent, int input)
747 {
748 struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
749 u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
750 struct mlx5_cmd_mailbox *next = msg->next;
751 int n = mlx5_calc_cmd_blocks(msg);
752 int data_only;
753 u32 offset = 0;
754 int dump_len;
755 int i;
756
757 data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
758
759 if (data_only)
760 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
761 "dump command data %s(0x%x) %s\n",
762 mlx5_command_str(op), op,
763 input ? "INPUT" : "OUTPUT");
764 else
765 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
766 mlx5_command_str(op), op,
767 input ? "INPUT" : "OUTPUT");
768
769 if (data_only) {
770 if (input) {
771 dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
772 offset += sizeof(ent->lay->in);
773 } else {
774 dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
775 offset += sizeof(ent->lay->out);
776 }
777 } else {
778 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
779 offset += sizeof(*ent->lay);
780 }
781
782 for (i = 0; i < n && next; i++) {
783 if (data_only) {
784 dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
785 dump_buf(next->buf, dump_len, 1, offset);
786 offset += MLX5_CMD_DATA_BLOCK_SIZE;
787 } else {
788 mlx5_core_dbg(dev, "command block:\n");
789 dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
790 offset += sizeof(struct mlx5_cmd_prot_block);
791 }
792 next = next->next;
793 }
794
795 if (data_only)
796 pr_debug("\n");
797 }
798
msg_to_opcode(struct mlx5_cmd_msg * in)799 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
800 {
801 return MLX5_GET(mbox_in, in->first.data, opcode);
802 }
803
cb_timeout_handler(struct work_struct * work)804 static void cb_timeout_handler(struct work_struct *work)
805 {
806 struct delayed_work *dwork = container_of(work, struct delayed_work,
807 work);
808 struct mlx5_cmd_work_ent *ent = container_of(dwork,
809 struct mlx5_cmd_work_ent,
810 cb_timeout_work);
811 struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
812 cmd);
813
814 ent->ret = -ETIMEDOUT;
815 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
816 mlx5_command_str(msg_to_opcode(ent->in)),
817 msg_to_opcode(ent->in));
818 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
819 }
820
821 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
822 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
823 struct mlx5_cmd_msg *msg);
824
cmd_work_handler(struct work_struct * work)825 static void cmd_work_handler(struct work_struct *work)
826 {
827 struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
828 struct mlx5_cmd *cmd = ent->cmd;
829 struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
830 unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
831 struct mlx5_cmd_layout *lay;
832 struct semaphore *sem;
833 unsigned long flags;
834 bool poll_cmd = ent->polling;
835 int alloc_ret;
836 int cmd_mode;
837
838 sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
839 down(sem);
840 if (!ent->page_queue) {
841 alloc_ret = alloc_ent(cmd);
842 if (alloc_ret < 0) {
843 mlx5_core_err(dev, "failed to allocate command entry\n");
844 if (ent->callback) {
845 ent->callback(-EAGAIN, ent->context);
846 mlx5_free_cmd_msg(dev, ent->out);
847 free_msg(dev, ent->in);
848 free_cmd(ent);
849 } else {
850 ent->ret = -EAGAIN;
851 complete(&ent->done);
852 }
853 up(sem);
854 return;
855 }
856 ent->idx = alloc_ret;
857 } else {
858 ent->idx = cmd->max_reg_cmds;
859 spin_lock_irqsave(&cmd->alloc_lock, flags);
860 clear_bit(ent->idx, &cmd->bitmask);
861 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
862 }
863
864 cmd->ent_arr[ent->idx] = ent;
865 set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
866 lay = get_inst(cmd, ent->idx);
867 ent->lay = lay;
868 memset(lay, 0, sizeof(*lay));
869 memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
870 ent->op = be32_to_cpu(lay->in[0]) >> 16;
871 if (ent->in->next)
872 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
873 lay->inlen = cpu_to_be32(ent->in->len);
874 if (ent->out->next)
875 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
876 lay->outlen = cpu_to_be32(ent->out->len);
877 lay->type = MLX5_PCI_CMD_XPORT;
878 lay->token = ent->token;
879 lay->status_own = CMD_OWNER_HW;
880 set_signature(ent, !cmd->checksum_disabled);
881 dump_command(dev, ent, 1);
882 ent->ts1 = ktime_get_ns();
883 cmd_mode = cmd->mode;
884
885 if (ent->callback)
886 schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
887
888 /* Skip sending command to fw if internal error */
889 if (pci_channel_offline(dev->pdev) ||
890 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
891 u8 status = 0;
892 u32 drv_synd;
893
894 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status);
895 MLX5_SET(mbox_out, ent->out, status, status);
896 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd);
897
898 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
899 return;
900 }
901
902 /* ring doorbell after the descriptor is valid */
903 mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
904 wmb();
905 iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
906 mmiowb();
907 /* if not in polling don't use ent after this point */
908 if (cmd_mode == CMD_MODE_POLLING || poll_cmd) {
909 poll_timeout(ent);
910 /* make sure we read the descriptor after ownership is SW */
911 rmb();
912 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, (ent->ret == -ETIMEDOUT));
913 }
914 }
915
deliv_status_to_str(u8 status)916 static const char *deliv_status_to_str(u8 status)
917 {
918 switch (status) {
919 case MLX5_CMD_DELIVERY_STAT_OK:
920 return "no errors";
921 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
922 return "signature error";
923 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
924 return "token error";
925 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
926 return "bad block number";
927 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
928 return "output pointer not aligned to block size";
929 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
930 return "input pointer not aligned to block size";
931 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
932 return "firmware internal error";
933 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
934 return "command input length error";
935 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
936 return "command output length error";
937 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
938 return "reserved fields not cleared";
939 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
940 return "bad command descriptor type";
941 default:
942 return "unknown status code";
943 }
944 }
945
wait_func(struct mlx5_core_dev * dev,struct mlx5_cmd_work_ent * ent)946 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
947 {
948 unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
949 struct mlx5_cmd *cmd = &dev->cmd;
950 int err;
951
952 if (cmd->mode == CMD_MODE_POLLING || ent->polling) {
953 wait_for_completion(&ent->done);
954 } else if (!wait_for_completion_timeout(&ent->done, timeout)) {
955 ent->ret = -ETIMEDOUT;
956 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
957 }
958
959 err = ent->ret;
960
961 if (err == -ETIMEDOUT) {
962 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
963 mlx5_command_str(msg_to_opcode(ent->in)),
964 msg_to_opcode(ent->in));
965 }
966 mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
967 err, deliv_status_to_str(ent->status), ent->status);
968
969 return err;
970 }
971
972 /* Notes:
973 * 1. Callback functions may not sleep
974 * 2. page queue commands do not support asynchrous completion
975 */
mlx5_cmd_invoke(struct mlx5_core_dev * dev,struct mlx5_cmd_msg * in,struct mlx5_cmd_msg * out,void * uout,int uout_size,mlx5_cmd_cbk_t callback,void * context,int page_queue,u8 * status,u8 token,bool force_polling)976 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
977 struct mlx5_cmd_msg *out, void *uout, int uout_size,
978 mlx5_cmd_cbk_t callback,
979 void *context, int page_queue, u8 *status,
980 u8 token, bool force_polling)
981 {
982 struct mlx5_cmd *cmd = &dev->cmd;
983 struct mlx5_cmd_work_ent *ent;
984 struct mlx5_cmd_stats *stats;
985 int err = 0;
986 s64 ds;
987 u16 op;
988
989 if (callback && page_queue)
990 return -EINVAL;
991
992 ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
993 page_queue);
994 if (IS_ERR(ent))
995 return PTR_ERR(ent);
996
997 ent->token = token;
998 ent->polling = force_polling;
999
1000 if (!callback)
1001 init_completion(&ent->done);
1002
1003 INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
1004 INIT_WORK(&ent->work, cmd_work_handler);
1005 if (page_queue) {
1006 cmd_work_handler(&ent->work);
1007 } else if (!queue_work(cmd->wq, &ent->work)) {
1008 mlx5_core_warn(dev, "failed to queue work\n");
1009 err = -ENOMEM;
1010 goto out_free;
1011 }
1012
1013 if (callback)
1014 goto out;
1015
1016 err = wait_func(dev, ent);
1017 if (err == -ETIMEDOUT)
1018 goto out;
1019
1020 ds = ent->ts2 - ent->ts1;
1021 op = MLX5_GET(mbox_in, in->first.data, opcode);
1022 if (op < ARRAY_SIZE(cmd->stats)) {
1023 stats = &cmd->stats[op];
1024 spin_lock_irq(&stats->lock);
1025 stats->sum += ds;
1026 ++stats->n;
1027 spin_unlock_irq(&stats->lock);
1028 }
1029 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
1030 "fw exec time for %s is %lld nsec\n",
1031 mlx5_command_str(op), ds);
1032 *status = ent->status;
1033
1034 out_free:
1035 free_cmd(ent);
1036 out:
1037 return err;
1038 }
1039
dbg_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)1040 static ssize_t dbg_write(struct file *filp, const char __user *buf,
1041 size_t count, loff_t *pos)
1042 {
1043 struct mlx5_core_dev *dev = filp->private_data;
1044 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1045 char lbuf[3];
1046 int err;
1047
1048 if (!dbg->in_msg || !dbg->out_msg)
1049 return -ENOMEM;
1050
1051 if (count < sizeof(lbuf) - 1)
1052 return -EINVAL;
1053
1054 if (copy_from_user(lbuf, buf, sizeof(lbuf) - 1))
1055 return -EFAULT;
1056
1057 lbuf[sizeof(lbuf) - 1] = 0;
1058
1059 if (strcmp(lbuf, "go"))
1060 return -EINVAL;
1061
1062 err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
1063
1064 return err ? err : count;
1065 }
1066
1067 static const struct file_operations fops = {
1068 .owner = THIS_MODULE,
1069 .open = simple_open,
1070 .write = dbg_write,
1071 };
1072
mlx5_copy_to_msg(struct mlx5_cmd_msg * to,void * from,int size,u8 token)1073 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
1074 u8 token)
1075 {
1076 struct mlx5_cmd_prot_block *block;
1077 struct mlx5_cmd_mailbox *next;
1078 int copy;
1079
1080 if (!to || !from)
1081 return -ENOMEM;
1082
1083 copy = min_t(int, size, sizeof(to->first.data));
1084 memcpy(to->first.data, from, copy);
1085 size -= copy;
1086 from += copy;
1087
1088 next = to->next;
1089 while (size) {
1090 if (!next) {
1091 /* this is a BUG */
1092 return -ENOMEM;
1093 }
1094
1095 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1096 block = next->buf;
1097 memcpy(block->data, from, copy);
1098 from += copy;
1099 size -= copy;
1100 block->token = token;
1101 next = next->next;
1102 }
1103
1104 return 0;
1105 }
1106
mlx5_copy_from_msg(void * to,struct mlx5_cmd_msg * from,int size)1107 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1108 {
1109 struct mlx5_cmd_prot_block *block;
1110 struct mlx5_cmd_mailbox *next;
1111 int copy;
1112
1113 if (!to || !from)
1114 return -ENOMEM;
1115
1116 copy = min_t(int, size, sizeof(from->first.data));
1117 memcpy(to, from->first.data, copy);
1118 size -= copy;
1119 to += copy;
1120
1121 next = from->next;
1122 while (size) {
1123 if (!next) {
1124 /* this is a BUG */
1125 return -ENOMEM;
1126 }
1127
1128 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1129 block = next->buf;
1130
1131 memcpy(to, block->data, copy);
1132 to += copy;
1133 size -= copy;
1134 next = next->next;
1135 }
1136
1137 return 0;
1138 }
1139
alloc_cmd_box(struct mlx5_core_dev * dev,gfp_t flags)1140 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1141 gfp_t flags)
1142 {
1143 struct mlx5_cmd_mailbox *mailbox;
1144
1145 mailbox = kmalloc(sizeof(*mailbox), flags);
1146 if (!mailbox)
1147 return ERR_PTR(-ENOMEM);
1148
1149 mailbox->buf = dma_pool_zalloc(dev->cmd.pool, flags,
1150 &mailbox->dma);
1151 if (!mailbox->buf) {
1152 mlx5_core_dbg(dev, "failed allocation\n");
1153 kfree(mailbox);
1154 return ERR_PTR(-ENOMEM);
1155 }
1156 mailbox->next = NULL;
1157
1158 return mailbox;
1159 }
1160
free_cmd_box(struct mlx5_core_dev * dev,struct mlx5_cmd_mailbox * mailbox)1161 static void free_cmd_box(struct mlx5_core_dev *dev,
1162 struct mlx5_cmd_mailbox *mailbox)
1163 {
1164 dma_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1165 kfree(mailbox);
1166 }
1167
mlx5_alloc_cmd_msg(struct mlx5_core_dev * dev,gfp_t flags,int size,u8 token)1168 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1169 gfp_t flags, int size,
1170 u8 token)
1171 {
1172 struct mlx5_cmd_mailbox *tmp, *head = NULL;
1173 struct mlx5_cmd_prot_block *block;
1174 struct mlx5_cmd_msg *msg;
1175 int err;
1176 int n;
1177 int i;
1178
1179 msg = kzalloc(sizeof(*msg), flags);
1180 if (!msg)
1181 return ERR_PTR(-ENOMEM);
1182
1183 msg->len = size;
1184 n = mlx5_calc_cmd_blocks(msg);
1185
1186 for (i = 0; i < n; i++) {
1187 tmp = alloc_cmd_box(dev, flags);
1188 if (IS_ERR(tmp)) {
1189 mlx5_core_warn(dev, "failed allocating block\n");
1190 err = PTR_ERR(tmp);
1191 goto err_alloc;
1192 }
1193
1194 block = tmp->buf;
1195 tmp->next = head;
1196 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1197 block->block_num = cpu_to_be32(n - i - 1);
1198 block->token = token;
1199 head = tmp;
1200 }
1201 msg->next = head;
1202 return msg;
1203
1204 err_alloc:
1205 while (head) {
1206 tmp = head->next;
1207 free_cmd_box(dev, head);
1208 head = tmp;
1209 }
1210 kfree(msg);
1211
1212 return ERR_PTR(err);
1213 }
1214
mlx5_free_cmd_msg(struct mlx5_core_dev * dev,struct mlx5_cmd_msg * msg)1215 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1216 struct mlx5_cmd_msg *msg)
1217 {
1218 struct mlx5_cmd_mailbox *head = msg->next;
1219 struct mlx5_cmd_mailbox *next;
1220
1221 while (head) {
1222 next = head->next;
1223 free_cmd_box(dev, head);
1224 head = next;
1225 }
1226 kfree(msg);
1227 }
1228
data_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)1229 static ssize_t data_write(struct file *filp, const char __user *buf,
1230 size_t count, loff_t *pos)
1231 {
1232 struct mlx5_core_dev *dev = filp->private_data;
1233 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1234 void *ptr;
1235
1236 if (*pos != 0)
1237 return -EINVAL;
1238
1239 kfree(dbg->in_msg);
1240 dbg->in_msg = NULL;
1241 dbg->inlen = 0;
1242 ptr = memdup_user(buf, count);
1243 if (IS_ERR(ptr))
1244 return PTR_ERR(ptr);
1245 dbg->in_msg = ptr;
1246 dbg->inlen = count;
1247
1248 *pos = count;
1249
1250 return count;
1251 }
1252
data_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)1253 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1254 loff_t *pos)
1255 {
1256 struct mlx5_core_dev *dev = filp->private_data;
1257 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1258
1259 if (!dbg->out_msg)
1260 return -ENOMEM;
1261
1262 return simple_read_from_buffer(buf, count, pos, dbg->out_msg,
1263 dbg->outlen);
1264 }
1265
1266 static const struct file_operations dfops = {
1267 .owner = THIS_MODULE,
1268 .open = simple_open,
1269 .write = data_write,
1270 .read = data_read,
1271 };
1272
outlen_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)1273 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1274 loff_t *pos)
1275 {
1276 struct mlx5_core_dev *dev = filp->private_data;
1277 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1278 char outlen[8];
1279 int err;
1280
1281 err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1282 if (err < 0)
1283 return err;
1284
1285 return simple_read_from_buffer(buf, count, pos, outlen, err);
1286 }
1287
outlen_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)1288 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1289 size_t count, loff_t *pos)
1290 {
1291 struct mlx5_core_dev *dev = filp->private_data;
1292 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1293 char outlen_str[8] = {0};
1294 int outlen;
1295 void *ptr;
1296 int err;
1297
1298 if (*pos != 0 || count > 6)
1299 return -EINVAL;
1300
1301 kfree(dbg->out_msg);
1302 dbg->out_msg = NULL;
1303 dbg->outlen = 0;
1304
1305 if (copy_from_user(outlen_str, buf, count))
1306 return -EFAULT;
1307
1308 err = sscanf(outlen_str, "%d", &outlen);
1309 if (err < 0)
1310 return err;
1311
1312 ptr = kzalloc(outlen, GFP_KERNEL);
1313 if (!ptr)
1314 return -ENOMEM;
1315
1316 dbg->out_msg = ptr;
1317 dbg->outlen = outlen;
1318
1319 *pos = count;
1320
1321 return count;
1322 }
1323
1324 static const struct file_operations olfops = {
1325 .owner = THIS_MODULE,
1326 .open = simple_open,
1327 .write = outlen_write,
1328 .read = outlen_read,
1329 };
1330
set_wqname(struct mlx5_core_dev * dev)1331 static void set_wqname(struct mlx5_core_dev *dev)
1332 {
1333 struct mlx5_cmd *cmd = &dev->cmd;
1334
1335 snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1336 dev_name(&dev->pdev->dev));
1337 }
1338
clean_debug_files(struct mlx5_core_dev * dev)1339 static void clean_debug_files(struct mlx5_core_dev *dev)
1340 {
1341 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1342
1343 if (!mlx5_debugfs_root)
1344 return;
1345
1346 mlx5_cmdif_debugfs_cleanup(dev);
1347 debugfs_remove_recursive(dbg->dbg_root);
1348 }
1349
create_debugfs_files(struct mlx5_core_dev * dev)1350 static int create_debugfs_files(struct mlx5_core_dev *dev)
1351 {
1352 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1353 int err = -ENOMEM;
1354
1355 if (!mlx5_debugfs_root)
1356 return 0;
1357
1358 dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1359 if (!dbg->dbg_root)
1360 return err;
1361
1362 dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1363 dev, &dfops);
1364 if (!dbg->dbg_in)
1365 goto err_dbg;
1366
1367 dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1368 dev, &dfops);
1369 if (!dbg->dbg_out)
1370 goto err_dbg;
1371
1372 dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1373 dev, &olfops);
1374 if (!dbg->dbg_outlen)
1375 goto err_dbg;
1376
1377 dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1378 &dbg->status);
1379 if (!dbg->dbg_status)
1380 goto err_dbg;
1381
1382 dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1383 if (!dbg->dbg_run)
1384 goto err_dbg;
1385
1386 mlx5_cmdif_debugfs_init(dev);
1387
1388 return 0;
1389
1390 err_dbg:
1391 clean_debug_files(dev);
1392 return err;
1393 }
1394
mlx5_cmd_change_mod(struct mlx5_core_dev * dev,int mode)1395 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1396 {
1397 struct mlx5_cmd *cmd = &dev->cmd;
1398 int i;
1399
1400 for (i = 0; i < cmd->max_reg_cmds; i++)
1401 down(&cmd->sem);
1402 down(&cmd->pages_sem);
1403
1404 cmd->mode = mode;
1405
1406 up(&cmd->pages_sem);
1407 for (i = 0; i < cmd->max_reg_cmds; i++)
1408 up(&cmd->sem);
1409 }
1410
mlx5_cmd_use_events(struct mlx5_core_dev * dev)1411 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1412 {
1413 mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1414 }
1415
mlx5_cmd_use_polling(struct mlx5_core_dev * dev)1416 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1417 {
1418 mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1419 }
1420
free_msg(struct mlx5_core_dev * dev,struct mlx5_cmd_msg * msg)1421 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1422 {
1423 unsigned long flags;
1424
1425 if (msg->parent) {
1426 spin_lock_irqsave(&msg->parent->lock, flags);
1427 list_add_tail(&msg->list, &msg->parent->head);
1428 spin_unlock_irqrestore(&msg->parent->lock, flags);
1429 } else {
1430 mlx5_free_cmd_msg(dev, msg);
1431 }
1432 }
1433
mlx5_cmd_comp_handler(struct mlx5_core_dev * dev,u64 vec,bool forced)1434 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
1435 {
1436 struct mlx5_cmd *cmd = &dev->cmd;
1437 struct mlx5_cmd_work_ent *ent;
1438 mlx5_cmd_cbk_t callback;
1439 void *context;
1440 int err;
1441 int i;
1442 s64 ds;
1443 struct mlx5_cmd_stats *stats;
1444 unsigned long flags;
1445 unsigned long vector;
1446
1447 /* there can be at most 32 command queues */
1448 vector = vec & 0xffffffff;
1449 for (i = 0; i < (1 << cmd->log_sz); i++) {
1450 if (test_bit(i, &vector)) {
1451 struct semaphore *sem;
1452
1453 ent = cmd->ent_arr[i];
1454
1455 /* if we already completed the command, ignore it */
1456 if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
1457 &ent->state)) {
1458 /* only real completion can free the cmd slot */
1459 if (!forced) {
1460 mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
1461 ent->idx);
1462 free_ent(cmd, ent->idx);
1463 free_cmd(ent);
1464 }
1465 continue;
1466 }
1467
1468 if (ent->callback)
1469 cancel_delayed_work(&ent->cb_timeout_work);
1470 if (ent->page_queue)
1471 sem = &cmd->pages_sem;
1472 else
1473 sem = &cmd->sem;
1474 ent->ts2 = ktime_get_ns();
1475 memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1476 dump_command(dev, ent, 0);
1477 if (!ent->ret) {
1478 if (!cmd->checksum_disabled)
1479 ent->ret = verify_signature(ent);
1480 else
1481 ent->ret = 0;
1482 if (vec & MLX5_TRIGGERED_CMD_COMP)
1483 ent->status = MLX5_DRIVER_STATUS_ABORTED;
1484 else
1485 ent->status = ent->lay->status_own >> 1;
1486
1487 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1488 ent->ret, deliv_status_to_str(ent->status), ent->status);
1489 }
1490
1491 /* only real completion will free the entry slot */
1492 if (!forced)
1493 free_ent(cmd, ent->idx);
1494
1495 if (ent->callback) {
1496 ds = ent->ts2 - ent->ts1;
1497 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1498 stats = &cmd->stats[ent->op];
1499 spin_lock_irqsave(&stats->lock, flags);
1500 stats->sum += ds;
1501 ++stats->n;
1502 spin_unlock_irqrestore(&stats->lock, flags);
1503 }
1504
1505 callback = ent->callback;
1506 context = ent->context;
1507 err = ent->ret;
1508 if (!err) {
1509 err = mlx5_copy_from_msg(ent->uout,
1510 ent->out,
1511 ent->uout_size);
1512
1513 err = err ? err : mlx5_cmd_check(dev,
1514 ent->in->first.data,
1515 ent->uout);
1516 }
1517
1518 mlx5_free_cmd_msg(dev, ent->out);
1519 free_msg(dev, ent->in);
1520
1521 err = err ? err : ent->status;
1522 if (!forced)
1523 free_cmd(ent);
1524 callback(err, context);
1525 } else {
1526 complete(&ent->done);
1527 }
1528 up(sem);
1529 }
1530 }
1531 }
1532 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1533
status_to_err(u8 status)1534 static int status_to_err(u8 status)
1535 {
1536 return status ? -1 : 0; /* TBD more meaningful codes */
1537 }
1538
alloc_msg(struct mlx5_core_dev * dev,int in_size,gfp_t gfp)1539 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1540 gfp_t gfp)
1541 {
1542 struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1543 struct cmd_msg_cache *ch = NULL;
1544 struct mlx5_cmd *cmd = &dev->cmd;
1545 int i;
1546
1547 if (in_size <= 16)
1548 goto cache_miss;
1549
1550 for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1551 ch = &cmd->cache[i];
1552 if (in_size > ch->max_inbox_size)
1553 continue;
1554 spin_lock_irq(&ch->lock);
1555 if (list_empty(&ch->head)) {
1556 spin_unlock_irq(&ch->lock);
1557 continue;
1558 }
1559 msg = list_entry(ch->head.next, typeof(*msg), list);
1560 /* For cached lists, we must explicitly state what is
1561 * the real size
1562 */
1563 msg->len = in_size;
1564 list_del(&msg->list);
1565 spin_unlock_irq(&ch->lock);
1566 break;
1567 }
1568
1569 if (!IS_ERR(msg))
1570 return msg;
1571
1572 cache_miss:
1573 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1574 return msg;
1575 }
1576
is_manage_pages(void * in)1577 static int is_manage_pages(void *in)
1578 {
1579 return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1580 }
1581
cmd_exec(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size,mlx5_cmd_cbk_t callback,void * context,bool force_polling)1582 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1583 int out_size, mlx5_cmd_cbk_t callback, void *context,
1584 bool force_polling)
1585 {
1586 struct mlx5_cmd_msg *inb;
1587 struct mlx5_cmd_msg *outb;
1588 int pages_queue;
1589 gfp_t gfp;
1590 int err;
1591 u8 status = 0;
1592 u32 drv_synd;
1593 u8 token;
1594
1595 if (pci_channel_offline(dev->pdev) ||
1596 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1597 u16 opcode = MLX5_GET(mbox_in, in, opcode);
1598
1599 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
1600 MLX5_SET(mbox_out, out, status, status);
1601 MLX5_SET(mbox_out, out, syndrome, drv_synd);
1602 return err;
1603 }
1604
1605 pages_queue = is_manage_pages(in);
1606 gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1607
1608 inb = alloc_msg(dev, in_size, gfp);
1609 if (IS_ERR(inb)) {
1610 err = PTR_ERR(inb);
1611 return err;
1612 }
1613
1614 token = alloc_token(&dev->cmd);
1615
1616 err = mlx5_copy_to_msg(inb, in, in_size, token);
1617 if (err) {
1618 mlx5_core_warn(dev, "err %d\n", err);
1619 goto out_in;
1620 }
1621
1622 outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1623 if (IS_ERR(outb)) {
1624 err = PTR_ERR(outb);
1625 goto out_in;
1626 }
1627
1628 err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1629 pages_queue, &status, token, force_polling);
1630 if (err)
1631 goto out_out;
1632
1633 mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1634 if (status) {
1635 err = status_to_err(status);
1636 goto out_out;
1637 }
1638
1639 if (!callback)
1640 err = mlx5_copy_from_msg(out, outb, out_size);
1641
1642 out_out:
1643 if (!callback)
1644 mlx5_free_cmd_msg(dev, outb);
1645
1646 out_in:
1647 if (!callback)
1648 free_msg(dev, inb);
1649 return err;
1650 }
1651
mlx5_cmd_exec(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size)1652 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1653 int out_size)
1654 {
1655 int err;
1656
1657 err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false);
1658 return err ? : mlx5_cmd_check(dev, in, out);
1659 }
1660 EXPORT_SYMBOL(mlx5_cmd_exec);
1661
mlx5_cmd_exec_cb(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size,mlx5_cmd_cbk_t callback,void * context)1662 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1663 void *out, int out_size, mlx5_cmd_cbk_t callback,
1664 void *context)
1665 {
1666 return cmd_exec(dev, in, in_size, out, out_size, callback, context,
1667 false);
1668 }
1669 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1670
mlx5_cmd_exec_polling(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size)1671 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1672 void *out, int out_size)
1673 {
1674 int err;
1675
1676 err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, true);
1677
1678 return err ? : mlx5_cmd_check(dev, in, out);
1679 }
1680 EXPORT_SYMBOL(mlx5_cmd_exec_polling);
1681
destroy_msg_cache(struct mlx5_core_dev * dev)1682 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1683 {
1684 struct cmd_msg_cache *ch;
1685 struct mlx5_cmd_msg *msg;
1686 struct mlx5_cmd_msg *n;
1687 int i;
1688
1689 for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1690 ch = &dev->cmd.cache[i];
1691 list_for_each_entry_safe(msg, n, &ch->head, list) {
1692 list_del(&msg->list);
1693 mlx5_free_cmd_msg(dev, msg);
1694 }
1695 }
1696 }
1697
1698 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
1699 512, 32, 16, 8, 2
1700 };
1701
1702 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
1703 16 + MLX5_CMD_DATA_BLOCK_SIZE,
1704 16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
1705 16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
1706 16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
1707 16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
1708 };
1709
create_msg_cache(struct mlx5_core_dev * dev)1710 static void create_msg_cache(struct mlx5_core_dev *dev)
1711 {
1712 struct mlx5_cmd *cmd = &dev->cmd;
1713 struct cmd_msg_cache *ch;
1714 struct mlx5_cmd_msg *msg;
1715 int i;
1716 int k;
1717
1718 /* Initialize and fill the caches with initial entries */
1719 for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) {
1720 ch = &cmd->cache[k];
1721 spin_lock_init(&ch->lock);
1722 INIT_LIST_HEAD(&ch->head);
1723 ch->num_ent = cmd_cache_num_ent[k];
1724 ch->max_inbox_size = cmd_cache_ent_size[k];
1725 for (i = 0; i < ch->num_ent; i++) {
1726 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
1727 ch->max_inbox_size, 0);
1728 if (IS_ERR(msg))
1729 break;
1730 msg->parent = ch;
1731 list_add_tail(&msg->list, &ch->head);
1732 }
1733 }
1734 }
1735
alloc_cmd_page(struct mlx5_core_dev * dev,struct mlx5_cmd * cmd)1736 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1737 {
1738 struct device *ddev = &dev->pdev->dev;
1739
1740 cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1741 &cmd->alloc_dma, GFP_KERNEL);
1742 if (!cmd->cmd_alloc_buf)
1743 return -ENOMEM;
1744
1745 /* make sure it is aligned to 4K */
1746 if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1747 cmd->cmd_buf = cmd->cmd_alloc_buf;
1748 cmd->dma = cmd->alloc_dma;
1749 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1750 return 0;
1751 }
1752
1753 dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1754 cmd->alloc_dma);
1755 cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1756 2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1757 &cmd->alloc_dma, GFP_KERNEL);
1758 if (!cmd->cmd_alloc_buf)
1759 return -ENOMEM;
1760
1761 cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1762 cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1763 cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1764 return 0;
1765 }
1766
free_cmd_page(struct mlx5_core_dev * dev,struct mlx5_cmd * cmd)1767 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1768 {
1769 struct device *ddev = &dev->pdev->dev;
1770
1771 dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1772 cmd->alloc_dma);
1773 }
1774
mlx5_cmd_init(struct mlx5_core_dev * dev)1775 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1776 {
1777 int size = sizeof(struct mlx5_cmd_prot_block);
1778 int align = roundup_pow_of_two(size);
1779 struct mlx5_cmd *cmd = &dev->cmd;
1780 u32 cmd_h, cmd_l;
1781 u16 cmd_if_rev;
1782 int err;
1783 int i;
1784
1785 memset(cmd, 0, sizeof(*cmd));
1786 cmd_if_rev = cmdif_rev(dev);
1787 if (cmd_if_rev != CMD_IF_REV) {
1788 dev_err(&dev->pdev->dev,
1789 "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1790 CMD_IF_REV, cmd_if_rev);
1791 return -EINVAL;
1792 }
1793
1794 cmd->pool = dma_pool_create("mlx5_cmd", &dev->pdev->dev, size, align,
1795 0);
1796 if (!cmd->pool)
1797 return -ENOMEM;
1798
1799 err = alloc_cmd_page(dev, cmd);
1800 if (err)
1801 goto err_free_pool;
1802
1803 cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1804 cmd->log_sz = cmd_l >> 4 & 0xf;
1805 cmd->log_stride = cmd_l & 0xf;
1806 if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1807 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1808 1 << cmd->log_sz);
1809 err = -EINVAL;
1810 goto err_free_page;
1811 }
1812
1813 if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1814 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1815 err = -EINVAL;
1816 goto err_free_page;
1817 }
1818
1819 cmd->checksum_disabled = 1;
1820 cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1821 cmd->bitmask = (1UL << cmd->max_reg_cmds) - 1;
1822
1823 cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1824 if (cmd->cmdif_rev > CMD_IF_REV) {
1825 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1826 CMD_IF_REV, cmd->cmdif_rev);
1827 err = -EOPNOTSUPP;
1828 goto err_free_page;
1829 }
1830
1831 spin_lock_init(&cmd->alloc_lock);
1832 spin_lock_init(&cmd->token_lock);
1833 for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1834 spin_lock_init(&cmd->stats[i].lock);
1835
1836 sema_init(&cmd->sem, cmd->max_reg_cmds);
1837 sema_init(&cmd->pages_sem, 1);
1838
1839 cmd_h = (u32)((u64)(cmd->dma) >> 32);
1840 cmd_l = (u32)(cmd->dma);
1841 if (cmd_l & 0xfff) {
1842 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1843 err = -ENOMEM;
1844 goto err_free_page;
1845 }
1846
1847 iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1848 iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1849
1850 /* Make sure firmware sees the complete address before we proceed */
1851 wmb();
1852
1853 mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1854
1855 cmd->mode = CMD_MODE_POLLING;
1856
1857 create_msg_cache(dev);
1858
1859 set_wqname(dev);
1860 cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1861 if (!cmd->wq) {
1862 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1863 err = -ENOMEM;
1864 goto err_cache;
1865 }
1866
1867 err = create_debugfs_files(dev);
1868 if (err) {
1869 err = -ENOMEM;
1870 goto err_wq;
1871 }
1872
1873 return 0;
1874
1875 err_wq:
1876 destroy_workqueue(cmd->wq);
1877
1878 err_cache:
1879 destroy_msg_cache(dev);
1880
1881 err_free_page:
1882 free_cmd_page(dev, cmd);
1883
1884 err_free_pool:
1885 dma_pool_destroy(cmd->pool);
1886
1887 return err;
1888 }
1889 EXPORT_SYMBOL(mlx5_cmd_init);
1890
mlx5_cmd_cleanup(struct mlx5_core_dev * dev)1891 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1892 {
1893 struct mlx5_cmd *cmd = &dev->cmd;
1894
1895 clean_debug_files(dev);
1896 destroy_workqueue(cmd->wq);
1897 destroy_msg_cache(dev);
1898 free_cmd_page(dev, cmd);
1899 dma_pool_destroy(cmd->pool);
1900 }
1901 EXPORT_SYMBOL(mlx5_cmd_cleanup);
1902
