1 /*
2 * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34 #ifdef CONFIG_MLX5_FPGA_IPSEC
35
36 #include <linux/mlx5/device.h>
37
38 #include "accel/ipsec.h"
39 #include "mlx5_core.h"
40 #include "fpga/ipsec.h"
41
mlx5_accel_ipsec_device_caps(struct mlx5_core_dev * mdev)42 u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev)
43 {
44 return mlx5_fpga_ipsec_device_caps(mdev);
45 }
46 EXPORT_SYMBOL_GPL(mlx5_accel_ipsec_device_caps);
47
mlx5_accel_ipsec_counters_count(struct mlx5_core_dev * mdev)48 unsigned int mlx5_accel_ipsec_counters_count(struct mlx5_core_dev *mdev)
49 {
50 return mlx5_fpga_ipsec_counters_count(mdev);
51 }
52
mlx5_accel_ipsec_counters_read(struct mlx5_core_dev * mdev,u64 * counters,unsigned int count)53 int mlx5_accel_ipsec_counters_read(struct mlx5_core_dev *mdev, u64 *counters,
54 unsigned int count)
55 {
56 return mlx5_fpga_ipsec_counters_read(mdev, counters, count);
57 }
58
mlx5_accel_esp_create_hw_context(struct mlx5_core_dev * mdev,struct mlx5_accel_esp_xfrm * xfrm,const __be32 saddr[4],const __be32 daddr[4],const __be32 spi,bool is_ipv6)59 void *mlx5_accel_esp_create_hw_context(struct mlx5_core_dev *mdev,
60 struct mlx5_accel_esp_xfrm *xfrm,
61 const __be32 saddr[4],
62 const __be32 daddr[4],
63 const __be32 spi, bool is_ipv6)
64 {
65 return mlx5_fpga_ipsec_create_sa_ctx(mdev, xfrm, saddr, daddr,
66 spi, is_ipv6);
67 }
68
mlx5_accel_esp_free_hw_context(void * context)69 void mlx5_accel_esp_free_hw_context(void *context)
70 {
71 mlx5_fpga_ipsec_delete_sa_ctx(context);
72 }
73
mlx5_accel_ipsec_init(struct mlx5_core_dev * mdev)74 int mlx5_accel_ipsec_init(struct mlx5_core_dev *mdev)
75 {
76 return mlx5_fpga_ipsec_init(mdev);
77 }
78
mlx5_accel_ipsec_build_fs_cmds(void)79 void mlx5_accel_ipsec_build_fs_cmds(void)
80 {
81 mlx5_fpga_ipsec_build_fs_cmds();
82 }
83
mlx5_accel_ipsec_cleanup(struct mlx5_core_dev * mdev)84 void mlx5_accel_ipsec_cleanup(struct mlx5_core_dev *mdev)
85 {
86 mlx5_fpga_ipsec_cleanup(mdev);
87 }
88
89 struct mlx5_accel_esp_xfrm *
mlx5_accel_esp_create_xfrm(struct mlx5_core_dev * mdev,const struct mlx5_accel_esp_xfrm_attrs * attrs,u32 flags)90 mlx5_accel_esp_create_xfrm(struct mlx5_core_dev *mdev,
91 const struct mlx5_accel_esp_xfrm_attrs *attrs,
92 u32 flags)
93 {
94 struct mlx5_accel_esp_xfrm *xfrm;
95
96 xfrm = mlx5_fpga_esp_create_xfrm(mdev, attrs, flags);
97 if (IS_ERR(xfrm))
98 return xfrm;
99
100 xfrm->mdev = mdev;
101 return xfrm;
102 }
103 EXPORT_SYMBOL_GPL(mlx5_accel_esp_create_xfrm);
104
mlx5_accel_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm * xfrm)105 void mlx5_accel_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm)
106 {
107 mlx5_fpga_esp_destroy_xfrm(xfrm);
108 }
109 EXPORT_SYMBOL_GPL(mlx5_accel_esp_destroy_xfrm);
110
mlx5_accel_esp_modify_xfrm(struct mlx5_accel_esp_xfrm * xfrm,const struct mlx5_accel_esp_xfrm_attrs * attrs)111 int mlx5_accel_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm,
112 const struct mlx5_accel_esp_xfrm_attrs *attrs)
113 {
114 return mlx5_fpga_esp_modify_xfrm(xfrm, attrs);
115 }
116 EXPORT_SYMBOL_GPL(mlx5_accel_esp_modify_xfrm);
117
118 #endif
119
