1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * comedi/drivers/mite.c
4 * Hardware driver for NI Mite PCI interface chip
5 *
6 * COMEDI - Linux Control and Measurement Device Interface
7 * Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org>
8 */
9
10 /*
11 * The PCI-MIO E series driver was originally written by
12 * Tomasz Motylewski <...>, and ported to comedi by ds.
13 *
14 * References for specifications:
15 *
16 * 321747b.pdf Register Level Programmer Manual (obsolete)
17 * 321747c.pdf Register Level Programmer Manual (new)
18 * DAQ-STC reference manual
19 *
20 * Other possibly relevant info:
21 *
22 * 320517c.pdf User manual (obsolete)
23 * 320517f.pdf User manual (new)
24 * 320889a.pdf delete
25 * 320906c.pdf maximum signal ratings
26 * 321066a.pdf about 16x
27 * 321791a.pdf discontinuation of at-mio-16e-10 rev. c
28 * 321808a.pdf about at-mio-16e-10 rev P
29 * 321837a.pdf discontinuation of at-mio-16de-10 rev d
30 * 321838a.pdf about at-mio-16de-10 rev N
31 *
32 * ISSUES:
33 *
34 */
35
36 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37
38 #include <linux/module.h>
39 #include <linux/slab.h>
40 #include <linux/log2.h>
41
42 #include "../comedi_pci.h"
43
44 #include "mite.h"
45
46 /*
47 * Mite registers
48 */
49 #define MITE_UNKNOWN_DMA_BURST_REG 0x28
50 #define UNKNOWN_DMA_BURST_ENABLE_BITS 0x600
51
52 #define MITE_PCI_CONFIG_OFFSET 0x300
53 #define MITE_CSIGR 0x460 /* chip signature */
54 #define CSIGR_TO_IOWINS(x) (((x) >> 29) & 0x7)
55 #define CSIGR_TO_WINS(x) (((x) >> 24) & 0x1f)
56 #define CSIGR_TO_WPDEP(x) (((x) >> 20) & 0x7)
57 #define CSIGR_TO_DMAC(x) (((x) >> 16) & 0xf)
58 #define CSIGR_TO_IMODE(x) (((x) >> 12) & 0x3) /* pci=0x3 */
59 #define CSIGR_TO_MMODE(x) (((x) >> 8) & 0x3) /* minimite=1 */
60 #define CSIGR_TO_TYPE(x) (((x) >> 4) & 0xf) /* mite=0, minimite=1 */
61 #define CSIGR_TO_VER(x) (((x) >> 0) & 0xf)
62
63 #define MITE_CHAN(x) (0x500 + 0x100 * (x))
64 #define MITE_CHOR(x) (0x00 + MITE_CHAN(x)) /* channel operation */
65 #define CHOR_DMARESET BIT(31)
66 #define CHOR_SET_SEND_TC BIT(11)
67 #define CHOR_CLR_SEND_TC BIT(10)
68 #define CHOR_SET_LPAUSE BIT(9)
69 #define CHOR_CLR_LPAUSE BIT(8)
70 #define CHOR_CLRDONE BIT(7)
71 #define CHOR_CLRRB BIT(6)
72 #define CHOR_CLRLC BIT(5)
73 #define CHOR_FRESET BIT(4)
74 #define CHOR_ABORT BIT(3) /* stop without emptying fifo */
75 #define CHOR_STOP BIT(2) /* stop after emptying fifo */
76 #define CHOR_CONT BIT(1)
77 #define CHOR_START BIT(0)
78 #define MITE_CHCR(x) (0x04 + MITE_CHAN(x)) /* channel control */
79 #define CHCR_SET_DMA_IE BIT(31)
80 #define CHCR_CLR_DMA_IE BIT(30)
81 #define CHCR_SET_LINKP_IE BIT(29)
82 #define CHCR_CLR_LINKP_IE BIT(28)
83 #define CHCR_SET_SAR_IE BIT(27)
84 #define CHCR_CLR_SAR_IE BIT(26)
85 #define CHCR_SET_DONE_IE BIT(25)
86 #define CHCR_CLR_DONE_IE BIT(24)
87 #define CHCR_SET_MRDY_IE BIT(23)
88 #define CHCR_CLR_MRDY_IE BIT(22)
89 #define CHCR_SET_DRDY_IE BIT(21)
90 #define CHCR_CLR_DRDY_IE BIT(20)
91 #define CHCR_SET_LC_IE BIT(19)
92 #define CHCR_CLR_LC_IE BIT(18)
93 #define CHCR_SET_CONT_RB_IE BIT(17)
94 #define CHCR_CLR_CONT_RB_IE BIT(16)
95 #define CHCR_FIFO(x) (((x) & 0x1) << 15)
96 #define CHCR_FIFODIS CHCR_FIFO(1)
97 #define CHCR_FIFO_ON CHCR_FIFO(0)
98 #define CHCR_BURST(x) (((x) & 0x1) << 14)
99 #define CHCR_BURSTEN CHCR_BURST(1)
100 #define CHCR_NO_BURSTEN CHCR_BURST(0)
101 #define CHCR_BYTE_SWAP_DEVICE BIT(6)
102 #define CHCR_BYTE_SWAP_MEMORY BIT(4)
103 #define CHCR_DIR(x) (((x) & 0x1) << 3)
104 #define CHCR_DEV_TO_MEM CHCR_DIR(1)
105 #define CHCR_MEM_TO_DEV CHCR_DIR(0)
106 #define CHCR_MODE(x) (((x) & 0x7) << 0)
107 #define CHCR_NORMAL CHCR_MODE(0)
108 #define CHCR_CONTINUE CHCR_MODE(1)
109 #define CHCR_RINGBUFF CHCR_MODE(2)
110 #define CHCR_LINKSHORT CHCR_MODE(4)
111 #define CHCR_LINKLONG CHCR_MODE(5)
112 #define MITE_TCR(x) (0x08 + MITE_CHAN(x)) /* transfer count */
113 #define MITE_MCR(x) (0x0c + MITE_CHAN(x)) /* memory config */
114 #define MITE_MAR(x) (0x10 + MITE_CHAN(x)) /* memory address */
115 #define MITE_DCR(x) (0x14 + MITE_CHAN(x)) /* device config */
116 #define DCR_NORMAL BIT(29)
117 #define MITE_DAR(x) (0x18 + MITE_CHAN(x)) /* device address */
118 #define MITE_LKCR(x) (0x1c + MITE_CHAN(x)) /* link config */
119 #define MITE_LKAR(x) (0x20 + MITE_CHAN(x)) /* link address */
120 #define MITE_LLKAR(x) (0x24 + MITE_CHAN(x)) /* see tnt5002 manual */
121 #define MITE_BAR(x) (0x28 + MITE_CHAN(x)) /* base address */
122 #define MITE_BCR(x) (0x2c + MITE_CHAN(x)) /* base count */
123 #define MITE_SAR(x) (0x30 + MITE_CHAN(x)) /* ? address */
124 #define MITE_WSCR(x) (0x34 + MITE_CHAN(x)) /* ? */
125 #define MITE_WSER(x) (0x38 + MITE_CHAN(x)) /* ? */
126 #define MITE_CHSR(x) (0x3c + MITE_CHAN(x)) /* channel status */
127 #define CHSR_INT BIT(31)
128 #define CHSR_LPAUSES BIT(29)
129 #define CHSR_SARS BIT(27)
130 #define CHSR_DONE BIT(25)
131 #define CHSR_MRDY BIT(23)
132 #define CHSR_DRDY BIT(21)
133 #define CHSR_LINKC BIT(19)
134 #define CHSR_CONTS_RB BIT(17)
135 #define CHSR_ERROR BIT(15)
136 #define CHSR_SABORT BIT(14)
137 #define CHSR_HABORT BIT(13)
138 #define CHSR_STOPS BIT(12)
139 #define CHSR_OPERR(x) (((x) & 0x3) << 10)
140 #define CHSR_OPERR_MASK CHSR_OPERR(3)
141 #define CHSR_OPERR_NOERROR CHSR_OPERR(0)
142 #define CHSR_OPERR_FIFOERROR CHSR_OPERR(1)
143 #define CHSR_OPERR_LINKERROR CHSR_OPERR(1) /* ??? */
144 #define CHSR_XFERR BIT(9)
145 #define CHSR_END BIT(8)
146 #define CHSR_DRQ1 BIT(7)
147 #define CHSR_DRQ0 BIT(6)
148 #define CHSR_LERR(x) (((x) & 0x3) << 4)
149 #define CHSR_LERR_MASK CHSR_LERR(3)
150 #define CHSR_LBERR CHSR_LERR(1)
151 #define CHSR_LRERR CHSR_LERR(2)
152 #define CHSR_LOERR CHSR_LERR(3)
153 #define CHSR_MERR(x) (((x) & 0x3) << 2)
154 #define CHSR_MERR_MASK CHSR_MERR(3)
155 #define CHSR_MBERR CHSR_MERR(1)
156 #define CHSR_MRERR CHSR_MERR(2)
157 #define CHSR_MOERR CHSR_MERR(3)
158 #define CHSR_DERR(x) (((x) & 0x3) << 0)
159 #define CHSR_DERR_MASK CHSR_DERR(3)
160 #define CHSR_DBERR CHSR_DERR(1)
161 #define CHSR_DRERR CHSR_DERR(2)
162 #define CHSR_DOERR CHSR_DERR(3)
163 #define MITE_FCR(x) (0x40 + MITE_CHAN(x)) /* fifo count */
164
165 /* common bits for the memory/device/link config registers */
166 #define CR_RL(x) (((x) & 0x7) << 21)
167 #define CR_REQS(x) (((x) & 0x7) << 16)
168 #define CR_REQS_MASK CR_REQS(7)
169 #define CR_ASEQ(x) (((x) & 0x3) << 10)
170 #define CR_ASEQDONT CR_ASEQ(0)
171 #define CR_ASEQUP CR_ASEQ(1)
172 #define CR_ASEQDOWN CR_ASEQ(2)
173 #define CR_ASEQ_MASK CR_ASEQ(3)
174 #define CR_PSIZE(x) (((x) & 0x3) << 8)
175 #define CR_PSIZE8 CR_PSIZE(1)
176 #define CR_PSIZE16 CR_PSIZE(2)
177 #define CR_PSIZE32 CR_PSIZE(3)
178 #define CR_PORT(x) (((x) & 0x3) << 6)
179 #define CR_PORTCPU CR_PORT(0)
180 #define CR_PORTIO CR_PORT(1)
181 #define CR_PORTVXI CR_PORT(2)
182 #define CR_PORTMXI CR_PORT(3)
183 #define CR_AMDEVICE BIT(0)
184
MITE_IODWBSR_1_WSIZE_bits(unsigned int size)185 static unsigned int MITE_IODWBSR_1_WSIZE_bits(unsigned int size)
186 {
187 return (ilog2(size) - 1) & 0x1f;
188 }
189
mite_retry_limit(unsigned int retry_limit)190 static unsigned int mite_retry_limit(unsigned int retry_limit)
191 {
192 unsigned int value = 0;
193
194 if (retry_limit)
195 value = 1 + ilog2(retry_limit);
196 if (value > 0x7)
197 value = 0x7;
198 return CR_RL(value);
199 }
200
mite_drq_reqs(unsigned int drq_line)201 static unsigned int mite_drq_reqs(unsigned int drq_line)
202 {
203 /* This also works on m-series when using channels (drq_line) 4 or 5. */
204 return CR_REQS((drq_line & 0x3) | 0x4);
205 }
206
mite_fifo_size(struct mite * mite,unsigned int channel)207 static unsigned int mite_fifo_size(struct mite *mite, unsigned int channel)
208 {
209 unsigned int fcr_bits = readl(mite->mmio + MITE_FCR(channel));
210 unsigned int empty_count = (fcr_bits >> 16) & 0xff;
211 unsigned int full_count = fcr_bits & 0xff;
212
213 return empty_count + full_count;
214 }
215
mite_device_bytes_transferred(struct mite_channel * mite_chan)216 static u32 mite_device_bytes_transferred(struct mite_channel *mite_chan)
217 {
218 struct mite *mite = mite_chan->mite;
219
220 return readl(mite->mmio + MITE_DAR(mite_chan->channel));
221 }
222
223 /**
224 * mite_bytes_in_transit() - Returns the number of unread bytes in the fifo.
225 * @mite_chan: MITE dma channel.
226 */
mite_bytes_in_transit(struct mite_channel * mite_chan)227 u32 mite_bytes_in_transit(struct mite_channel *mite_chan)
228 {
229 struct mite *mite = mite_chan->mite;
230
231 return readl(mite->mmio + MITE_FCR(mite_chan->channel)) & 0xff;
232 }
233 EXPORT_SYMBOL_GPL(mite_bytes_in_transit);
234
235 /* returns lower bound for number of bytes transferred from device to memory */
mite_bytes_written_to_memory_lb(struct mite_channel * mite_chan)236 static u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan)
237 {
238 u32 device_byte_count;
239
240 device_byte_count = mite_device_bytes_transferred(mite_chan);
241 return device_byte_count - mite_bytes_in_transit(mite_chan);
242 }
243
244 /* returns upper bound for number of bytes transferred from device to memory */
mite_bytes_written_to_memory_ub(struct mite_channel * mite_chan)245 static u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan)
246 {
247 u32 in_transit_count;
248
249 in_transit_count = mite_bytes_in_transit(mite_chan);
250 return mite_device_bytes_transferred(mite_chan) - in_transit_count;
251 }
252
253 /* returns lower bound for number of bytes read from memory to device */
mite_bytes_read_from_memory_lb(struct mite_channel * mite_chan)254 static u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan)
255 {
256 u32 device_byte_count;
257
258 device_byte_count = mite_device_bytes_transferred(mite_chan);
259 return device_byte_count + mite_bytes_in_transit(mite_chan);
260 }
261
262 /* returns upper bound for number of bytes read from memory to device */
mite_bytes_read_from_memory_ub(struct mite_channel * mite_chan)263 static u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan)
264 {
265 u32 in_transit_count;
266
267 in_transit_count = mite_bytes_in_transit(mite_chan);
268 return mite_device_bytes_transferred(mite_chan) + in_transit_count;
269 }
270
mite_sync_input_dma(struct mite_channel * mite_chan,struct comedi_subdevice * s)271 static void mite_sync_input_dma(struct mite_channel *mite_chan,
272 struct comedi_subdevice *s)
273 {
274 struct comedi_async *async = s->async;
275 int count;
276 unsigned int nbytes, old_alloc_count;
277
278 old_alloc_count = async->buf_write_alloc_count;
279 /* write alloc as much as we can */
280 comedi_buf_write_alloc(s, async->prealloc_bufsz);
281
282 nbytes = mite_bytes_written_to_memory_lb(mite_chan);
283 if ((int)(mite_bytes_written_to_memory_ub(mite_chan) -
284 old_alloc_count) > 0) {
285 dev_warn(s->device->class_dev,
286 "mite: DMA overwrite of free area\n");
287 async->events |= COMEDI_CB_OVERFLOW;
288 return;
289 }
290
291 count = nbytes - async->buf_write_count;
292 /*
293 * it's possible count will be negative due to conservative value
294 * returned by mite_bytes_written_to_memory_lb
295 */
296 if (count > 0) {
297 comedi_buf_write_free(s, count);
298 comedi_inc_scan_progress(s, count);
299 async->events |= COMEDI_CB_BLOCK;
300 }
301 }
302
mite_sync_output_dma(struct mite_channel * mite_chan,struct comedi_subdevice * s)303 static void mite_sync_output_dma(struct mite_channel *mite_chan,
304 struct comedi_subdevice *s)
305 {
306 struct comedi_async *async = s->async;
307 struct comedi_cmd *cmd = &async->cmd;
308 u32 stop_count = cmd->stop_arg * comedi_bytes_per_scan(s);
309 unsigned int old_alloc_count = async->buf_read_alloc_count;
310 u32 nbytes_ub, nbytes_lb;
311 int count;
312 bool finite_regen = (cmd->stop_src == TRIG_NONE && stop_count != 0);
313
314 /* read alloc as much as we can */
315 comedi_buf_read_alloc(s, async->prealloc_bufsz);
316 nbytes_lb = mite_bytes_read_from_memory_lb(mite_chan);
317 if (cmd->stop_src == TRIG_COUNT && (int)(nbytes_lb - stop_count) > 0)
318 nbytes_lb = stop_count;
319 nbytes_ub = mite_bytes_read_from_memory_ub(mite_chan);
320 if (cmd->stop_src == TRIG_COUNT && (int)(nbytes_ub - stop_count) > 0)
321 nbytes_ub = stop_count;
322
323 if ((!finite_regen || stop_count > old_alloc_count) &&
324 ((int)(nbytes_ub - old_alloc_count) > 0)) {
325 dev_warn(s->device->class_dev, "mite: DMA underrun\n");
326 async->events |= COMEDI_CB_OVERFLOW;
327 return;
328 }
329
330 if (finite_regen) {
331 /*
332 * This is a special case where we continuously output a finite
333 * buffer. In this case, we do not free any of the memory,
334 * hence we expect that old_alloc_count will reach a maximum of
335 * stop_count bytes.
336 */
337 return;
338 }
339
340 count = nbytes_lb - async->buf_read_count;
341 if (count > 0) {
342 comedi_buf_read_free(s, count);
343 async->events |= COMEDI_CB_BLOCK;
344 }
345 }
346
347 /**
348 * mite_sync_dma() - Sync the MITE dma with the COMEDI async buffer.
349 * @mite_chan: MITE dma channel.
350 * @s: COMEDI subdevice.
351 */
mite_sync_dma(struct mite_channel * mite_chan,struct comedi_subdevice * s)352 void mite_sync_dma(struct mite_channel *mite_chan, struct comedi_subdevice *s)
353 {
354 if (mite_chan->dir == COMEDI_INPUT)
355 mite_sync_input_dma(mite_chan, s);
356 else
357 mite_sync_output_dma(mite_chan, s);
358 }
359 EXPORT_SYMBOL_GPL(mite_sync_dma);
360
mite_get_status(struct mite_channel * mite_chan)361 static unsigned int mite_get_status(struct mite_channel *mite_chan)
362 {
363 struct mite *mite = mite_chan->mite;
364 unsigned int status;
365 unsigned long flags;
366
367 spin_lock_irqsave(&mite->lock, flags);
368 status = readl(mite->mmio + MITE_CHSR(mite_chan->channel));
369 if (status & CHSR_DONE) {
370 mite_chan->done = 1;
371 writel(CHOR_CLRDONE,
372 mite->mmio + MITE_CHOR(mite_chan->channel));
373 }
374 spin_unlock_irqrestore(&mite->lock, flags);
375 return status;
376 }
377
378 /**
379 * mite_ack_linkc() - Check and ack the LINKC interrupt,
380 * @mite_chan: MITE dma channel.
381 * @s: COMEDI subdevice.
382 * @sync: flag to force a mite_sync_dma().
383 *
384 * This will also ack the DONE interrupt if active.
385 */
mite_ack_linkc(struct mite_channel * mite_chan,struct comedi_subdevice * s,bool sync)386 void mite_ack_linkc(struct mite_channel *mite_chan,
387 struct comedi_subdevice *s,
388 bool sync)
389 {
390 struct mite *mite = mite_chan->mite;
391 unsigned int status;
392
393 status = mite_get_status(mite_chan);
394 if (status & CHSR_LINKC) {
395 writel(CHOR_CLRLC, mite->mmio + MITE_CHOR(mite_chan->channel));
396 sync = true;
397 }
398 if (sync)
399 mite_sync_dma(mite_chan, s);
400
401 if (status & CHSR_XFERR) {
402 dev_err(s->device->class_dev,
403 "mite: transfer error %08x\n", status);
404 s->async->events |= COMEDI_CB_ERROR;
405 }
406 }
407 EXPORT_SYMBOL_GPL(mite_ack_linkc);
408
409 /**
410 * mite_done() - Check is a MITE dma transfer is complete.
411 * @mite_chan: MITE dma channel.
412 *
413 * This will also ack the DONE interrupt if active.
414 */
mite_done(struct mite_channel * mite_chan)415 int mite_done(struct mite_channel *mite_chan)
416 {
417 struct mite *mite = mite_chan->mite;
418 unsigned long flags;
419 int done;
420
421 mite_get_status(mite_chan);
422 spin_lock_irqsave(&mite->lock, flags);
423 done = mite_chan->done;
424 spin_unlock_irqrestore(&mite->lock, flags);
425 return done;
426 }
427 EXPORT_SYMBOL_GPL(mite_done);
428
mite_dma_reset(struct mite_channel * mite_chan)429 static void mite_dma_reset(struct mite_channel *mite_chan)
430 {
431 writel(CHOR_DMARESET | CHOR_FRESET,
432 mite_chan->mite->mmio + MITE_CHOR(mite_chan->channel));
433 }
434
435 /**
436 * mite_dma_arm() - Start a MITE dma transfer.
437 * @mite_chan: MITE dma channel.
438 */
mite_dma_arm(struct mite_channel * mite_chan)439 void mite_dma_arm(struct mite_channel *mite_chan)
440 {
441 struct mite *mite = mite_chan->mite;
442 unsigned long flags;
443
444 /*
445 * memory barrier is intended to insure any twiddling with the buffer
446 * is done before writing to the mite to arm dma transfer
447 */
448 smp_mb();
449 spin_lock_irqsave(&mite->lock, flags);
450 mite_chan->done = 0;
451 /* arm */
452 writel(CHOR_START, mite->mmio + MITE_CHOR(mite_chan->channel));
453 spin_unlock_irqrestore(&mite->lock, flags);
454 }
455 EXPORT_SYMBOL_GPL(mite_dma_arm);
456
457 /**
458 * mite_dma_disarm() - Stop a MITE dma transfer.
459 * @mite_chan: MITE dma channel.
460 */
mite_dma_disarm(struct mite_channel * mite_chan)461 void mite_dma_disarm(struct mite_channel *mite_chan)
462 {
463 struct mite *mite = mite_chan->mite;
464
465 /* disarm */
466 writel(CHOR_ABORT, mite->mmio + MITE_CHOR(mite_chan->channel));
467 }
468 EXPORT_SYMBOL_GPL(mite_dma_disarm);
469
470 /**
471 * mite_prep_dma() - Prepare a MITE dma channel for transfers.
472 * @mite_chan: MITE dma channel.
473 * @num_device_bits: device transfer size (8, 16, or 32-bits).
474 * @num_memory_bits: memory transfer size (8, 16, or 32-bits).
475 */
mite_prep_dma(struct mite_channel * mite_chan,unsigned int num_device_bits,unsigned int num_memory_bits)476 void mite_prep_dma(struct mite_channel *mite_chan,
477 unsigned int num_device_bits, unsigned int num_memory_bits)
478 {
479 struct mite *mite = mite_chan->mite;
480 unsigned int chcr, mcr, dcr, lkcr;
481
482 mite_dma_reset(mite_chan);
483
484 /* short link chaining mode */
485 chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE |
486 CHCR_BURSTEN;
487 /*
488 * Link Complete Interrupt: interrupt every time a link
489 * in MITE_RING is completed. This can generate a lot of
490 * extra interrupts, but right now we update the values
491 * of buf_int_ptr and buf_int_count at each interrupt. A
492 * better method is to poll the MITE before each user
493 * "read()" to calculate the number of bytes available.
494 */
495 chcr |= CHCR_SET_LC_IE;
496 if (num_memory_bits == 32 && num_device_bits == 16) {
497 /*
498 * Doing a combined 32 and 16 bit byteswap gets the 16 bit
499 * samples into the fifo in the right order. Tested doing 32 bit
500 * memory to 16 bit device transfers to the analog out of a
501 * pxi-6281, which has mite version = 1, type = 4. This also
502 * works for dma reads from the counters on e-series boards.
503 */
504 chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY;
505 }
506 if (mite_chan->dir == COMEDI_INPUT)
507 chcr |= CHCR_DEV_TO_MEM;
508
509 writel(chcr, mite->mmio + MITE_CHCR(mite_chan->channel));
510
511 /* to/from memory */
512 mcr = mite_retry_limit(64) | CR_ASEQUP;
513 switch (num_memory_bits) {
514 case 8:
515 mcr |= CR_PSIZE8;
516 break;
517 case 16:
518 mcr |= CR_PSIZE16;
519 break;
520 case 32:
521 mcr |= CR_PSIZE32;
522 break;
523 default:
524 pr_warn("bug! invalid mem bit width for dma transfer\n");
525 break;
526 }
527 writel(mcr, mite->mmio + MITE_MCR(mite_chan->channel));
528
529 /* from/to device */
530 dcr = mite_retry_limit(64) | CR_ASEQUP;
531 dcr |= CR_PORTIO | CR_AMDEVICE | mite_drq_reqs(mite_chan->channel);
532 switch (num_device_bits) {
533 case 8:
534 dcr |= CR_PSIZE8;
535 break;
536 case 16:
537 dcr |= CR_PSIZE16;
538 break;
539 case 32:
540 dcr |= CR_PSIZE32;
541 break;
542 default:
543 pr_warn("bug! invalid dev bit width for dma transfer\n");
544 break;
545 }
546 writel(dcr, mite->mmio + MITE_DCR(mite_chan->channel));
547
548 /* reset the DAR */
549 writel(0, mite->mmio + MITE_DAR(mite_chan->channel));
550
551 /* the link is 32bits */
552 lkcr = mite_retry_limit(64) | CR_ASEQUP | CR_PSIZE32;
553 writel(lkcr, mite->mmio + MITE_LKCR(mite_chan->channel));
554
555 /* starting address for link chaining */
556 writel(mite_chan->ring->dma_addr,
557 mite->mmio + MITE_LKAR(mite_chan->channel));
558 }
559 EXPORT_SYMBOL_GPL(mite_prep_dma);
560
561 /**
562 * mite_request_channel_in_range() - Request a MITE dma channel.
563 * @mite: MITE device.
564 * @ring: MITE dma ring.
565 * @min_channel: minimum channel index to use.
566 * @max_channel: maximum channel index to use.
567 */
mite_request_channel_in_range(struct mite * mite,struct mite_ring * ring,unsigned int min_channel,unsigned int max_channel)568 struct mite_channel *mite_request_channel_in_range(struct mite *mite,
569 struct mite_ring *ring,
570 unsigned int min_channel,
571 unsigned int max_channel)
572 {
573 struct mite_channel *mite_chan = NULL;
574 unsigned long flags;
575 int i;
576
577 /*
578 * spin lock so mite_release_channel can be called safely
579 * from interrupts
580 */
581 spin_lock_irqsave(&mite->lock, flags);
582 for (i = min_channel; i <= max_channel; ++i) {
583 mite_chan = &mite->channels[i];
584 if (!mite_chan->ring) {
585 mite_chan->ring = ring;
586 break;
587 }
588 mite_chan = NULL;
589 }
590 spin_unlock_irqrestore(&mite->lock, flags);
591 return mite_chan;
592 }
593 EXPORT_SYMBOL_GPL(mite_request_channel_in_range);
594
595 /**
596 * mite_request_channel() - Request a MITE dma channel.
597 * @mite: MITE device.
598 * @ring: MITE dma ring.
599 */
mite_request_channel(struct mite * mite,struct mite_ring * ring)600 struct mite_channel *mite_request_channel(struct mite *mite,
601 struct mite_ring *ring)
602 {
603 return mite_request_channel_in_range(mite, ring, 0,
604 mite->num_channels - 1);
605 }
606 EXPORT_SYMBOL_GPL(mite_request_channel);
607
608 /**
609 * mite_release_channel() - Release a MITE dma channel.
610 * @mite_chan: MITE dma channel.
611 */
mite_release_channel(struct mite_channel * mite_chan)612 void mite_release_channel(struct mite_channel *mite_chan)
613 {
614 struct mite *mite = mite_chan->mite;
615 unsigned long flags;
616
617 /* spin lock to prevent races with mite_request_channel */
618 spin_lock_irqsave(&mite->lock, flags);
619 if (mite_chan->ring) {
620 mite_dma_disarm(mite_chan);
621 mite_dma_reset(mite_chan);
622 /*
623 * disable all channel's interrupts (do it after disarm/reset so
624 * MITE_CHCR reg isn't changed while dma is still active!)
625 */
626 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE |
627 CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE |
628 CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
629 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
630 mite->mmio + MITE_CHCR(mite_chan->channel));
631 mite_chan->ring = NULL;
632 }
633 spin_unlock_irqrestore(&mite->lock, flags);
634 }
635 EXPORT_SYMBOL_GPL(mite_release_channel);
636
637 /**
638 * mite_init_ring_descriptors() - Initialize a MITE dma ring descriptors.
639 * @ring: MITE dma ring.
640 * @s: COMEDI subdevice.
641 * @nbytes: the size of the dma ring (in bytes).
642 *
643 * Initializes the ring buffer descriptors to provide correct DMA transfer
644 * links to the exact amount of memory required. When the ring buffer is
645 * allocated by mite_buf_change(), the default is to initialize the ring
646 * to refer to the entire DMA data buffer. A command may call this function
647 * later to re-initialize and shorten the amount of memory that will be
648 * transferred.
649 */
mite_init_ring_descriptors(struct mite_ring * ring,struct comedi_subdevice * s,unsigned int nbytes)650 int mite_init_ring_descriptors(struct mite_ring *ring,
651 struct comedi_subdevice *s,
652 unsigned int nbytes)
653 {
654 struct comedi_async *async = s->async;
655 struct mite_dma_desc *desc = NULL;
656 unsigned int n_full_links = nbytes >> PAGE_SHIFT;
657 unsigned int remainder = nbytes % PAGE_SIZE;
658 int i;
659
660 dev_dbg(s->device->class_dev,
661 "mite: init ring buffer to %u bytes\n", nbytes);
662
663 if ((n_full_links + (remainder > 0 ? 1 : 0)) > ring->n_links) {
664 dev_err(s->device->class_dev,
665 "mite: ring buffer too small for requested init\n");
666 return -ENOMEM;
667 }
668
669 /* We set the descriptors for all full links. */
670 for (i = 0; i < n_full_links; ++i) {
671 desc = &ring->descs[i];
672 desc->count = cpu_to_le32(PAGE_SIZE);
673 desc->addr = cpu_to_le32(async->buf_map->page_list[i].dma_addr);
674 desc->next = cpu_to_le32(ring->dma_addr +
675 (i + 1) * sizeof(*desc));
676 }
677
678 /* the last link is either a remainder or was a full link. */
679 if (remainder > 0) {
680 desc = &ring->descs[i];
681 /* set the lesser count for the remainder link */
682 desc->count = cpu_to_le32(remainder);
683 desc->addr = cpu_to_le32(async->buf_map->page_list[i].dma_addr);
684 }
685
686 /* Assign the last link->next to point back to the head of the list. */
687 desc->next = cpu_to_le32(ring->dma_addr);
688
689 /*
690 * barrier is meant to insure that all the writes to the dma descriptors
691 * have completed before the dma controller is commanded to read them
692 */
693 smp_wmb();
694 return 0;
695 }
696 EXPORT_SYMBOL_GPL(mite_init_ring_descriptors);
697
mite_free_dma_descs(struct mite_ring * ring)698 static void mite_free_dma_descs(struct mite_ring *ring)
699 {
700 struct mite_dma_desc *descs = ring->descs;
701
702 if (descs) {
703 dma_free_coherent(ring->hw_dev,
704 ring->n_links * sizeof(*descs),
705 descs, ring->dma_addr);
706 ring->descs = NULL;
707 ring->dma_addr = 0;
708 ring->n_links = 0;
709 }
710 }
711
712 /**
713 * mite_buf_change() - COMEDI subdevice (*buf_change) for a MITE dma ring.
714 * @ring: MITE dma ring.
715 * @s: COMEDI subdevice.
716 */
mite_buf_change(struct mite_ring * ring,struct comedi_subdevice * s)717 int mite_buf_change(struct mite_ring *ring, struct comedi_subdevice *s)
718 {
719 struct comedi_async *async = s->async;
720 struct mite_dma_desc *descs;
721 unsigned int n_links;
722
723 mite_free_dma_descs(ring);
724
725 if (async->prealloc_bufsz == 0)
726 return 0;
727
728 n_links = async->prealloc_bufsz >> PAGE_SHIFT;
729
730 descs = dma_alloc_coherent(ring->hw_dev,
731 n_links * sizeof(*descs),
732 &ring->dma_addr, GFP_KERNEL);
733 if (!descs) {
734 dev_err(s->device->class_dev,
735 "mite: ring buffer allocation failed\n");
736 return -ENOMEM;
737 }
738 ring->descs = descs;
739 ring->n_links = n_links;
740
741 return mite_init_ring_descriptors(ring, s, n_links << PAGE_SHIFT);
742 }
743 EXPORT_SYMBOL_GPL(mite_buf_change);
744
745 /**
746 * mite_alloc_ring() - Allocate a MITE dma ring.
747 * @mite: MITE device.
748 */
mite_alloc_ring(struct mite * mite)749 struct mite_ring *mite_alloc_ring(struct mite *mite)
750 {
751 struct mite_ring *ring;
752
753 ring = kmalloc(sizeof(*ring), GFP_KERNEL);
754 if (!ring)
755 return NULL;
756 ring->hw_dev = get_device(&mite->pcidev->dev);
757 if (!ring->hw_dev) {
758 kfree(ring);
759 return NULL;
760 }
761 ring->n_links = 0;
762 ring->descs = NULL;
763 ring->dma_addr = 0;
764 return ring;
765 }
766 EXPORT_SYMBOL_GPL(mite_alloc_ring);
767
768 /**
769 * mite_free_ring() - Free a MITE dma ring and its descriptors.
770 * @ring: MITE dma ring.
771 */
mite_free_ring(struct mite_ring * ring)772 void mite_free_ring(struct mite_ring *ring)
773 {
774 if (ring) {
775 mite_free_dma_descs(ring);
776 put_device(ring->hw_dev);
777 kfree(ring);
778 }
779 }
780 EXPORT_SYMBOL_GPL(mite_free_ring);
781
mite_setup(struct comedi_device * dev,struct mite * mite,bool use_win1)782 static int mite_setup(struct comedi_device *dev, struct mite *mite,
783 bool use_win1)
784 {
785 resource_size_t daq_phys_addr;
786 unsigned long length;
787 int i;
788 u32 csigr_bits;
789 unsigned int unknown_dma_burst_bits;
790 unsigned int wpdep;
791
792 pci_set_master(mite->pcidev);
793
794 mite->mmio = pci_ioremap_bar(mite->pcidev, 0);
795 if (!mite->mmio)
796 return -ENOMEM;
797
798 dev->mmio = pci_ioremap_bar(mite->pcidev, 1);
799 if (!dev->mmio)
800 return -ENOMEM;
801 daq_phys_addr = pci_resource_start(mite->pcidev, 1);
802 length = pci_resource_len(mite->pcidev, 1);
803
804 if (use_win1) {
805 writel(0, mite->mmio + MITE_IODWBSR);
806 dev_dbg(dev->class_dev,
807 "mite: using I/O Window Base Size register 1\n");
808 writel(daq_phys_addr | WENAB |
809 MITE_IODWBSR_1_WSIZE_bits(length),
810 mite->mmio + MITE_IODWBSR_1);
811 writel(0, mite->mmio + MITE_IODWCR_1);
812 } else {
813 writel(daq_phys_addr | WENAB, mite->mmio + MITE_IODWBSR);
814 }
815 /*
816 * Make sure dma bursts work. I got this from running a bus analyzer
817 * on a pxi-6281 and a pxi-6713. 6713 powered up with register value
818 * of 0x61f and bursts worked. 6281 powered up with register value of
819 * 0x1f and bursts didn't work. The NI windows driver reads the
820 * register, then does a bitwise-or of 0x600 with it and writes it back.
821 *
822 * The bits 0x90180700 in MITE_UNKNOWN_DMA_BURST_REG can be
823 * written and read back. The bits 0x1f always read as 1.
824 * The rest always read as zero.
825 */
826 unknown_dma_burst_bits = readl(mite->mmio + MITE_UNKNOWN_DMA_BURST_REG);
827 unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS;
828 writel(unknown_dma_burst_bits, mite->mmio + MITE_UNKNOWN_DMA_BURST_REG);
829
830 csigr_bits = readl(mite->mmio + MITE_CSIGR);
831 mite->num_channels = CSIGR_TO_DMAC(csigr_bits);
832 if (mite->num_channels > MAX_MITE_DMA_CHANNELS) {
833 dev_warn(dev->class_dev,
834 "mite: bug? chip claims to have %i dma channels. Setting to %i.\n",
835 mite->num_channels, MAX_MITE_DMA_CHANNELS);
836 mite->num_channels = MAX_MITE_DMA_CHANNELS;
837 }
838
839 /* get the wpdep bits and convert it to the write port fifo depth */
840 wpdep = CSIGR_TO_WPDEP(csigr_bits);
841 if (wpdep)
842 wpdep = BIT(wpdep);
843
844 dev_dbg(dev->class_dev,
845 "mite: version = %i, type = %i, mite mode = %i, interface mode = %i\n",
846 CSIGR_TO_VER(csigr_bits), CSIGR_TO_TYPE(csigr_bits),
847 CSIGR_TO_MMODE(csigr_bits), CSIGR_TO_IMODE(csigr_bits));
848 dev_dbg(dev->class_dev,
849 "mite: num channels = %i, write post fifo depth = %i, wins = %i, iowins = %i\n",
850 CSIGR_TO_DMAC(csigr_bits), wpdep,
851 CSIGR_TO_WINS(csigr_bits), CSIGR_TO_IOWINS(csigr_bits));
852
853 for (i = 0; i < mite->num_channels; i++) {
854 writel(CHOR_DMARESET, mite->mmio + MITE_CHOR(i));
855 /* disable interrupts */
856 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
857 CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
858 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
859 mite->mmio + MITE_CHCR(i));
860 }
861 mite->fifo_size = mite_fifo_size(mite, 0);
862 dev_dbg(dev->class_dev, "mite: fifo size is %i.\n", mite->fifo_size);
863 return 0;
864 }
865
866 /**
867 * mite_attach() - Allocate and initialize a MITE device for a comedi driver.
868 * @dev: COMEDI device.
869 * @use_win1: flag to use I/O Window 1 instead of I/O Window 0.
870 *
871 * Called by a COMEDI drivers (*auto_attach).
872 *
873 * Returns a pointer to the MITE device on success, or NULL if the MITE cannot
874 * be allocated or remapped.
875 */
mite_attach(struct comedi_device * dev,bool use_win1)876 struct mite *mite_attach(struct comedi_device *dev, bool use_win1)
877 {
878 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
879 struct mite *mite;
880 unsigned int i;
881 int ret;
882
883 mite = kzalloc(sizeof(*mite), GFP_KERNEL);
884 if (!mite)
885 return NULL;
886
887 spin_lock_init(&mite->lock);
888 mite->pcidev = pcidev;
889 for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) {
890 mite->channels[i].mite = mite;
891 mite->channels[i].channel = i;
892 mite->channels[i].done = 1;
893 }
894
895 ret = mite_setup(dev, mite, use_win1);
896 if (ret) {
897 if (mite->mmio)
898 iounmap(mite->mmio);
899 kfree(mite);
900 return NULL;
901 }
902
903 return mite;
904 }
905 EXPORT_SYMBOL_GPL(mite_attach);
906
907 /**
908 * mite_detach() - Unmap and free a MITE device for a comedi driver.
909 * @mite: MITE device.
910 *
911 * Called by a COMEDI drivers (*detach).
912 */
mite_detach(struct mite * mite)913 void mite_detach(struct mite *mite)
914 {
915 if (!mite)
916 return;
917
918 if (mite->mmio)
919 iounmap(mite->mmio);
920
921 kfree(mite);
922 }
923 EXPORT_SYMBOL_GPL(mite_detach);
924
mite_module_init(void)925 static int __init mite_module_init(void)
926 {
927 return 0;
928 }
929 module_init(mite_module_init);
930
mite_module_exit(void)931 static void __exit mite_module_exit(void)
932 {
933 }
934 module_exit(mite_module_exit);
935
936 MODULE_AUTHOR("Comedi http://www.comedi.org");
937 MODULE_DESCRIPTION("Comedi helper for NI Mite PCI interface chip");
938 MODULE_LICENSE("GPL");
939
