1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000 by Ralf Baechle and others.
7 * Copyright (C) 2005, 2006 by Ralf Baechle (ralf@linux-mips.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 2004 Thiemo Seufer
10 * Copyright (C) 2013 Imagination Technologies Ltd.
11 */
12 #include <linux/errno.h>
13 #include <linux/sched.h>
14 #include <linux/sched/debug.h>
15 #include <linux/sched/task.h>
16 #include <linux/sched/task_stack.h>
17 #include <linux/tick.h>
18 #include <linux/kernel.h>
19 #include <linux/mm.h>
20 #include <linux/stddef.h>
21 #include <linux/unistd.h>
22 #include <linux/export.h>
23 #include <linux/ptrace.h>
24 #include <linux/mman.h>
25 #include <linux/personality.h>
26 #include <linux/sys.h>
27 #include <linux/init.h>
28 #include <linux/completion.h>
29 #include <linux/kallsyms.h>
30 #include <linux/random.h>
31 #include <linux/prctl.h>
32 #include <linux/nmi.h>
33 #include <linux/cpu.h>
34
35 #include <asm/abi.h>
36 #include <asm/asm.h>
37 #include <asm/bootinfo.h>
38 #include <asm/cpu.h>
39 #include <asm/dsemul.h>
40 #include <asm/dsp.h>
41 #include <asm/fpu.h>
42 #include <asm/irq.h>
43 #include <asm/mips-cps.h>
44 #include <asm/msa.h>
45 #include <asm/mipsregs.h>
46 #include <asm/processor.h>
47 #include <asm/reg.h>
48 #include <linux/uaccess.h>
49 #include <asm/io.h>
50 #include <asm/elf.h>
51 #include <asm/isadep.h>
52 #include <asm/inst.h>
53 #include <asm/stacktrace.h>
54 #include <asm/irq_regs.h>
55 #include <asm/exec.h>
56
57 #ifdef CONFIG_HOTPLUG_CPU
arch_cpu_idle_dead(void)58 void arch_cpu_idle_dead(void)
59 {
60 play_dead();
61 }
62 #endif
63
64 asmlinkage void ret_from_fork(void);
65 asmlinkage void ret_from_kernel_thread(void);
66
start_thread(struct pt_regs * regs,unsigned long pc,unsigned long sp)67 void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp)
68 {
69 unsigned long status;
70
71 /* New thread loses kernel privileges. */
72 status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_CU2|ST0_FR|KU_MASK);
73 status |= KU_USER;
74 regs->cp0_status = status;
75 lose_fpu(0);
76 clear_thread_flag(TIF_MSA_CTX_LIVE);
77 clear_used_math();
78 #ifdef CONFIG_MIPS_FP_SUPPORT
79 atomic_set(¤t->thread.bd_emu_frame, BD_EMUFRAME_NONE);
80 #endif
81 init_dsp();
82 regs->cp0_epc = pc;
83 regs->regs[29] = sp;
84 }
85
exit_thread(struct task_struct * tsk)86 void exit_thread(struct task_struct *tsk)
87 {
88 /*
89 * User threads may have allocated a delay slot emulation frame.
90 * If so, clean up that allocation.
91 */
92 if (!(current->flags & PF_KTHREAD))
93 dsemul_thread_cleanup(tsk);
94 }
95
arch_dup_task_struct(struct task_struct * dst,struct task_struct * src)96 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
97 {
98 /*
99 * Save any process state which is live in hardware registers to the
100 * parent context prior to duplication. This prevents the new child
101 * state becoming stale if the parent is preempted before copy_thread()
102 * gets a chance to save the parent's live hardware registers to the
103 * child context.
104 */
105 preempt_disable();
106
107 if (is_msa_enabled())
108 save_msa(current);
109 else if (is_fpu_owner())
110 _save_fp(current);
111
112 save_dsp(current);
113
114 preempt_enable();
115
116 *dst = *src;
117 return 0;
118 }
119
120 /*
121 * Copy architecture-specific thread state
122 */
copy_thread(unsigned long clone_flags,unsigned long usp,unsigned long kthread_arg,struct task_struct * p,unsigned long tls)123 int copy_thread(unsigned long clone_flags, unsigned long usp,
124 unsigned long kthread_arg, struct task_struct *p,
125 unsigned long tls)
126 {
127 struct thread_info *ti = task_thread_info(p);
128 struct pt_regs *childregs, *regs = current_pt_regs();
129 unsigned long childksp;
130
131 childksp = (unsigned long)task_stack_page(p) + THREAD_SIZE - 32;
132
133 /* set up new TSS. */
134 childregs = (struct pt_regs *) childksp - 1;
135 /* Put the stack after the struct pt_regs. */
136 childksp = (unsigned long) childregs;
137 p->thread.cp0_status = (read_c0_status() & ~(ST0_CU2|ST0_CU1)) | ST0_KERNEL_CUMASK;
138 if (unlikely(p->flags & PF_KTHREAD)) {
139 /* kernel thread */
140 unsigned long status = p->thread.cp0_status;
141 memset(childregs, 0, sizeof(struct pt_regs));
142 ti->addr_limit = KERNEL_DS;
143 p->thread.reg16 = usp; /* fn */
144 p->thread.reg17 = kthread_arg;
145 p->thread.reg29 = childksp;
146 p->thread.reg31 = (unsigned long) ret_from_kernel_thread;
147 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
148 status = (status & ~(ST0_KUP | ST0_IEP | ST0_IEC)) |
149 ((status & (ST0_KUC | ST0_IEC)) << 2);
150 #else
151 status |= ST0_EXL;
152 #endif
153 childregs->cp0_status = status;
154 return 0;
155 }
156
157 /* user thread */
158 *childregs = *regs;
159 childregs->regs[7] = 0; /* Clear error flag */
160 childregs->regs[2] = 0; /* Child gets zero as return value */
161 if (usp)
162 childregs->regs[29] = usp;
163 ti->addr_limit = USER_DS;
164
165 p->thread.reg29 = (unsigned long) childregs;
166 p->thread.reg31 = (unsigned long) ret_from_fork;
167
168 /*
169 * New tasks lose permission to use the fpu. This accelerates context
170 * switching for most programs since they don't use the fpu.
171 */
172 childregs->cp0_status &= ~(ST0_CU2|ST0_CU1);
173
174 clear_tsk_thread_flag(p, TIF_USEDFPU);
175 clear_tsk_thread_flag(p, TIF_USEDMSA);
176 clear_tsk_thread_flag(p, TIF_MSA_CTX_LIVE);
177
178 #ifdef CONFIG_MIPS_MT_FPAFF
179 clear_tsk_thread_flag(p, TIF_FPUBOUND);
180 #endif /* CONFIG_MIPS_MT_FPAFF */
181
182 #ifdef CONFIG_MIPS_FP_SUPPORT
183 atomic_set(&p->thread.bd_emu_frame, BD_EMUFRAME_NONE);
184 #endif
185
186 if (clone_flags & CLONE_SETTLS)
187 ti->tp_value = tls;
188
189 return 0;
190 }
191
192 #ifdef CONFIG_STACKPROTECTOR
193 #include <linux/stackprotector.h>
194 unsigned long __stack_chk_guard __read_mostly;
195 EXPORT_SYMBOL(__stack_chk_guard);
196 #endif
197
198 struct mips_frame_info {
199 void *func;
200 unsigned long func_size;
201 int frame_size;
202 int pc_offset;
203 };
204
205 #define J_TARGET(pc,target) \
206 (((unsigned long)(pc) & 0xf0000000) | ((target) << 2))
207
is_ra_save_ins(union mips_instruction * ip,int * poff)208 static inline int is_ra_save_ins(union mips_instruction *ip, int *poff)
209 {
210 #ifdef CONFIG_CPU_MICROMIPS
211 /*
212 * swsp ra,offset
213 * swm16 reglist,offset(sp)
214 * swm32 reglist,offset(sp)
215 * sw32 ra,offset(sp)
216 * jradiussp - NOT SUPPORTED
217 *
218 * microMIPS is way more fun...
219 */
220 if (mm_insn_16bit(ip->word >> 16)) {
221 switch (ip->mm16_r5_format.opcode) {
222 case mm_swsp16_op:
223 if (ip->mm16_r5_format.rt != 31)
224 return 0;
225
226 *poff = ip->mm16_r5_format.imm;
227 *poff = (*poff << 2) / sizeof(ulong);
228 return 1;
229
230 case mm_pool16c_op:
231 switch (ip->mm16_m_format.func) {
232 case mm_swm16_op:
233 *poff = ip->mm16_m_format.imm;
234 *poff += 1 + ip->mm16_m_format.rlist;
235 *poff = (*poff << 2) / sizeof(ulong);
236 return 1;
237
238 default:
239 return 0;
240 }
241
242 default:
243 return 0;
244 }
245 }
246
247 switch (ip->i_format.opcode) {
248 case mm_sw32_op:
249 if (ip->i_format.rs != 29)
250 return 0;
251 if (ip->i_format.rt != 31)
252 return 0;
253
254 *poff = ip->i_format.simmediate / sizeof(ulong);
255 return 1;
256
257 case mm_pool32b_op:
258 switch (ip->mm_m_format.func) {
259 case mm_swm32_func:
260 if (ip->mm_m_format.rd < 0x10)
261 return 0;
262 if (ip->mm_m_format.base != 29)
263 return 0;
264
265 *poff = ip->mm_m_format.simmediate;
266 *poff += (ip->mm_m_format.rd & 0xf) * sizeof(u32);
267 *poff /= sizeof(ulong);
268 return 1;
269 default:
270 return 0;
271 }
272
273 default:
274 return 0;
275 }
276 #else
277 /* sw / sd $ra, offset($sp) */
278 if ((ip->i_format.opcode == sw_op || ip->i_format.opcode == sd_op) &&
279 ip->i_format.rs == 29 && ip->i_format.rt == 31) {
280 *poff = ip->i_format.simmediate / sizeof(ulong);
281 return 1;
282 }
283 #ifdef CONFIG_CPU_LOONGSON64
284 if ((ip->loongson3_lswc2_format.opcode == swc2_op) &&
285 (ip->loongson3_lswc2_format.ls == 1) &&
286 (ip->loongson3_lswc2_format.fr == 0) &&
287 (ip->loongson3_lswc2_format.base == 29)) {
288 if (ip->loongson3_lswc2_format.rt == 31) {
289 *poff = ip->loongson3_lswc2_format.offset << 1;
290 return 1;
291 }
292 if (ip->loongson3_lswc2_format.rq == 31) {
293 *poff = (ip->loongson3_lswc2_format.offset << 1) + 1;
294 return 1;
295 }
296 }
297 #endif
298 return 0;
299 #endif
300 }
301
is_jump_ins(union mips_instruction * ip)302 static inline int is_jump_ins(union mips_instruction *ip)
303 {
304 #ifdef CONFIG_CPU_MICROMIPS
305 /*
306 * jr16,jrc,jalr16,jalr16
307 * jal
308 * jalr/jr,jalr.hb/jr.hb,jalrs,jalrs.hb
309 * jraddiusp - NOT SUPPORTED
310 *
311 * microMIPS is kind of more fun...
312 */
313 if (mm_insn_16bit(ip->word >> 16)) {
314 if ((ip->mm16_r5_format.opcode == mm_pool16c_op &&
315 (ip->mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op))
316 return 1;
317 return 0;
318 }
319
320 if (ip->j_format.opcode == mm_j32_op)
321 return 1;
322 if (ip->j_format.opcode == mm_jal32_op)
323 return 1;
324 if (ip->r_format.opcode != mm_pool32a_op ||
325 ip->r_format.func != mm_pool32axf_op)
326 return 0;
327 return ((ip->u_format.uimmediate >> 6) & mm_jalr_op) == mm_jalr_op;
328 #else
329 if (ip->j_format.opcode == j_op)
330 return 1;
331 if (ip->j_format.opcode == jal_op)
332 return 1;
333 if (ip->r_format.opcode != spec_op)
334 return 0;
335 return ip->r_format.func == jalr_op || ip->r_format.func == jr_op;
336 #endif
337 }
338
is_sp_move_ins(union mips_instruction * ip,int * frame_size)339 static inline int is_sp_move_ins(union mips_instruction *ip, int *frame_size)
340 {
341 #ifdef CONFIG_CPU_MICROMIPS
342 unsigned short tmp;
343
344 /*
345 * addiusp -imm
346 * addius5 sp,-imm
347 * addiu32 sp,sp,-imm
348 * jradiussp - NOT SUPPORTED
349 *
350 * microMIPS is not more fun...
351 */
352 if (mm_insn_16bit(ip->word >> 16)) {
353 if (ip->mm16_r3_format.opcode == mm_pool16d_op &&
354 ip->mm16_r3_format.simmediate & mm_addiusp_func) {
355 tmp = ip->mm_b0_format.simmediate >> 1;
356 tmp = ((tmp & 0x1ff) ^ 0x100) - 0x100;
357 if ((tmp + 2) < 4) /* 0x0,0x1,0x1fe,0x1ff are special */
358 tmp ^= 0x100;
359 *frame_size = -(signed short)(tmp << 2);
360 return 1;
361 }
362 if (ip->mm16_r5_format.opcode == mm_pool16d_op &&
363 ip->mm16_r5_format.rt == 29) {
364 tmp = ip->mm16_r5_format.imm >> 1;
365 *frame_size = -(signed short)(tmp & 0xf);
366 return 1;
367 }
368 return 0;
369 }
370
371 if (ip->mm_i_format.opcode == mm_addiu32_op &&
372 ip->mm_i_format.rt == 29 && ip->mm_i_format.rs == 29) {
373 *frame_size = -ip->i_format.simmediate;
374 return 1;
375 }
376 #else
377 /* addiu/daddiu sp,sp,-imm */
378 if (ip->i_format.rs != 29 || ip->i_format.rt != 29)
379 return 0;
380
381 if (ip->i_format.opcode == addiu_op ||
382 ip->i_format.opcode == daddiu_op) {
383 *frame_size = -ip->i_format.simmediate;
384 return 1;
385 }
386 #endif
387 return 0;
388 }
389
get_frame_info(struct mips_frame_info * info)390 static int get_frame_info(struct mips_frame_info *info)
391 {
392 bool is_mmips = IS_ENABLED(CONFIG_CPU_MICROMIPS);
393 union mips_instruction insn, *ip;
394 const unsigned int max_insns = 128;
395 unsigned int last_insn_size = 0;
396 unsigned int i;
397 bool saw_jump = false;
398
399 info->pc_offset = -1;
400 info->frame_size = 0;
401
402 ip = (void *)msk_isa16_mode((ulong)info->func);
403 if (!ip)
404 goto err;
405
406 for (i = 0; i < max_insns; i++) {
407 ip = (void *)ip + last_insn_size;
408
409 if (is_mmips && mm_insn_16bit(ip->halfword[0])) {
410 insn.word = ip->halfword[0] << 16;
411 last_insn_size = 2;
412 } else if (is_mmips) {
413 insn.word = ip->halfword[0] << 16 | ip->halfword[1];
414 last_insn_size = 4;
415 } else {
416 insn.word = ip->word;
417 last_insn_size = 4;
418 }
419
420 if (!info->frame_size) {
421 is_sp_move_ins(&insn, &info->frame_size);
422 continue;
423 } else if (!saw_jump && is_jump_ins(ip)) {
424 /*
425 * If we see a jump instruction, we are finished
426 * with the frame save.
427 *
428 * Some functions can have a shortcut return at
429 * the beginning of the function, so don't start
430 * looking for jump instruction until we see the
431 * frame setup.
432 *
433 * The RA save instruction can get put into the
434 * delay slot of the jump instruction, so look
435 * at the next instruction, too.
436 */
437 saw_jump = true;
438 continue;
439 }
440 if (info->pc_offset == -1 &&
441 is_ra_save_ins(&insn, &info->pc_offset))
442 break;
443 if (saw_jump)
444 break;
445 }
446 if (info->frame_size && info->pc_offset >= 0) /* nested */
447 return 0;
448 if (info->pc_offset < 0) /* leaf */
449 return 1;
450 /* prologue seems bogus... */
451 err:
452 return -1;
453 }
454
455 static struct mips_frame_info schedule_mfi __read_mostly;
456
457 #ifdef CONFIG_KALLSYMS
get___schedule_addr(void)458 static unsigned long get___schedule_addr(void)
459 {
460 return kallsyms_lookup_name("__schedule");
461 }
462 #else
get___schedule_addr(void)463 static unsigned long get___schedule_addr(void)
464 {
465 union mips_instruction *ip = (void *)schedule;
466 int max_insns = 8;
467 int i;
468
469 for (i = 0; i < max_insns; i++, ip++) {
470 if (ip->j_format.opcode == j_op)
471 return J_TARGET(ip, ip->j_format.target);
472 }
473 return 0;
474 }
475 #endif
476
frame_info_init(void)477 static int __init frame_info_init(void)
478 {
479 unsigned long size = 0;
480 #ifdef CONFIG_KALLSYMS
481 unsigned long ofs;
482 #endif
483 unsigned long addr;
484
485 addr = get___schedule_addr();
486 if (!addr)
487 addr = (unsigned long)schedule;
488
489 #ifdef CONFIG_KALLSYMS
490 kallsyms_lookup_size_offset(addr, &size, &ofs);
491 #endif
492 schedule_mfi.func = (void *)addr;
493 schedule_mfi.func_size = size;
494
495 get_frame_info(&schedule_mfi);
496
497 /*
498 * Without schedule() frame info, result given by
499 * thread_saved_pc() and get_wchan() are not reliable.
500 */
501 if (schedule_mfi.pc_offset < 0)
502 printk("Can't analyze schedule() prologue at %p\n", schedule);
503
504 return 0;
505 }
506
507 arch_initcall(frame_info_init);
508
509 /*
510 * Return saved PC of a blocked thread.
511 */
thread_saved_pc(struct task_struct * tsk)512 static unsigned long thread_saved_pc(struct task_struct *tsk)
513 {
514 struct thread_struct *t = &tsk->thread;
515
516 /* New born processes are a special case */
517 if (t->reg31 == (unsigned long) ret_from_fork)
518 return t->reg31;
519 if (schedule_mfi.pc_offset < 0)
520 return 0;
521 return ((unsigned long *)t->reg29)[schedule_mfi.pc_offset];
522 }
523
524
525 #ifdef CONFIG_KALLSYMS
526 /* generic stack unwinding function */
unwind_stack_by_address(unsigned long stack_page,unsigned long * sp,unsigned long pc,unsigned long * ra)527 unsigned long notrace unwind_stack_by_address(unsigned long stack_page,
528 unsigned long *sp,
529 unsigned long pc,
530 unsigned long *ra)
531 {
532 unsigned long low, high, irq_stack_high;
533 struct mips_frame_info info;
534 unsigned long size, ofs;
535 struct pt_regs *regs;
536 int leaf;
537
538 if (!stack_page)
539 return 0;
540
541 /*
542 * IRQ stacks start at IRQ_STACK_START
543 * task stacks at THREAD_SIZE - 32
544 */
545 low = stack_page;
546 if (!preemptible() && on_irq_stack(raw_smp_processor_id(), *sp)) {
547 high = stack_page + IRQ_STACK_START;
548 irq_stack_high = high;
549 } else {
550 high = stack_page + THREAD_SIZE - 32;
551 irq_stack_high = 0;
552 }
553
554 /*
555 * If we reached the top of the interrupt stack, start unwinding
556 * the interrupted task stack.
557 */
558 if (unlikely(*sp == irq_stack_high)) {
559 unsigned long task_sp = *(unsigned long *)*sp;
560
561 /*
562 * Check that the pointer saved in the IRQ stack head points to
563 * something within the stack of the current task
564 */
565 if (!object_is_on_stack((void *)task_sp))
566 return 0;
567
568 /*
569 * Follow pointer to tasks kernel stack frame where interrupted
570 * state was saved.
571 */
572 regs = (struct pt_regs *)task_sp;
573 pc = regs->cp0_epc;
574 if (!user_mode(regs) && __kernel_text_address(pc)) {
575 *sp = regs->regs[29];
576 *ra = regs->regs[31];
577 return pc;
578 }
579 return 0;
580 }
581 if (!kallsyms_lookup_size_offset(pc, &size, &ofs))
582 return 0;
583 /*
584 * Return ra if an exception occurred at the first instruction
585 */
586 if (unlikely(ofs == 0)) {
587 pc = *ra;
588 *ra = 0;
589 return pc;
590 }
591
592 info.func = (void *)(pc - ofs);
593 info.func_size = ofs; /* analyze from start to ofs */
594 leaf = get_frame_info(&info);
595 if (leaf < 0)
596 return 0;
597
598 if (*sp < low || *sp + info.frame_size > high)
599 return 0;
600
601 if (leaf)
602 /*
603 * For some extreme cases, get_frame_info() can
604 * consider wrongly a nested function as a leaf
605 * one. In that cases avoid to return always the
606 * same value.
607 */
608 pc = pc != *ra ? *ra : 0;
609 else
610 pc = ((unsigned long *)(*sp))[info.pc_offset];
611
612 *sp += info.frame_size;
613 *ra = 0;
614 return __kernel_text_address(pc) ? pc : 0;
615 }
616 EXPORT_SYMBOL(unwind_stack_by_address);
617
618 /* used by show_backtrace() */
unwind_stack(struct task_struct * task,unsigned long * sp,unsigned long pc,unsigned long * ra)619 unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
620 unsigned long pc, unsigned long *ra)
621 {
622 unsigned long stack_page = 0;
623 int cpu;
624
625 for_each_possible_cpu(cpu) {
626 if (on_irq_stack(cpu, *sp)) {
627 stack_page = (unsigned long)irq_stack[cpu];
628 break;
629 }
630 }
631
632 if (!stack_page)
633 stack_page = (unsigned long)task_stack_page(task);
634
635 return unwind_stack_by_address(stack_page, sp, pc, ra);
636 }
637 #endif
638
639 /*
640 * get_wchan - a maintenance nightmare^W^Wpain in the ass ...
641 */
get_wchan(struct task_struct * task)642 unsigned long get_wchan(struct task_struct *task)
643 {
644 unsigned long pc = 0;
645 #ifdef CONFIG_KALLSYMS
646 unsigned long sp;
647 unsigned long ra = 0;
648 #endif
649
650 if (!task || task == current || task->state == TASK_RUNNING)
651 goto out;
652 if (!task_stack_page(task))
653 goto out;
654
655 pc = thread_saved_pc(task);
656
657 #ifdef CONFIG_KALLSYMS
658 sp = task->thread.reg29 + schedule_mfi.frame_size;
659
660 while (in_sched_functions(pc))
661 pc = unwind_stack(task, &sp, pc, &ra);
662 #endif
663
664 out:
665 return pc;
666 }
667
mips_stack_top(void)668 unsigned long mips_stack_top(void)
669 {
670 unsigned long top = TASK_SIZE & PAGE_MASK;
671
672 if (IS_ENABLED(CONFIG_MIPS_FP_SUPPORT)) {
673 /* One page for branch delay slot "emulation" */
674 top -= PAGE_SIZE;
675 }
676
677 /* Space for the VDSO, data page & GIC user page */
678 top -= PAGE_ALIGN(current->thread.abi->vdso->size);
679 top -= PAGE_SIZE;
680 top -= mips_gic_present() ? PAGE_SIZE : 0;
681
682 /* Space for cache colour alignment */
683 if (cpu_has_dc_aliases)
684 top -= shm_align_mask + 1;
685
686 /* Space to randomize the VDSO base */
687 if (current->flags & PF_RANDOMIZE)
688 top -= VDSO_RANDOMIZE_SIZE;
689
690 return top;
691 }
692
693 /*
694 * Don't forget that the stack pointer must be aligned on a 8 bytes
695 * boundary for 32-bits ABI and 16 bytes for 64-bits ABI.
696 */
arch_align_stack(unsigned long sp)697 unsigned long arch_align_stack(unsigned long sp)
698 {
699 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
700 sp -= get_random_int() & ~PAGE_MASK;
701
702 return sp & ALMASK;
703 }
704
705 static DEFINE_PER_CPU(call_single_data_t, backtrace_csd);
706 static struct cpumask backtrace_csd_busy;
707
handle_backtrace(void * info)708 static void handle_backtrace(void *info)
709 {
710 nmi_cpu_backtrace(get_irq_regs());
711 cpumask_clear_cpu(smp_processor_id(), &backtrace_csd_busy);
712 }
713
raise_backtrace(cpumask_t * mask)714 static void raise_backtrace(cpumask_t *mask)
715 {
716 call_single_data_t *csd;
717 int cpu;
718
719 for_each_cpu(cpu, mask) {
720 /*
721 * If we previously sent an IPI to the target CPU & it hasn't
722 * cleared its bit in the busy cpumask then it didn't handle
723 * our previous IPI & it's not safe for us to reuse the
724 * call_single_data_t.
725 */
726 if (cpumask_test_and_set_cpu(cpu, &backtrace_csd_busy)) {
727 pr_warn("Unable to send backtrace IPI to CPU%u - perhaps it hung?\n",
728 cpu);
729 continue;
730 }
731
732 csd = &per_cpu(backtrace_csd, cpu);
733 csd->func = handle_backtrace;
734 smp_call_function_single_async(cpu, csd);
735 }
736 }
737
arch_trigger_cpumask_backtrace(const cpumask_t * mask,bool exclude_self)738 void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
739 {
740 nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_backtrace);
741 }
742
mips_get_process_fp_mode(struct task_struct * task)743 int mips_get_process_fp_mode(struct task_struct *task)
744 {
745 int value = 0;
746
747 if (!test_tsk_thread_flag(task, TIF_32BIT_FPREGS))
748 value |= PR_FP_MODE_FR;
749 if (test_tsk_thread_flag(task, TIF_HYBRID_FPREGS))
750 value |= PR_FP_MODE_FRE;
751
752 return value;
753 }
754
prepare_for_fp_mode_switch(void * unused)755 static long prepare_for_fp_mode_switch(void *unused)
756 {
757 /*
758 * This is icky, but we use this to simply ensure that all CPUs have
759 * context switched, regardless of whether they were previously running
760 * kernel or user code. This ensures that no CPU that a mode-switching
761 * program may execute on keeps its FPU enabled (& in the old mode)
762 * throughout the mode switch.
763 */
764 return 0;
765 }
766
mips_set_process_fp_mode(struct task_struct * task,unsigned int value)767 int mips_set_process_fp_mode(struct task_struct *task, unsigned int value)
768 {
769 const unsigned int known_bits = PR_FP_MODE_FR | PR_FP_MODE_FRE;
770 struct task_struct *t;
771 struct cpumask process_cpus;
772 int cpu;
773
774 /* If nothing to change, return right away, successfully. */
775 if (value == mips_get_process_fp_mode(task))
776 return 0;
777
778 /* Only accept a mode change if 64-bit FP enabled for o32. */
779 if (!IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT))
780 return -EOPNOTSUPP;
781
782 /* And only for o32 tasks. */
783 if (IS_ENABLED(CONFIG_64BIT) && !test_thread_flag(TIF_32BIT_REGS))
784 return -EOPNOTSUPP;
785
786 /* Check the value is valid */
787 if (value & ~known_bits)
788 return -EOPNOTSUPP;
789
790 /* Setting FRE without FR is not supported. */
791 if ((value & (PR_FP_MODE_FR | PR_FP_MODE_FRE)) == PR_FP_MODE_FRE)
792 return -EOPNOTSUPP;
793
794 /* Avoid inadvertently triggering emulation */
795 if ((value & PR_FP_MODE_FR) && raw_cpu_has_fpu &&
796 !(raw_current_cpu_data.fpu_id & MIPS_FPIR_F64))
797 return -EOPNOTSUPP;
798 if ((value & PR_FP_MODE_FRE) && raw_cpu_has_fpu && !cpu_has_fre)
799 return -EOPNOTSUPP;
800
801 /* FR = 0 not supported in MIPS R6 */
802 if (!(value & PR_FP_MODE_FR) && raw_cpu_has_fpu && cpu_has_mips_r6)
803 return -EOPNOTSUPP;
804
805 /* Indicate the new FP mode in each thread */
806 for_each_thread(task, t) {
807 /* Update desired FP register width */
808 if (value & PR_FP_MODE_FR) {
809 clear_tsk_thread_flag(t, TIF_32BIT_FPREGS);
810 } else {
811 set_tsk_thread_flag(t, TIF_32BIT_FPREGS);
812 clear_tsk_thread_flag(t, TIF_MSA_CTX_LIVE);
813 }
814
815 /* Update desired FP single layout */
816 if (value & PR_FP_MODE_FRE)
817 set_tsk_thread_flag(t, TIF_HYBRID_FPREGS);
818 else
819 clear_tsk_thread_flag(t, TIF_HYBRID_FPREGS);
820 }
821
822 /*
823 * We need to ensure that all threads in the process have switched mode
824 * before returning, in order to allow userland to not worry about
825 * races. We can do this by forcing all CPUs that any thread in the
826 * process may be running on to schedule something else - in this case
827 * prepare_for_fp_mode_switch().
828 *
829 * We begin by generating a mask of all CPUs that any thread in the
830 * process may be running on.
831 */
832 cpumask_clear(&process_cpus);
833 for_each_thread(task, t)
834 cpumask_set_cpu(task_cpu(t), &process_cpus);
835
836 /*
837 * Now we schedule prepare_for_fp_mode_switch() on each of those CPUs.
838 *
839 * The CPUs may have rescheduled already since we switched mode or
840 * generated the cpumask, but that doesn't matter. If the task in this
841 * process is scheduled out then our scheduling
842 * prepare_for_fp_mode_switch() will simply be redundant. If it's
843 * scheduled in then it will already have picked up the new FP mode
844 * whilst doing so.
845 */
846 get_online_cpus();
847 for_each_cpu_and(cpu, &process_cpus, cpu_online_mask)
848 work_on_cpu(cpu, prepare_for_fp_mode_switch, NULL);
849 put_online_cpus();
850
851 return 0;
852 }
853
854 #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32)
mips_dump_regs32(u32 * uregs,const struct pt_regs * regs)855 void mips_dump_regs32(u32 *uregs, const struct pt_regs *regs)
856 {
857 unsigned int i;
858
859 for (i = MIPS32_EF_R1; i <= MIPS32_EF_R31; i++) {
860 /* k0/k1 are copied as zero. */
861 if (i == MIPS32_EF_R26 || i == MIPS32_EF_R27)
862 uregs[i] = 0;
863 else
864 uregs[i] = regs->regs[i - MIPS32_EF_R0];
865 }
866
867 uregs[MIPS32_EF_LO] = regs->lo;
868 uregs[MIPS32_EF_HI] = regs->hi;
869 uregs[MIPS32_EF_CP0_EPC] = regs->cp0_epc;
870 uregs[MIPS32_EF_CP0_BADVADDR] = regs->cp0_badvaddr;
871 uregs[MIPS32_EF_CP0_STATUS] = regs->cp0_status;
872 uregs[MIPS32_EF_CP0_CAUSE] = regs->cp0_cause;
873 }
874 #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */
875
876 #ifdef CONFIG_64BIT
mips_dump_regs64(u64 * uregs,const struct pt_regs * regs)877 void mips_dump_regs64(u64 *uregs, const struct pt_regs *regs)
878 {
879 unsigned int i;
880
881 for (i = MIPS64_EF_R1; i <= MIPS64_EF_R31; i++) {
882 /* k0/k1 are copied as zero. */
883 if (i == MIPS64_EF_R26 || i == MIPS64_EF_R27)
884 uregs[i] = 0;
885 else
886 uregs[i] = regs->regs[i - MIPS64_EF_R0];
887 }
888
889 uregs[MIPS64_EF_LO] = regs->lo;
890 uregs[MIPS64_EF_HI] = regs->hi;
891 uregs[MIPS64_EF_CP0_EPC] = regs->cp0_epc;
892 uregs[MIPS64_EF_CP0_BADVADDR] = regs->cp0_badvaddr;
893 uregs[MIPS64_EF_CP0_STATUS] = regs->cp0_status;
894 uregs[MIPS64_EF_CP0_CAUSE] = regs->cp0_cause;
895 }
896 #endif /* CONFIG_64BIT */
897