1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (C) 2015-2018 Etnaviv Project
4 */
5
6 #ifndef __ETNAVIV_GPU_H__
7 #define __ETNAVIV_GPU_H__
8
9 #include <linux/clk.h>
10 #include <linux/regulator/consumer.h>
11
12 #include "etnaviv_cmdbuf.h"
13 #include "etnaviv_drv.h"
14
15 struct etnaviv_gem_submit;
16 struct etnaviv_vram_mapping;
17
18 struct etnaviv_chip_identity {
19 /* Chip model. */
20 u32 model;
21
22 /* Revision value.*/
23 u32 revision;
24
25 /* Supported feature fields. */
26 u32 features;
27
28 /* Supported minor feature fields. */
29 u32 minor_features0;
30 u32 minor_features1;
31 u32 minor_features2;
32 u32 minor_features3;
33 u32 minor_features4;
34 u32 minor_features5;
35 u32 minor_features6;
36 u32 minor_features7;
37 u32 minor_features8;
38 u32 minor_features9;
39 u32 minor_features10;
40 u32 minor_features11;
41
42 /* Number of streams supported. */
43 u32 stream_count;
44
45 /* Total number of temporary registers per thread. */
46 u32 register_max;
47
48 /* Maximum number of threads. */
49 u32 thread_count;
50
51 /* Number of shader cores. */
52 u32 shader_core_count;
53
54 /* Size of the vertex cache. */
55 u32 vertex_cache_size;
56
57 /* Number of entries in the vertex output buffer. */
58 u32 vertex_output_buffer_size;
59
60 /* Number of pixel pipes. */
61 u32 pixel_pipes;
62
63 /* Number of instructions. */
64 u32 instruction_count;
65
66 /* Number of constants. */
67 u32 num_constants;
68
69 /* Buffer size */
70 u32 buffer_size;
71
72 /* Number of varyings */
73 u8 varyings_count;
74 };
75
76 enum etnaviv_sec_mode {
77 ETNA_SEC_NONE = 0,
78 ETNA_SEC_KERNEL,
79 ETNA_SEC_TZ
80 };
81
82 struct etnaviv_event {
83 struct dma_fence *fence;
84 struct etnaviv_gem_submit *submit;
85
86 void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event);
87 };
88
89 struct etnaviv_cmdbuf_suballoc;
90 struct etnaviv_cmdbuf;
91
92 #define ETNA_NR_EVENTS 30
93
94 struct etnaviv_gpu {
95 struct drm_device *drm;
96 struct thermal_cooling_device *cooling;
97 struct device *dev;
98 struct mutex lock;
99 struct etnaviv_chip_identity identity;
100 enum etnaviv_sec_mode sec_mode;
101 struct etnaviv_file_private *lastctx;
102 struct workqueue_struct *wq;
103 struct drm_gpu_scheduler sched;
104
105 /* 'ring'-buffer: */
106 struct etnaviv_cmdbuf buffer;
107 int exec_state;
108
109 /* bus base address of memory */
110 u32 memory_base;
111
112 /* event management: */
113 DECLARE_BITMAP(event_bitmap, ETNA_NR_EVENTS);
114 struct etnaviv_event event[ETNA_NR_EVENTS];
115 struct completion event_free;
116 spinlock_t event_spinlock;
117
118 u32 idle_mask;
119
120 /* Fencing support */
121 struct mutex fence_lock;
122 struct idr fence_idr;
123 u32 next_fence;
124 u32 active_fence;
125 u32 completed_fence;
126 wait_queue_head_t fence_event;
127 u64 fence_context;
128 spinlock_t fence_spinlock;
129
130 /* worker for handling 'sync' points: */
131 struct work_struct sync_point_work;
132 int sync_point_event;
133
134 /* hang detection */
135 u32 hangcheck_dma_addr;
136
137 void __iomem *mmio;
138 int irq;
139
140 struct etnaviv_iommu *mmu;
141 struct etnaviv_cmdbuf_suballoc *cmdbuf_suballoc;
142
143 /* Power Control: */
144 struct clk *clk_bus;
145 struct clk *clk_reg;
146 struct clk *clk_core;
147 struct clk *clk_shader;
148
149 unsigned int freq_scale;
150 unsigned long base_rate_core;
151 unsigned long base_rate_shader;
152 };
153
gpu_write(struct etnaviv_gpu * gpu,u32 reg,u32 data)154 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data)
155 {
156 writel(data, gpu->mmio + reg);
157 }
158
gpu_read(struct etnaviv_gpu * gpu,u32 reg)159 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg)
160 {
161 return readl(gpu->mmio + reg);
162 }
163
fence_completed(struct etnaviv_gpu * gpu,u32 fence)164 static inline bool fence_completed(struct etnaviv_gpu *gpu, u32 fence)
165 {
166 return fence_after_eq(gpu->completed_fence, fence);
167 }
168
169 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value);
170
171 int etnaviv_gpu_init(struct etnaviv_gpu *gpu);
172 bool etnaviv_fill_identity_from_hwdb(struct etnaviv_gpu *gpu);
173
174 #ifdef CONFIG_DEBUG_FS
175 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m);
176 #endif
177
178 void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu);
179 void etnaviv_gpu_retire(struct etnaviv_gpu *gpu);
180 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
181 u32 fence, struct timespec *timeout);
182 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
183 struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout);
184 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit);
185 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu);
186 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu);
187 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms);
188 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch);
189
190 extern struct platform_driver etnaviv_gpu_driver;
191
192 #endif /* __ETNAVIV_GPU_H__ */
193
