1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
4 *
5 */
6
7 #include <linux/delay.h>
8 #include <linux/device.h>
9 #include <linux/dma-direction.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/interrupt.h>
12 #include <linux/list.h>
13 #include <linux/mhi.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/wait.h>
17 #include "internal.h"
18
19 /*
20 * Not all MHI state transitions are synchronous. Transitions like Linkdown,
21 * SYS_ERR, and shutdown can happen anytime asynchronously. This function will
22 * transition to a new state only if we're allowed to.
23 *
24 * Priority increases as we go down. For instance, from any state in L0, the
25 * transition can be made to states in L1, L2 and L3. A notable exception to
26 * this rule is state DISABLE. From DISABLE state we can only transition to
27 * POR state. Also, while in L2 state, user cannot jump back to previous
28 * L1 or L0 states.
29 *
30 * Valid transitions:
31 * L0: DISABLE <--> POR
32 * POR <--> POR
33 * POR -> M0 -> M2 --> M0
34 * POR -> FW_DL_ERR
35 * FW_DL_ERR <--> FW_DL_ERR
36 * M0 <--> M0
37 * M0 -> FW_DL_ERR
38 * M0 -> M3_ENTER -> M3 -> M3_EXIT --> M0
39 * L1: SYS_ERR_DETECT -> SYS_ERR_PROCESS --> POR
40 * L2: SHUTDOWN_PROCESS -> DISABLE
41 * L3: LD_ERR_FATAL_DETECT <--> LD_ERR_FATAL_DETECT
42 * LD_ERR_FATAL_DETECT -> SHUTDOWN_PROCESS
43 */
44 static struct mhi_pm_transitions const dev_state_transitions[] = {
45 /* L0 States */
46 {
47 MHI_PM_DISABLE,
48 MHI_PM_POR
49 },
50 {
51 MHI_PM_POR,
52 MHI_PM_POR | MHI_PM_DISABLE | MHI_PM_M0 |
53 MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
54 MHI_PM_LD_ERR_FATAL_DETECT | MHI_PM_FW_DL_ERR
55 },
56 {
57 MHI_PM_M0,
58 MHI_PM_M0 | MHI_PM_M2 | MHI_PM_M3_ENTER |
59 MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
60 MHI_PM_LD_ERR_FATAL_DETECT | MHI_PM_FW_DL_ERR
61 },
62 {
63 MHI_PM_M2,
64 MHI_PM_M0 | MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
65 MHI_PM_LD_ERR_FATAL_DETECT
66 },
67 {
68 MHI_PM_M3_ENTER,
69 MHI_PM_M3 | MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
70 MHI_PM_LD_ERR_FATAL_DETECT
71 },
72 {
73 MHI_PM_M3,
74 MHI_PM_M3_EXIT | MHI_PM_SYS_ERR_DETECT |
75 MHI_PM_SHUTDOWN_PROCESS | MHI_PM_LD_ERR_FATAL_DETECT
76 },
77 {
78 MHI_PM_M3_EXIT,
79 MHI_PM_M0 | MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
80 MHI_PM_LD_ERR_FATAL_DETECT
81 },
82 {
83 MHI_PM_FW_DL_ERR,
84 MHI_PM_FW_DL_ERR | MHI_PM_SYS_ERR_DETECT |
85 MHI_PM_SHUTDOWN_PROCESS | MHI_PM_LD_ERR_FATAL_DETECT
86 },
87 /* L1 States */
88 {
89 MHI_PM_SYS_ERR_DETECT,
90 MHI_PM_SYS_ERR_PROCESS | MHI_PM_SHUTDOWN_PROCESS |
91 MHI_PM_LD_ERR_FATAL_DETECT
92 },
93 {
94 MHI_PM_SYS_ERR_PROCESS,
95 MHI_PM_POR | MHI_PM_SHUTDOWN_PROCESS |
96 MHI_PM_LD_ERR_FATAL_DETECT
97 },
98 /* L2 States */
99 {
100 MHI_PM_SHUTDOWN_PROCESS,
101 MHI_PM_DISABLE | MHI_PM_LD_ERR_FATAL_DETECT
102 },
103 /* L3 States */
104 {
105 MHI_PM_LD_ERR_FATAL_DETECT,
106 MHI_PM_LD_ERR_FATAL_DETECT | MHI_PM_SHUTDOWN_PROCESS
107 },
108 };
109
mhi_tryset_pm_state(struct mhi_controller * mhi_cntrl,enum mhi_pm_state state)110 enum mhi_pm_state __must_check mhi_tryset_pm_state(struct mhi_controller *mhi_cntrl,
111 enum mhi_pm_state state)
112 {
113 unsigned long cur_state = mhi_cntrl->pm_state;
114 int index = find_last_bit(&cur_state, 32);
115
116 if (unlikely(index >= ARRAY_SIZE(dev_state_transitions)))
117 return cur_state;
118
119 if (unlikely(dev_state_transitions[index].from_state != cur_state))
120 return cur_state;
121
122 if (unlikely(!(dev_state_transitions[index].to_states & state)))
123 return cur_state;
124
125 mhi_cntrl->pm_state = state;
126 return mhi_cntrl->pm_state;
127 }
128
mhi_set_mhi_state(struct mhi_controller * mhi_cntrl,enum mhi_state state)129 void mhi_set_mhi_state(struct mhi_controller *mhi_cntrl, enum mhi_state state)
130 {
131 if (state == MHI_STATE_RESET) {
132 mhi_write_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
133 MHICTRL_RESET_MASK, MHICTRL_RESET_SHIFT, 1);
134 } else {
135 mhi_write_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
136 MHICTRL_MHISTATE_MASK,
137 MHICTRL_MHISTATE_SHIFT, state);
138 }
139 }
140
141 /* NOP for backward compatibility, host allowed to ring DB in M2 state */
mhi_toggle_dev_wake_nop(struct mhi_controller * mhi_cntrl)142 static void mhi_toggle_dev_wake_nop(struct mhi_controller *mhi_cntrl)
143 {
144 }
145
mhi_toggle_dev_wake(struct mhi_controller * mhi_cntrl)146 static void mhi_toggle_dev_wake(struct mhi_controller *mhi_cntrl)
147 {
148 mhi_cntrl->wake_get(mhi_cntrl, false);
149 mhi_cntrl->wake_put(mhi_cntrl, true);
150 }
151
152 /* Handle device ready state transition */
mhi_ready_state_transition(struct mhi_controller * mhi_cntrl)153 int mhi_ready_state_transition(struct mhi_controller *mhi_cntrl)
154 {
155 void __iomem *base = mhi_cntrl->regs;
156 struct mhi_event *mhi_event;
157 enum mhi_pm_state cur_state;
158 struct device *dev = &mhi_cntrl->mhi_dev->dev;
159 u32 reset = 1, ready = 0;
160 int ret, i;
161
162 /* Wait for RESET to be cleared and READY bit to be set by the device */
163 wait_event_timeout(mhi_cntrl->state_event,
164 MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state) ||
165 mhi_read_reg_field(mhi_cntrl, base, MHICTRL,
166 MHICTRL_RESET_MASK,
167 MHICTRL_RESET_SHIFT, &reset) ||
168 mhi_read_reg_field(mhi_cntrl, base, MHISTATUS,
169 MHISTATUS_READY_MASK,
170 MHISTATUS_READY_SHIFT, &ready) ||
171 (!reset && ready),
172 msecs_to_jiffies(mhi_cntrl->timeout_ms));
173
174 /* Check if device entered error state */
175 if (MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state)) {
176 dev_err(dev, "Device link is not accessible\n");
177 return -EIO;
178 }
179
180 /* Timeout if device did not transition to ready state */
181 if (reset || !ready) {
182 dev_err(dev, "Device Ready timeout\n");
183 return -ETIMEDOUT;
184 }
185
186 dev_dbg(dev, "Device in READY State\n");
187 write_lock_irq(&mhi_cntrl->pm_lock);
188 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_POR);
189 mhi_cntrl->dev_state = MHI_STATE_READY;
190 write_unlock_irq(&mhi_cntrl->pm_lock);
191
192 if (cur_state != MHI_PM_POR) {
193 dev_err(dev, "Error moving to state %s from %s\n",
194 to_mhi_pm_state_str(MHI_PM_POR),
195 to_mhi_pm_state_str(cur_state));
196 return -EIO;
197 }
198
199 read_lock_bh(&mhi_cntrl->pm_lock);
200 if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) {
201 dev_err(dev, "Device registers not accessible\n");
202 goto error_mmio;
203 }
204
205 /* Configure MMIO registers */
206 ret = mhi_init_mmio(mhi_cntrl);
207 if (ret) {
208 dev_err(dev, "Error configuring MMIO registers\n");
209 goto error_mmio;
210 }
211
212 /* Add elements to all SW event rings */
213 mhi_event = mhi_cntrl->mhi_event;
214 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
215 struct mhi_ring *ring = &mhi_event->ring;
216
217 /* Skip if this is an offload or HW event */
218 if (mhi_event->offload_ev || mhi_event->hw_ring)
219 continue;
220
221 ring->wp = ring->base + ring->len - ring->el_size;
222 *ring->ctxt_wp = ring->iommu_base + ring->len - ring->el_size;
223 /* Update all cores */
224 smp_wmb();
225
226 /* Ring the event ring db */
227 spin_lock_irq(&mhi_event->lock);
228 mhi_ring_er_db(mhi_event);
229 spin_unlock_irq(&mhi_event->lock);
230 }
231
232 /* Set MHI to M0 state */
233 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M0);
234 read_unlock_bh(&mhi_cntrl->pm_lock);
235
236 return 0;
237
238 error_mmio:
239 read_unlock_bh(&mhi_cntrl->pm_lock);
240
241 return -EIO;
242 }
243
mhi_pm_m0_transition(struct mhi_controller * mhi_cntrl)244 int mhi_pm_m0_transition(struct mhi_controller *mhi_cntrl)
245 {
246 enum mhi_pm_state cur_state;
247 struct mhi_chan *mhi_chan;
248 struct device *dev = &mhi_cntrl->mhi_dev->dev;
249 int i;
250
251 write_lock_irq(&mhi_cntrl->pm_lock);
252 mhi_cntrl->dev_state = MHI_STATE_M0;
253 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M0);
254 write_unlock_irq(&mhi_cntrl->pm_lock);
255 if (unlikely(cur_state != MHI_PM_M0)) {
256 dev_err(dev, "Unable to transition to M0 state\n");
257 return -EIO;
258 }
259 mhi_cntrl->M0++;
260
261 /* Wake up the device */
262 read_lock_bh(&mhi_cntrl->pm_lock);
263 mhi_cntrl->wake_get(mhi_cntrl, true);
264
265 /* Ring all event rings and CMD ring only if we're in mission mode */
266 if (MHI_IN_MISSION_MODE(mhi_cntrl->ee)) {
267 struct mhi_event *mhi_event = mhi_cntrl->mhi_event;
268 struct mhi_cmd *mhi_cmd =
269 &mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING];
270
271 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
272 if (mhi_event->offload_ev)
273 continue;
274
275 spin_lock_irq(&mhi_event->lock);
276 mhi_ring_er_db(mhi_event);
277 spin_unlock_irq(&mhi_event->lock);
278 }
279
280 /* Only ring primary cmd ring if ring is not empty */
281 spin_lock_irq(&mhi_cmd->lock);
282 if (mhi_cmd->ring.rp != mhi_cmd->ring.wp)
283 mhi_ring_cmd_db(mhi_cntrl, mhi_cmd);
284 spin_unlock_irq(&mhi_cmd->lock);
285 }
286
287 /* Ring channel DB registers */
288 mhi_chan = mhi_cntrl->mhi_chan;
289 for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) {
290 struct mhi_ring *tre_ring = &mhi_chan->tre_ring;
291
292 if (mhi_chan->db_cfg.reset_req) {
293 write_lock_irq(&mhi_chan->lock);
294 mhi_chan->db_cfg.db_mode = true;
295 write_unlock_irq(&mhi_chan->lock);
296 }
297
298 read_lock_irq(&mhi_chan->lock);
299
300 /* Only ring DB if ring is not empty */
301 if (tre_ring->base && tre_ring->wp != tre_ring->rp)
302 mhi_ring_chan_db(mhi_cntrl, mhi_chan);
303 read_unlock_irq(&mhi_chan->lock);
304 }
305
306 mhi_cntrl->wake_put(mhi_cntrl, false);
307 read_unlock_bh(&mhi_cntrl->pm_lock);
308 wake_up_all(&mhi_cntrl->state_event);
309
310 return 0;
311 }
312
313 /*
314 * After receiving the MHI state change event from the device indicating the
315 * transition to M1 state, the host can transition the device to M2 state
316 * for keeping it in low power state.
317 */
mhi_pm_m1_transition(struct mhi_controller * mhi_cntrl)318 void mhi_pm_m1_transition(struct mhi_controller *mhi_cntrl)
319 {
320 enum mhi_pm_state state;
321 struct device *dev = &mhi_cntrl->mhi_dev->dev;
322
323 write_lock_irq(&mhi_cntrl->pm_lock);
324 state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M2);
325 if (state == MHI_PM_M2) {
326 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M2);
327 mhi_cntrl->dev_state = MHI_STATE_M2;
328
329 write_unlock_irq(&mhi_cntrl->pm_lock);
330
331 mhi_cntrl->M2++;
332 wake_up_all(&mhi_cntrl->state_event);
333
334 /* If there are any pending resources, exit M2 immediately */
335 if (unlikely(atomic_read(&mhi_cntrl->pending_pkts) ||
336 atomic_read(&mhi_cntrl->dev_wake))) {
337 dev_dbg(dev,
338 "Exiting M2, pending_pkts: %d dev_wake: %d\n",
339 atomic_read(&mhi_cntrl->pending_pkts),
340 atomic_read(&mhi_cntrl->dev_wake));
341 read_lock_bh(&mhi_cntrl->pm_lock);
342 mhi_cntrl->wake_get(mhi_cntrl, true);
343 mhi_cntrl->wake_put(mhi_cntrl, true);
344 read_unlock_bh(&mhi_cntrl->pm_lock);
345 } else {
346 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_IDLE);
347 }
348 } else {
349 write_unlock_irq(&mhi_cntrl->pm_lock);
350 }
351 }
352
353 /* MHI M3 completion handler */
mhi_pm_m3_transition(struct mhi_controller * mhi_cntrl)354 int mhi_pm_m3_transition(struct mhi_controller *mhi_cntrl)
355 {
356 enum mhi_pm_state state;
357 struct device *dev = &mhi_cntrl->mhi_dev->dev;
358
359 write_lock_irq(&mhi_cntrl->pm_lock);
360 mhi_cntrl->dev_state = MHI_STATE_M3;
361 state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3);
362 write_unlock_irq(&mhi_cntrl->pm_lock);
363 if (state != MHI_PM_M3) {
364 dev_err(dev, "Unable to transition to M3 state\n");
365 return -EIO;
366 }
367
368 mhi_cntrl->M3++;
369 wake_up_all(&mhi_cntrl->state_event);
370
371 return 0;
372 }
373
374 /* Handle device Mission Mode transition */
mhi_pm_mission_mode_transition(struct mhi_controller * mhi_cntrl)375 static int mhi_pm_mission_mode_transition(struct mhi_controller *mhi_cntrl)
376 {
377 struct mhi_event *mhi_event;
378 struct device *dev = &mhi_cntrl->mhi_dev->dev;
379 int i, ret;
380
381 dev_dbg(dev, "Processing Mission Mode transition\n");
382
383 write_lock_irq(&mhi_cntrl->pm_lock);
384 if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state))
385 mhi_cntrl->ee = mhi_get_exec_env(mhi_cntrl);
386 write_unlock_irq(&mhi_cntrl->pm_lock);
387
388 if (!MHI_IN_MISSION_MODE(mhi_cntrl->ee))
389 return -EIO;
390
391 wake_up_all(&mhi_cntrl->state_event);
392
393 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_EE_MISSION_MODE);
394
395 /* Force MHI to be in M0 state before continuing */
396 ret = __mhi_device_get_sync(mhi_cntrl);
397 if (ret)
398 return ret;
399
400 read_lock_bh(&mhi_cntrl->pm_lock);
401
402 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
403 ret = -EIO;
404 goto error_mission_mode;
405 }
406
407 /* Add elements to all HW event rings */
408 mhi_event = mhi_cntrl->mhi_event;
409 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
410 struct mhi_ring *ring = &mhi_event->ring;
411
412 if (mhi_event->offload_ev || !mhi_event->hw_ring)
413 continue;
414
415 ring->wp = ring->base + ring->len - ring->el_size;
416 *ring->ctxt_wp = ring->iommu_base + ring->len - ring->el_size;
417 /* Update to all cores */
418 smp_wmb();
419
420 spin_lock_irq(&mhi_event->lock);
421 if (MHI_DB_ACCESS_VALID(mhi_cntrl))
422 mhi_ring_er_db(mhi_event);
423 spin_unlock_irq(&mhi_event->lock);
424 }
425
426 read_unlock_bh(&mhi_cntrl->pm_lock);
427
428 /*
429 * The MHI devices are only created when the client device switches its
430 * Execution Environment (EE) to either SBL or AMSS states
431 */
432 mhi_create_devices(mhi_cntrl);
433
434 read_lock_bh(&mhi_cntrl->pm_lock);
435
436 error_mission_mode:
437 mhi_cntrl->wake_put(mhi_cntrl, false);
438 read_unlock_bh(&mhi_cntrl->pm_lock);
439
440 return ret;
441 }
442
443 /* Handle SYS_ERR and Shutdown transitions */
mhi_pm_disable_transition(struct mhi_controller * mhi_cntrl,enum mhi_pm_state transition_state)444 static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl,
445 enum mhi_pm_state transition_state)
446 {
447 enum mhi_pm_state cur_state, prev_state;
448 struct mhi_event *mhi_event;
449 struct mhi_cmd_ctxt *cmd_ctxt;
450 struct mhi_cmd *mhi_cmd;
451 struct mhi_event_ctxt *er_ctxt;
452 struct device *dev = &mhi_cntrl->mhi_dev->dev;
453 int ret, i;
454
455 dev_dbg(dev, "Transitioning from PM state: %s to: %s\n",
456 to_mhi_pm_state_str(mhi_cntrl->pm_state),
457 to_mhi_pm_state_str(transition_state));
458
459 /* We must notify MHI control driver so it can clean up first */
460 if (transition_state == MHI_PM_SYS_ERR_PROCESS)
461 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_SYS_ERROR);
462
463 mutex_lock(&mhi_cntrl->pm_mutex);
464 write_lock_irq(&mhi_cntrl->pm_lock);
465 prev_state = mhi_cntrl->pm_state;
466 cur_state = mhi_tryset_pm_state(mhi_cntrl, transition_state);
467 if (cur_state == transition_state) {
468 mhi_cntrl->ee = MHI_EE_DISABLE_TRANSITION;
469 mhi_cntrl->dev_state = MHI_STATE_RESET;
470 }
471 write_unlock_irq(&mhi_cntrl->pm_lock);
472
473 /* Wake up threads waiting for state transition */
474 wake_up_all(&mhi_cntrl->state_event);
475
476 if (cur_state != transition_state) {
477 dev_err(dev, "Failed to transition to state: %s from: %s\n",
478 to_mhi_pm_state_str(transition_state),
479 to_mhi_pm_state_str(cur_state));
480 mutex_unlock(&mhi_cntrl->pm_mutex);
481 return;
482 }
483
484 /* Trigger MHI RESET so that the device will not access host memory */
485 if (MHI_REG_ACCESS_VALID(prev_state)) {
486 u32 in_reset = -1;
487 unsigned long timeout = msecs_to_jiffies(mhi_cntrl->timeout_ms);
488
489 dev_dbg(dev, "Triggering MHI Reset in device\n");
490 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET);
491
492 /* Wait for the reset bit to be cleared by the device */
493 ret = wait_event_timeout(mhi_cntrl->state_event,
494 mhi_read_reg_field(mhi_cntrl,
495 mhi_cntrl->regs,
496 MHICTRL,
497 MHICTRL_RESET_MASK,
498 MHICTRL_RESET_SHIFT,
499 &in_reset) ||
500 !in_reset, timeout);
501 if ((!ret || in_reset) && cur_state == MHI_PM_SYS_ERR_PROCESS) {
502 dev_err(dev, "Device failed to exit MHI Reset state\n");
503 mutex_unlock(&mhi_cntrl->pm_mutex);
504 return;
505 }
506
507 /*
508 * Device will clear BHI_INTVEC as a part of RESET processing,
509 * hence re-program it
510 */
511 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
512 }
513
514 dev_dbg(dev,
515 "Waiting for all pending event ring processing to complete\n");
516 mhi_event = mhi_cntrl->mhi_event;
517 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
518 if (mhi_event->offload_ev)
519 continue;
520 tasklet_kill(&mhi_event->task);
521 }
522
523 /* Release lock and wait for all pending threads to complete */
524 mutex_unlock(&mhi_cntrl->pm_mutex);
525 dev_dbg(dev, "Waiting for all pending threads to complete\n");
526 wake_up_all(&mhi_cntrl->state_event);
527
528 dev_dbg(dev, "Reset all active channels and remove MHI devices\n");
529 device_for_each_child(mhi_cntrl->cntrl_dev, NULL, mhi_destroy_device);
530
531 mutex_lock(&mhi_cntrl->pm_mutex);
532
533 WARN_ON(atomic_read(&mhi_cntrl->dev_wake));
534 WARN_ON(atomic_read(&mhi_cntrl->pending_pkts));
535
536 /* Reset the ev rings and cmd rings */
537 dev_dbg(dev, "Resetting EV CTXT and CMD CTXT\n");
538 mhi_cmd = mhi_cntrl->mhi_cmd;
539 cmd_ctxt = mhi_cntrl->mhi_ctxt->cmd_ctxt;
540 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++, cmd_ctxt++) {
541 struct mhi_ring *ring = &mhi_cmd->ring;
542
543 ring->rp = ring->base;
544 ring->wp = ring->base;
545 cmd_ctxt->rp = cmd_ctxt->rbase;
546 cmd_ctxt->wp = cmd_ctxt->rbase;
547 }
548
549 mhi_event = mhi_cntrl->mhi_event;
550 er_ctxt = mhi_cntrl->mhi_ctxt->er_ctxt;
551 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, er_ctxt++,
552 mhi_event++) {
553 struct mhi_ring *ring = &mhi_event->ring;
554
555 /* Skip offload events */
556 if (mhi_event->offload_ev)
557 continue;
558
559 ring->rp = ring->base;
560 ring->wp = ring->base;
561 er_ctxt->rp = er_ctxt->rbase;
562 er_ctxt->wp = er_ctxt->rbase;
563 }
564
565 if (cur_state == MHI_PM_SYS_ERR_PROCESS) {
566 mhi_ready_state_transition(mhi_cntrl);
567 } else {
568 /* Move to disable state */
569 write_lock_irq(&mhi_cntrl->pm_lock);
570 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_DISABLE);
571 write_unlock_irq(&mhi_cntrl->pm_lock);
572 if (unlikely(cur_state != MHI_PM_DISABLE))
573 dev_err(dev, "Error moving from PM state: %s to: %s\n",
574 to_mhi_pm_state_str(cur_state),
575 to_mhi_pm_state_str(MHI_PM_DISABLE));
576 }
577
578 dev_dbg(dev, "Exiting with PM state: %s, MHI state: %s\n",
579 to_mhi_pm_state_str(mhi_cntrl->pm_state),
580 TO_MHI_STATE_STR(mhi_cntrl->dev_state));
581
582 mutex_unlock(&mhi_cntrl->pm_mutex);
583 }
584
585 /* Queue a new work item and schedule work */
mhi_queue_state_transition(struct mhi_controller * mhi_cntrl,enum dev_st_transition state)586 int mhi_queue_state_transition(struct mhi_controller *mhi_cntrl,
587 enum dev_st_transition state)
588 {
589 struct state_transition *item = kmalloc(sizeof(*item), GFP_ATOMIC);
590 unsigned long flags;
591
592 if (!item)
593 return -ENOMEM;
594
595 item->state = state;
596 spin_lock_irqsave(&mhi_cntrl->transition_lock, flags);
597 list_add_tail(&item->node, &mhi_cntrl->transition_list);
598 spin_unlock_irqrestore(&mhi_cntrl->transition_lock, flags);
599
600 schedule_work(&mhi_cntrl->st_worker);
601
602 return 0;
603 }
604
605 /* SYS_ERR worker */
mhi_pm_sys_err_handler(struct mhi_controller * mhi_cntrl)606 void mhi_pm_sys_err_handler(struct mhi_controller *mhi_cntrl)
607 {
608 struct device *dev = &mhi_cntrl->mhi_dev->dev;
609
610 /* skip if controller supports RDDM */
611 if (mhi_cntrl->rddm_image) {
612 dev_dbg(dev, "Controller supports RDDM, skip SYS_ERROR\n");
613 return;
614 }
615
616 mhi_queue_state_transition(mhi_cntrl, DEV_ST_TRANSITION_SYS_ERR);
617 }
618
619 /* Device State Transition worker */
mhi_pm_st_worker(struct work_struct * work)620 void mhi_pm_st_worker(struct work_struct *work)
621 {
622 struct state_transition *itr, *tmp;
623 LIST_HEAD(head);
624 struct mhi_controller *mhi_cntrl = container_of(work,
625 struct mhi_controller,
626 st_worker);
627 struct device *dev = &mhi_cntrl->mhi_dev->dev;
628
629 spin_lock_irq(&mhi_cntrl->transition_lock);
630 list_splice_tail_init(&mhi_cntrl->transition_list, &head);
631 spin_unlock_irq(&mhi_cntrl->transition_lock);
632
633 list_for_each_entry_safe(itr, tmp, &head, node) {
634 list_del(&itr->node);
635 dev_dbg(dev, "Handling state transition: %s\n",
636 TO_DEV_STATE_TRANS_STR(itr->state));
637
638 switch (itr->state) {
639 case DEV_ST_TRANSITION_PBL:
640 write_lock_irq(&mhi_cntrl->pm_lock);
641 if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state))
642 mhi_cntrl->ee = mhi_get_exec_env(mhi_cntrl);
643 write_unlock_irq(&mhi_cntrl->pm_lock);
644 if (MHI_IN_PBL(mhi_cntrl->ee))
645 mhi_fw_load_handler(mhi_cntrl);
646 break;
647 case DEV_ST_TRANSITION_SBL:
648 write_lock_irq(&mhi_cntrl->pm_lock);
649 mhi_cntrl->ee = MHI_EE_SBL;
650 write_unlock_irq(&mhi_cntrl->pm_lock);
651 /*
652 * The MHI devices are only created when the client
653 * device switches its Execution Environment (EE) to
654 * either SBL or AMSS states
655 */
656 mhi_create_devices(mhi_cntrl);
657 break;
658 case DEV_ST_TRANSITION_MISSION_MODE:
659 mhi_pm_mission_mode_transition(mhi_cntrl);
660 break;
661 case DEV_ST_TRANSITION_READY:
662 mhi_ready_state_transition(mhi_cntrl);
663 break;
664 case DEV_ST_TRANSITION_SYS_ERR:
665 mhi_pm_disable_transition
666 (mhi_cntrl, MHI_PM_SYS_ERR_PROCESS);
667 break;
668 case DEV_ST_TRANSITION_DISABLE:
669 mhi_pm_disable_transition
670 (mhi_cntrl, MHI_PM_SHUTDOWN_PROCESS);
671 break;
672 default:
673 break;
674 }
675 kfree(itr);
676 }
677 }
678
mhi_pm_suspend(struct mhi_controller * mhi_cntrl)679 int mhi_pm_suspend(struct mhi_controller *mhi_cntrl)
680 {
681 struct mhi_chan *itr, *tmp;
682 struct device *dev = &mhi_cntrl->mhi_dev->dev;
683 enum mhi_pm_state new_state;
684 int ret;
685
686 if (mhi_cntrl->pm_state == MHI_PM_DISABLE)
687 return -EINVAL;
688
689 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))
690 return -EIO;
691
692 /* Return busy if there are any pending resources */
693 if (atomic_read(&mhi_cntrl->dev_wake) ||
694 atomic_read(&mhi_cntrl->pending_pkts))
695 return -EBUSY;
696
697 /* Take MHI out of M2 state */
698 read_lock_bh(&mhi_cntrl->pm_lock);
699 mhi_cntrl->wake_get(mhi_cntrl, false);
700 read_unlock_bh(&mhi_cntrl->pm_lock);
701
702 ret = wait_event_timeout(mhi_cntrl->state_event,
703 mhi_cntrl->dev_state == MHI_STATE_M0 ||
704 mhi_cntrl->dev_state == MHI_STATE_M1 ||
705 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
706 msecs_to_jiffies(mhi_cntrl->timeout_ms));
707
708 read_lock_bh(&mhi_cntrl->pm_lock);
709 mhi_cntrl->wake_put(mhi_cntrl, false);
710 read_unlock_bh(&mhi_cntrl->pm_lock);
711
712 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
713 dev_err(dev,
714 "Could not enter M0/M1 state");
715 return -EIO;
716 }
717
718 write_lock_irq(&mhi_cntrl->pm_lock);
719
720 if (atomic_read(&mhi_cntrl->dev_wake) ||
721 atomic_read(&mhi_cntrl->pending_pkts)) {
722 write_unlock_irq(&mhi_cntrl->pm_lock);
723 return -EBUSY;
724 }
725
726 dev_info(dev, "Allowing M3 transition\n");
727 new_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3_ENTER);
728 if (new_state != MHI_PM_M3_ENTER) {
729 write_unlock_irq(&mhi_cntrl->pm_lock);
730 dev_err(dev,
731 "Error setting to PM state: %s from: %s\n",
732 to_mhi_pm_state_str(MHI_PM_M3_ENTER),
733 to_mhi_pm_state_str(mhi_cntrl->pm_state));
734 return -EIO;
735 }
736
737 /* Set MHI to M3 and wait for completion */
738 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M3);
739 write_unlock_irq(&mhi_cntrl->pm_lock);
740 dev_info(dev, "Wait for M3 completion\n");
741
742 ret = wait_event_timeout(mhi_cntrl->state_event,
743 mhi_cntrl->dev_state == MHI_STATE_M3 ||
744 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
745 msecs_to_jiffies(mhi_cntrl->timeout_ms));
746
747 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
748 dev_err(dev,
749 "Did not enter M3 state, MHI state: %s, PM state: %s\n",
750 TO_MHI_STATE_STR(mhi_cntrl->dev_state),
751 to_mhi_pm_state_str(mhi_cntrl->pm_state));
752 return -EIO;
753 }
754
755 /* Notify clients about entering LPM */
756 list_for_each_entry_safe(itr, tmp, &mhi_cntrl->lpm_chans, node) {
757 mutex_lock(&itr->mutex);
758 if (itr->mhi_dev)
759 mhi_notify(itr->mhi_dev, MHI_CB_LPM_ENTER);
760 mutex_unlock(&itr->mutex);
761 }
762
763 return 0;
764 }
765 EXPORT_SYMBOL_GPL(mhi_pm_suspend);
766
mhi_pm_resume(struct mhi_controller * mhi_cntrl)767 int mhi_pm_resume(struct mhi_controller *mhi_cntrl)
768 {
769 struct mhi_chan *itr, *tmp;
770 struct device *dev = &mhi_cntrl->mhi_dev->dev;
771 enum mhi_pm_state cur_state;
772 int ret;
773
774 dev_info(dev, "Entered with PM state: %s, MHI state: %s\n",
775 to_mhi_pm_state_str(mhi_cntrl->pm_state),
776 TO_MHI_STATE_STR(mhi_cntrl->dev_state));
777
778 if (mhi_cntrl->pm_state == MHI_PM_DISABLE)
779 return 0;
780
781 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))
782 return -EIO;
783
784 /* Notify clients about exiting LPM */
785 list_for_each_entry_safe(itr, tmp, &mhi_cntrl->lpm_chans, node) {
786 mutex_lock(&itr->mutex);
787 if (itr->mhi_dev)
788 mhi_notify(itr->mhi_dev, MHI_CB_LPM_EXIT);
789 mutex_unlock(&itr->mutex);
790 }
791
792 write_lock_irq(&mhi_cntrl->pm_lock);
793 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3_EXIT);
794 if (cur_state != MHI_PM_M3_EXIT) {
795 write_unlock_irq(&mhi_cntrl->pm_lock);
796 dev_info(dev,
797 "Error setting to PM state: %s from: %s\n",
798 to_mhi_pm_state_str(MHI_PM_M3_EXIT),
799 to_mhi_pm_state_str(mhi_cntrl->pm_state));
800 return -EIO;
801 }
802
803 /* Set MHI to M0 and wait for completion */
804 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M0);
805 write_unlock_irq(&mhi_cntrl->pm_lock);
806
807 ret = wait_event_timeout(mhi_cntrl->state_event,
808 mhi_cntrl->dev_state == MHI_STATE_M0 ||
809 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
810 msecs_to_jiffies(mhi_cntrl->timeout_ms));
811
812 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
813 dev_err(dev,
814 "Did not enter M0 state, MHI state: %s, PM state: %s\n",
815 TO_MHI_STATE_STR(mhi_cntrl->dev_state),
816 to_mhi_pm_state_str(mhi_cntrl->pm_state));
817 return -EIO;
818 }
819
820 return 0;
821 }
822 EXPORT_SYMBOL_GPL(mhi_pm_resume);
823
__mhi_device_get_sync(struct mhi_controller * mhi_cntrl)824 int __mhi_device_get_sync(struct mhi_controller *mhi_cntrl)
825 {
826 int ret;
827
828 /* Wake up the device */
829 read_lock_bh(&mhi_cntrl->pm_lock);
830 mhi_cntrl->wake_get(mhi_cntrl, true);
831 if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state))
832 mhi_trigger_resume(mhi_cntrl);
833 read_unlock_bh(&mhi_cntrl->pm_lock);
834
835 ret = wait_event_timeout(mhi_cntrl->state_event,
836 mhi_cntrl->pm_state == MHI_PM_M0 ||
837 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
838 msecs_to_jiffies(mhi_cntrl->timeout_ms));
839
840 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
841 read_lock_bh(&mhi_cntrl->pm_lock);
842 mhi_cntrl->wake_put(mhi_cntrl, false);
843 read_unlock_bh(&mhi_cntrl->pm_lock);
844 return -EIO;
845 }
846
847 return 0;
848 }
849
850 /* Assert device wake db */
mhi_assert_dev_wake(struct mhi_controller * mhi_cntrl,bool force)851 static void mhi_assert_dev_wake(struct mhi_controller *mhi_cntrl, bool force)
852 {
853 unsigned long flags;
854
855 /*
856 * If force flag is set, then increment the wake count value and
857 * ring wake db
858 */
859 if (unlikely(force)) {
860 spin_lock_irqsave(&mhi_cntrl->wlock, flags);
861 atomic_inc(&mhi_cntrl->dev_wake);
862 if (MHI_WAKE_DB_FORCE_SET_VALID(mhi_cntrl->pm_state) &&
863 !mhi_cntrl->wake_set) {
864 mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 1);
865 mhi_cntrl->wake_set = true;
866 }
867 spin_unlock_irqrestore(&mhi_cntrl->wlock, flags);
868 } else {
869 /*
870 * If resources are already requested, then just increment
871 * the wake count value and return
872 */
873 if (likely(atomic_add_unless(&mhi_cntrl->dev_wake, 1, 0)))
874 return;
875
876 spin_lock_irqsave(&mhi_cntrl->wlock, flags);
877 if ((atomic_inc_return(&mhi_cntrl->dev_wake) == 1) &&
878 MHI_WAKE_DB_SET_VALID(mhi_cntrl->pm_state) &&
879 !mhi_cntrl->wake_set) {
880 mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 1);
881 mhi_cntrl->wake_set = true;
882 }
883 spin_unlock_irqrestore(&mhi_cntrl->wlock, flags);
884 }
885 }
886
887 /* De-assert device wake db */
mhi_deassert_dev_wake(struct mhi_controller * mhi_cntrl,bool override)888 static void mhi_deassert_dev_wake(struct mhi_controller *mhi_cntrl,
889 bool override)
890 {
891 unsigned long flags;
892
893 /*
894 * Only continue if there is a single resource, else just decrement
895 * and return
896 */
897 if (likely(atomic_add_unless(&mhi_cntrl->dev_wake, -1, 1)))
898 return;
899
900 spin_lock_irqsave(&mhi_cntrl->wlock, flags);
901 if ((atomic_dec_return(&mhi_cntrl->dev_wake) == 0) &&
902 MHI_WAKE_DB_CLEAR_VALID(mhi_cntrl->pm_state) && !override &&
903 mhi_cntrl->wake_set) {
904 mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 0);
905 mhi_cntrl->wake_set = false;
906 }
907 spin_unlock_irqrestore(&mhi_cntrl->wlock, flags);
908 }
909
mhi_async_power_up(struct mhi_controller * mhi_cntrl)910 int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
911 {
912 enum mhi_state state;
913 enum mhi_ee_type current_ee;
914 enum dev_st_transition next_state;
915 struct device *dev = &mhi_cntrl->mhi_dev->dev;
916 u32 val;
917 int ret;
918
919 dev_info(dev, "Requested to power ON\n");
920
921 if (mhi_cntrl->nr_irqs < 1)
922 return -EINVAL;
923
924 /* Supply default wake routines if not provided by controller driver */
925 if (!mhi_cntrl->wake_get || !mhi_cntrl->wake_put ||
926 !mhi_cntrl->wake_toggle) {
927 mhi_cntrl->wake_get = mhi_assert_dev_wake;
928 mhi_cntrl->wake_put = mhi_deassert_dev_wake;
929 mhi_cntrl->wake_toggle = (mhi_cntrl->db_access & MHI_PM_M2) ?
930 mhi_toggle_dev_wake_nop : mhi_toggle_dev_wake;
931 }
932
933 mutex_lock(&mhi_cntrl->pm_mutex);
934 mhi_cntrl->pm_state = MHI_PM_DISABLE;
935
936 if (!mhi_cntrl->pre_init) {
937 /* Setup device context */
938 ret = mhi_init_dev_ctxt(mhi_cntrl);
939 if (ret)
940 goto error_dev_ctxt;
941 }
942
943 ret = mhi_init_irq_setup(mhi_cntrl);
944 if (ret)
945 goto error_setup_irq;
946
947 /* Setup BHI offset & INTVEC */
948 write_lock_irq(&mhi_cntrl->pm_lock);
949 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIOFF, &val);
950 if (ret) {
951 write_unlock_irq(&mhi_cntrl->pm_lock);
952 goto error_bhi_offset;
953 }
954
955 mhi_cntrl->bhi = mhi_cntrl->regs + val;
956
957 /* Setup BHIE offset */
958 if (mhi_cntrl->fbc_download) {
959 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF, &val);
960 if (ret) {
961 write_unlock_irq(&mhi_cntrl->pm_lock);
962 dev_err(dev, "Error reading BHIE offset\n");
963 goto error_bhi_offset;
964 }
965
966 mhi_cntrl->bhie = mhi_cntrl->regs + val;
967 }
968
969 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
970 mhi_cntrl->pm_state = MHI_PM_POR;
971 mhi_cntrl->ee = MHI_EE_MAX;
972 current_ee = mhi_get_exec_env(mhi_cntrl);
973 write_unlock_irq(&mhi_cntrl->pm_lock);
974
975 /* Confirm that the device is in valid exec env */
976 if (!MHI_IN_PBL(current_ee) && current_ee != MHI_EE_AMSS) {
977 dev_err(dev, "Not a valid EE for power on\n");
978 ret = -EIO;
979 goto error_bhi_offset;
980 }
981
982 state = mhi_get_mhi_state(mhi_cntrl);
983 if (state == MHI_STATE_SYS_ERR) {
984 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET);
985 ret = wait_event_timeout(mhi_cntrl->state_event,
986 MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state) ||
987 mhi_read_reg_field(mhi_cntrl,
988 mhi_cntrl->regs,
989 MHICTRL,
990 MHICTRL_RESET_MASK,
991 MHICTRL_RESET_SHIFT,
992 &val) ||
993 !val,
994 msecs_to_jiffies(mhi_cntrl->timeout_ms));
995 if (ret) {
996 ret = -EIO;
997 dev_info(dev, "Failed to reset MHI due to syserr state\n");
998 goto error_bhi_offset;
999 }
1000
1001 /*
1002 * device cleares INTVEC as part of RESET processing,
1003 * re-program it
1004 */
1005 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
1006 }
1007
1008 /* Transition to next state */
1009 next_state = MHI_IN_PBL(current_ee) ?
1010 DEV_ST_TRANSITION_PBL : DEV_ST_TRANSITION_READY;
1011
1012 mhi_queue_state_transition(mhi_cntrl, next_state);
1013
1014 mutex_unlock(&mhi_cntrl->pm_mutex);
1015
1016 dev_info(dev, "Power on setup success\n");
1017
1018 return 0;
1019
1020 error_bhi_offset:
1021 mhi_deinit_free_irq(mhi_cntrl);
1022
1023 error_setup_irq:
1024 if (!mhi_cntrl->pre_init)
1025 mhi_deinit_dev_ctxt(mhi_cntrl);
1026
1027 error_dev_ctxt:
1028 mutex_unlock(&mhi_cntrl->pm_mutex);
1029
1030 return ret;
1031 }
1032 EXPORT_SYMBOL_GPL(mhi_async_power_up);
1033
mhi_power_down(struct mhi_controller * mhi_cntrl,bool graceful)1034 void mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful)
1035 {
1036 enum mhi_pm_state cur_state;
1037 struct device *dev = &mhi_cntrl->mhi_dev->dev;
1038
1039 /* If it's not a graceful shutdown, force MHI to linkdown state */
1040 if (!graceful) {
1041 mutex_lock(&mhi_cntrl->pm_mutex);
1042 write_lock_irq(&mhi_cntrl->pm_lock);
1043 cur_state = mhi_tryset_pm_state(mhi_cntrl,
1044 MHI_PM_LD_ERR_FATAL_DETECT);
1045 write_unlock_irq(&mhi_cntrl->pm_lock);
1046 mutex_unlock(&mhi_cntrl->pm_mutex);
1047 if (cur_state != MHI_PM_LD_ERR_FATAL_DETECT)
1048 dev_dbg(dev, "Failed to move to state: %s from: %s\n",
1049 to_mhi_pm_state_str(MHI_PM_LD_ERR_FATAL_DETECT),
1050 to_mhi_pm_state_str(mhi_cntrl->pm_state));
1051 }
1052
1053 mhi_queue_state_transition(mhi_cntrl, DEV_ST_TRANSITION_DISABLE);
1054
1055 /* Wait for shutdown to complete */
1056 flush_work(&mhi_cntrl->st_worker);
1057
1058 mhi_deinit_free_irq(mhi_cntrl);
1059
1060 if (!mhi_cntrl->pre_init) {
1061 /* Free all allocated resources */
1062 if (mhi_cntrl->fbc_image) {
1063 mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->fbc_image);
1064 mhi_cntrl->fbc_image = NULL;
1065 }
1066 mhi_deinit_dev_ctxt(mhi_cntrl);
1067 }
1068 }
1069 EXPORT_SYMBOL_GPL(mhi_power_down);
1070
mhi_sync_power_up(struct mhi_controller * mhi_cntrl)1071 int mhi_sync_power_up(struct mhi_controller *mhi_cntrl)
1072 {
1073 int ret = mhi_async_power_up(mhi_cntrl);
1074
1075 if (ret)
1076 return ret;
1077
1078 wait_event_timeout(mhi_cntrl->state_event,
1079 MHI_IN_MISSION_MODE(mhi_cntrl->ee) ||
1080 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
1081 msecs_to_jiffies(mhi_cntrl->timeout_ms));
1082
1083 ret = (MHI_IN_MISSION_MODE(mhi_cntrl->ee)) ? 0 : -ETIMEDOUT;
1084 if (ret)
1085 mhi_power_down(mhi_cntrl, false);
1086
1087 return ret;
1088 }
1089 EXPORT_SYMBOL(mhi_sync_power_up);
1090
mhi_force_rddm_mode(struct mhi_controller * mhi_cntrl)1091 int mhi_force_rddm_mode(struct mhi_controller *mhi_cntrl)
1092 {
1093 struct device *dev = &mhi_cntrl->mhi_dev->dev;
1094 int ret;
1095
1096 /* Check if device is already in RDDM */
1097 if (mhi_cntrl->ee == MHI_EE_RDDM)
1098 return 0;
1099
1100 dev_dbg(dev, "Triggering SYS_ERR to force RDDM state\n");
1101 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_SYS_ERR);
1102
1103 /* Wait for RDDM event */
1104 ret = wait_event_timeout(mhi_cntrl->state_event,
1105 mhi_cntrl->ee == MHI_EE_RDDM,
1106 msecs_to_jiffies(mhi_cntrl->timeout_ms));
1107 ret = ret ? 0 : -EIO;
1108
1109 return ret;
1110 }
1111 EXPORT_SYMBOL_GPL(mhi_force_rddm_mode);
1112
mhi_device_get(struct mhi_device * mhi_dev)1113 void mhi_device_get(struct mhi_device *mhi_dev)
1114 {
1115 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1116
1117 mhi_dev->dev_wake++;
1118 read_lock_bh(&mhi_cntrl->pm_lock);
1119 if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state))
1120 mhi_trigger_resume(mhi_cntrl);
1121
1122 mhi_cntrl->wake_get(mhi_cntrl, true);
1123 read_unlock_bh(&mhi_cntrl->pm_lock);
1124 }
1125 EXPORT_SYMBOL_GPL(mhi_device_get);
1126
mhi_device_get_sync(struct mhi_device * mhi_dev)1127 int mhi_device_get_sync(struct mhi_device *mhi_dev)
1128 {
1129 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1130 int ret;
1131
1132 ret = __mhi_device_get_sync(mhi_cntrl);
1133 if (!ret)
1134 mhi_dev->dev_wake++;
1135
1136 return ret;
1137 }
1138 EXPORT_SYMBOL_GPL(mhi_device_get_sync);
1139
mhi_device_put(struct mhi_device * mhi_dev)1140 void mhi_device_put(struct mhi_device *mhi_dev)
1141 {
1142 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1143
1144 mhi_dev->dev_wake--;
1145 read_lock_bh(&mhi_cntrl->pm_lock);
1146 if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state))
1147 mhi_trigger_resume(mhi_cntrl);
1148
1149 mhi_cntrl->wake_put(mhi_cntrl, false);
1150 read_unlock_bh(&mhi_cntrl->pm_lock);
1151 }
1152 EXPORT_SYMBOL_GPL(mhi_device_put);
1153
