1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright 2010 Matt Turner.
4 * Copyright 2012 Red Hat
5 *
6 * Authors: Matthew Garrett
7 * Matt Turner
8 * Dave Airlie
9 */
10
11 #include <linux/delay.h>
12
13 #include <drm/drm_atomic_helper.h>
14 #include <drm/drm_atomic_state_helper.h>
15 #include <drm/drm_crtc_helper.h>
16 #include <drm/drm_damage_helper.h>
17 #include <drm/drm_format_helper.h>
18 #include <drm/drm_fourcc.h>
19 #include <drm/drm_gem_framebuffer_helper.h>
20 #include <drm/drm_plane_helper.h>
21 #include <drm/drm_print.h>
22 #include <drm/drm_probe_helper.h>
23 #include <drm/drm_simple_kms_helper.h>
24
25 #include "mgag200_drv.h"
26
27 #define MGAG200_LUT_SIZE 256
28
29 /*
30 * This file contains setup code for the CRTC.
31 */
32
mga_crtc_load_lut(struct drm_crtc * crtc)33 static void mga_crtc_load_lut(struct drm_crtc *crtc)
34 {
35 struct drm_device *dev = crtc->dev;
36 struct mga_device *mdev = to_mga_device(dev);
37 struct drm_framebuffer *fb;
38 u16 *r_ptr, *g_ptr, *b_ptr;
39 int i;
40
41 if (!crtc->enabled)
42 return;
43
44 if (!mdev->display_pipe.plane.state)
45 return;
46
47 fb = mdev->display_pipe.plane.state->fb;
48
49 r_ptr = crtc->gamma_store;
50 g_ptr = r_ptr + crtc->gamma_size;
51 b_ptr = g_ptr + crtc->gamma_size;
52
53 WREG8(DAC_INDEX + MGA1064_INDEX, 0);
54
55 if (fb && fb->format->cpp[0] * 8 == 16) {
56 int inc = (fb->format->depth == 15) ? 8 : 4;
57 u8 r, b;
58 for (i = 0; i < MGAG200_LUT_SIZE; i += inc) {
59 if (fb->format->depth == 16) {
60 if (i > (MGAG200_LUT_SIZE >> 1)) {
61 r = b = 0;
62 } else {
63 r = *r_ptr++ >> 8;
64 b = *b_ptr++ >> 8;
65 r_ptr++;
66 b_ptr++;
67 }
68 } else {
69 r = *r_ptr++ >> 8;
70 b = *b_ptr++ >> 8;
71 }
72 /* VGA registers */
73 WREG8(DAC_INDEX + MGA1064_COL_PAL, r);
74 WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8);
75 WREG8(DAC_INDEX + MGA1064_COL_PAL, b);
76 }
77 return;
78 }
79 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
80 /* VGA registers */
81 WREG8(DAC_INDEX + MGA1064_COL_PAL, *r_ptr++ >> 8);
82 WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8);
83 WREG8(DAC_INDEX + MGA1064_COL_PAL, *b_ptr++ >> 8);
84 }
85 }
86
mga_wait_vsync(struct mga_device * mdev)87 static inline void mga_wait_vsync(struct mga_device *mdev)
88 {
89 unsigned long timeout = jiffies + HZ/10;
90 unsigned int status = 0;
91
92 do {
93 status = RREG32(MGAREG_Status);
94 } while ((status & 0x08) && time_before(jiffies, timeout));
95 timeout = jiffies + HZ/10;
96 status = 0;
97 do {
98 status = RREG32(MGAREG_Status);
99 } while (!(status & 0x08) && time_before(jiffies, timeout));
100 }
101
mga_wait_busy(struct mga_device * mdev)102 static inline void mga_wait_busy(struct mga_device *mdev)
103 {
104 unsigned long timeout = jiffies + HZ;
105 unsigned int status = 0;
106 do {
107 status = RREG8(MGAREG_Status + 2);
108 } while ((status & 0x01) && time_before(jiffies, timeout));
109 }
110
111 /*
112 * PLL setup
113 */
114
mgag200_g200_set_plls(struct mga_device * mdev,long clock)115 static int mgag200_g200_set_plls(struct mga_device *mdev, long clock)
116 {
117 struct drm_device *dev = &mdev->base;
118 const int post_div_max = 7;
119 const int in_div_min = 1;
120 const int in_div_max = 6;
121 const int feed_div_min = 7;
122 const int feed_div_max = 127;
123 u8 testm, testn;
124 u8 n = 0, m = 0, p, s;
125 long f_vco;
126 long computed;
127 long delta, tmp_delta;
128 long ref_clk = mdev->model.g200.ref_clk;
129 long p_clk_min = mdev->model.g200.pclk_min;
130 long p_clk_max = mdev->model.g200.pclk_max;
131
132 if (clock > p_clk_max) {
133 drm_err(dev, "Pixel Clock %ld too high\n", clock);
134 return 1;
135 }
136
137 if (clock < p_clk_min >> 3)
138 clock = p_clk_min >> 3;
139
140 f_vco = clock;
141 for (p = 0;
142 p <= post_div_max && f_vco < p_clk_min;
143 p = (p << 1) + 1, f_vco <<= 1)
144 ;
145
146 delta = clock;
147
148 for (testm = in_div_min; testm <= in_div_max; testm++) {
149 for (testn = feed_div_min; testn <= feed_div_max; testn++) {
150 computed = ref_clk * (testn + 1) / (testm + 1);
151 if (computed < f_vco)
152 tmp_delta = f_vco - computed;
153 else
154 tmp_delta = computed - f_vco;
155 if (tmp_delta < delta) {
156 delta = tmp_delta;
157 m = testm;
158 n = testn;
159 }
160 }
161 }
162 f_vco = ref_clk * (n + 1) / (m + 1);
163 if (f_vco < 100000)
164 s = 0;
165 else if (f_vco < 140000)
166 s = 1;
167 else if (f_vco < 180000)
168 s = 2;
169 else
170 s = 3;
171
172 drm_dbg_kms(dev, "clock: %ld vco: %ld m: %d n: %d p: %d s: %d\n",
173 clock, f_vco, m, n, p, s);
174
175 WREG_DAC(MGA1064_PIX_PLLC_M, m);
176 WREG_DAC(MGA1064_PIX_PLLC_N, n);
177 WREG_DAC(MGA1064_PIX_PLLC_P, (p | (s << 3)));
178
179 return 0;
180 }
181
182 #define P_ARRAY_SIZE 9
183
mga_g200se_set_plls(struct mga_device * mdev,long clock)184 static int mga_g200se_set_plls(struct mga_device *mdev, long clock)
185 {
186 u32 unique_rev_id = mdev->model.g200se.unique_rev_id;
187 unsigned int vcomax, vcomin, pllreffreq;
188 unsigned int delta, tmpdelta, permitteddelta;
189 unsigned int testp, testm, testn;
190 unsigned int p, m, n;
191 unsigned int computed;
192 unsigned int pvalues_e4[P_ARRAY_SIZE] = {16, 14, 12, 10, 8, 6, 4, 2, 1};
193 unsigned int fvv;
194 unsigned int i;
195
196 if (unique_rev_id <= 0x03) {
197
198 m = n = p = 0;
199 vcomax = 320000;
200 vcomin = 160000;
201 pllreffreq = 25000;
202
203 delta = 0xffffffff;
204 permitteddelta = clock * 5 / 1000;
205
206 for (testp = 8; testp > 0; testp /= 2) {
207 if (clock * testp > vcomax)
208 continue;
209 if (clock * testp < vcomin)
210 continue;
211
212 for (testn = 17; testn < 256; testn++) {
213 for (testm = 1; testm < 32; testm++) {
214 computed = (pllreffreq * testn) /
215 (testm * testp);
216 if (computed > clock)
217 tmpdelta = computed - clock;
218 else
219 tmpdelta = clock - computed;
220 if (tmpdelta < delta) {
221 delta = tmpdelta;
222 m = testm - 1;
223 n = testn - 1;
224 p = testp - 1;
225 }
226 }
227 }
228 }
229 } else {
230
231
232 m = n = p = 0;
233 vcomax = 1600000;
234 vcomin = 800000;
235 pllreffreq = 25000;
236
237 if (clock < 25000)
238 clock = 25000;
239
240 clock = clock * 2;
241
242 delta = 0xFFFFFFFF;
243 /* Permited delta is 0.5% as VESA Specification */
244 permitteddelta = clock * 5 / 1000;
245
246 for (i = 0 ; i < P_ARRAY_SIZE ; i++) {
247 testp = pvalues_e4[i];
248
249 if ((clock * testp) > vcomax)
250 continue;
251 if ((clock * testp) < vcomin)
252 continue;
253
254 for (testn = 50; testn <= 256; testn++) {
255 for (testm = 1; testm <= 32; testm++) {
256 computed = (pllreffreq * testn) /
257 (testm * testp);
258 if (computed > clock)
259 tmpdelta = computed - clock;
260 else
261 tmpdelta = clock - computed;
262
263 if (tmpdelta < delta) {
264 delta = tmpdelta;
265 m = testm - 1;
266 n = testn - 1;
267 p = testp - 1;
268 }
269 }
270 }
271 }
272
273 fvv = pllreffreq * (n + 1) / (m + 1);
274 fvv = (fvv - 800000) / 50000;
275
276 if (fvv > 15)
277 fvv = 15;
278
279 p |= (fvv << 4);
280 m |= 0x80;
281
282 clock = clock / 2;
283 }
284
285 if (delta > permitteddelta) {
286 pr_warn("PLL delta too large\n");
287 return 1;
288 }
289
290 WREG_DAC(MGA1064_PIX_PLLC_M, m);
291 WREG_DAC(MGA1064_PIX_PLLC_N, n);
292 WREG_DAC(MGA1064_PIX_PLLC_P, p);
293
294 if (unique_rev_id >= 0x04) {
295 WREG_DAC(0x1a, 0x09);
296 msleep(20);
297 WREG_DAC(0x1a, 0x01);
298
299 }
300
301 return 0;
302 }
303
mga_g200wb_set_plls(struct mga_device * mdev,long clock)304 static int mga_g200wb_set_plls(struct mga_device *mdev, long clock)
305 {
306 unsigned int vcomax, vcomin, pllreffreq;
307 unsigned int delta, tmpdelta;
308 unsigned int testp, testm, testn, testp2;
309 unsigned int p, m, n;
310 unsigned int computed;
311 int i, j, tmpcount, vcount;
312 bool pll_locked = false;
313 u8 tmp;
314
315 m = n = p = 0;
316
317 delta = 0xffffffff;
318
319 if (mdev->type == G200_EW3) {
320
321 vcomax = 800000;
322 vcomin = 400000;
323 pllreffreq = 25000;
324
325 for (testp = 1; testp < 8; testp++) {
326 for (testp2 = 1; testp2 < 8; testp2++) {
327 if (testp < testp2)
328 continue;
329 if ((clock * testp * testp2) > vcomax)
330 continue;
331 if ((clock * testp * testp2) < vcomin)
332 continue;
333 for (testm = 1; testm < 26; testm++) {
334 for (testn = 32; testn < 2048 ; testn++) {
335 computed = (pllreffreq * testn) /
336 (testm * testp * testp2);
337 if (computed > clock)
338 tmpdelta = computed - clock;
339 else
340 tmpdelta = clock - computed;
341 if (tmpdelta < delta) {
342 delta = tmpdelta;
343 m = ((testn & 0x100) >> 1) |
344 (testm);
345 n = (testn & 0xFF);
346 p = ((testn & 0x600) >> 3) |
347 (testp2 << 3) |
348 (testp);
349 }
350 }
351 }
352 }
353 }
354 } else {
355
356 vcomax = 550000;
357 vcomin = 150000;
358 pllreffreq = 48000;
359
360 for (testp = 1; testp < 9; testp++) {
361 if (clock * testp > vcomax)
362 continue;
363 if (clock * testp < vcomin)
364 continue;
365
366 for (testm = 1; testm < 17; testm++) {
367 for (testn = 1; testn < 151; testn++) {
368 computed = (pllreffreq * testn) /
369 (testm * testp);
370 if (computed > clock)
371 tmpdelta = computed - clock;
372 else
373 tmpdelta = clock - computed;
374 if (tmpdelta < delta) {
375 delta = tmpdelta;
376 n = testn - 1;
377 m = (testm - 1) |
378 ((n >> 1) & 0x80);
379 p = testp - 1;
380 }
381 }
382 }
383 }
384 }
385
386 for (i = 0; i <= 32 && pll_locked == false; i++) {
387 if (i > 0) {
388 WREG8(MGAREG_CRTC_INDEX, 0x1e);
389 tmp = RREG8(MGAREG_CRTC_DATA);
390 if (tmp < 0xff)
391 WREG8(MGAREG_CRTC_DATA, tmp+1);
392 }
393
394 /* set pixclkdis to 1 */
395 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
396 tmp = RREG8(DAC_DATA);
397 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
398 WREG8(DAC_DATA, tmp);
399
400 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
401 tmp = RREG8(DAC_DATA);
402 tmp |= MGA1064_REMHEADCTL_CLKDIS;
403 WREG8(DAC_DATA, tmp);
404
405 /* select PLL Set C */
406 tmp = RREG8(MGAREG_MEM_MISC_READ);
407 tmp |= 0x3 << 2;
408 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
409
410 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
411 tmp = RREG8(DAC_DATA);
412 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80;
413 WREG8(DAC_DATA, tmp);
414
415 udelay(500);
416
417 /* reset the PLL */
418 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
419 tmp = RREG8(DAC_DATA);
420 tmp &= ~0x04;
421 WREG8(DAC_DATA, tmp);
422
423 udelay(50);
424
425 /* program pixel pll register */
426 WREG_DAC(MGA1064_WB_PIX_PLLC_N, n);
427 WREG_DAC(MGA1064_WB_PIX_PLLC_M, m);
428 WREG_DAC(MGA1064_WB_PIX_PLLC_P, p);
429
430 udelay(50);
431
432 /* turn pll on */
433 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
434 tmp = RREG8(DAC_DATA);
435 tmp |= 0x04;
436 WREG_DAC(MGA1064_VREF_CTL, tmp);
437
438 udelay(500);
439
440 /* select the pixel pll */
441 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
442 tmp = RREG8(DAC_DATA);
443 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
444 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
445 WREG8(DAC_DATA, tmp);
446
447 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
448 tmp = RREG8(DAC_DATA);
449 tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK;
450 tmp |= MGA1064_REMHEADCTL_CLKSL_PLL;
451 WREG8(DAC_DATA, tmp);
452
453 /* reset dotclock rate bit */
454 WREG8(MGAREG_SEQ_INDEX, 1);
455 tmp = RREG8(MGAREG_SEQ_DATA);
456 tmp &= ~0x8;
457 WREG8(MGAREG_SEQ_DATA, tmp);
458
459 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
460 tmp = RREG8(DAC_DATA);
461 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
462 WREG8(DAC_DATA, tmp);
463
464 vcount = RREG8(MGAREG_VCOUNT);
465
466 for (j = 0; j < 30 && pll_locked == false; j++) {
467 tmpcount = RREG8(MGAREG_VCOUNT);
468 if (tmpcount < vcount)
469 vcount = 0;
470 if ((tmpcount - vcount) > 2)
471 pll_locked = true;
472 else
473 udelay(5);
474 }
475 }
476 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
477 tmp = RREG8(DAC_DATA);
478 tmp &= ~MGA1064_REMHEADCTL_CLKDIS;
479 WREG_DAC(MGA1064_REMHEADCTL, tmp);
480 return 0;
481 }
482
mga_g200ev_set_plls(struct mga_device * mdev,long clock)483 static int mga_g200ev_set_plls(struct mga_device *mdev, long clock)
484 {
485 unsigned int vcomax, vcomin, pllreffreq;
486 unsigned int delta, tmpdelta;
487 unsigned int testp, testm, testn;
488 unsigned int p, m, n;
489 unsigned int computed;
490 u8 tmp;
491
492 m = n = p = 0;
493 vcomax = 550000;
494 vcomin = 150000;
495 pllreffreq = 50000;
496
497 delta = 0xffffffff;
498
499 for (testp = 16; testp > 0; testp--) {
500 if (clock * testp > vcomax)
501 continue;
502 if (clock * testp < vcomin)
503 continue;
504
505 for (testn = 1; testn < 257; testn++) {
506 for (testm = 1; testm < 17; testm++) {
507 computed = (pllreffreq * testn) /
508 (testm * testp);
509 if (computed > clock)
510 tmpdelta = computed - clock;
511 else
512 tmpdelta = clock - computed;
513 if (tmpdelta < delta) {
514 delta = tmpdelta;
515 n = testn - 1;
516 m = testm - 1;
517 p = testp - 1;
518 }
519 }
520 }
521 }
522
523 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
524 tmp = RREG8(DAC_DATA);
525 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
526 WREG8(DAC_DATA, tmp);
527
528 tmp = RREG8(MGAREG_MEM_MISC_READ);
529 tmp |= 0x3 << 2;
530 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
531
532 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
533 tmp = RREG8(DAC_DATA);
534 WREG8(DAC_DATA, tmp & ~0x40);
535
536 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
537 tmp = RREG8(DAC_DATA);
538 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
539 WREG8(DAC_DATA, tmp);
540
541 WREG_DAC(MGA1064_EV_PIX_PLLC_M, m);
542 WREG_DAC(MGA1064_EV_PIX_PLLC_N, n);
543 WREG_DAC(MGA1064_EV_PIX_PLLC_P, p);
544
545 udelay(50);
546
547 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
548 tmp = RREG8(DAC_DATA);
549 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
550 WREG8(DAC_DATA, tmp);
551
552 udelay(500);
553
554 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
555 tmp = RREG8(DAC_DATA);
556 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
557 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
558 WREG8(DAC_DATA, tmp);
559
560 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
561 tmp = RREG8(DAC_DATA);
562 WREG8(DAC_DATA, tmp | 0x40);
563
564 tmp = RREG8(MGAREG_MEM_MISC_READ);
565 tmp |= (0x3 << 2);
566 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
567
568 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
569 tmp = RREG8(DAC_DATA);
570 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
571 WREG8(DAC_DATA, tmp);
572
573 return 0;
574 }
575
mga_g200eh_set_plls(struct mga_device * mdev,long clock)576 static int mga_g200eh_set_plls(struct mga_device *mdev, long clock)
577 {
578 unsigned int vcomax, vcomin, pllreffreq;
579 unsigned int delta, tmpdelta;
580 unsigned int testp, testm, testn;
581 unsigned int p, m, n;
582 unsigned int computed;
583 int i, j, tmpcount, vcount;
584 u8 tmp;
585 bool pll_locked = false;
586
587 m = n = p = 0;
588
589 if (mdev->type == G200_EH3) {
590 vcomax = 3000000;
591 vcomin = 1500000;
592 pllreffreq = 25000;
593
594 delta = 0xffffffff;
595
596 testp = 0;
597
598 for (testm = 150; testm >= 6; testm--) {
599 if (clock * testm > vcomax)
600 continue;
601 if (clock * testm < vcomin)
602 continue;
603 for (testn = 120; testn >= 60; testn--) {
604 computed = (pllreffreq * testn) / testm;
605 if (computed > clock)
606 tmpdelta = computed - clock;
607 else
608 tmpdelta = clock - computed;
609 if (tmpdelta < delta) {
610 delta = tmpdelta;
611 n = testn;
612 m = testm;
613 p = testp;
614 }
615 if (delta == 0)
616 break;
617 }
618 if (delta == 0)
619 break;
620 }
621 } else {
622
623 vcomax = 800000;
624 vcomin = 400000;
625 pllreffreq = 33333;
626
627 delta = 0xffffffff;
628
629 for (testp = 16; testp > 0; testp >>= 1) {
630 if (clock * testp > vcomax)
631 continue;
632 if (clock * testp < vcomin)
633 continue;
634
635 for (testm = 1; testm < 33; testm++) {
636 for (testn = 17; testn < 257; testn++) {
637 computed = (pllreffreq * testn) /
638 (testm * testp);
639 if (computed > clock)
640 tmpdelta = computed - clock;
641 else
642 tmpdelta = clock - computed;
643 if (tmpdelta < delta) {
644 delta = tmpdelta;
645 n = testn - 1;
646 m = (testm - 1);
647 p = testp - 1;
648 }
649 if ((clock * testp) >= 600000)
650 p |= 0x80;
651 }
652 }
653 }
654 }
655 for (i = 0; i <= 32 && pll_locked == false; i++) {
656 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
657 tmp = RREG8(DAC_DATA);
658 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
659 WREG8(DAC_DATA, tmp);
660
661 tmp = RREG8(MGAREG_MEM_MISC_READ);
662 tmp |= 0x3 << 2;
663 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
664
665 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
666 tmp = RREG8(DAC_DATA);
667 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
668 WREG8(DAC_DATA, tmp);
669
670 udelay(500);
671
672 WREG_DAC(MGA1064_EH_PIX_PLLC_M, m);
673 WREG_DAC(MGA1064_EH_PIX_PLLC_N, n);
674 WREG_DAC(MGA1064_EH_PIX_PLLC_P, p);
675
676 udelay(500);
677
678 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
679 tmp = RREG8(DAC_DATA);
680 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
681 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
682 WREG8(DAC_DATA, tmp);
683
684 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
685 tmp = RREG8(DAC_DATA);
686 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
687 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
688 WREG8(DAC_DATA, tmp);
689
690 vcount = RREG8(MGAREG_VCOUNT);
691
692 for (j = 0; j < 30 && pll_locked == false; j++) {
693 tmpcount = RREG8(MGAREG_VCOUNT);
694 if (tmpcount < vcount)
695 vcount = 0;
696 if ((tmpcount - vcount) > 2)
697 pll_locked = true;
698 else
699 udelay(5);
700 }
701 }
702
703 return 0;
704 }
705
mga_g200er_set_plls(struct mga_device * mdev,long clock)706 static int mga_g200er_set_plls(struct mga_device *mdev, long clock)
707 {
708 unsigned int vcomax, vcomin, pllreffreq;
709 unsigned int delta, tmpdelta;
710 int testr, testn, testm, testo;
711 unsigned int p, m, n;
712 unsigned int computed, vco;
713 int tmp;
714 const unsigned int m_div_val[] = { 1, 2, 4, 8 };
715
716 m = n = p = 0;
717 vcomax = 1488000;
718 vcomin = 1056000;
719 pllreffreq = 48000;
720
721 delta = 0xffffffff;
722
723 for (testr = 0; testr < 4; testr++) {
724 if (delta == 0)
725 break;
726 for (testn = 5; testn < 129; testn++) {
727 if (delta == 0)
728 break;
729 for (testm = 3; testm >= 0; testm--) {
730 if (delta == 0)
731 break;
732 for (testo = 5; testo < 33; testo++) {
733 vco = pllreffreq * (testn + 1) /
734 (testr + 1);
735 if (vco < vcomin)
736 continue;
737 if (vco > vcomax)
738 continue;
739 computed = vco / (m_div_val[testm] * (testo + 1));
740 if (computed > clock)
741 tmpdelta = computed - clock;
742 else
743 tmpdelta = clock - computed;
744 if (tmpdelta < delta) {
745 delta = tmpdelta;
746 m = testm | (testo << 3);
747 n = testn;
748 p = testr | (testr << 3);
749 }
750 }
751 }
752 }
753 }
754
755 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
756 tmp = RREG8(DAC_DATA);
757 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
758 WREG8(DAC_DATA, tmp);
759
760 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
761 tmp = RREG8(DAC_DATA);
762 tmp |= MGA1064_REMHEADCTL_CLKDIS;
763 WREG8(DAC_DATA, tmp);
764
765 tmp = RREG8(MGAREG_MEM_MISC_READ);
766 tmp |= (0x3<<2) | 0xc0;
767 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
768
769 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
770 tmp = RREG8(DAC_DATA);
771 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
772 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
773 WREG8(DAC_DATA, tmp);
774
775 udelay(500);
776
777 WREG_DAC(MGA1064_ER_PIX_PLLC_N, n);
778 WREG_DAC(MGA1064_ER_PIX_PLLC_M, m);
779 WREG_DAC(MGA1064_ER_PIX_PLLC_P, p);
780
781 udelay(50);
782
783 return 0;
784 }
785
mgag200_crtc_set_plls(struct mga_device * mdev,long clock)786 static int mgag200_crtc_set_plls(struct mga_device *mdev, long clock)
787 {
788 u8 misc;
789
790 switch(mdev->type) {
791 case G200_PCI:
792 case G200_AGP:
793 return mgag200_g200_set_plls(mdev, clock);
794 case G200_SE_A:
795 case G200_SE_B:
796 return mga_g200se_set_plls(mdev, clock);
797 break;
798 case G200_WB:
799 case G200_EW3:
800 return mga_g200wb_set_plls(mdev, clock);
801 break;
802 case G200_EV:
803 return mga_g200ev_set_plls(mdev, clock);
804 break;
805 case G200_EH:
806 case G200_EH3:
807 return mga_g200eh_set_plls(mdev, clock);
808 break;
809 case G200_ER:
810 return mga_g200er_set_plls(mdev, clock);
811 break;
812 }
813
814 misc = RREG8(MGA_MISC_IN);
815 misc &= ~MGAREG_MISC_CLK_SEL_MASK;
816 misc |= MGAREG_MISC_CLK_SEL_MGA_MSK;
817 WREG8(MGA_MISC_OUT, misc);
818
819 return 0;
820 }
821
mgag200_g200wb_hold_bmc(struct mga_device * mdev)822 static void mgag200_g200wb_hold_bmc(struct mga_device *mdev)
823 {
824 u8 tmp;
825 int iter_max;
826
827 /* 1- The first step is to warn the BMC of an upcoming mode change.
828 * We are putting the misc<0> to output.*/
829
830 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL);
831 tmp = RREG8(DAC_DATA);
832 tmp |= 0x10;
833 WREG_DAC(MGA1064_GEN_IO_CTL, tmp);
834
835 /* we are putting a 1 on the misc<0> line */
836 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
837 tmp = RREG8(DAC_DATA);
838 tmp |= 0x10;
839 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
840
841 /* 2- Second step to mask and further scan request
842 * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>)
843 */
844 WREG8(DAC_INDEX, MGA1064_SPAREREG);
845 tmp = RREG8(DAC_DATA);
846 tmp |= 0x80;
847 WREG_DAC(MGA1064_SPAREREG, tmp);
848
849 /* 3a- the third step is to verifu if there is an active scan
850 * We are searching for a 0 on remhsyncsts <XSPAREREG<0>)
851 */
852 iter_max = 300;
853 while (!(tmp & 0x1) && iter_max) {
854 WREG8(DAC_INDEX, MGA1064_SPAREREG);
855 tmp = RREG8(DAC_DATA);
856 udelay(1000);
857 iter_max--;
858 }
859
860 /* 3b- this step occurs only if the remove is actually scanning
861 * we are waiting for the end of the frame which is a 1 on
862 * remvsyncsts (XSPAREREG<1>)
863 */
864 if (iter_max) {
865 iter_max = 300;
866 while ((tmp & 0x2) && iter_max) {
867 WREG8(DAC_INDEX, MGA1064_SPAREREG);
868 tmp = RREG8(DAC_DATA);
869 udelay(1000);
870 iter_max--;
871 }
872 }
873 }
874
mgag200_g200wb_release_bmc(struct mga_device * mdev)875 static void mgag200_g200wb_release_bmc(struct mga_device *mdev)
876 {
877 u8 tmp;
878
879 /* 1- The first step is to ensure that the vrsten and hrsten are set */
880 WREG8(MGAREG_CRTCEXT_INDEX, 1);
881 tmp = RREG8(MGAREG_CRTCEXT_DATA);
882 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88);
883
884 /* 2- second step is to assert the rstlvl2 */
885 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
886 tmp = RREG8(DAC_DATA);
887 tmp |= 0x8;
888 WREG8(DAC_DATA, tmp);
889
890 /* wait 10 us */
891 udelay(10);
892
893 /* 3- deassert rstlvl2 */
894 tmp &= ~0x08;
895 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
896 WREG8(DAC_DATA, tmp);
897
898 /* 4- remove mask of scan request */
899 WREG8(DAC_INDEX, MGA1064_SPAREREG);
900 tmp = RREG8(DAC_DATA);
901 tmp &= ~0x80;
902 WREG8(DAC_DATA, tmp);
903
904 /* 5- put back a 0 on the misc<0> line */
905 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
906 tmp = RREG8(DAC_DATA);
907 tmp &= ~0x10;
908 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
909 }
910
911 /*
912 * This is how the framebuffer base address is stored in g200 cards:
913 * * Assume @offset is the gpu_addr variable of the framebuffer object
914 * * Then addr is the number of _pixels_ (not bytes) from the start of
915 * VRAM to the first pixel we want to display. (divided by 2 for 32bit
916 * framebuffers)
917 * * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers
918 * addr<20> -> CRTCEXT0<6>
919 * addr<19-16> -> CRTCEXT0<3-0>
920 * addr<15-8> -> CRTCC<7-0>
921 * addr<7-0> -> CRTCD<7-0>
922 *
923 * CRTCEXT0 has to be programmed last to trigger an update and make the
924 * new addr variable take effect.
925 */
mgag200_set_startadd(struct mga_device * mdev,unsigned long offset)926 static void mgag200_set_startadd(struct mga_device *mdev,
927 unsigned long offset)
928 {
929 struct drm_device *dev = &mdev->base;
930 u32 startadd;
931 u8 crtcc, crtcd, crtcext0;
932
933 startadd = offset / 8;
934
935 /*
936 * Can't store addresses any higher than that, but we also
937 * don't have more than 16 MiB of memory, so it should be fine.
938 */
939 drm_WARN_ON(dev, startadd > 0x1fffff);
940
941 RREG_ECRT(0x00, crtcext0);
942
943 crtcc = (startadd >> 8) & 0xff;
944 crtcd = startadd & 0xff;
945 crtcext0 &= 0xb0;
946 crtcext0 |= ((startadd >> 14) & BIT(6)) |
947 ((startadd >> 16) & 0x0f);
948
949 WREG_CRT(0x0c, crtcc);
950 WREG_CRT(0x0d, crtcd);
951 WREG_ECRT(0x00, crtcext0);
952 }
953
mgag200_set_dac_regs(struct mga_device * mdev)954 static void mgag200_set_dac_regs(struct mga_device *mdev)
955 {
956 size_t i;
957 u8 dacvalue[] = {
958 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0,
959 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0,
960 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0,
961 /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20,
962 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
963 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40,
964 /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83,
965 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A,
966 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0,
967 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0
968 };
969
970 switch (mdev->type) {
971 case G200_PCI:
972 case G200_AGP:
973 dacvalue[MGA1064_SYS_PLL_M] = 0x04;
974 dacvalue[MGA1064_SYS_PLL_N] = 0x2D;
975 dacvalue[MGA1064_SYS_PLL_P] = 0x19;
976 break;
977 case G200_SE_A:
978 case G200_SE_B:
979 dacvalue[MGA1064_VREF_CTL] = 0x03;
980 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
981 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN |
982 MGA1064_MISC_CTL_VGA8 |
983 MGA1064_MISC_CTL_DAC_RAM_CS;
984 break;
985 case G200_WB:
986 case G200_EW3:
987 dacvalue[MGA1064_VREF_CTL] = 0x07;
988 break;
989 case G200_EV:
990 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
991 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
992 MGA1064_MISC_CTL_DAC_RAM_CS;
993 break;
994 case G200_EH:
995 case G200_EH3:
996 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
997 MGA1064_MISC_CTL_DAC_RAM_CS;
998 break;
999 case G200_ER:
1000 break;
1001 }
1002
1003 for (i = 0; i < ARRAY_SIZE(dacvalue); i++) {
1004 if ((i <= 0x17) ||
1005 (i == 0x1b) ||
1006 (i == 0x1c) ||
1007 ((i >= 0x1f) && (i <= 0x29)) ||
1008 ((i >= 0x30) && (i <= 0x37)))
1009 continue;
1010 if (IS_G200_SE(mdev) &&
1011 ((i == 0x2c) || (i == 0x2d) || (i == 0x2e)))
1012 continue;
1013 if ((mdev->type == G200_EV ||
1014 mdev->type == G200_WB ||
1015 mdev->type == G200_EH ||
1016 mdev->type == G200_EW3 ||
1017 mdev->type == G200_EH3) &&
1018 (i >= 0x44) && (i <= 0x4e))
1019 continue;
1020
1021 WREG_DAC(i, dacvalue[i]);
1022 }
1023
1024 if (mdev->type == G200_ER)
1025 WREG_DAC(0x90, 0);
1026 }
1027
mgag200_init_regs(struct mga_device * mdev)1028 static void mgag200_init_regs(struct mga_device *mdev)
1029 {
1030 u8 crtc11, misc;
1031
1032 mgag200_set_dac_regs(mdev);
1033
1034 WREG_SEQ(2, 0x0f);
1035 WREG_SEQ(3, 0x00);
1036 WREG_SEQ(4, 0x0e);
1037
1038 WREG_CRT(10, 0);
1039 WREG_CRT(11, 0);
1040 WREG_CRT(12, 0);
1041 WREG_CRT(13, 0);
1042 WREG_CRT(14, 0);
1043 WREG_CRT(15, 0);
1044
1045 RREG_CRT(0x11, crtc11);
1046 crtc11 &= ~(MGAREG_CRTC11_CRTCPROTECT |
1047 MGAREG_CRTC11_VINTEN |
1048 MGAREG_CRTC11_VINTCLR);
1049 WREG_CRT(0x11, crtc11);
1050
1051 if (mdev->type == G200_ER)
1052 WREG_ECRT(0x24, 0x5);
1053
1054 if (mdev->type == G200_EW3)
1055 WREG_ECRT(0x34, 0x5);
1056
1057 misc = RREG8(MGA_MISC_IN);
1058 misc |= MGAREG_MISC_IOADSEL;
1059 WREG8(MGA_MISC_OUT, misc);
1060 }
1061
mgag200_set_mode_regs(struct mga_device * mdev,const struct drm_display_mode * mode)1062 static void mgag200_set_mode_regs(struct mga_device *mdev,
1063 const struct drm_display_mode *mode)
1064 {
1065 unsigned int hdisplay, hsyncstart, hsyncend, htotal;
1066 unsigned int vdisplay, vsyncstart, vsyncend, vtotal;
1067 u8 misc, crtcext1, crtcext2, crtcext5;
1068
1069 hdisplay = mode->hdisplay / 8 - 1;
1070 hsyncstart = mode->hsync_start / 8 - 1;
1071 hsyncend = mode->hsync_end / 8 - 1;
1072 htotal = mode->htotal / 8 - 1;
1073
1074 /* Work around hardware quirk */
1075 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04)
1076 htotal++;
1077
1078 vdisplay = mode->vdisplay - 1;
1079 vsyncstart = mode->vsync_start - 1;
1080 vsyncend = mode->vsync_end - 1;
1081 vtotal = mode->vtotal - 2;
1082
1083 misc = RREG8(MGA_MISC_IN);
1084
1085 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1086 misc |= MGAREG_MISC_HSYNCPOL;
1087 else
1088 misc &= ~MGAREG_MISC_HSYNCPOL;
1089
1090 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1091 misc |= MGAREG_MISC_VSYNCPOL;
1092 else
1093 misc &= ~MGAREG_MISC_VSYNCPOL;
1094
1095 crtcext1 = (((htotal - 4) & 0x100) >> 8) |
1096 ((hdisplay & 0x100) >> 7) |
1097 ((hsyncstart & 0x100) >> 6) |
1098 (htotal & 0x40);
1099 if (mdev->type == G200_WB || mdev->type == G200_EW3)
1100 crtcext1 |= BIT(7) | /* vrsten */
1101 BIT(3); /* hrsten */
1102
1103 crtcext2 = ((vtotal & 0xc00) >> 10) |
1104 ((vdisplay & 0x400) >> 8) |
1105 ((vdisplay & 0xc00) >> 7) |
1106 ((vsyncstart & 0xc00) >> 5) |
1107 ((vdisplay & 0x400) >> 3);
1108 crtcext5 = 0x00;
1109
1110 WREG_CRT(0, htotal - 4);
1111 WREG_CRT(1, hdisplay);
1112 WREG_CRT(2, hdisplay);
1113 WREG_CRT(3, (htotal & 0x1F) | 0x80);
1114 WREG_CRT(4, hsyncstart);
1115 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F));
1116 WREG_CRT(6, vtotal & 0xFF);
1117 WREG_CRT(7, ((vtotal & 0x100) >> 8) |
1118 ((vdisplay & 0x100) >> 7) |
1119 ((vsyncstart & 0x100) >> 6) |
1120 ((vdisplay & 0x100) >> 5) |
1121 ((vdisplay & 0x100) >> 4) | /* linecomp */
1122 ((vtotal & 0x200) >> 4) |
1123 ((vdisplay & 0x200) >> 3) |
1124 ((vsyncstart & 0x200) >> 2));
1125 WREG_CRT(9, ((vdisplay & 0x200) >> 4) |
1126 ((vdisplay & 0x200) >> 3));
1127 WREG_CRT(16, vsyncstart & 0xFF);
1128 WREG_CRT(17, (vsyncend & 0x0F) | 0x20);
1129 WREG_CRT(18, vdisplay & 0xFF);
1130 WREG_CRT(20, 0);
1131 WREG_CRT(21, vdisplay & 0xFF);
1132 WREG_CRT(22, (vtotal + 1) & 0xFF);
1133 WREG_CRT(23, 0xc3);
1134 WREG_CRT(24, vdisplay & 0xFF);
1135
1136 WREG_ECRT(0x01, crtcext1);
1137 WREG_ECRT(0x02, crtcext2);
1138 WREG_ECRT(0x05, crtcext5);
1139
1140 WREG8(MGA_MISC_OUT, misc);
1141 }
1142
mgag200_get_bpp_shift(struct mga_device * mdev,const struct drm_format_info * format)1143 static u8 mgag200_get_bpp_shift(struct mga_device *mdev,
1144 const struct drm_format_info *format)
1145 {
1146 return mdev->bpp_shifts[format->cpp[0] - 1];
1147 }
1148
1149 /*
1150 * Calculates the HW offset value from the framebuffer's pitch. The
1151 * offset is a multiple of the pixel size and depends on the display
1152 * format.
1153 */
mgag200_calculate_offset(struct mga_device * mdev,const struct drm_framebuffer * fb)1154 static u32 mgag200_calculate_offset(struct mga_device *mdev,
1155 const struct drm_framebuffer *fb)
1156 {
1157 u32 offset = fb->pitches[0] / fb->format->cpp[0];
1158 u8 bppshift = mgag200_get_bpp_shift(mdev, fb->format);
1159
1160 if (fb->format->cpp[0] * 8 == 24)
1161 offset = (offset * 3) >> (4 - bppshift);
1162 else
1163 offset = offset >> (4 - bppshift);
1164
1165 return offset;
1166 }
1167
mgag200_set_offset(struct mga_device * mdev,const struct drm_framebuffer * fb)1168 static void mgag200_set_offset(struct mga_device *mdev,
1169 const struct drm_framebuffer *fb)
1170 {
1171 u8 crtc13, crtcext0;
1172 u32 offset = mgag200_calculate_offset(mdev, fb);
1173
1174 RREG_ECRT(0, crtcext0);
1175
1176 crtc13 = offset & 0xff;
1177
1178 crtcext0 &= ~MGAREG_CRTCEXT0_OFFSET_MASK;
1179 crtcext0 |= (offset >> 4) & MGAREG_CRTCEXT0_OFFSET_MASK;
1180
1181 WREG_CRT(0x13, crtc13);
1182 WREG_ECRT(0x00, crtcext0);
1183 }
1184
mgag200_set_format_regs(struct mga_device * mdev,const struct drm_framebuffer * fb)1185 static void mgag200_set_format_regs(struct mga_device *mdev,
1186 const struct drm_framebuffer *fb)
1187 {
1188 struct drm_device *dev = &mdev->base;
1189 const struct drm_format_info *format = fb->format;
1190 unsigned int bpp, bppshift, scale;
1191 u8 crtcext3, xmulctrl;
1192
1193 bpp = format->cpp[0] * 8;
1194
1195 bppshift = mgag200_get_bpp_shift(mdev, format);
1196 switch (bpp) {
1197 case 24:
1198 scale = ((1 << bppshift) * 3) - 1;
1199 break;
1200 default:
1201 scale = (1 << bppshift) - 1;
1202 break;
1203 }
1204
1205 RREG_ECRT(3, crtcext3);
1206
1207 switch (bpp) {
1208 case 8:
1209 xmulctrl = MGA1064_MUL_CTL_8bits;
1210 break;
1211 case 16:
1212 if (format->depth == 15)
1213 xmulctrl = MGA1064_MUL_CTL_15bits;
1214 else
1215 xmulctrl = MGA1064_MUL_CTL_16bits;
1216 break;
1217 case 24:
1218 xmulctrl = MGA1064_MUL_CTL_24bits;
1219 break;
1220 case 32:
1221 xmulctrl = MGA1064_MUL_CTL_32_24bits;
1222 break;
1223 default:
1224 /* BUG: We should have caught this problem already. */
1225 drm_WARN_ON(dev, "invalid format depth\n");
1226 return;
1227 }
1228
1229 crtcext3 &= ~GENMASK(2, 0);
1230 crtcext3 |= scale;
1231
1232 WREG_DAC(MGA1064_MUL_CTL, xmulctrl);
1233
1234 WREG_GFX(0, 0x00);
1235 WREG_GFX(1, 0x00);
1236 WREG_GFX(2, 0x00);
1237 WREG_GFX(3, 0x00);
1238 WREG_GFX(4, 0x00);
1239 WREG_GFX(5, 0x40);
1240 WREG_GFX(6, 0x05);
1241 WREG_GFX(7, 0x0f);
1242 WREG_GFX(8, 0x0f);
1243
1244 WREG_ECRT(3, crtcext3);
1245 }
1246
mgag200_g200er_reset_tagfifo(struct mga_device * mdev)1247 static void mgag200_g200er_reset_tagfifo(struct mga_device *mdev)
1248 {
1249 static uint32_t RESET_FLAG = 0x00200000; /* undocumented magic value */
1250 u32 memctl;
1251
1252 memctl = RREG32(MGAREG_MEMCTL);
1253
1254 memctl |= RESET_FLAG;
1255 WREG32(MGAREG_MEMCTL, memctl);
1256
1257 udelay(1000);
1258
1259 memctl &= ~RESET_FLAG;
1260 WREG32(MGAREG_MEMCTL, memctl);
1261 }
1262
mgag200_g200se_set_hiprilvl(struct mga_device * mdev,const struct drm_display_mode * mode,const struct drm_framebuffer * fb)1263 static void mgag200_g200se_set_hiprilvl(struct mga_device *mdev,
1264 const struct drm_display_mode *mode,
1265 const struct drm_framebuffer *fb)
1266 {
1267 u32 unique_rev_id = mdev->model.g200se.unique_rev_id;
1268 unsigned int hiprilvl;
1269 u8 crtcext6;
1270
1271 if (unique_rev_id >= 0x04) {
1272 hiprilvl = 0;
1273 } else if (unique_rev_id >= 0x02) {
1274 unsigned int bpp;
1275 unsigned long mb;
1276
1277 if (fb->format->cpp[0] * 8 > 16)
1278 bpp = 32;
1279 else if (fb->format->cpp[0] * 8 > 8)
1280 bpp = 16;
1281 else
1282 bpp = 8;
1283
1284 mb = (mode->clock * bpp) / 1000;
1285 if (mb > 3100)
1286 hiprilvl = 0;
1287 else if (mb > 2600)
1288 hiprilvl = 1;
1289 else if (mb > 1900)
1290 hiprilvl = 2;
1291 else if (mb > 1160)
1292 hiprilvl = 3;
1293 else if (mb > 440)
1294 hiprilvl = 4;
1295 else
1296 hiprilvl = 5;
1297
1298 } else if (unique_rev_id >= 0x01) {
1299 hiprilvl = 3;
1300 } else {
1301 hiprilvl = 4;
1302 }
1303
1304 crtcext6 = hiprilvl; /* implicitly sets maxhipri to 0 */
1305
1306 WREG_ECRT(0x06, crtcext6);
1307 }
1308
mgag200_g200ev_set_hiprilvl(struct mga_device * mdev)1309 static void mgag200_g200ev_set_hiprilvl(struct mga_device *mdev)
1310 {
1311 WREG_ECRT(0x06, 0x00);
1312 }
1313
mgag200_enable_display(struct mga_device * mdev)1314 static void mgag200_enable_display(struct mga_device *mdev)
1315 {
1316 u8 seq0, seq1, crtcext1;
1317
1318 RREG_SEQ(0x00, seq0);
1319 seq0 |= MGAREG_SEQ0_SYNCRST |
1320 MGAREG_SEQ0_ASYNCRST;
1321 WREG_SEQ(0x00, seq0);
1322
1323 /*
1324 * TODO: replace busy waiting with vblank IRQ; put
1325 * msleep(50) before changing SCROFF
1326 */
1327 mga_wait_vsync(mdev);
1328 mga_wait_busy(mdev);
1329
1330 RREG_SEQ(0x01, seq1);
1331 seq1 &= ~MGAREG_SEQ1_SCROFF;
1332 WREG_SEQ(0x01, seq1);
1333
1334 msleep(20);
1335
1336 RREG_ECRT(0x01, crtcext1);
1337 crtcext1 &= ~MGAREG_CRTCEXT1_VSYNCOFF;
1338 crtcext1 &= ~MGAREG_CRTCEXT1_HSYNCOFF;
1339 WREG_ECRT(0x01, crtcext1);
1340 }
1341
mgag200_disable_display(struct mga_device * mdev)1342 static void mgag200_disable_display(struct mga_device *mdev)
1343 {
1344 u8 seq0, seq1, crtcext1;
1345
1346 RREG_SEQ(0x00, seq0);
1347 seq0 &= ~MGAREG_SEQ0_SYNCRST;
1348 WREG_SEQ(0x00, seq0);
1349
1350 /*
1351 * TODO: replace busy waiting with vblank IRQ; put
1352 * msleep(50) before changing SCROFF
1353 */
1354 mga_wait_vsync(mdev);
1355 mga_wait_busy(mdev);
1356
1357 RREG_SEQ(0x01, seq1);
1358 seq1 |= MGAREG_SEQ1_SCROFF;
1359 WREG_SEQ(0x01, seq1);
1360
1361 msleep(20);
1362
1363 RREG_ECRT(0x01, crtcext1);
1364 crtcext1 |= MGAREG_CRTCEXT1_VSYNCOFF |
1365 MGAREG_CRTCEXT1_HSYNCOFF;
1366 WREG_ECRT(0x01, crtcext1);
1367 }
1368
1369 /*
1370 * Connector
1371 */
1372
mga_vga_get_modes(struct drm_connector * connector)1373 static int mga_vga_get_modes(struct drm_connector *connector)
1374 {
1375 struct mga_connector *mga_connector = to_mga_connector(connector);
1376 struct edid *edid;
1377 int ret = 0;
1378
1379 edid = drm_get_edid(connector, &mga_connector->i2c->adapter);
1380 if (edid) {
1381 drm_connector_update_edid_property(connector, edid);
1382 ret = drm_add_edid_modes(connector, edid);
1383 kfree(edid);
1384 }
1385 return ret;
1386 }
1387
mga_vga_calculate_mode_bandwidth(struct drm_display_mode * mode,int bits_per_pixel)1388 static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode *mode,
1389 int bits_per_pixel)
1390 {
1391 uint32_t total_area, divisor;
1392 uint64_t active_area, pixels_per_second, bandwidth;
1393 uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8;
1394
1395 divisor = 1024;
1396
1397 if (!mode->htotal || !mode->vtotal || !mode->clock)
1398 return 0;
1399
1400 active_area = mode->hdisplay * mode->vdisplay;
1401 total_area = mode->htotal * mode->vtotal;
1402
1403 pixels_per_second = active_area * mode->clock * 1000;
1404 do_div(pixels_per_second, total_area);
1405
1406 bandwidth = pixels_per_second * bytes_per_pixel * 100;
1407 do_div(bandwidth, divisor);
1408
1409 return (uint32_t)(bandwidth);
1410 }
1411
1412 #define MODE_BANDWIDTH MODE_BAD
1413
mga_vga_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)1414 static enum drm_mode_status mga_vga_mode_valid(struct drm_connector *connector,
1415 struct drm_display_mode *mode)
1416 {
1417 struct drm_device *dev = connector->dev;
1418 struct mga_device *mdev = to_mga_device(dev);
1419 int bpp = 32;
1420
1421 if (IS_G200_SE(mdev)) {
1422 u32 unique_rev_id = mdev->model.g200se.unique_rev_id;
1423
1424 if (unique_rev_id == 0x01) {
1425 if (mode->hdisplay > 1600)
1426 return MODE_VIRTUAL_X;
1427 if (mode->vdisplay > 1200)
1428 return MODE_VIRTUAL_Y;
1429 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1430 > (24400 * 1024))
1431 return MODE_BANDWIDTH;
1432 } else if (unique_rev_id == 0x02) {
1433 if (mode->hdisplay > 1920)
1434 return MODE_VIRTUAL_X;
1435 if (mode->vdisplay > 1200)
1436 return MODE_VIRTUAL_Y;
1437 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1438 > (30100 * 1024))
1439 return MODE_BANDWIDTH;
1440 } else {
1441 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1442 > (55000 * 1024))
1443 return MODE_BANDWIDTH;
1444 }
1445 } else if (mdev->type == G200_WB) {
1446 if (mode->hdisplay > 1280)
1447 return MODE_VIRTUAL_X;
1448 if (mode->vdisplay > 1024)
1449 return MODE_VIRTUAL_Y;
1450 if (mga_vga_calculate_mode_bandwidth(mode, bpp) >
1451 (31877 * 1024))
1452 return MODE_BANDWIDTH;
1453 } else if (mdev->type == G200_EV &&
1454 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1455 > (32700 * 1024))) {
1456 return MODE_BANDWIDTH;
1457 } else if (mdev->type == G200_EH &&
1458 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1459 > (37500 * 1024))) {
1460 return MODE_BANDWIDTH;
1461 } else if (mdev->type == G200_ER &&
1462 (mga_vga_calculate_mode_bandwidth(mode,
1463 bpp) > (55000 * 1024))) {
1464 return MODE_BANDWIDTH;
1465 }
1466
1467 if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 ||
1468 (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) {
1469 return MODE_H_ILLEGAL;
1470 }
1471
1472 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 ||
1473 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 ||
1474 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 ||
1475 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) {
1476 return MODE_BAD;
1477 }
1478
1479 /* Validate the mode input by the user */
1480 if (connector->cmdline_mode.specified) {
1481 if (connector->cmdline_mode.bpp_specified)
1482 bpp = connector->cmdline_mode.bpp;
1483 }
1484
1485 if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->vram_fb_available) {
1486 if (connector->cmdline_mode.specified)
1487 connector->cmdline_mode.specified = false;
1488 return MODE_BAD;
1489 }
1490
1491 return MODE_OK;
1492 }
1493
mga_connector_destroy(struct drm_connector * connector)1494 static void mga_connector_destroy(struct drm_connector *connector)
1495 {
1496 struct mga_connector *mga_connector = to_mga_connector(connector);
1497 mgag200_i2c_destroy(mga_connector->i2c);
1498 drm_connector_cleanup(connector);
1499 }
1500
1501 static const struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = {
1502 .get_modes = mga_vga_get_modes,
1503 .mode_valid = mga_vga_mode_valid,
1504 };
1505
1506 static const struct drm_connector_funcs mga_vga_connector_funcs = {
1507 .reset = drm_atomic_helper_connector_reset,
1508 .fill_modes = drm_helper_probe_single_connector_modes,
1509 .destroy = mga_connector_destroy,
1510 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1511 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1512 };
1513
mgag200_vga_connector_init(struct mga_device * mdev)1514 static int mgag200_vga_connector_init(struct mga_device *mdev)
1515 {
1516 struct drm_device *dev = &mdev->base;
1517 struct mga_connector *mconnector = &mdev->connector;
1518 struct drm_connector *connector = &mconnector->base;
1519 struct mga_i2c_chan *i2c;
1520 int ret;
1521
1522 i2c = mgag200_i2c_create(dev);
1523 if (!i2c)
1524 drm_warn(dev, "failed to add DDC bus\n");
1525
1526 ret = drm_connector_init_with_ddc(dev, connector,
1527 &mga_vga_connector_funcs,
1528 DRM_MODE_CONNECTOR_VGA,
1529 &i2c->adapter);
1530 if (ret)
1531 goto err_mgag200_i2c_destroy;
1532 drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs);
1533
1534 mconnector->i2c = i2c;
1535
1536 return 0;
1537
1538 err_mgag200_i2c_destroy:
1539 mgag200_i2c_destroy(i2c);
1540 return ret;
1541 }
1542
1543 /*
1544 * Simple Display Pipe
1545 */
1546
1547 static enum drm_mode_status
mgag200_simple_display_pipe_mode_valid(struct drm_simple_display_pipe * pipe,const struct drm_display_mode * mode)1548 mgag200_simple_display_pipe_mode_valid(struct drm_simple_display_pipe *pipe,
1549 const struct drm_display_mode *mode)
1550 {
1551 return MODE_OK;
1552 }
1553
1554 static void
mgag200_handle_damage(struct mga_device * mdev,struct drm_framebuffer * fb,struct drm_rect * clip)1555 mgag200_handle_damage(struct mga_device *mdev, struct drm_framebuffer *fb,
1556 struct drm_rect *clip)
1557 {
1558 struct drm_device *dev = &mdev->base;
1559 void *vmap;
1560
1561 vmap = drm_gem_shmem_vmap(fb->obj[0]);
1562 if (drm_WARN_ON(dev, !vmap))
1563 return; /* BUG: SHMEM BO should always be vmapped */
1564
1565 drm_fb_memcpy_dstclip(mdev->vram, vmap, fb, clip);
1566
1567 drm_gem_shmem_vunmap(fb->obj[0], vmap);
1568
1569 /* Always scanout image at VRAM offset 0 */
1570 mgag200_set_startadd(mdev, (u32)0);
1571 mgag200_set_offset(mdev, fb);
1572 }
1573
1574 static void
mgag200_simple_display_pipe_enable(struct drm_simple_display_pipe * pipe,struct drm_crtc_state * crtc_state,struct drm_plane_state * plane_state)1575 mgag200_simple_display_pipe_enable(struct drm_simple_display_pipe *pipe,
1576 struct drm_crtc_state *crtc_state,
1577 struct drm_plane_state *plane_state)
1578 {
1579 struct drm_crtc *crtc = &pipe->crtc;
1580 struct drm_device *dev = crtc->dev;
1581 struct mga_device *mdev = to_mga_device(dev);
1582 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1583 struct drm_framebuffer *fb = plane_state->fb;
1584 struct drm_rect fullscreen = {
1585 .x1 = 0,
1586 .x2 = fb->width,
1587 .y1 = 0,
1588 .y2 = fb->height,
1589 };
1590
1591 if (mdev->type == G200_WB || mdev->type == G200_EW3)
1592 mgag200_g200wb_hold_bmc(mdev);
1593
1594 mgag200_set_format_regs(mdev, fb);
1595 mgag200_set_mode_regs(mdev, adjusted_mode);
1596 mgag200_crtc_set_plls(mdev, adjusted_mode->clock);
1597
1598 if (mdev->type == G200_ER)
1599 mgag200_g200er_reset_tagfifo(mdev);
1600
1601 if (IS_G200_SE(mdev))
1602 mgag200_g200se_set_hiprilvl(mdev, adjusted_mode, fb);
1603 else if (mdev->type == G200_EV)
1604 mgag200_g200ev_set_hiprilvl(mdev);
1605
1606 if (mdev->type == G200_WB || mdev->type == G200_EW3)
1607 mgag200_g200wb_release_bmc(mdev);
1608
1609 mga_crtc_load_lut(crtc);
1610 mgag200_enable_display(mdev);
1611
1612 mgag200_handle_damage(mdev, fb, &fullscreen);
1613 }
1614
1615 static void
mgag200_simple_display_pipe_disable(struct drm_simple_display_pipe * pipe)1616 mgag200_simple_display_pipe_disable(struct drm_simple_display_pipe *pipe)
1617 {
1618 struct drm_crtc *crtc = &pipe->crtc;
1619 struct mga_device *mdev = to_mga_device(crtc->dev);
1620
1621 mgag200_disable_display(mdev);
1622 }
1623
1624 static int
mgag200_simple_display_pipe_check(struct drm_simple_display_pipe * pipe,struct drm_plane_state * plane_state,struct drm_crtc_state * crtc_state)1625 mgag200_simple_display_pipe_check(struct drm_simple_display_pipe *pipe,
1626 struct drm_plane_state *plane_state,
1627 struct drm_crtc_state *crtc_state)
1628 {
1629 struct drm_plane *plane = plane_state->plane;
1630 struct drm_framebuffer *new_fb = plane_state->fb;
1631 struct drm_framebuffer *fb = NULL;
1632
1633 if (!new_fb)
1634 return 0;
1635
1636 if (plane->state)
1637 fb = plane->state->fb;
1638
1639 if (!fb || (fb->format != new_fb->format))
1640 crtc_state->mode_changed = true; /* update PLL settings */
1641
1642 return 0;
1643 }
1644
1645 static void
mgag200_simple_display_pipe_update(struct drm_simple_display_pipe * pipe,struct drm_plane_state * old_state)1646 mgag200_simple_display_pipe_update(struct drm_simple_display_pipe *pipe,
1647 struct drm_plane_state *old_state)
1648 {
1649 struct drm_plane *plane = &pipe->plane;
1650 struct drm_device *dev = plane->dev;
1651 struct mga_device *mdev = to_mga_device(dev);
1652 struct drm_plane_state *state = plane->state;
1653 struct drm_framebuffer *fb = state->fb;
1654 struct drm_rect damage;
1655
1656 if (!fb)
1657 return;
1658
1659 if (drm_atomic_helper_damage_merged(old_state, state, &damage))
1660 mgag200_handle_damage(mdev, fb, &damage);
1661 }
1662
1663 static const struct drm_simple_display_pipe_funcs
1664 mgag200_simple_display_pipe_funcs = {
1665 .mode_valid = mgag200_simple_display_pipe_mode_valid,
1666 .enable = mgag200_simple_display_pipe_enable,
1667 .disable = mgag200_simple_display_pipe_disable,
1668 .check = mgag200_simple_display_pipe_check,
1669 .update = mgag200_simple_display_pipe_update,
1670 .prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
1671 };
1672
1673 static const uint32_t mgag200_simple_display_pipe_formats[] = {
1674 DRM_FORMAT_XRGB8888,
1675 DRM_FORMAT_RGB565,
1676 DRM_FORMAT_RGB888,
1677 };
1678
1679 static const uint64_t mgag200_simple_display_pipe_fmtmods[] = {
1680 DRM_FORMAT_MOD_LINEAR,
1681 DRM_FORMAT_MOD_INVALID
1682 };
1683
1684 /*
1685 * Mode config
1686 */
1687
1688 static const struct drm_mode_config_funcs mgag200_mode_config_funcs = {
1689 .fb_create = drm_gem_fb_create_with_dirty,
1690 .atomic_check = drm_atomic_helper_check,
1691 .atomic_commit = drm_atomic_helper_commit,
1692 };
1693
mgag200_preferred_depth(struct mga_device * mdev)1694 static unsigned int mgag200_preferred_depth(struct mga_device *mdev)
1695 {
1696 if (IS_G200_SE(mdev) && mdev->vram_fb_available < (2048*1024))
1697 return 16;
1698 else
1699 return 32;
1700 }
1701
mgag200_modeset_init(struct mga_device * mdev)1702 int mgag200_modeset_init(struct mga_device *mdev)
1703 {
1704 struct drm_device *dev = &mdev->base;
1705 struct drm_connector *connector = &mdev->connector.base;
1706 struct drm_simple_display_pipe *pipe = &mdev->display_pipe;
1707 size_t format_count = ARRAY_SIZE(mgag200_simple_display_pipe_formats);
1708 int ret;
1709
1710 mdev->bpp_shifts[0] = 0;
1711 mdev->bpp_shifts[1] = 1;
1712 mdev->bpp_shifts[2] = 0;
1713 mdev->bpp_shifts[3] = 2;
1714
1715 mgag200_init_regs(mdev);
1716
1717 ret = drmm_mode_config_init(dev);
1718 if (ret) {
1719 drm_err(dev, "drmm_mode_config_init() failed, error %d\n",
1720 ret);
1721 return ret;
1722 }
1723
1724 dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH;
1725 dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT;
1726
1727 dev->mode_config.preferred_depth = mgag200_preferred_depth(mdev);
1728
1729 dev->mode_config.fb_base = mdev->mc.vram_base;
1730
1731 dev->mode_config.funcs = &mgag200_mode_config_funcs;
1732
1733 ret = mgag200_vga_connector_init(mdev);
1734 if (ret) {
1735 drm_err(dev,
1736 "mgag200_vga_connector_init() failed, error %d\n",
1737 ret);
1738 return ret;
1739 }
1740
1741 ret = drm_simple_display_pipe_init(dev, pipe,
1742 &mgag200_simple_display_pipe_funcs,
1743 mgag200_simple_display_pipe_formats,
1744 format_count,
1745 mgag200_simple_display_pipe_fmtmods,
1746 connector);
1747 if (ret) {
1748 drm_err(dev,
1749 "drm_simple_display_pipe_init() failed, error %d\n",
1750 ret);
1751 return ret;
1752 }
1753
1754 /* FIXME: legacy gamma tables; convert to CRTC state */
1755 drm_mode_crtc_set_gamma_size(&pipe->crtc, MGAG200_LUT_SIZE);
1756
1757 drm_mode_config_reset(dev);
1758
1759 return 0;
1760 }
1761
