1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2016 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
6 * Copyright (C) 2014 Endless Mobile
7 *
8 * Written by:
9 * Jasper St. Pierre <jstpierre@mecheye.net>
10 */
11
12 #include <linux/export.h>
13 #include <linux/of_graph.h>
14
15 #include <drm/drm_atomic_helper.h>
16 #include <drm/drm_device.h>
17 #include <drm/drm_edid.h>
18 #include <drm/drm_probe_helper.h>
19 #include <drm/drm_print.h>
20
21 #include "meson_registers.h"
22 #include "meson_vclk.h"
23 #include "meson_venc_cvbs.h"
24
25 /* HHI VDAC Registers */
26 #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
27 #define HHI_VDAC_CNTL0_G12A 0x2EC /* 0xbd offset in data sheet */
28 #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
29 #define HHI_VDAC_CNTL1_G12A 0x2F0 /* 0xbe offset in data sheet */
30
31 struct meson_venc_cvbs {
32 struct drm_encoder encoder;
33 struct drm_connector connector;
34 struct meson_drm *priv;
35 };
36 #define encoder_to_meson_venc_cvbs(x) \
37 container_of(x, struct meson_venc_cvbs, encoder)
38
39 #define connector_to_meson_venc_cvbs(x) \
40 container_of(x, struct meson_venc_cvbs, connector)
41
42 /* Supported Modes */
43
44 struct meson_cvbs_mode meson_cvbs_modes[MESON_CVBS_MODES_COUNT] = {
45 { /* PAL */
46 .enci = &meson_cvbs_enci_pal,
47 .mode = {
48 DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500,
49 720, 732, 795, 864, 0, 576, 580, 586, 625, 0,
50 DRM_MODE_FLAG_INTERLACE),
51 .vrefresh = 50,
52 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
53 },
54 },
55 { /* NTSC */
56 .enci = &meson_cvbs_enci_ntsc,
57 .mode = {
58 DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500,
59 720, 739, 801, 858, 0, 480, 488, 494, 525, 0,
60 DRM_MODE_FLAG_INTERLACE),
61 .vrefresh = 60,
62 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
63 },
64 },
65 };
66
67 /* Connector */
68
meson_cvbs_connector_destroy(struct drm_connector * connector)69 static void meson_cvbs_connector_destroy(struct drm_connector *connector)
70 {
71 drm_connector_cleanup(connector);
72 }
73
74 static enum drm_connector_status
meson_cvbs_connector_detect(struct drm_connector * connector,bool force)75 meson_cvbs_connector_detect(struct drm_connector *connector, bool force)
76 {
77 /* FIXME: Add load-detect or jack-detect if possible */
78 return connector_status_connected;
79 }
80
meson_cvbs_connector_get_modes(struct drm_connector * connector)81 static int meson_cvbs_connector_get_modes(struct drm_connector *connector)
82 {
83 struct drm_device *dev = connector->dev;
84 struct drm_display_mode *mode;
85 int i;
86
87 for (i = 0; i < MESON_CVBS_MODES_COUNT; ++i) {
88 struct meson_cvbs_mode *meson_mode = &meson_cvbs_modes[i];
89
90 mode = drm_mode_duplicate(dev, &meson_mode->mode);
91 if (!mode) {
92 DRM_ERROR("Failed to create a new display mode\n");
93 return 0;
94 }
95
96 drm_mode_probed_add(connector, mode);
97 }
98
99 return i;
100 }
101
meson_cvbs_connector_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)102 static int meson_cvbs_connector_mode_valid(struct drm_connector *connector,
103 struct drm_display_mode *mode)
104 {
105 /* Validate the modes added in get_modes */
106 return MODE_OK;
107 }
108
109 static const struct drm_connector_funcs meson_cvbs_connector_funcs = {
110 .detect = meson_cvbs_connector_detect,
111 .fill_modes = drm_helper_probe_single_connector_modes,
112 .destroy = meson_cvbs_connector_destroy,
113 .reset = drm_atomic_helper_connector_reset,
114 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
115 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
116 };
117
118 static const
119 struct drm_connector_helper_funcs meson_cvbs_connector_helper_funcs = {
120 .get_modes = meson_cvbs_connector_get_modes,
121 .mode_valid = meson_cvbs_connector_mode_valid,
122 };
123
124 /* Encoder */
125
meson_venc_cvbs_encoder_destroy(struct drm_encoder * encoder)126 static void meson_venc_cvbs_encoder_destroy(struct drm_encoder *encoder)
127 {
128 drm_encoder_cleanup(encoder);
129 }
130
131 static const struct drm_encoder_funcs meson_venc_cvbs_encoder_funcs = {
132 .destroy = meson_venc_cvbs_encoder_destroy,
133 };
134
meson_venc_cvbs_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)135 static int meson_venc_cvbs_encoder_atomic_check(struct drm_encoder *encoder,
136 struct drm_crtc_state *crtc_state,
137 struct drm_connector_state *conn_state)
138 {
139 int i;
140
141 for (i = 0; i < MESON_CVBS_MODES_COUNT; ++i) {
142 struct meson_cvbs_mode *meson_mode = &meson_cvbs_modes[i];
143
144 if (drm_mode_equal(&crtc_state->mode, &meson_mode->mode))
145 return 0;
146 }
147
148 return -EINVAL;
149 }
150
meson_venc_cvbs_encoder_disable(struct drm_encoder * encoder)151 static void meson_venc_cvbs_encoder_disable(struct drm_encoder *encoder)
152 {
153 struct meson_venc_cvbs *meson_venc_cvbs =
154 encoder_to_meson_venc_cvbs(encoder);
155 struct meson_drm *priv = meson_venc_cvbs->priv;
156
157 /* Disable CVBS VDAC */
158 if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
159 regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0);
160 regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0);
161 } else {
162 regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);
163 regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8);
164 }
165 }
166
meson_venc_cvbs_encoder_enable(struct drm_encoder * encoder)167 static void meson_venc_cvbs_encoder_enable(struct drm_encoder *encoder)
168 {
169 struct meson_venc_cvbs *meson_venc_cvbs =
170 encoder_to_meson_venc_cvbs(encoder);
171 struct meson_drm *priv = meson_venc_cvbs->priv;
172
173 /* VDAC0 source is not from ATV */
174 writel_bits_relaxed(VENC_VDAC_SEL_ATV_DMD, 0,
175 priv->io_base + _REG(VENC_VDAC_DACSEL0));
176
177 if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
178 regmap_write(priv->hhi, HHI_VDAC_CNTL0, 1);
179 regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0);
180 } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
181 meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
182 regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0xf0001);
183 regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0);
184 } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
185 regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0x906001);
186 regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0);
187 }
188 }
189
meson_venc_cvbs_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)190 static void meson_venc_cvbs_encoder_mode_set(struct drm_encoder *encoder,
191 struct drm_display_mode *mode,
192 struct drm_display_mode *adjusted_mode)
193 {
194 struct meson_venc_cvbs *meson_venc_cvbs =
195 encoder_to_meson_venc_cvbs(encoder);
196 struct meson_drm *priv = meson_venc_cvbs->priv;
197 int i;
198
199 for (i = 0; i < MESON_CVBS_MODES_COUNT; ++i) {
200 struct meson_cvbs_mode *meson_mode = &meson_cvbs_modes[i];
201
202 if (drm_mode_equal(mode, &meson_mode->mode)) {
203 meson_venci_cvbs_mode_set(priv,
204 meson_mode->enci);
205
206 /* Setup 27MHz vclk2 for ENCI and VDAC */
207 meson_vclk_setup(priv, MESON_VCLK_TARGET_CVBS,
208 MESON_VCLK_CVBS, MESON_VCLK_CVBS,
209 MESON_VCLK_CVBS, true);
210 break;
211 }
212 }
213 }
214
215 static const struct drm_encoder_helper_funcs
216 meson_venc_cvbs_encoder_helper_funcs = {
217 .atomic_check = meson_venc_cvbs_encoder_atomic_check,
218 .disable = meson_venc_cvbs_encoder_disable,
219 .enable = meson_venc_cvbs_encoder_enable,
220 .mode_set = meson_venc_cvbs_encoder_mode_set,
221 };
222
meson_venc_cvbs_connector_is_available(struct meson_drm * priv)223 static bool meson_venc_cvbs_connector_is_available(struct meson_drm *priv)
224 {
225 struct device_node *remote;
226
227 remote = of_graph_get_remote_node(priv->dev->of_node, 0, 0);
228 if (!remote)
229 return false;
230
231 of_node_put(remote);
232 return true;
233 }
234
meson_venc_cvbs_create(struct meson_drm * priv)235 int meson_venc_cvbs_create(struct meson_drm *priv)
236 {
237 struct drm_device *drm = priv->drm;
238 struct meson_venc_cvbs *meson_venc_cvbs;
239 struct drm_connector *connector;
240 struct drm_encoder *encoder;
241 int ret;
242
243 if (!meson_venc_cvbs_connector_is_available(priv)) {
244 dev_info(drm->dev, "CVBS Output connector not available\n");
245 return 0;
246 }
247
248 meson_venc_cvbs = devm_kzalloc(priv->dev, sizeof(*meson_venc_cvbs),
249 GFP_KERNEL);
250 if (!meson_venc_cvbs)
251 return -ENOMEM;
252
253 meson_venc_cvbs->priv = priv;
254 encoder = &meson_venc_cvbs->encoder;
255 connector = &meson_venc_cvbs->connector;
256
257 /* Connector */
258
259 drm_connector_helper_add(connector,
260 &meson_cvbs_connector_helper_funcs);
261
262 ret = drm_connector_init(drm, connector, &meson_cvbs_connector_funcs,
263 DRM_MODE_CONNECTOR_Composite);
264 if (ret) {
265 dev_err(priv->dev, "Failed to init CVBS connector\n");
266 return ret;
267 }
268
269 connector->interlace_allowed = 1;
270
271 /* Encoder */
272
273 drm_encoder_helper_add(encoder, &meson_venc_cvbs_encoder_helper_funcs);
274
275 ret = drm_encoder_init(drm, encoder, &meson_venc_cvbs_encoder_funcs,
276 DRM_MODE_ENCODER_TVDAC, "meson_venc_cvbs");
277 if (ret) {
278 dev_err(priv->dev, "Failed to init CVBS encoder\n");
279 return ret;
280 }
281
282 encoder->possible_crtcs = BIT(0);
283
284 drm_connector_attach_encoder(connector, encoder);
285
286 return 0;
287 }
288
