1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
4 */
5
6 #include "mdp5_kms.h"
7 #include "mdp5_cfg.h"
8
9 struct mdp5_cfg_handler {
10 int revision;
11 struct mdp5_cfg config;
12 };
13
14 /* mdp5_cfg must be exposed (used in mdp5.xml.h) */
15 const struct mdp5_cfg_hw *mdp5_cfg = NULL;
16
17 static const struct mdp5_cfg_hw msm8x74v1_config = {
18 .name = "msm8x74v1",
19 .mdp = {
20 .count = 1,
21 .caps = MDP_CAP_SMP |
22 0,
23 },
24 .smp = {
25 .mmb_count = 22,
26 .mmb_size = 4096,
27 .clients = {
28 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
29 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
30 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
31 },
32 },
33 .ctl = {
34 .count = 5,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
37 },
38 .pipe_vig = {
39 .count = 3,
40 .base = { 0x01100, 0x01500, 0x01900 },
41 .caps = MDP_PIPE_CAP_HFLIP |
42 MDP_PIPE_CAP_VFLIP |
43 MDP_PIPE_CAP_SCALE |
44 MDP_PIPE_CAP_CSC |
45 0,
46 },
47 .pipe_rgb = {
48 .count = 3,
49 .base = { 0x01d00, 0x02100, 0x02500 },
50 .caps = MDP_PIPE_CAP_HFLIP |
51 MDP_PIPE_CAP_VFLIP |
52 MDP_PIPE_CAP_SCALE |
53 0,
54 },
55 .pipe_dma = {
56 .count = 2,
57 .base = { 0x02900, 0x02d00 },
58 .caps = MDP_PIPE_CAP_HFLIP |
59 MDP_PIPE_CAP_VFLIP |
60 0,
61 },
62 .lm = {
63 .count = 5,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
65 .instances = {
66 { .id = 0, .pp = 0, .dspp = 0,
67 .caps = MDP_LM_CAP_DISPLAY, },
68 { .id = 1, .pp = 1, .dspp = 1,
69 .caps = MDP_LM_CAP_DISPLAY, },
70 { .id = 2, .pp = 2, .dspp = 2,
71 .caps = MDP_LM_CAP_DISPLAY, },
72 { .id = 3, .pp = -1, .dspp = -1,
73 .caps = MDP_LM_CAP_WB },
74 { .id = 4, .pp = -1, .dspp = -1,
75 .caps = MDP_LM_CAP_WB },
76 },
77 .nb_stages = 5,
78 .max_width = 2048,
79 .max_height = 0xFFFF,
80 },
81 .dspp = {
82 .count = 3,
83 .base = { 0x04500, 0x04900, 0x04d00 },
84 },
85 .pp = {
86 .count = 3,
87 .base = { 0x21a00, 0x21b00, 0x21c00 },
88 },
89 .intf = {
90 .base = { 0x21000, 0x21200, 0x21400, 0x21600 },
91 .connect = {
92 [0] = INTF_eDP,
93 [1] = INTF_DSI,
94 [2] = INTF_DSI,
95 [3] = INTF_HDMI,
96 },
97 },
98 .perf = {
99 .ab_inefficiency = 200,
100 .ib_inefficiency = 120,
101 .clk_inefficiency = 125
102 },
103 .max_clk = 200000000,
104 };
105
106 static const struct mdp5_cfg_hw msm8x26_config = {
107 .name = "msm8x26",
108 .mdp = {
109 .count = 1,
110 .caps = MDP_CAP_SMP |
111 0,
112 },
113 .smp = {
114 .mmb_count = 7,
115 .mmb_size = 4096,
116 .clients = {
117 [SSPP_VIG0] = 1,
118 [SSPP_DMA0] = 4,
119 [SSPP_RGB0] = 7,
120 },
121 },
122 .ctl = {
123 .count = 2,
124 .base = { 0x00500, 0x00600 },
125 .flush_hw_mask = 0x0003ffff,
126 },
127 .pipe_vig = {
128 .count = 1,
129 .base = { 0x01100 },
130 .caps = MDP_PIPE_CAP_HFLIP |
131 MDP_PIPE_CAP_VFLIP |
132 MDP_PIPE_CAP_SCALE |
133 MDP_PIPE_CAP_CSC |
134 0,
135 },
136 .pipe_rgb = {
137 .count = 1,
138 .base = { 0x01d00 },
139 .caps = MDP_PIPE_CAP_HFLIP |
140 MDP_PIPE_CAP_VFLIP |
141 MDP_PIPE_CAP_SCALE |
142 0,
143 },
144 .pipe_dma = {
145 .count = 1,
146 .base = { 0x02900 },
147 .caps = MDP_PIPE_CAP_HFLIP |
148 MDP_PIPE_CAP_VFLIP |
149 0,
150 },
151 .lm = {
152 .count = 2,
153 .base = { 0x03100, 0x03d00 },
154 .instances = {
155 { .id = 0, .pp = 0, .dspp = 0,
156 .caps = MDP_LM_CAP_DISPLAY, },
157 { .id = 1, .pp = -1, .dspp = -1,
158 .caps = MDP_LM_CAP_WB },
159 },
160 .nb_stages = 2,
161 .max_width = 2048,
162 .max_height = 0xFFFF,
163 },
164 .dspp = {
165 .count = 1,
166 .base = { 0x04500 },
167 },
168 .pp = {
169 .count = 1,
170 .base = { 0x21a00 },
171 },
172 .intf = {
173 .base = { 0x00000, 0x21200 },
174 .connect = {
175 [0] = INTF_DISABLED,
176 [1] = INTF_DSI,
177 },
178 },
179 .perf = {
180 .ab_inefficiency = 100,
181 .ib_inefficiency = 200,
182 .clk_inefficiency = 125
183 },
184 .max_clk = 200000000,
185 };
186
187 static const struct mdp5_cfg_hw msm8x74v2_config = {
188 .name = "msm8x74",
189 .mdp = {
190 .count = 1,
191 .caps = MDP_CAP_SMP |
192 0,
193 },
194 .smp = {
195 .mmb_count = 22,
196 .mmb_size = 4096,
197 .clients = {
198 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
199 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
200 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
201 },
202 },
203 .ctl = {
204 .count = 5,
205 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
206 .flush_hw_mask = 0x0003ffff,
207 },
208 .pipe_vig = {
209 .count = 3,
210 .base = { 0x01100, 0x01500, 0x01900 },
211 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
212 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
213 MDP_PIPE_CAP_DECIMATION,
214 },
215 .pipe_rgb = {
216 .count = 3,
217 .base = { 0x01d00, 0x02100, 0x02500 },
218 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
219 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
220 },
221 .pipe_dma = {
222 .count = 2,
223 .base = { 0x02900, 0x02d00 },
224 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
225 },
226 .lm = {
227 .count = 5,
228 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
229 .instances = {
230 { .id = 0, .pp = 0, .dspp = 0,
231 .caps = MDP_LM_CAP_DISPLAY, },
232 { .id = 1, .pp = 1, .dspp = 1,
233 .caps = MDP_LM_CAP_DISPLAY, },
234 { .id = 2, .pp = 2, .dspp = 2,
235 .caps = MDP_LM_CAP_DISPLAY, },
236 { .id = 3, .pp = -1, .dspp = -1,
237 .caps = MDP_LM_CAP_WB, },
238 { .id = 4, .pp = -1, .dspp = -1,
239 .caps = MDP_LM_CAP_WB, },
240 },
241 .nb_stages = 5,
242 .max_width = 2048,
243 .max_height = 0xFFFF,
244 },
245 .dspp = {
246 .count = 3,
247 .base = { 0x04500, 0x04900, 0x04d00 },
248 },
249 .ad = {
250 .count = 2,
251 .base = { 0x13000, 0x13200 },
252 },
253 .pp = {
254 .count = 3,
255 .base = { 0x12c00, 0x12d00, 0x12e00 },
256 },
257 .intf = {
258 .base = { 0x12400, 0x12600, 0x12800, 0x12a00 },
259 .connect = {
260 [0] = INTF_eDP,
261 [1] = INTF_DSI,
262 [2] = INTF_DSI,
263 [3] = INTF_HDMI,
264 },
265 },
266 .perf = {
267 .ab_inefficiency = 200,
268 .ib_inefficiency = 120,
269 .clk_inefficiency = 125
270 },
271 .max_clk = 320000000,
272 };
273
274 static const struct mdp5_cfg_hw apq8084_config = {
275 .name = "apq8084",
276 .mdp = {
277 .count = 1,
278 .caps = MDP_CAP_SMP |
279 MDP_CAP_SRC_SPLIT |
280 0,
281 },
282 .smp = {
283 .mmb_count = 44,
284 .mmb_size = 8192,
285 .clients = {
286 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
287 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
288 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
289 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
290 [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
291 },
292 .reserved_state[0] = GENMASK(7, 0), /* first 8 MMBs */
293 .reserved = {
294 /* Two SMP blocks are statically tied to RGB pipes: */
295 [16] = 2, [17] = 2, [18] = 2, [22] = 2,
296 },
297 },
298 .ctl = {
299 .count = 5,
300 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
301 .flush_hw_mask = 0x003fffff,
302 },
303 .pipe_vig = {
304 .count = 4,
305 .base = { 0x01100, 0x01500, 0x01900, 0x01d00 },
306 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
307 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
308 MDP_PIPE_CAP_DECIMATION,
309 },
310 .pipe_rgb = {
311 .count = 4,
312 .base = { 0x02100, 0x02500, 0x02900, 0x02d00 },
313 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
314 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
315 },
316 .pipe_dma = {
317 .count = 2,
318 .base = { 0x03100, 0x03500 },
319 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
320 },
321 .lm = {
322 .count = 6,
323 .base = { 0x03900, 0x03d00, 0x04100, 0x04500, 0x04900, 0x04d00 },
324 .instances = {
325 { .id = 0, .pp = 0, .dspp = 0,
326 .caps = MDP_LM_CAP_DISPLAY |
327 MDP_LM_CAP_PAIR, },
328 { .id = 1, .pp = 1, .dspp = 1,
329 .caps = MDP_LM_CAP_DISPLAY, },
330 { .id = 2, .pp = 2, .dspp = 2,
331 .caps = MDP_LM_CAP_DISPLAY |
332 MDP_LM_CAP_PAIR, },
333 { .id = 3, .pp = -1, .dspp = -1,
334 .caps = MDP_LM_CAP_WB, },
335 { .id = 4, .pp = -1, .dspp = -1,
336 .caps = MDP_LM_CAP_WB, },
337 { .id = 5, .pp = 3, .dspp = 3,
338 .caps = MDP_LM_CAP_DISPLAY, },
339 },
340 .nb_stages = 5,
341 .max_width = 2048,
342 .max_height = 0xFFFF,
343 },
344 .dspp = {
345 .count = 4,
346 .base = { 0x05100, 0x05500, 0x05900, 0x05d00 },
347
348 },
349 .ad = {
350 .count = 3,
351 .base = { 0x13400, 0x13600, 0x13800 },
352 },
353 .pp = {
354 .count = 4,
355 .base = { 0x12e00, 0x12f00, 0x13000, 0x13100 },
356 },
357 .intf = {
358 .base = { 0x12400, 0x12600, 0x12800, 0x12a00, 0x12c00 },
359 .connect = {
360 [0] = INTF_eDP,
361 [1] = INTF_DSI,
362 [2] = INTF_DSI,
363 [3] = INTF_HDMI,
364 },
365 },
366 .perf = {
367 .ab_inefficiency = 200,
368 .ib_inefficiency = 120,
369 .clk_inefficiency = 105
370 },
371 .max_clk = 320000000,
372 };
373
374 static const struct mdp5_cfg_hw msm8x16_config = {
375 .name = "msm8x16",
376 .mdp = {
377 .count = 1,
378 .base = { 0x0 },
379 .caps = MDP_CAP_SMP |
380 0,
381 },
382 .smp = {
383 .mmb_count = 8,
384 .mmb_size = 8192,
385 .clients = {
386 [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
387 [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
388 },
389 },
390 .ctl = {
391 .count = 5,
392 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
393 .flush_hw_mask = 0x4003ffff,
394 },
395 .pipe_vig = {
396 .count = 1,
397 .base = { 0x04000 },
398 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
399 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
400 MDP_PIPE_CAP_DECIMATION,
401 },
402 .pipe_rgb = {
403 .count = 2,
404 .base = { 0x14000, 0x16000 },
405 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
406 MDP_PIPE_CAP_DECIMATION,
407 },
408 .pipe_dma = {
409 .count = 1,
410 .base = { 0x24000 },
411 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
412 },
413 .lm = {
414 .count = 2, /* LM0 and LM3 */
415 .base = { 0x44000, 0x47000 },
416 .instances = {
417 { .id = 0, .pp = 0, .dspp = 0,
418 .caps = MDP_LM_CAP_DISPLAY, },
419 { .id = 3, .pp = -1, .dspp = -1,
420 .caps = MDP_LM_CAP_WB },
421 },
422 .nb_stages = 8,
423 .max_width = 2048,
424 .max_height = 0xFFFF,
425 },
426 .dspp = {
427 .count = 1,
428 .base = { 0x54000 },
429
430 },
431 .intf = {
432 .base = { 0x00000, 0x6a800 },
433 .connect = {
434 [0] = INTF_DISABLED,
435 [1] = INTF_DSI,
436 },
437 },
438 .perf = {
439 .ab_inefficiency = 100,
440 .ib_inefficiency = 200,
441 .clk_inefficiency = 105
442 },
443 .max_clk = 320000000,
444 };
445
446 static const struct mdp5_cfg_hw msm8x36_config = {
447 .name = "msm8x36",
448 .mdp = {
449 .count = 1,
450 .base = { 0x0 },
451 .caps = MDP_CAP_SMP |
452 0,
453 },
454 .smp = {
455 .mmb_count = 8,
456 .mmb_size = 10240,
457 .clients = {
458 [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
459 [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
460 },
461 },
462 .ctl = {
463 .count = 3,
464 .base = { 0x01000, 0x01200, 0x01400 },
465 .flush_hw_mask = 0x4003ffff,
466 },
467 .pipe_vig = {
468 .count = 1,
469 .base = { 0x04000 },
470 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
471 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
472 MDP_PIPE_CAP_DECIMATION,
473 },
474 .pipe_rgb = {
475 .count = 2,
476 .base = { 0x14000, 0x16000 },
477 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
478 MDP_PIPE_CAP_DECIMATION,
479 },
480 .pipe_dma = {
481 .count = 1,
482 .base = { 0x24000 },
483 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
484 },
485 .lm = {
486 .count = 2,
487 .base = { 0x44000, 0x47000 },
488 .instances = {
489 { .id = 0, .pp = 0, .dspp = 0,
490 .caps = MDP_LM_CAP_DISPLAY, },
491 { .id = 1, .pp = -1, .dspp = -1,
492 .caps = MDP_LM_CAP_WB, },
493 },
494 .nb_stages = 8,
495 .max_width = 2560,
496 .max_height = 0xFFFF,
497 },
498 .pp = {
499 .count = 1,
500 .base = { 0x70000 },
501 },
502 .ad = {
503 .count = 1,
504 .base = { 0x78000 },
505 },
506 .dspp = {
507 .count = 1,
508 .base = { 0x54000 },
509 },
510 .intf = {
511 .base = { 0x00000, 0x6a800, 0x6b000 },
512 .connect = {
513 [0] = INTF_DISABLED,
514 [1] = INTF_DSI,
515 [2] = INTF_DSI,
516 },
517 },
518 .perf = {
519 .ab_inefficiency = 100,
520 .ib_inefficiency = 200,
521 .clk_inefficiency = 105
522 },
523 .max_clk = 366670000,
524 };
525
526 static const struct mdp5_cfg_hw msm8x94_config = {
527 .name = "msm8x94",
528 .mdp = {
529 .count = 1,
530 .caps = MDP_CAP_SMP |
531 MDP_CAP_SRC_SPLIT |
532 0,
533 },
534 .smp = {
535 .mmb_count = 44,
536 .mmb_size = 8192,
537 .clients = {
538 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
539 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
540 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
541 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
542 [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
543 },
544 .reserved_state[0] = GENMASK(23, 0), /* first 24 MMBs */
545 .reserved = {
546 [1] = 1, [4] = 1, [7] = 1, [19] = 1,
547 [16] = 5, [17] = 5, [18] = 5, [22] = 5,
548 },
549 },
550 .ctl = {
551 .count = 5,
552 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
553 .flush_hw_mask = 0xf0ffffff,
554 },
555 .pipe_vig = {
556 .count = 4,
557 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
558 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
559 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
560 MDP_PIPE_CAP_DECIMATION,
561 },
562 .pipe_rgb = {
563 .count = 4,
564 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
565 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
566 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
567 },
568 .pipe_dma = {
569 .count = 2,
570 .base = { 0x24000, 0x26000 },
571 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
572 },
573 .lm = {
574 .count = 6,
575 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
576 .instances = {
577 { .id = 0, .pp = 0, .dspp = 0,
578 .caps = MDP_LM_CAP_DISPLAY |
579 MDP_LM_CAP_PAIR, },
580 { .id = 1, .pp = 1, .dspp = 1,
581 .caps = MDP_LM_CAP_DISPLAY, },
582 { .id = 2, .pp = 2, .dspp = 2,
583 .caps = MDP_LM_CAP_DISPLAY |
584 MDP_LM_CAP_PAIR, },
585 { .id = 3, .pp = -1, .dspp = -1,
586 .caps = MDP_LM_CAP_WB, },
587 { .id = 4, .pp = -1, .dspp = -1,
588 .caps = MDP_LM_CAP_WB, },
589 { .id = 5, .pp = 3, .dspp = 3,
590 .caps = MDP_LM_CAP_DISPLAY, },
591 },
592 .nb_stages = 8,
593 .max_width = 2048,
594 .max_height = 0xFFFF,
595 },
596 .dspp = {
597 .count = 4,
598 .base = { 0x54000, 0x56000, 0x58000, 0x5a000 },
599
600 },
601 .ad = {
602 .count = 3,
603 .base = { 0x78000, 0x78800, 0x79000 },
604 },
605 .pp = {
606 .count = 4,
607 .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
608 },
609 .intf = {
610 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
611 .connect = {
612 [0] = INTF_DISABLED,
613 [1] = INTF_DSI,
614 [2] = INTF_DSI,
615 [3] = INTF_HDMI,
616 },
617 },
618 .perf = {
619 .ab_inefficiency = 100,
620 .ib_inefficiency = 100,
621 .clk_inefficiency = 105
622 },
623 .max_clk = 400000000,
624 };
625
626 static const struct mdp5_cfg_hw msm8x96_config = {
627 .name = "msm8x96",
628 .mdp = {
629 .count = 1,
630 .caps = MDP_CAP_DSC |
631 MDP_CAP_CDM |
632 MDP_CAP_SRC_SPLIT |
633 0,
634 },
635 .ctl = {
636 .count = 5,
637 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
638 .flush_hw_mask = 0xf4ffffff,
639 },
640 .pipe_vig = {
641 .count = 4,
642 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
643 .caps = MDP_PIPE_CAP_HFLIP |
644 MDP_PIPE_CAP_VFLIP |
645 MDP_PIPE_CAP_SCALE |
646 MDP_PIPE_CAP_CSC |
647 MDP_PIPE_CAP_DECIMATION |
648 MDP_PIPE_CAP_SW_PIX_EXT |
649 0,
650 },
651 .pipe_rgb = {
652 .count = 4,
653 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
654 .caps = MDP_PIPE_CAP_HFLIP |
655 MDP_PIPE_CAP_VFLIP |
656 MDP_PIPE_CAP_SCALE |
657 MDP_PIPE_CAP_DECIMATION |
658 MDP_PIPE_CAP_SW_PIX_EXT |
659 0,
660 },
661 .pipe_dma = {
662 .count = 2,
663 .base = { 0x24000, 0x26000 },
664 .caps = MDP_PIPE_CAP_HFLIP |
665 MDP_PIPE_CAP_VFLIP |
666 MDP_PIPE_CAP_SW_PIX_EXT |
667 0,
668 },
669 .pipe_cursor = {
670 .count = 2,
671 .base = { 0x34000, 0x36000 },
672 .caps = MDP_PIPE_CAP_HFLIP |
673 MDP_PIPE_CAP_VFLIP |
674 MDP_PIPE_CAP_SW_PIX_EXT |
675 MDP_PIPE_CAP_CURSOR |
676 0,
677 },
678
679 .lm = {
680 .count = 6,
681 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
682 .instances = {
683 { .id = 0, .pp = 0, .dspp = 0,
684 .caps = MDP_LM_CAP_DISPLAY |
685 MDP_LM_CAP_PAIR, },
686 { .id = 1, .pp = 1, .dspp = 1,
687 .caps = MDP_LM_CAP_DISPLAY, },
688 { .id = 2, .pp = 2, .dspp = -1,
689 .caps = MDP_LM_CAP_DISPLAY |
690 MDP_LM_CAP_PAIR, },
691 { .id = 3, .pp = -1, .dspp = -1,
692 .caps = MDP_LM_CAP_WB, },
693 { .id = 4, .pp = -1, .dspp = -1,
694 .caps = MDP_LM_CAP_WB, },
695 { .id = 5, .pp = 3, .dspp = -1,
696 .caps = MDP_LM_CAP_DISPLAY, },
697 },
698 .nb_stages = 8,
699 .max_width = 2560,
700 .max_height = 0xFFFF,
701 },
702 .dspp = {
703 .count = 2,
704 .base = { 0x54000, 0x56000 },
705 },
706 .ad = {
707 .count = 3,
708 .base = { 0x78000, 0x78800, 0x79000 },
709 },
710 .pp = {
711 .count = 4,
712 .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
713 },
714 .cdm = {
715 .count = 1,
716 .base = { 0x79200 },
717 },
718 .dsc = {
719 .count = 2,
720 .base = { 0x80000, 0x80400 },
721 },
722 .intf = {
723 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
724 .connect = {
725 [0] = INTF_DISABLED,
726 [1] = INTF_DSI,
727 [2] = INTF_DSI,
728 [3] = INTF_HDMI,
729 },
730 },
731 .perf = {
732 .ab_inefficiency = 100,
733 .ib_inefficiency = 200,
734 .clk_inefficiency = 105
735 },
736 .max_clk = 412500000,
737 };
738
739 static const struct mdp5_cfg_hw msm8x76_config = {
740 .name = "msm8x76",
741 .mdp = {
742 .count = 1,
743 .caps = MDP_CAP_SMP |
744 MDP_CAP_DSC |
745 MDP_CAP_SRC_SPLIT |
746 0,
747 },
748 .ctl = {
749 .count = 3,
750 .base = { 0x01000, 0x01200, 0x01400 },
751 .flush_hw_mask = 0xffffffff,
752 },
753 .smp = {
754 .mmb_count = 10,
755 .mmb_size = 10240,
756 .clients = {
757 [SSPP_VIG0] = 1, [SSPP_VIG1] = 9,
758 [SSPP_DMA0] = 4,
759 [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
760 },
761 },
762 .pipe_vig = {
763 .count = 2,
764 .base = { 0x04000, 0x06000 },
765 .caps = MDP_PIPE_CAP_HFLIP |
766 MDP_PIPE_CAP_VFLIP |
767 MDP_PIPE_CAP_SCALE |
768 MDP_PIPE_CAP_CSC |
769 MDP_PIPE_CAP_DECIMATION |
770 MDP_PIPE_CAP_SW_PIX_EXT |
771 0,
772 },
773 .pipe_rgb = {
774 .count = 2,
775 .base = { 0x14000, 0x16000 },
776 .caps = MDP_PIPE_CAP_HFLIP |
777 MDP_PIPE_CAP_VFLIP |
778 MDP_PIPE_CAP_DECIMATION |
779 MDP_PIPE_CAP_SW_PIX_EXT |
780 0,
781 },
782 .pipe_dma = {
783 .count = 1,
784 .base = { 0x24000 },
785 .caps = MDP_PIPE_CAP_HFLIP |
786 MDP_PIPE_CAP_VFLIP |
787 MDP_PIPE_CAP_SW_PIX_EXT |
788 0,
789 },
790 .pipe_cursor = {
791 .count = 1,
792 .base = { 0x440DC },
793 .caps = MDP_PIPE_CAP_HFLIP |
794 MDP_PIPE_CAP_VFLIP |
795 MDP_PIPE_CAP_SW_PIX_EXT |
796 MDP_PIPE_CAP_CURSOR |
797 0,
798 },
799 .lm = {
800 .count = 2,
801 .base = { 0x44000, 0x45000 },
802 .instances = {
803 { .id = 0, .pp = 0, .dspp = 0,
804 .caps = MDP_LM_CAP_DISPLAY, },
805 { .id = 1, .pp = -1, .dspp = -1,
806 .caps = MDP_LM_CAP_WB },
807 },
808 .nb_stages = 8,
809 .max_width = 2560,
810 .max_height = 0xFFFF,
811 },
812 .dspp = {
813 .count = 1,
814 .base = { 0x54000 },
815
816 },
817 .pp = {
818 .count = 3,
819 .base = { 0x70000, 0x70800, 0x72000 },
820 },
821 .dsc = {
822 .count = 2,
823 .base = { 0x80000, 0x80400 },
824 },
825 .intf = {
826 .base = { 0x6a000, 0x6a800, 0x6b000 },
827 .connect = {
828 [0] = INTF_DISABLED,
829 [1] = INTF_DSI,
830 [2] = INTF_DSI,
831 },
832 },
833 .max_clk = 360000000,
834 };
835
836 static const struct mdp5_cfg_hw msm8x53_config = {
837 .name = "msm8x53",
838 .mdp = {
839 .count = 1,
840 .caps = MDP_CAP_CDM |
841 MDP_CAP_SRC_SPLIT,
842 },
843 .ctl = {
844 .count = 3,
845 .base = { 0x01000, 0x01200, 0x01400 },
846 .flush_hw_mask = 0xffffffff,
847 },
848 .pipe_vig = {
849 .count = 1,
850 .base = { 0x04000 },
851 .caps = MDP_PIPE_CAP_HFLIP |
852 MDP_PIPE_CAP_VFLIP |
853 MDP_PIPE_CAP_SCALE |
854 MDP_PIPE_CAP_CSC |
855 MDP_PIPE_CAP_DECIMATION |
856 MDP_PIPE_CAP_SW_PIX_EXT |
857 0,
858 },
859 .pipe_rgb = {
860 .count = 2,
861 .base = { 0x14000, 0x16000 },
862 .caps = MDP_PIPE_CAP_HFLIP |
863 MDP_PIPE_CAP_VFLIP |
864 MDP_PIPE_CAP_DECIMATION |
865 MDP_PIPE_CAP_SW_PIX_EXT |
866 0,
867 },
868 .pipe_dma = {
869 .count = 1,
870 .base = { 0x24000 },
871 .caps = MDP_PIPE_CAP_HFLIP |
872 MDP_PIPE_CAP_VFLIP |
873 MDP_PIPE_CAP_SW_PIX_EXT |
874 0,
875 },
876 .pipe_cursor = {
877 .count = 1,
878 .base = { 0x34000 },
879 .caps = MDP_PIPE_CAP_HFLIP |
880 MDP_PIPE_CAP_VFLIP |
881 MDP_PIPE_CAP_SW_PIX_EXT |
882 MDP_PIPE_CAP_CURSOR |
883 0,
884 },
885
886 .lm = {
887 .count = 3,
888 .base = { 0x44000, 0x45000 },
889 .instances = {
890 { .id = 0, .pp = 0, .dspp = 0,
891 .caps = MDP_LM_CAP_DISPLAY |
892 MDP_LM_CAP_PAIR },
893 { .id = 1, .pp = 1, .dspp = -1,
894 .caps = MDP_LM_CAP_DISPLAY },
895 },
896 .nb_stages = 5,
897 .max_width = 2048,
898 .max_height = 0xFFFF,
899 },
900 .dspp = {
901 .count = 1,
902 .base = { 0x54000 },
903
904 },
905 .pp = {
906 .count = 2,
907 .base = { 0x70000, 0x70800 },
908 },
909 .cdm = {
910 .count = 1,
911 .base = { 0x79200 },
912 },
913 .intf = {
914 .base = { 0x6a000, 0x6a800, 0x6b000 },
915 .connect = {
916 [0] = INTF_DISABLED,
917 [1] = INTF_DSI,
918 [2] = INTF_DSI,
919 },
920 },
921 .perf = {
922 .ab_inefficiency = 100,
923 .ib_inefficiency = 200,
924 .clk_inefficiency = 105
925 },
926 .max_clk = 400000000,
927 };
928
929 static const struct mdp5_cfg_hw msm8917_config = {
930 .name = "msm8917",
931 .mdp = {
932 .count = 1,
933 .caps = MDP_CAP_CDM,
934 },
935 .ctl = {
936 .count = 3,
937 .base = { 0x01000, 0x01200, 0x01400 },
938 .flush_hw_mask = 0xffffffff,
939 },
940 .pipe_vig = {
941 .count = 1,
942 .base = { 0x04000 },
943 .caps = MDP_PIPE_CAP_HFLIP |
944 MDP_PIPE_CAP_VFLIP |
945 MDP_PIPE_CAP_SCALE |
946 MDP_PIPE_CAP_CSC |
947 MDP_PIPE_CAP_DECIMATION |
948 MDP_PIPE_CAP_SW_PIX_EXT |
949 0,
950 },
951 .pipe_rgb = {
952 .count = 2,
953 .base = { 0x14000, 0x16000 },
954 .caps = MDP_PIPE_CAP_HFLIP |
955 MDP_PIPE_CAP_VFLIP |
956 MDP_PIPE_CAP_DECIMATION |
957 MDP_PIPE_CAP_SW_PIX_EXT |
958 0,
959 },
960 .pipe_dma = {
961 .count = 1,
962 .base = { 0x24000 },
963 .caps = MDP_PIPE_CAP_HFLIP |
964 MDP_PIPE_CAP_VFLIP |
965 MDP_PIPE_CAP_SW_PIX_EXT |
966 0,
967 },
968 .pipe_cursor = {
969 .count = 1,
970 .base = { 0x34000 },
971 .caps = MDP_PIPE_CAP_HFLIP |
972 MDP_PIPE_CAP_VFLIP |
973 MDP_PIPE_CAP_SW_PIX_EXT |
974 MDP_PIPE_CAP_CURSOR |
975 0,
976 },
977
978 .lm = {
979 .count = 2,
980 .base = { 0x44000, 0x45000 },
981 .instances = {
982 { .id = 0, .pp = 0, .dspp = 0,
983 .caps = MDP_LM_CAP_DISPLAY, },
984 { .id = 1, .pp = -1, .dspp = -1,
985 .caps = MDP_LM_CAP_WB },
986 },
987 .nb_stages = 8,
988 .max_width = 2048,
989 .max_height = 0xFFFF,
990 },
991 .dspp = {
992 .count = 1,
993 .base = { 0x54000 },
994
995 },
996 .pp = {
997 .count = 1,
998 .base = { 0x70000 },
999 },
1000 .cdm = {
1001 .count = 1,
1002 .base = { 0x79200 },
1003 },
1004 .intf = {
1005 .base = { 0x6a000, 0x6a800 },
1006 .connect = {
1007 [0] = INTF_DISABLED,
1008 [1] = INTF_DSI,
1009 },
1010 },
1011 .max_clk = 320000000,
1012 };
1013
1014 static const struct mdp5_cfg_hw msm8998_config = {
1015 .name = "msm8998",
1016 .mdp = {
1017 .count = 1,
1018 .caps = MDP_CAP_DSC |
1019 MDP_CAP_CDM |
1020 MDP_CAP_SRC_SPLIT |
1021 0,
1022 },
1023 .ctl = {
1024 .count = 5,
1025 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
1026 .flush_hw_mask = 0xf7ffffff,
1027 },
1028 .pipe_vig = {
1029 .count = 4,
1030 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
1031 .caps = MDP_PIPE_CAP_HFLIP |
1032 MDP_PIPE_CAP_VFLIP |
1033 MDP_PIPE_CAP_SCALE |
1034 MDP_PIPE_CAP_CSC |
1035 MDP_PIPE_CAP_DECIMATION |
1036 MDP_PIPE_CAP_SW_PIX_EXT |
1037 0,
1038 },
1039 .pipe_rgb = {
1040 .count = 4,
1041 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
1042 .caps = MDP_PIPE_CAP_HFLIP |
1043 MDP_PIPE_CAP_VFLIP |
1044 MDP_PIPE_CAP_SCALE |
1045 MDP_PIPE_CAP_DECIMATION |
1046 MDP_PIPE_CAP_SW_PIX_EXT |
1047 0,
1048 },
1049 .pipe_dma = {
1050 .count = 2, /* driver supports max of 2 currently */
1051 .base = { 0x24000, 0x26000, 0x28000, 0x2a000 },
1052 .caps = MDP_PIPE_CAP_HFLIP |
1053 MDP_PIPE_CAP_VFLIP |
1054 MDP_PIPE_CAP_SW_PIX_EXT |
1055 0,
1056 },
1057 .pipe_cursor = {
1058 .count = 2,
1059 .base = { 0x34000, 0x36000 },
1060 .caps = MDP_PIPE_CAP_HFLIP |
1061 MDP_PIPE_CAP_VFLIP |
1062 MDP_PIPE_CAP_SW_PIX_EXT |
1063 MDP_PIPE_CAP_CURSOR |
1064 0,
1065 },
1066
1067 .lm = {
1068 .count = 6,
1069 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
1070 .instances = {
1071 { .id = 0, .pp = 0, .dspp = 0,
1072 .caps = MDP_LM_CAP_DISPLAY |
1073 MDP_LM_CAP_PAIR, },
1074 { .id = 1, .pp = 1, .dspp = 1,
1075 .caps = MDP_LM_CAP_DISPLAY, },
1076 { .id = 2, .pp = 2, .dspp = -1,
1077 .caps = MDP_LM_CAP_DISPLAY |
1078 MDP_LM_CAP_PAIR, },
1079 { .id = 3, .pp = -1, .dspp = -1,
1080 .caps = MDP_LM_CAP_WB, },
1081 { .id = 4, .pp = -1, .dspp = -1,
1082 .caps = MDP_LM_CAP_WB, },
1083 { .id = 5, .pp = 3, .dspp = -1,
1084 .caps = MDP_LM_CAP_DISPLAY, },
1085 },
1086 .nb_stages = 8,
1087 .max_width = 2560,
1088 .max_height = 0xFFFF,
1089 },
1090 .dspp = {
1091 .count = 2,
1092 .base = { 0x54000, 0x56000 },
1093 },
1094 .ad = {
1095 .count = 3,
1096 .base = { 0x78000, 0x78800, 0x79000 },
1097 },
1098 .pp = {
1099 .count = 4,
1100 .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
1101 },
1102 .cdm = {
1103 .count = 1,
1104 .base = { 0x79200 },
1105 },
1106 .dsc = {
1107 .count = 2,
1108 .base = { 0x80000, 0x80400 },
1109 },
1110 .intf = {
1111 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
1112 .connect = {
1113 [0] = INTF_eDP,
1114 [1] = INTF_DSI,
1115 [2] = INTF_DSI,
1116 [3] = INTF_HDMI,
1117 },
1118 },
1119 .max_clk = 412500000,
1120 };
1121
1122 static const struct mdp5_cfg_hw sdm630_config = {
1123 .name = "sdm630",
1124 .mdp = {
1125 .count = 1,
1126 .caps = MDP_CAP_CDM |
1127 MDP_CAP_SRC_SPLIT |
1128 0,
1129 },
1130 .ctl = {
1131 .count = 5,
1132 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
1133 .flush_hw_mask = 0xf4ffffff,
1134 },
1135 .pipe_vig = {
1136 .count = 1,
1137 .base = { 0x04000 },
1138 .caps = MDP_PIPE_CAP_HFLIP |
1139 MDP_PIPE_CAP_VFLIP |
1140 MDP_PIPE_CAP_SCALE |
1141 MDP_PIPE_CAP_CSC |
1142 MDP_PIPE_CAP_DECIMATION |
1143 MDP_PIPE_CAP_SW_PIX_EXT |
1144 0,
1145 },
1146 .pipe_rgb = {
1147 .count = 4,
1148 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
1149 .caps = MDP_PIPE_CAP_HFLIP |
1150 MDP_PIPE_CAP_VFLIP |
1151 MDP_PIPE_CAP_SCALE |
1152 MDP_PIPE_CAP_DECIMATION |
1153 MDP_PIPE_CAP_SW_PIX_EXT |
1154 0,
1155 },
1156 .pipe_dma = {
1157 .count = 2, /* driver supports max of 2 currently */
1158 .base = { 0x24000, 0x26000, 0x28000 },
1159 .caps = MDP_PIPE_CAP_HFLIP |
1160 MDP_PIPE_CAP_VFLIP |
1161 MDP_PIPE_CAP_SW_PIX_EXT |
1162 0,
1163 },
1164 .pipe_cursor = {
1165 .count = 1,
1166 .base = { 0x34000 },
1167 .caps = MDP_PIPE_CAP_HFLIP |
1168 MDP_PIPE_CAP_VFLIP |
1169 MDP_PIPE_CAP_SW_PIX_EXT |
1170 MDP_PIPE_CAP_CURSOR |
1171 0,
1172 },
1173
1174 .lm = {
1175 .count = 2,
1176 .base = { 0x44000, 0x46000 },
1177 .instances = {
1178 { .id = 0, .pp = 0, .dspp = 0,
1179 .caps = MDP_LM_CAP_DISPLAY |
1180 MDP_LM_CAP_PAIR, },
1181 { .id = 1, .pp = 1, .dspp = -1,
1182 .caps = MDP_LM_CAP_WB, },
1183 },
1184 .nb_stages = 8,
1185 .max_width = 2048,
1186 .max_height = 0xFFFF,
1187 },
1188 .dspp = {
1189 .count = 1,
1190 .base = { 0x54000 },
1191 },
1192 .ad = {
1193 .count = 2,
1194 .base = { 0x78000, 0x78800 },
1195 },
1196 .pp = {
1197 .count = 3,
1198 .base = { 0x70000, 0x71000, 0x72000 },
1199 },
1200 .cdm = {
1201 .count = 1,
1202 .base = { 0x79200 },
1203 },
1204 .intf = {
1205 .base = { 0x6a000, 0x6a800 },
1206 .connect = {
1207 [0] = INTF_DISABLED,
1208 [1] = INTF_DSI,
1209 },
1210 },
1211 .max_clk = 412500000,
1212 };
1213
1214 static const struct mdp5_cfg_hw sdm660_config = {
1215 .name = "sdm660",
1216 .mdp = {
1217 .count = 1,
1218 .caps = MDP_CAP_DSC |
1219 MDP_CAP_CDM |
1220 MDP_CAP_SRC_SPLIT |
1221 0,
1222 },
1223 .ctl = {
1224 .count = 5,
1225 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
1226 .flush_hw_mask = 0xf4ffffff,
1227 },
1228 .pipe_vig = {
1229 .count = 2,
1230 .base = { 0x04000, 0x6000 },
1231 .caps = MDP_PIPE_CAP_HFLIP |
1232 MDP_PIPE_CAP_VFLIP |
1233 MDP_PIPE_CAP_SCALE |
1234 MDP_PIPE_CAP_CSC |
1235 MDP_PIPE_CAP_DECIMATION |
1236 MDP_PIPE_CAP_SW_PIX_EXT |
1237 0,
1238 },
1239 .pipe_rgb = {
1240 .count = 4,
1241 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
1242 .caps = MDP_PIPE_CAP_HFLIP |
1243 MDP_PIPE_CAP_VFLIP |
1244 MDP_PIPE_CAP_SCALE |
1245 MDP_PIPE_CAP_DECIMATION |
1246 MDP_PIPE_CAP_SW_PIX_EXT |
1247 0,
1248 },
1249 .pipe_dma = {
1250 .count = 2, /* driver supports max of 2 currently */
1251 .base = { 0x24000, 0x26000, 0x28000 },
1252 .caps = MDP_PIPE_CAP_HFLIP |
1253 MDP_PIPE_CAP_VFLIP |
1254 MDP_PIPE_CAP_SW_PIX_EXT |
1255 0,
1256 },
1257 .pipe_cursor = {
1258 .count = 1,
1259 .base = { 0x34000 },
1260 .caps = MDP_PIPE_CAP_HFLIP |
1261 MDP_PIPE_CAP_VFLIP |
1262 MDP_PIPE_CAP_SW_PIX_EXT |
1263 MDP_PIPE_CAP_CURSOR |
1264 0,
1265 },
1266
1267 .lm = {
1268 .count = 4,
1269 .base = { 0x44000, 0x45000, 0x46000, 0x49000 },
1270 .instances = {
1271 { .id = 0, .pp = 0, .dspp = 0,
1272 .caps = MDP_LM_CAP_DISPLAY |
1273 MDP_LM_CAP_PAIR, },
1274 { .id = 1, .pp = 1, .dspp = 1,
1275 .caps = MDP_LM_CAP_DISPLAY, },
1276 { .id = 2, .pp = 2, .dspp = -1,
1277 .caps = MDP_LM_CAP_DISPLAY |
1278 MDP_LM_CAP_PAIR, },
1279 { .id = 3, .pp = 3, .dspp = -1,
1280 .caps = MDP_LM_CAP_WB, },
1281 },
1282 .nb_stages = 8,
1283 .max_width = 2560,
1284 .max_height = 0xFFFF,
1285 },
1286 .dspp = {
1287 .count = 2,
1288 .base = { 0x54000, 0x56000 },
1289 },
1290 .ad = {
1291 .count = 2,
1292 .base = { 0x78000, 0x78800 },
1293 },
1294 .pp = {
1295 .count = 5,
1296 .base = { 0x70000, 0x70800, 0x71000, 0x71800, 0x72000 },
1297 },
1298 .cdm = {
1299 .count = 1,
1300 .base = { 0x79200 },
1301 },
1302 .dsc = {
1303 .count = 2,
1304 .base = { 0x80000, 0x80400 },
1305 },
1306 .intf = {
1307 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800 },
1308 .connect = {
1309 [0] = INTF_DISABLED,
1310 [1] = INTF_DSI,
1311 [2] = INTF_DSI,
1312 [3] = INTF_HDMI,
1313 },
1314 },
1315 .max_clk = 412500000,
1316 };
1317
1318 static const struct mdp5_cfg_handler cfg_handlers_v1[] = {
1319 { .revision = 0, .config = { .hw = &msm8x74v1_config } },
1320 { .revision = 1, .config = { .hw = &msm8x26_config } },
1321 { .revision = 2, .config = { .hw = &msm8x74v2_config } },
1322 { .revision = 3, .config = { .hw = &apq8084_config } },
1323 { .revision = 6, .config = { .hw = &msm8x16_config } },
1324 { .revision = 8, .config = { .hw = &msm8x36_config } },
1325 { .revision = 9, .config = { .hw = &msm8x94_config } },
1326 { .revision = 7, .config = { .hw = &msm8x96_config } },
1327 { .revision = 11, .config = { .hw = &msm8x76_config } },
1328 { .revision = 15, .config = { .hw = &msm8917_config } },
1329 { .revision = 16, .config = { .hw = &msm8x53_config } },
1330 };
1331
1332 static const struct mdp5_cfg_handler cfg_handlers_v3[] = {
1333 { .revision = 0, .config = { .hw = &msm8998_config } },
1334 { .revision = 2, .config = { .hw = &sdm660_config } },
1335 { .revision = 3, .config = { .hw = &sdm630_config } },
1336 };
1337
mdp5_cfg_get_hw_config(struct mdp5_cfg_handler * cfg_handler)1338 const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *cfg_handler)
1339 {
1340 return cfg_handler->config.hw;
1341 }
1342
mdp5_cfg_get_config(struct mdp5_cfg_handler * cfg_handler)1343 struct mdp5_cfg *mdp5_cfg_get_config(struct mdp5_cfg_handler *cfg_handler)
1344 {
1345 return &cfg_handler->config;
1346 }
1347
mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler * cfg_handler)1348 int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_handler)
1349 {
1350 return cfg_handler->revision;
1351 }
1352
mdp5_cfg_destroy(struct mdp5_cfg_handler * cfg_handler)1353 void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_handler)
1354 {
1355 kfree(cfg_handler);
1356 }
1357
mdp5_cfg_init(struct mdp5_kms * mdp5_kms,uint32_t major,uint32_t minor)1358 struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
1359 uint32_t major, uint32_t minor)
1360 {
1361 struct drm_device *dev = mdp5_kms->dev;
1362 struct mdp5_cfg_handler *cfg_handler;
1363 const struct mdp5_cfg_handler *cfg_handlers;
1364 int i, ret = 0, num_handlers;
1365
1366 cfg_handler = kzalloc(sizeof(*cfg_handler), GFP_KERNEL);
1367 if (unlikely(!cfg_handler)) {
1368 ret = -ENOMEM;
1369 goto fail;
1370 }
1371
1372 switch (major) {
1373 case 1:
1374 cfg_handlers = cfg_handlers_v1;
1375 num_handlers = ARRAY_SIZE(cfg_handlers_v1);
1376 break;
1377 case 3:
1378 cfg_handlers = cfg_handlers_v3;
1379 num_handlers = ARRAY_SIZE(cfg_handlers_v3);
1380 break;
1381 default:
1382 DRM_DEV_ERROR(dev->dev, "unexpected MDP major version: v%d.%d\n",
1383 major, minor);
1384 ret = -ENXIO;
1385 goto fail;
1386 }
1387
1388 /* only after mdp5_cfg global pointer's init can we access the hw */
1389 for (i = 0; i < num_handlers; i++) {
1390 if (cfg_handlers[i].revision != minor)
1391 continue;
1392 mdp5_cfg = cfg_handlers[i].config.hw;
1393
1394 break;
1395 }
1396 if (unlikely(!mdp5_cfg)) {
1397 DRM_DEV_ERROR(dev->dev, "unexpected MDP minor revision: v%d.%d\n",
1398 major, minor);
1399 ret = -ENXIO;
1400 goto fail;
1401 }
1402
1403 cfg_handler->revision = minor;
1404 cfg_handler->config.hw = mdp5_cfg;
1405
1406 DBG("MDP5: %s hw config selected", mdp5_cfg->name);
1407
1408 return cfg_handler;
1409
1410 fail:
1411 if (cfg_handler)
1412 mdp5_cfg_destroy(cfg_handler);
1413
1414 return ERR_PTR(ret);
1415 }
1416
