1 /*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18
19 #include "msm_drv.h"
20 #include "msm_gem.h"
21 #include "msm_mmu.h"
22 #include "mdp4_kms.h"
23
24 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev);
25
mdp4_hw_init(struct msm_kms * kms)26 static int mdp4_hw_init(struct msm_kms *kms)
27 {
28 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
29 struct drm_device *dev = mdp4_kms->dev;
30 uint32_t version, major, minor, dmap_cfg, vg_cfg;
31 unsigned long clk;
32 int ret = 0;
33
34 pm_runtime_get_sync(dev->dev);
35
36 mdp4_enable(mdp4_kms);
37 version = mdp4_read(mdp4_kms, REG_MDP4_VERSION);
38 mdp4_disable(mdp4_kms);
39
40 major = FIELD(version, MDP4_VERSION_MAJOR);
41 minor = FIELD(version, MDP4_VERSION_MINOR);
42
43 DBG("found MDP4 version v%d.%d", major, minor);
44
45 if (major != 4) {
46 dev_err(dev->dev, "unexpected MDP version: v%d.%d\n",
47 major, minor);
48 ret = -ENXIO;
49 goto out;
50 }
51
52 mdp4_kms->rev = minor;
53
54 if (mdp4_kms->rev > 1) {
55 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);
56 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);
57 }
58
59 mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);
60
61 /* max read pending cmd config, 3 pending requests: */
62 mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);
63
64 clk = clk_get_rate(mdp4_kms->clk);
65
66 if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) {
67 dmap_cfg = 0x47; /* 16 bytes-burst x 8 req */
68 vg_cfg = 0x47; /* 16 bytes-burs x 8 req */
69 } else {
70 dmap_cfg = 0x27; /* 8 bytes-burst x 8 req */
71 vg_cfg = 0x43; /* 16 bytes-burst x 4 req */
72 }
73
74 DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg);
75
76 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);
77 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);
78
79 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);
80 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);
81 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);
82 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg);
83
84 if (mdp4_kms->rev >= 2)
85 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1);
86 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0);
87
88 /* disable CSC matrix / YUV by default: */
89 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0);
90 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0);
91 mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0);
92 mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0);
93 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0);
94 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0);
95
96 if (mdp4_kms->rev > 1)
97 mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);
98
99 dev->mode_config.allow_fb_modifiers = true;
100
101 out:
102 pm_runtime_put_sync(dev->dev);
103
104 return ret;
105 }
106
mdp4_prepare_commit(struct msm_kms * kms,struct drm_atomic_state * state)107 static void mdp4_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state)
108 {
109 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
110 int i;
111 struct drm_crtc *crtc;
112 struct drm_crtc_state *crtc_state;
113
114 mdp4_enable(mdp4_kms);
115
116 /* see 119ecb7fd */
117 for_each_new_crtc_in_state(state, crtc, crtc_state, i)
118 drm_crtc_vblank_get(crtc);
119 }
120
mdp4_complete_commit(struct msm_kms * kms,struct drm_atomic_state * state)121 static void mdp4_complete_commit(struct msm_kms *kms, struct drm_atomic_state *state)
122 {
123 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
124 int i;
125 struct drm_crtc *crtc;
126 struct drm_crtc_state *crtc_state;
127
128 drm_atomic_helper_wait_for_vblanks(mdp4_kms->dev, state);
129
130 /* see 119ecb7fd */
131 for_each_new_crtc_in_state(state, crtc, crtc_state, i)
132 drm_crtc_vblank_put(crtc);
133
134 mdp4_disable(mdp4_kms);
135 }
136
mdp4_wait_for_crtc_commit_done(struct msm_kms * kms,struct drm_crtc * crtc)137 static void mdp4_wait_for_crtc_commit_done(struct msm_kms *kms,
138 struct drm_crtc *crtc)
139 {
140 mdp4_crtc_wait_for_commit_done(crtc);
141 }
142
mdp4_round_pixclk(struct msm_kms * kms,unsigned long rate,struct drm_encoder * encoder)143 static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate,
144 struct drm_encoder *encoder)
145 {
146 /* if we had >1 encoder, we'd need something more clever: */
147 switch (encoder->encoder_type) {
148 case DRM_MODE_ENCODER_TMDS:
149 return mdp4_dtv_round_pixclk(encoder, rate);
150 case DRM_MODE_ENCODER_LVDS:
151 case DRM_MODE_ENCODER_DSI:
152 default:
153 return rate;
154 }
155 }
156
157 static const char * const iommu_ports[] = {
158 "mdp_port0_cb0", "mdp_port1_cb0",
159 };
160
mdp4_destroy(struct msm_kms * kms)161 static void mdp4_destroy(struct msm_kms *kms)
162 {
163 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
164 struct device *dev = mdp4_kms->dev->dev;
165 struct msm_gem_address_space *aspace = kms->aspace;
166
167 if (mdp4_kms->blank_cursor_iova)
168 msm_gem_put_iova(mdp4_kms->blank_cursor_bo, kms->aspace);
169 drm_gem_object_put_unlocked(mdp4_kms->blank_cursor_bo);
170
171 if (aspace) {
172 aspace->mmu->funcs->detach(aspace->mmu,
173 iommu_ports, ARRAY_SIZE(iommu_ports));
174 msm_gem_address_space_put(aspace);
175 }
176
177 if (mdp4_kms->rpm_enabled)
178 pm_runtime_disable(dev);
179
180 kfree(mdp4_kms);
181 }
182
183 static const struct mdp_kms_funcs kms_funcs = {
184 .base = {
185 .hw_init = mdp4_hw_init,
186 .irq_preinstall = mdp4_irq_preinstall,
187 .irq_postinstall = mdp4_irq_postinstall,
188 .irq_uninstall = mdp4_irq_uninstall,
189 .irq = mdp4_irq,
190 .enable_vblank = mdp4_enable_vblank,
191 .disable_vblank = mdp4_disable_vblank,
192 .prepare_commit = mdp4_prepare_commit,
193 .complete_commit = mdp4_complete_commit,
194 .wait_for_crtc_commit_done = mdp4_wait_for_crtc_commit_done,
195 .get_format = mdp_get_format,
196 .round_pixclk = mdp4_round_pixclk,
197 .destroy = mdp4_destroy,
198 },
199 .set_irqmask = mdp4_set_irqmask,
200 };
201
mdp4_disable(struct mdp4_kms * mdp4_kms)202 int mdp4_disable(struct mdp4_kms *mdp4_kms)
203 {
204 DBG("");
205
206 clk_disable_unprepare(mdp4_kms->clk);
207 if (mdp4_kms->pclk)
208 clk_disable_unprepare(mdp4_kms->pclk);
209 clk_disable_unprepare(mdp4_kms->lut_clk);
210 if (mdp4_kms->axi_clk)
211 clk_disable_unprepare(mdp4_kms->axi_clk);
212
213 return 0;
214 }
215
mdp4_enable(struct mdp4_kms * mdp4_kms)216 int mdp4_enable(struct mdp4_kms *mdp4_kms)
217 {
218 DBG("");
219
220 clk_prepare_enable(mdp4_kms->clk);
221 if (mdp4_kms->pclk)
222 clk_prepare_enable(mdp4_kms->pclk);
223 clk_prepare_enable(mdp4_kms->lut_clk);
224 if (mdp4_kms->axi_clk)
225 clk_prepare_enable(mdp4_kms->axi_clk);
226
227 return 0;
228 }
229
230
mdp4_modeset_init_intf(struct mdp4_kms * mdp4_kms,int intf_type)231 static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms,
232 int intf_type)
233 {
234 struct drm_device *dev = mdp4_kms->dev;
235 struct msm_drm_private *priv = dev->dev_private;
236 struct drm_encoder *encoder;
237 struct drm_connector *connector;
238 struct device_node *panel_node;
239 int dsi_id;
240 int ret;
241
242 switch (intf_type) {
243 case DRM_MODE_ENCODER_LVDS:
244 /*
245 * bail out early if there is no panel node (no need to
246 * initialize LCDC encoder and LVDS connector)
247 */
248 panel_node = of_graph_get_remote_node(dev->dev->of_node, 0, 0);
249 if (!panel_node)
250 return 0;
251
252 encoder = mdp4_lcdc_encoder_init(dev, panel_node);
253 if (IS_ERR(encoder)) {
254 dev_err(dev->dev, "failed to construct LCDC encoder\n");
255 return PTR_ERR(encoder);
256 }
257
258 /* LCDC can be hooked to DMA_P (TODO: Add DMA_S later?) */
259 encoder->possible_crtcs = 1 << DMA_P;
260
261 connector = mdp4_lvds_connector_init(dev, panel_node, encoder);
262 if (IS_ERR(connector)) {
263 dev_err(dev->dev, "failed to initialize LVDS connector\n");
264 return PTR_ERR(connector);
265 }
266
267 priv->encoders[priv->num_encoders++] = encoder;
268 priv->connectors[priv->num_connectors++] = connector;
269
270 break;
271 case DRM_MODE_ENCODER_TMDS:
272 encoder = mdp4_dtv_encoder_init(dev);
273 if (IS_ERR(encoder)) {
274 dev_err(dev->dev, "failed to construct DTV encoder\n");
275 return PTR_ERR(encoder);
276 }
277
278 /* DTV can be hooked to DMA_E: */
279 encoder->possible_crtcs = 1 << 1;
280
281 if (priv->hdmi) {
282 /* Construct bridge/connector for HDMI: */
283 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
284 if (ret) {
285 dev_err(dev->dev, "failed to initialize HDMI: %d\n", ret);
286 return ret;
287 }
288 }
289
290 priv->encoders[priv->num_encoders++] = encoder;
291
292 break;
293 case DRM_MODE_ENCODER_DSI:
294 /* only DSI1 supported for now */
295 dsi_id = 0;
296
297 if (!priv->dsi[dsi_id])
298 break;
299
300 encoder = mdp4_dsi_encoder_init(dev);
301 if (IS_ERR(encoder)) {
302 ret = PTR_ERR(encoder);
303 dev_err(dev->dev,
304 "failed to construct DSI encoder: %d\n", ret);
305 return ret;
306 }
307
308 /* TODO: Add DMA_S later? */
309 encoder->possible_crtcs = 1 << DMA_P;
310 priv->encoders[priv->num_encoders++] = encoder;
311
312 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder);
313 if (ret) {
314 dev_err(dev->dev, "failed to initialize DSI: %d\n",
315 ret);
316 return ret;
317 }
318
319 break;
320 default:
321 dev_err(dev->dev, "Invalid or unsupported interface\n");
322 return -EINVAL;
323 }
324
325 return 0;
326 }
327
modeset_init(struct mdp4_kms * mdp4_kms)328 static int modeset_init(struct mdp4_kms *mdp4_kms)
329 {
330 struct drm_device *dev = mdp4_kms->dev;
331 struct msm_drm_private *priv = dev->dev_private;
332 struct drm_plane *plane;
333 struct drm_crtc *crtc;
334 int i, ret;
335 static const enum mdp4_pipe rgb_planes[] = {
336 RGB1, RGB2,
337 };
338 static const enum mdp4_pipe vg_planes[] = {
339 VG1, VG2,
340 };
341 static const enum mdp4_dma mdp4_crtcs[] = {
342 DMA_P, DMA_E,
343 };
344 static const char * const mdp4_crtc_names[] = {
345 "DMA_P", "DMA_E",
346 };
347 static const int mdp4_intfs[] = {
348 DRM_MODE_ENCODER_LVDS,
349 DRM_MODE_ENCODER_DSI,
350 DRM_MODE_ENCODER_TMDS,
351 };
352
353 /* construct non-private planes: */
354 for (i = 0; i < ARRAY_SIZE(vg_planes); i++) {
355 plane = mdp4_plane_init(dev, vg_planes[i], false);
356 if (IS_ERR(plane)) {
357 dev_err(dev->dev,
358 "failed to construct plane for VG%d\n", i + 1);
359 ret = PTR_ERR(plane);
360 goto fail;
361 }
362 priv->planes[priv->num_planes++] = plane;
363 }
364
365 for (i = 0; i < ARRAY_SIZE(mdp4_crtcs); i++) {
366 plane = mdp4_plane_init(dev, rgb_planes[i], true);
367 if (IS_ERR(plane)) {
368 dev_err(dev->dev,
369 "failed to construct plane for RGB%d\n", i + 1);
370 ret = PTR_ERR(plane);
371 goto fail;
372 }
373
374 crtc = mdp4_crtc_init(dev, plane, priv->num_crtcs, i,
375 mdp4_crtcs[i]);
376 if (IS_ERR(crtc)) {
377 dev_err(dev->dev, "failed to construct crtc for %s\n",
378 mdp4_crtc_names[i]);
379 ret = PTR_ERR(crtc);
380 goto fail;
381 }
382
383 priv->crtcs[priv->num_crtcs++] = crtc;
384 }
385
386 /*
387 * we currently set up two relatively fixed paths:
388 *
389 * LCDC/LVDS path: RGB1 -> DMA_P -> LCDC -> LVDS
390 * or
391 * DSI path: RGB1 -> DMA_P -> DSI1 -> DSI Panel
392 *
393 * DTV/HDMI path: RGB2 -> DMA_E -> DTV -> HDMI
394 */
395
396 for (i = 0; i < ARRAY_SIZE(mdp4_intfs); i++) {
397 ret = mdp4_modeset_init_intf(mdp4_kms, mdp4_intfs[i]);
398 if (ret) {
399 dev_err(dev->dev, "failed to initialize intf: %d, %d\n",
400 i, ret);
401 goto fail;
402 }
403 }
404
405 return 0;
406
407 fail:
408 return ret;
409 }
410
mdp4_kms_init(struct drm_device * dev)411 struct msm_kms *mdp4_kms_init(struct drm_device *dev)
412 {
413 struct platform_device *pdev = to_platform_device(dev->dev);
414 struct mdp4_platform_config *config = mdp4_get_config(pdev);
415 struct mdp4_kms *mdp4_kms;
416 struct msm_kms *kms = NULL;
417 struct msm_gem_address_space *aspace;
418 int irq, ret;
419
420 mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL);
421 if (!mdp4_kms) {
422 dev_err(dev->dev, "failed to allocate kms\n");
423 ret = -ENOMEM;
424 goto fail;
425 }
426
427 mdp_kms_init(&mdp4_kms->base, &kms_funcs);
428
429 kms = &mdp4_kms->base.base;
430
431 mdp4_kms->dev = dev;
432
433 mdp4_kms->mmio = msm_ioremap(pdev, NULL, "MDP4");
434 if (IS_ERR(mdp4_kms->mmio)) {
435 ret = PTR_ERR(mdp4_kms->mmio);
436 goto fail;
437 }
438
439 irq = platform_get_irq(pdev, 0);
440 if (irq < 0) {
441 ret = irq;
442 dev_err(dev->dev, "failed to get irq: %d\n", ret);
443 goto fail;
444 }
445
446 kms->irq = irq;
447
448 /* NOTE: driver for this regulator still missing upstream.. use
449 * _get_exclusive() and ignore the error if it does not exist
450 * (and hope that the bootloader left it on for us)
451 */
452 mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd");
453 if (IS_ERR(mdp4_kms->vdd))
454 mdp4_kms->vdd = NULL;
455
456 if (mdp4_kms->vdd) {
457 ret = regulator_enable(mdp4_kms->vdd);
458 if (ret) {
459 dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret);
460 goto fail;
461 }
462 }
463
464 mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk");
465 if (IS_ERR(mdp4_kms->clk)) {
466 dev_err(dev->dev, "failed to get core_clk\n");
467 ret = PTR_ERR(mdp4_kms->clk);
468 goto fail;
469 }
470
471 mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk");
472 if (IS_ERR(mdp4_kms->pclk))
473 mdp4_kms->pclk = NULL;
474
475 // XXX if (rev >= MDP_REV_42) { ???
476 mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk");
477 if (IS_ERR(mdp4_kms->lut_clk)) {
478 dev_err(dev->dev, "failed to get lut_clk\n");
479 ret = PTR_ERR(mdp4_kms->lut_clk);
480 goto fail;
481 }
482
483 mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "bus_clk");
484 if (IS_ERR(mdp4_kms->axi_clk)) {
485 dev_err(dev->dev, "failed to get axi_clk\n");
486 ret = PTR_ERR(mdp4_kms->axi_clk);
487 goto fail;
488 }
489
490 clk_set_rate(mdp4_kms->clk, config->max_clk);
491 clk_set_rate(mdp4_kms->lut_clk, config->max_clk);
492
493 pm_runtime_enable(dev->dev);
494 mdp4_kms->rpm_enabled = true;
495
496 /* make sure things are off before attaching iommu (bootloader could
497 * have left things on, in which case we'll start getting faults if
498 * we don't disable):
499 */
500 mdp4_enable(mdp4_kms);
501 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
502 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
503 mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
504 mdp4_disable(mdp4_kms);
505 mdelay(16);
506
507 if (config->iommu) {
508 aspace = msm_gem_address_space_create(&pdev->dev,
509 config->iommu, "mdp4");
510 if (IS_ERR(aspace)) {
511 ret = PTR_ERR(aspace);
512 goto fail;
513 }
514
515 kms->aspace = aspace;
516
517 ret = aspace->mmu->funcs->attach(aspace->mmu, iommu_ports,
518 ARRAY_SIZE(iommu_ports));
519 if (ret)
520 goto fail;
521 } else {
522 dev_info(dev->dev, "no iommu, fallback to phys "
523 "contig buffers for scanout\n");
524 aspace = NULL;
525 }
526
527 ret = modeset_init(mdp4_kms);
528 if (ret) {
529 dev_err(dev->dev, "modeset_init failed: %d\n", ret);
530 goto fail;
531 }
532
533 mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC);
534 if (IS_ERR(mdp4_kms->blank_cursor_bo)) {
535 ret = PTR_ERR(mdp4_kms->blank_cursor_bo);
536 dev_err(dev->dev, "could not allocate blank-cursor bo: %d\n", ret);
537 mdp4_kms->blank_cursor_bo = NULL;
538 goto fail;
539 }
540
541 ret = msm_gem_get_iova(mdp4_kms->blank_cursor_bo, kms->aspace,
542 &mdp4_kms->blank_cursor_iova);
543 if (ret) {
544 dev_err(dev->dev, "could not pin blank-cursor bo: %d\n", ret);
545 goto fail;
546 }
547
548 dev->mode_config.min_width = 0;
549 dev->mode_config.min_height = 0;
550 dev->mode_config.max_width = 2048;
551 dev->mode_config.max_height = 2048;
552
553 return kms;
554
555 fail:
556 if (kms)
557 mdp4_destroy(kms);
558 return ERR_PTR(ret);
559 }
560
mdp4_get_config(struct platform_device * dev)561 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev)
562 {
563 static struct mdp4_platform_config config = {};
564
565 /* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */
566 config.max_clk = 266667000;
567 config.iommu = iommu_domain_alloc(&platform_bus_type);
568 if (config.iommu) {
569 config.iommu->geometry.aperture_start = 0x1000;
570 config.iommu->geometry.aperture_end = 0xffffffff;
571 }
572
573 return &config;
574 }
575
