1 /*
2 * Copyright 2009-2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * loosely based on an earlier driver that has
6 * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
7 *
8 * This program is free software; you can redistribute it and/or modify it under
9 * the terms of the GNU General Public License version 2 as published by the
10 * Free Software Foundation.
11 */
12
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
17 #include <linux/mfd/core.h>
18
19 #include "mc13xxx.h"
20
21 #define MC13XXX_IRQSTAT0 0
22 #define MC13XXX_IRQMASK0 1
23 #define MC13XXX_IRQSTAT1 3
24 #define MC13XXX_IRQMASK1 4
25
26 #define MC13XXX_REVISION 7
27 #define MC13XXX_REVISION_REVMETAL (0x07 << 0)
28 #define MC13XXX_REVISION_REVFULL (0x03 << 3)
29 #define MC13XXX_REVISION_ICID (0x07 << 6)
30 #define MC13XXX_REVISION_FIN (0x03 << 9)
31 #define MC13XXX_REVISION_FAB (0x03 << 11)
32 #define MC13XXX_REVISION_ICIDCODE (0x3f << 13)
33
34 #define MC34708_REVISION_REVMETAL (0x07 << 0)
35 #define MC34708_REVISION_REVFULL (0x07 << 3)
36 #define MC34708_REVISION_FIN (0x07 << 6)
37 #define MC34708_REVISION_FAB (0x07 << 9)
38
39 #define MC13XXX_PWRCTRL 15
40 #define MC13XXX_PWRCTRL_WDIRESET (1 << 12)
41
42 #define MC13XXX_ADC1 44
43 #define MC13XXX_ADC1_ADEN (1 << 0)
44 #define MC13XXX_ADC1_RAND (1 << 1)
45 #define MC13XXX_ADC1_ADSEL (1 << 3)
46 #define MC13XXX_ADC1_ASC (1 << 20)
47 #define MC13XXX_ADC1_ADTRIGIGN (1 << 21)
48
49 #define MC13XXX_ADC2 45
50
mc13xxx_lock(struct mc13xxx * mc13xxx)51 void mc13xxx_lock(struct mc13xxx *mc13xxx)
52 {
53 if (!mutex_trylock(&mc13xxx->lock)) {
54 dev_dbg(mc13xxx->dev, "wait for %s from %ps\n",
55 __func__, __builtin_return_address(0));
56
57 mutex_lock(&mc13xxx->lock);
58 }
59 dev_dbg(mc13xxx->dev, "%s from %ps\n",
60 __func__, __builtin_return_address(0));
61 }
62 EXPORT_SYMBOL(mc13xxx_lock);
63
mc13xxx_unlock(struct mc13xxx * mc13xxx)64 void mc13xxx_unlock(struct mc13xxx *mc13xxx)
65 {
66 dev_dbg(mc13xxx->dev, "%s from %ps\n",
67 __func__, __builtin_return_address(0));
68 mutex_unlock(&mc13xxx->lock);
69 }
70 EXPORT_SYMBOL(mc13xxx_unlock);
71
mc13xxx_reg_read(struct mc13xxx * mc13xxx,unsigned int offset,u32 * val)72 int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
73 {
74 int ret;
75
76 ret = regmap_read(mc13xxx->regmap, offset, val);
77 dev_vdbg(mc13xxx->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
78
79 return ret;
80 }
81 EXPORT_SYMBOL(mc13xxx_reg_read);
82
mc13xxx_reg_write(struct mc13xxx * mc13xxx,unsigned int offset,u32 val)83 int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
84 {
85 dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x\n", offset, val);
86
87 if (val >= BIT(24))
88 return -EINVAL;
89
90 return regmap_write(mc13xxx->regmap, offset, val);
91 }
92 EXPORT_SYMBOL(mc13xxx_reg_write);
93
mc13xxx_reg_rmw(struct mc13xxx * mc13xxx,unsigned int offset,u32 mask,u32 val)94 int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
95 u32 mask, u32 val)
96 {
97 BUG_ON(val & ~mask);
98 dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x (mask: 0x%06x)\n",
99 offset, val, mask);
100
101 return regmap_update_bits(mc13xxx->regmap, offset, mask, val);
102 }
103 EXPORT_SYMBOL(mc13xxx_reg_rmw);
104
mc13xxx_irq_mask(struct mc13xxx * mc13xxx,int irq)105 int mc13xxx_irq_mask(struct mc13xxx *mc13xxx, int irq)
106 {
107 int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);
108
109 disable_irq_nosync(virq);
110
111 return 0;
112 }
113 EXPORT_SYMBOL(mc13xxx_irq_mask);
114
mc13xxx_irq_unmask(struct mc13xxx * mc13xxx,int irq)115 int mc13xxx_irq_unmask(struct mc13xxx *mc13xxx, int irq)
116 {
117 int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);
118
119 enable_irq(virq);
120
121 return 0;
122 }
123 EXPORT_SYMBOL(mc13xxx_irq_unmask);
124
mc13xxx_irq_status(struct mc13xxx * mc13xxx,int irq,int * enabled,int * pending)125 int mc13xxx_irq_status(struct mc13xxx *mc13xxx, int irq,
126 int *enabled, int *pending)
127 {
128 int ret;
129 unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
130 unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
131 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
132
133 if (irq < 0 || irq >= ARRAY_SIZE(mc13xxx->irqs))
134 return -EINVAL;
135
136 if (enabled) {
137 u32 mask;
138
139 ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
140 if (ret)
141 return ret;
142
143 *enabled = mask & irqbit;
144 }
145
146 if (pending) {
147 u32 stat;
148
149 ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
150 if (ret)
151 return ret;
152
153 *pending = stat & irqbit;
154 }
155
156 return 0;
157 }
158 EXPORT_SYMBOL(mc13xxx_irq_status);
159
mc13xxx_irq_request(struct mc13xxx * mc13xxx,int irq,irq_handler_t handler,const char * name,void * dev)160 int mc13xxx_irq_request(struct mc13xxx *mc13xxx, int irq,
161 irq_handler_t handler, const char *name, void *dev)
162 {
163 int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);
164
165 return devm_request_threaded_irq(mc13xxx->dev, virq, NULL, handler,
166 IRQF_ONESHOT, name, dev);
167 }
168 EXPORT_SYMBOL(mc13xxx_irq_request);
169
mc13xxx_irq_free(struct mc13xxx * mc13xxx,int irq,void * dev)170 int mc13xxx_irq_free(struct mc13xxx *mc13xxx, int irq, void *dev)
171 {
172 int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);
173
174 devm_free_irq(mc13xxx->dev, virq, dev);
175
176 return 0;
177 }
178 EXPORT_SYMBOL(mc13xxx_irq_free);
179
180 #define maskval(reg, mask) (((reg) & (mask)) >> __ffs(mask))
mc13xxx_print_revision(struct mc13xxx * mc13xxx,u32 revision)181 static void mc13xxx_print_revision(struct mc13xxx *mc13xxx, u32 revision)
182 {
183 dev_info(mc13xxx->dev, "%s: rev: %d.%d, "
184 "fin: %d, fab: %d, icid: %d/%d\n",
185 mc13xxx->variant->name,
186 maskval(revision, MC13XXX_REVISION_REVFULL),
187 maskval(revision, MC13XXX_REVISION_REVMETAL),
188 maskval(revision, MC13XXX_REVISION_FIN),
189 maskval(revision, MC13XXX_REVISION_FAB),
190 maskval(revision, MC13XXX_REVISION_ICID),
191 maskval(revision, MC13XXX_REVISION_ICIDCODE));
192 }
193
mc34708_print_revision(struct mc13xxx * mc13xxx,u32 revision)194 static void mc34708_print_revision(struct mc13xxx *mc13xxx, u32 revision)
195 {
196 dev_info(mc13xxx->dev, "%s: rev %d.%d, fin: %d, fab: %d\n",
197 mc13xxx->variant->name,
198 maskval(revision, MC34708_REVISION_REVFULL),
199 maskval(revision, MC34708_REVISION_REVMETAL),
200 maskval(revision, MC34708_REVISION_FIN),
201 maskval(revision, MC34708_REVISION_FAB));
202 }
203
204 /* These are only exported for mc13xxx-i2c and mc13xxx-spi */
205 struct mc13xxx_variant mc13xxx_variant_mc13783 = {
206 .name = "mc13783",
207 .print_revision = mc13xxx_print_revision,
208 };
209 EXPORT_SYMBOL_GPL(mc13xxx_variant_mc13783);
210
211 struct mc13xxx_variant mc13xxx_variant_mc13892 = {
212 .name = "mc13892",
213 .print_revision = mc13xxx_print_revision,
214 };
215 EXPORT_SYMBOL_GPL(mc13xxx_variant_mc13892);
216
217 struct mc13xxx_variant mc13xxx_variant_mc34708 = {
218 .name = "mc34708",
219 .print_revision = mc34708_print_revision,
220 };
221 EXPORT_SYMBOL_GPL(mc13xxx_variant_mc34708);
222
mc13xxx_get_chipname(struct mc13xxx * mc13xxx)223 static const char *mc13xxx_get_chipname(struct mc13xxx *mc13xxx)
224 {
225 return mc13xxx->variant->name;
226 }
227
mc13xxx_get_flags(struct mc13xxx * mc13xxx)228 int mc13xxx_get_flags(struct mc13xxx *mc13xxx)
229 {
230 return mc13xxx->flags;
231 }
232 EXPORT_SYMBOL(mc13xxx_get_flags);
233
234 #define MC13XXX_ADC1_CHAN0_SHIFT 5
235 #define MC13XXX_ADC1_CHAN1_SHIFT 8
236 #define MC13783_ADC1_ATO_SHIFT 11
237 #define MC13783_ADC1_ATOX (1 << 19)
238
239 struct mc13xxx_adcdone_data {
240 struct mc13xxx *mc13xxx;
241 struct completion done;
242 };
243
mc13xxx_handler_adcdone(int irq,void * data)244 static irqreturn_t mc13xxx_handler_adcdone(int irq, void *data)
245 {
246 struct mc13xxx_adcdone_data *adcdone_data = data;
247
248 complete_all(&adcdone_data->done);
249
250 return IRQ_HANDLED;
251 }
252
253 #define MC13XXX_ADC_WORKING (1 << 0)
254
mc13xxx_adc_do_conversion(struct mc13xxx * mc13xxx,unsigned int mode,unsigned int channel,u8 ato,bool atox,unsigned int * sample)255 int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, unsigned int mode,
256 unsigned int channel, u8 ato, bool atox,
257 unsigned int *sample)
258 {
259 u32 adc0, adc1, old_adc0;
260 int i, ret;
261 struct mc13xxx_adcdone_data adcdone_data = {
262 .mc13xxx = mc13xxx,
263 };
264 init_completion(&adcdone_data.done);
265
266 dev_dbg(mc13xxx->dev, "%s\n", __func__);
267
268 mc13xxx_lock(mc13xxx);
269
270 if (mc13xxx->adcflags & MC13XXX_ADC_WORKING) {
271 ret = -EBUSY;
272 goto out;
273 }
274
275 mc13xxx->adcflags |= MC13XXX_ADC_WORKING;
276
277 mc13xxx_reg_read(mc13xxx, MC13XXX_ADC0, &old_adc0);
278
279 adc0 = MC13XXX_ADC0_ADINC1 | MC13XXX_ADC0_ADINC2;
280 adc1 = MC13XXX_ADC1_ADEN | MC13XXX_ADC1_ADTRIGIGN | MC13XXX_ADC1_ASC;
281
282 /*
283 * Channels mapped through ADIN7:
284 * 7 - General purpose ADIN7
285 * 16 - UID
286 * 17 - Die temperature
287 */
288 if (channel > 7 && channel < 16) {
289 adc1 |= MC13XXX_ADC1_ADSEL;
290 } else if (channel == 16) {
291 adc0 |= MC13XXX_ADC0_ADIN7SEL_UID;
292 channel = 7;
293 } else if (channel == 17) {
294 adc0 |= MC13XXX_ADC0_ADIN7SEL_DIE;
295 channel = 7;
296 }
297
298 switch (mode) {
299 case MC13XXX_ADC_MODE_TS:
300 adc0 |= MC13XXX_ADC0_ADREFEN | MC13XXX_ADC0_TSMOD0 |
301 MC13XXX_ADC0_TSMOD1;
302 adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
303 break;
304
305 case MC13XXX_ADC_MODE_SINGLE_CHAN:
306 adc0 |= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
307 adc1 |= (channel & 0x7) << MC13XXX_ADC1_CHAN0_SHIFT;
308 adc1 |= MC13XXX_ADC1_RAND;
309 break;
310
311 case MC13XXX_ADC_MODE_MULT_CHAN:
312 adc0 |= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
313 adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
314 break;
315
316 default:
317 mc13xxx_unlock(mc13xxx);
318 return -EINVAL;
319 }
320
321 adc1 |= ato << MC13783_ADC1_ATO_SHIFT;
322 if (atox)
323 adc1 |= MC13783_ADC1_ATOX;
324
325 dev_dbg(mc13xxx->dev, "%s: request irq\n", __func__);
326 mc13xxx_irq_request(mc13xxx, MC13XXX_IRQ_ADCDONE,
327 mc13xxx_handler_adcdone, __func__, &adcdone_data);
328
329 mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, adc0);
330 mc13xxx_reg_write(mc13xxx, MC13XXX_ADC1, adc1);
331
332 mc13xxx_unlock(mc13xxx);
333
334 ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);
335
336 if (!ret)
337 ret = -ETIMEDOUT;
338
339 mc13xxx_lock(mc13xxx);
340
341 mc13xxx_irq_free(mc13xxx, MC13XXX_IRQ_ADCDONE, &adcdone_data);
342
343 if (ret > 0)
344 for (i = 0; i < 4; ++i) {
345 ret = mc13xxx_reg_read(mc13xxx,
346 MC13XXX_ADC2, &sample[i]);
347 if (ret)
348 break;
349 }
350
351 if (mode == MC13XXX_ADC_MODE_TS)
352 /* restore TSMOD */
353 mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, old_adc0);
354
355 mc13xxx->adcflags &= ~MC13XXX_ADC_WORKING;
356 out:
357 mc13xxx_unlock(mc13xxx);
358
359 return ret;
360 }
361 EXPORT_SYMBOL_GPL(mc13xxx_adc_do_conversion);
362
mc13xxx_add_subdevice_pdata(struct mc13xxx * mc13xxx,const char * format,void * pdata,size_t pdata_size)363 static int mc13xxx_add_subdevice_pdata(struct mc13xxx *mc13xxx,
364 const char *format, void *pdata, size_t pdata_size)
365 {
366 char buf[30];
367 const char *name = mc13xxx_get_chipname(mc13xxx);
368
369 struct mfd_cell cell = {
370 .platform_data = pdata,
371 .pdata_size = pdata_size,
372 };
373
374 /* there is no asnprintf in the kernel :-( */
375 if (snprintf(buf, sizeof(buf), format, name) > sizeof(buf))
376 return -E2BIG;
377
378 cell.name = kmemdup(buf, strlen(buf) + 1, GFP_KERNEL);
379 if (!cell.name)
380 return -ENOMEM;
381
382 return mfd_add_devices(mc13xxx->dev, -1, &cell, 1, NULL, 0,
383 regmap_irq_get_domain(mc13xxx->irq_data));
384 }
385
mc13xxx_add_subdevice(struct mc13xxx * mc13xxx,const char * format)386 static int mc13xxx_add_subdevice(struct mc13xxx *mc13xxx, const char *format)
387 {
388 return mc13xxx_add_subdevice_pdata(mc13xxx, format, NULL, 0);
389 }
390
391 #ifdef CONFIG_OF
mc13xxx_probe_flags_dt(struct mc13xxx * mc13xxx)392 static int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
393 {
394 struct device_node *np = mc13xxx->dev->of_node;
395
396 if (!np)
397 return -ENODEV;
398
399 if (of_property_read_bool(np, "fsl,mc13xxx-uses-adc"))
400 mc13xxx->flags |= MC13XXX_USE_ADC;
401
402 if (of_property_read_bool(np, "fsl,mc13xxx-uses-codec"))
403 mc13xxx->flags |= MC13XXX_USE_CODEC;
404
405 if (of_property_read_bool(np, "fsl,mc13xxx-uses-rtc"))
406 mc13xxx->flags |= MC13XXX_USE_RTC;
407
408 if (of_property_read_bool(np, "fsl,mc13xxx-uses-touch"))
409 mc13xxx->flags |= MC13XXX_USE_TOUCHSCREEN;
410
411 return 0;
412 }
413 #else
mc13xxx_probe_flags_dt(struct mc13xxx * mc13xxx)414 static inline int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
415 {
416 return -ENODEV;
417 }
418 #endif
419
mc13xxx_common_init(struct device * dev)420 int mc13xxx_common_init(struct device *dev)
421 {
422 struct mc13xxx_platform_data *pdata = dev_get_platdata(dev);
423 struct mc13xxx *mc13xxx = dev_get_drvdata(dev);
424 u32 revision;
425 int i, ret;
426
427 mc13xxx->dev = dev;
428
429 ret = mc13xxx_reg_read(mc13xxx, MC13XXX_REVISION, &revision);
430 if (ret)
431 return ret;
432
433 mc13xxx->variant->print_revision(mc13xxx, revision);
434
435 ret = mc13xxx_reg_rmw(mc13xxx, MC13XXX_PWRCTRL,
436 MC13XXX_PWRCTRL_WDIRESET, MC13XXX_PWRCTRL_WDIRESET);
437 if (ret)
438 return ret;
439
440 for (i = 0; i < ARRAY_SIZE(mc13xxx->irqs); i++) {
441 mc13xxx->irqs[i].reg_offset = i / MC13XXX_IRQ_PER_REG;
442 mc13xxx->irqs[i].mask = BIT(i % MC13XXX_IRQ_PER_REG);
443 }
444
445 mc13xxx->irq_chip.name = dev_name(dev);
446 mc13xxx->irq_chip.status_base = MC13XXX_IRQSTAT0;
447 mc13xxx->irq_chip.mask_base = MC13XXX_IRQMASK0;
448 mc13xxx->irq_chip.ack_base = MC13XXX_IRQSTAT0;
449 mc13xxx->irq_chip.irq_reg_stride = MC13XXX_IRQSTAT1 - MC13XXX_IRQSTAT0;
450 mc13xxx->irq_chip.init_ack_masked = true;
451 mc13xxx->irq_chip.use_ack = true;
452 mc13xxx->irq_chip.num_regs = MC13XXX_IRQ_REG_CNT;
453 mc13xxx->irq_chip.irqs = mc13xxx->irqs;
454 mc13xxx->irq_chip.num_irqs = ARRAY_SIZE(mc13xxx->irqs);
455
456 ret = regmap_add_irq_chip(mc13xxx->regmap, mc13xxx->irq, IRQF_ONESHOT,
457 0, &mc13xxx->irq_chip, &mc13xxx->irq_data);
458 if (ret)
459 return ret;
460
461 mutex_init(&mc13xxx->lock);
462
463 if (mc13xxx_probe_flags_dt(mc13xxx) < 0 && pdata)
464 mc13xxx->flags = pdata->flags;
465
466 if (pdata) {
467 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-regulator",
468 &pdata->regulators, sizeof(pdata->regulators));
469 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-led",
470 pdata->leds, sizeof(*pdata->leds));
471 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-pwrbutton",
472 pdata->buttons, sizeof(*pdata->buttons));
473 if (mc13xxx->flags & MC13XXX_USE_CODEC)
474 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-codec",
475 pdata->codec, sizeof(*pdata->codec));
476 if (mc13xxx->flags & MC13XXX_USE_TOUCHSCREEN)
477 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-ts",
478 &pdata->touch, sizeof(pdata->touch));
479 } else {
480 mc13xxx_add_subdevice(mc13xxx, "%s-regulator");
481 mc13xxx_add_subdevice(mc13xxx, "%s-led");
482 mc13xxx_add_subdevice(mc13xxx, "%s-pwrbutton");
483 if (mc13xxx->flags & MC13XXX_USE_CODEC)
484 mc13xxx_add_subdevice(mc13xxx, "%s-codec");
485 if (mc13xxx->flags & MC13XXX_USE_TOUCHSCREEN)
486 mc13xxx_add_subdevice(mc13xxx, "%s-ts");
487 }
488
489 if (mc13xxx->flags & MC13XXX_USE_ADC)
490 mc13xxx_add_subdevice(mc13xxx, "%s-adc");
491
492 if (mc13xxx->flags & MC13XXX_USE_RTC)
493 mc13xxx_add_subdevice(mc13xxx, "%s-rtc");
494
495 return 0;
496 }
497 EXPORT_SYMBOL_GPL(mc13xxx_common_init);
498
mc13xxx_common_exit(struct device * dev)499 int mc13xxx_common_exit(struct device *dev)
500 {
501 struct mc13xxx *mc13xxx = dev_get_drvdata(dev);
502
503 mfd_remove_devices(dev);
504 regmap_del_irq_chip(mc13xxx->irq, mc13xxx->irq_data);
505 mutex_destroy(&mc13xxx->lock);
506
507 return 0;
508 }
509 EXPORT_SYMBOL_GPL(mc13xxx_common_exit);
510
511 MODULE_DESCRIPTION("Core driver for Freescale MC13XXX PMIC");
512 MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
513 MODULE_LICENSE("GPL v2");
514
