1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef RVU_H 12 #define RVU_H 13 14 #include <linux/pci.h> 15 #include "rvu_struct.h" 16 #include "common.h" 17 #include "mbox.h" 18 19 /* PCI device IDs */ 20 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065 21 22 /* Subsystem Device ID */ 23 #define PCI_SUBSYS_DEVID_96XX 0xB200 24 25 /* PCI BAR nos */ 26 #define PCI_AF_REG_BAR_NUM 0 27 #define PCI_PF_REG_BAR_NUM 2 28 #define PCI_MBOX_BAR_NUM 4 29 30 #define NAME_SIZE 32 31 32 /* PF_FUNC */ 33 #define RVU_PFVF_PF_SHIFT 10 34 #define RVU_PFVF_PF_MASK 0x3F 35 #define RVU_PFVF_FUNC_SHIFT 0 36 #define RVU_PFVF_FUNC_MASK 0x3FF 37 38 struct rvu_work { 39 struct work_struct work; 40 struct rvu *rvu; 41 }; 42 43 struct rsrc_bmap { 44 unsigned long *bmap; /* Pointer to resource bitmap */ 45 u16 max; /* Max resource id or count */ 46 }; 47 48 struct rvu_block { 49 struct rsrc_bmap lf; 50 struct admin_queue *aq; /* NIX/NPA AQ */ 51 u16 *fn_map; /* LF to pcifunc mapping */ 52 bool multislot; 53 bool implemented; 54 u8 addr; /* RVU_BLOCK_ADDR_E */ 55 u8 type; /* RVU_BLOCK_TYPE_E */ 56 u8 lfshift; 57 u64 lookup_reg; 58 u64 pf_lfcnt_reg; 59 u64 vf_lfcnt_reg; 60 u64 lfcfg_reg; 61 u64 msixcfg_reg; 62 u64 lfreset_reg; 63 unsigned char name[NAME_SIZE]; 64 }; 65 66 struct nix_mcast { 67 struct qmem *mce_ctx; 68 struct qmem *mcast_buf; 69 int replay_pkind; 70 int next_free_mce; 71 struct mutex mce_lock; /* Serialize MCE updates */ 72 }; 73 74 struct nix_mce_list { 75 struct hlist_head head; 76 int count; 77 int max; 78 }; 79 80 struct npc_mcam { 81 struct rsrc_bmap counters; 82 struct mutex lock; /* MCAM entries and counters update lock */ 83 unsigned long *bmap; /* bitmap, 0 => bmap_entries */ 84 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */ 85 u16 bmap_entries; /* Number of unreserved MCAM entries */ 86 u16 bmap_fcnt; /* MCAM entries free count */ 87 u16 *entry2pfvf_map; 88 u16 *entry2cntr_map; 89 u16 *cntr2pfvf_map; 90 u16 *cntr_refcnt; 91 u8 keysize; /* MCAM keysize 112/224/448 bits */ 92 u8 banks; /* Number of MCAM banks */ 93 u8 banks_per_entry;/* Number of keywords in key */ 94 u16 banksize; /* Number of MCAM entries in each bank */ 95 u16 total_entries; /* Total number of MCAM entries */ 96 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */ 97 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */ 98 u16 lprio_count; 99 u16 lprio_start; 100 u16 hprio_count; 101 u16 hprio_end; 102 }; 103 104 /* Structure for per RVU func info ie PF/VF */ 105 struct rvu_pfvf { 106 bool npalf; /* Only one NPALF per RVU_FUNC */ 107 bool nixlf; /* Only one NIXLF per RVU_FUNC */ 108 u16 sso; 109 u16 ssow; 110 u16 cptlfs; 111 u16 timlfs; 112 u8 cgx_lmac; 113 114 /* Block LF's MSIX vector info */ 115 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */ 116 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF)) 117 u16 *msix_lfmap; /* Vector to block LF mapping */ 118 119 /* NPA contexts */ 120 struct qmem *aura_ctx; 121 struct qmem *pool_ctx; 122 struct qmem *npa_qints_ctx; 123 unsigned long *aura_bmap; 124 unsigned long *pool_bmap; 125 126 /* NIX contexts */ 127 struct qmem *rq_ctx; 128 struct qmem *sq_ctx; 129 struct qmem *cq_ctx; 130 struct qmem *rss_ctx; 131 struct qmem *cq_ints_ctx; 132 struct qmem *nix_qints_ctx; 133 unsigned long *sq_bmap; 134 unsigned long *rq_bmap; 135 unsigned long *cq_bmap; 136 137 u16 rx_chan_base; 138 u16 tx_chan_base; 139 u8 rx_chan_cnt; /* total number of RX channels */ 140 u8 tx_chan_cnt; /* total number of TX channels */ 141 u16 maxlen; 142 u16 minlen; 143 144 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */ 145 146 /* Broadcast pkt replication info */ 147 u16 bcast_mce_idx; 148 struct nix_mce_list bcast_mce_list; 149 150 /* VLAN offload */ 151 struct mcam_entry entry; 152 int rxvlan_index; 153 bool rxvlan; 154 }; 155 156 struct nix_txsch { 157 struct rsrc_bmap schq; 158 u8 lvl; 159 #define NIX_TXSCHQ_TL1_CFG_DONE BIT_ULL(0) 160 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF) 161 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16) 162 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16)) 163 u32 *pfvf_map; 164 }; 165 166 struct nix_mark_format { 167 u8 total; 168 u8 in_use; 169 u32 *cfg; 170 }; 171 172 struct npc_pkind { 173 struct rsrc_bmap rsrc; 174 u32 *pfchan_map; 175 }; 176 177 struct nix_flowkey { 178 #define NIX_FLOW_KEY_ALG_MAX 32 179 u32 flowkey[NIX_FLOW_KEY_ALG_MAX]; 180 int in_use; 181 }; 182 183 struct nix_lso { 184 u8 total; 185 u8 in_use; 186 }; 187 188 struct nix_hw { 189 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */ 190 struct nix_mcast mcast; 191 struct nix_flowkey flowkey; 192 struct nix_mark_format mark_format; 193 struct nix_lso lso; 194 }; 195 196 struct rvu_hwinfo { 197 u8 total_pfs; /* MAX RVU PFs HW supports */ 198 u16 total_vfs; /* Max RVU VFs HW supports */ 199 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */ 200 u8 cgx; 201 u8 lmac_per_cgx; 202 u8 cgx_links; 203 u8 lbk_links; 204 u8 sdp_links; 205 u8 npc_kpus; /* No of parser units */ 206 207 208 struct rvu_block block[BLK_COUNT]; /* Block info */ 209 struct nix_hw *nix0; 210 struct npc_pkind pkind; 211 struct npc_mcam mcam; 212 }; 213 214 struct mbox_wq_info { 215 struct otx2_mbox mbox; 216 struct rvu_work *mbox_wrk; 217 218 struct otx2_mbox mbox_up; 219 struct rvu_work *mbox_wrk_up; 220 221 struct workqueue_struct *mbox_wq; 222 }; 223 224 struct rvu { 225 void __iomem *afreg_base; 226 void __iomem *pfreg_base; 227 struct pci_dev *pdev; 228 struct device *dev; 229 struct rvu_hwinfo *hw; 230 struct rvu_pfvf *pf; 231 struct rvu_pfvf *hwvf; 232 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 233 int vfs; /* Number of VFs attached to RVU */ 234 235 /* Mbox */ 236 struct mbox_wq_info afpf_wq_info; 237 struct mbox_wq_info afvf_wq_info; 238 239 /* PF FLR */ 240 struct rvu_work *flr_wrk; 241 struct workqueue_struct *flr_wq; 242 struct mutex flr_lock; /* Serialize FLRs */ 243 244 /* MSI-X */ 245 u16 num_vec; 246 char *irq_name; 247 bool *irq_allocated; 248 dma_addr_t msix_base_iova; 249 250 /* CGX */ 251 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */ 252 u8 cgx_mapped_pfs; 253 u8 cgx_cnt_max; /* CGX port count max */ 254 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */ 255 u16 *cgxlmac2pf_map; /* bitmap of mapped pfs for 256 * every cgx lmac port 257 */ 258 unsigned long pf_notify_bmap; /* Flags for PF notification */ 259 void **cgx_idmap; /* cgx id to cgx data map table */ 260 struct work_struct cgx_evh_work; 261 struct workqueue_struct *cgx_evh_wq; 262 spinlock_t cgx_evq_lock; /* cgx event queue lock */ 263 struct list_head cgx_evq_head; /* cgx event queue head */ 264 265 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */ 266 }; 267 rvu_write64(struct rvu * rvu,u64 block,u64 offset,u64 val)268 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 269 { 270 writeq(val, rvu->afreg_base + ((block << 28) | offset)); 271 } 272 rvu_read64(struct rvu * rvu,u64 block,u64 offset)273 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset) 274 { 275 return readq(rvu->afreg_base + ((block << 28) | offset)); 276 } 277 rvupf_write64(struct rvu * rvu,u64 offset,u64 val)278 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val) 279 { 280 writeq(val, rvu->pfreg_base + offset); 281 } 282 rvupf_read64(struct rvu * rvu,u64 offset)283 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset) 284 { 285 return readq(rvu->pfreg_base + offset); 286 } 287 is_rvu_9xxx_A0(struct rvu * rvu)288 static inline bool is_rvu_9xxx_A0(struct rvu *rvu) 289 { 290 struct pci_dev *pdev = rvu->pdev; 291 292 return (pdev->revision == 0x00) && 293 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX); 294 } 295 296 /* Function Prototypes 297 * RVU 298 */ is_afvf(u16 pcifunc)299 static inline int is_afvf(u16 pcifunc) 300 { 301 return !(pcifunc & ~RVU_PFVF_FUNC_MASK); 302 } 303 304 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc); 305 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc); 306 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id); 307 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc); 308 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc); 309 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc); 310 int rvu_get_pf(u16 pcifunc); 311 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc); 312 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf); 313 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr); 314 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype); 315 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot); 316 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf); 317 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc); 318 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero); 319 320 /* RVU HW reg validation */ 321 enum regmap_block { 322 TXSCHQ_HWREGMAP = 0, 323 MAX_HWREGMAP, 324 }; 325 326 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg); 327 328 /* NPA/NIX AQ APIs */ 329 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 330 int qsize, int inst_size, int res_size); 331 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq); 332 333 /* CGX APIs */ is_pf_cgxmapped(struct rvu * rvu,u8 pf)334 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf) 335 { 336 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs); 337 } 338 rvu_get_cgx_lmac_id(u8 map,u8 * cgx_id,u8 * lmac_id)339 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id) 340 { 341 *cgx_id = (map >> 4) & 0xF; 342 *lmac_id = (map & 0xF); 343 } 344 345 int rvu_cgx_init(struct rvu *rvu); 346 int rvu_cgx_exit(struct rvu *rvu); 347 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu); 348 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start); 349 int rvu_mbox_handler_cgx_start_rxtx(struct rvu *rvu, struct msg_req *req, 350 struct msg_rsp *rsp); 351 int rvu_mbox_handler_cgx_stop_rxtx(struct rvu *rvu, struct msg_req *req, 352 struct msg_rsp *rsp); 353 int rvu_mbox_handler_cgx_stats(struct rvu *rvu, struct msg_req *req, 354 struct cgx_stats_rsp *rsp); 355 int rvu_mbox_handler_cgx_mac_addr_set(struct rvu *rvu, 356 struct cgx_mac_addr_set_or_get *req, 357 struct cgx_mac_addr_set_or_get *rsp); 358 int rvu_mbox_handler_cgx_mac_addr_get(struct rvu *rvu, 359 struct cgx_mac_addr_set_or_get *req, 360 struct cgx_mac_addr_set_or_get *rsp); 361 int rvu_mbox_handler_cgx_promisc_enable(struct rvu *rvu, struct msg_req *req, 362 struct msg_rsp *rsp); 363 int rvu_mbox_handler_cgx_promisc_disable(struct rvu *rvu, struct msg_req *req, 364 struct msg_rsp *rsp); 365 int rvu_mbox_handler_cgx_start_linkevents(struct rvu *rvu, struct msg_req *req, 366 struct msg_rsp *rsp); 367 int rvu_mbox_handler_cgx_stop_linkevents(struct rvu *rvu, struct msg_req *req, 368 struct msg_rsp *rsp); 369 int rvu_mbox_handler_cgx_get_linkinfo(struct rvu *rvu, struct msg_req *req, 370 struct cgx_link_info_msg *rsp); 371 int rvu_mbox_handler_cgx_intlbk_enable(struct rvu *rvu, struct msg_req *req, 372 struct msg_rsp *rsp); 373 int rvu_mbox_handler_cgx_intlbk_disable(struct rvu *rvu, struct msg_req *req, 374 struct msg_rsp *rsp); 375 376 /* NPA APIs */ 377 int rvu_npa_init(struct rvu *rvu); 378 void rvu_npa_freemem(struct rvu *rvu); 379 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf); 380 int rvu_mbox_handler_npa_aq_enq(struct rvu *rvu, 381 struct npa_aq_enq_req *req, 382 struct npa_aq_enq_rsp *rsp); 383 int rvu_mbox_handler_npa_hwctx_disable(struct rvu *rvu, 384 struct hwctx_disable_req *req, 385 struct msg_rsp *rsp); 386 int rvu_mbox_handler_npa_lf_alloc(struct rvu *rvu, 387 struct npa_lf_alloc_req *req, 388 struct npa_lf_alloc_rsp *rsp); 389 int rvu_mbox_handler_npa_lf_free(struct rvu *rvu, struct msg_req *req, 390 struct msg_rsp *rsp); 391 392 /* NIX APIs */ 393 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc); 394 int rvu_nix_init(struct rvu *rvu); 395 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw, 396 int blkaddr, u32 cfg); 397 void rvu_nix_freemem(struct rvu *rvu); 398 int rvu_get_nixlf_count(struct rvu *rvu); 399 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf); 400 int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu, 401 struct nix_lf_alloc_req *req, 402 struct nix_lf_alloc_rsp *rsp); 403 int rvu_mbox_handler_nix_lf_free(struct rvu *rvu, struct msg_req *req, 404 struct msg_rsp *rsp); 405 int rvu_mbox_handler_nix_aq_enq(struct rvu *rvu, 406 struct nix_aq_enq_req *req, 407 struct nix_aq_enq_rsp *rsp); 408 int rvu_mbox_handler_nix_hwctx_disable(struct rvu *rvu, 409 struct hwctx_disable_req *req, 410 struct msg_rsp *rsp); 411 int rvu_mbox_handler_nix_txsch_alloc(struct rvu *rvu, 412 struct nix_txsch_alloc_req *req, 413 struct nix_txsch_alloc_rsp *rsp); 414 int rvu_mbox_handler_nix_txsch_free(struct rvu *rvu, 415 struct nix_txsch_free_req *req, 416 struct msg_rsp *rsp); 417 int rvu_mbox_handler_nix_txschq_cfg(struct rvu *rvu, 418 struct nix_txschq_config *req, 419 struct msg_rsp *rsp); 420 int rvu_mbox_handler_nix_stats_rst(struct rvu *rvu, struct msg_req *req, 421 struct msg_rsp *rsp); 422 int rvu_mbox_handler_nix_vtag_cfg(struct rvu *rvu, 423 struct nix_vtag_config *req, 424 struct msg_rsp *rsp); 425 int rvu_mbox_handler_nix_rxvlan_alloc(struct rvu *rvu, struct msg_req *req, 426 struct msg_rsp *rsp); 427 int rvu_mbox_handler_nix_rss_flowkey_cfg(struct rvu *rvu, 428 struct nix_rss_flowkey_cfg *req, 429 struct nix_rss_flowkey_cfg_rsp *rsp); 430 int rvu_mbox_handler_nix_set_mac_addr(struct rvu *rvu, 431 struct nix_set_mac_addr *req, 432 struct msg_rsp *rsp); 433 int rvu_mbox_handler_nix_set_rx_mode(struct rvu *rvu, struct nix_rx_mode *req, 434 struct msg_rsp *rsp); 435 int rvu_mbox_handler_nix_set_hw_frs(struct rvu *rvu, struct nix_frs_cfg *req, 436 struct msg_rsp *rsp); 437 int rvu_mbox_handler_nix_lf_start_rx(struct rvu *rvu, struct msg_req *req, 438 struct msg_rsp *rsp); 439 int rvu_mbox_handler_nix_lf_stop_rx(struct rvu *rvu, struct msg_req *req, 440 struct msg_rsp *rsp); 441 int rvu_mbox_handler_nix_mark_format_cfg(struct rvu *rvu, 442 struct nix_mark_format_cfg *req, 443 struct nix_mark_format_cfg_rsp *rsp); 444 int rvu_mbox_handler_nix_set_rx_cfg(struct rvu *rvu, struct nix_rx_cfg *req, 445 struct msg_rsp *rsp); 446 int rvu_mbox_handler_nix_lso_format_cfg(struct rvu *rvu, 447 struct nix_lso_format_cfg *req, 448 struct nix_lso_format_cfg_rsp *rsp); 449 450 /* NPC APIs */ 451 int rvu_npc_init(struct rvu *rvu); 452 void rvu_npc_freemem(struct rvu *rvu); 453 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf); 454 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf); 455 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, 456 int nixlf, u64 chan, u8 *mac_addr); 457 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, 458 int nixlf, u64 chan, bool allmulti); 459 void rvu_npc_disable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf); 460 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf); 461 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, 462 int nixlf, u64 chan); 463 int rvu_npc_update_rxvlan(struct rvu *rvu, u16 pcifunc, int nixlf); 464 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 465 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 466 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 467 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, 468 int group, int alg_idx, int mcam_index); 469 int rvu_mbox_handler_npc_mcam_alloc_entry(struct rvu *rvu, 470 struct npc_mcam_alloc_entry_req *req, 471 struct npc_mcam_alloc_entry_rsp *rsp); 472 int rvu_mbox_handler_npc_mcam_free_entry(struct rvu *rvu, 473 struct npc_mcam_free_entry_req *req, 474 struct msg_rsp *rsp); 475 int rvu_mbox_handler_npc_mcam_write_entry(struct rvu *rvu, 476 struct npc_mcam_write_entry_req *req, 477 struct msg_rsp *rsp); 478 int rvu_mbox_handler_npc_mcam_ena_entry(struct rvu *rvu, 479 struct npc_mcam_ena_dis_entry_req *req, 480 struct msg_rsp *rsp); 481 int rvu_mbox_handler_npc_mcam_dis_entry(struct rvu *rvu, 482 struct npc_mcam_ena_dis_entry_req *req, 483 struct msg_rsp *rsp); 484 int rvu_mbox_handler_npc_mcam_shift_entry(struct rvu *rvu, 485 struct npc_mcam_shift_entry_req *req, 486 struct npc_mcam_shift_entry_rsp *rsp); 487 int rvu_mbox_handler_npc_mcam_alloc_counter(struct rvu *rvu, 488 struct npc_mcam_alloc_counter_req *req, 489 struct npc_mcam_alloc_counter_rsp *rsp); 490 int rvu_mbox_handler_npc_mcam_free_counter(struct rvu *rvu, 491 struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp); 492 int rvu_mbox_handler_npc_mcam_clear_counter(struct rvu *rvu, 493 struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp); 494 int rvu_mbox_handler_npc_mcam_unmap_counter(struct rvu *rvu, 495 struct npc_mcam_unmap_counter_req *req, struct msg_rsp *rsp); 496 int rvu_mbox_handler_npc_mcam_counter_stats(struct rvu *rvu, 497 struct npc_mcam_oper_counter_req *req, 498 struct npc_mcam_oper_counter_rsp *rsp); 499 int rvu_mbox_handler_npc_mcam_alloc_and_write_entry(struct rvu *rvu, 500 struct npc_mcam_alloc_and_write_entry_req *req, 501 struct npc_mcam_alloc_and_write_entry_rsp *rsp); 502 int rvu_mbox_handler_npc_get_kex_cfg(struct rvu *rvu, struct msg_req *req, 503 struct npc_get_kex_cfg_rsp *rsp); 504 #endif /* RVU_H */ 505
