1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Resource Director Technology(RDT)
4 * - Cache Allocation code.
5 *
6 * Copyright (C) 2016 Intel Corporation
7 *
8 * Authors:
9 * Fenghua Yu <fenghua.yu@intel.com>
10 * Tony Luck <tony.luck@intel.com>
11 * Vikas Shivappa <vikas.shivappa@intel.com>
12 *
13 * More information about RDT be found in the Intel (R) x86 Architecture
14 * Software Developer Manual June 2016, volume 3, section 17.17.
15 */
16
17 #define pr_fmt(fmt) "resctrl: " fmt
18
19 #include <linux/slab.h>
20 #include <linux/err.h>
21 #include <linux/cacheinfo.h>
22 #include <linux/cpuhotplug.h>
23
24 #include <asm/intel-family.h>
25 #include <asm/resctrl.h>
26 #include "internal.h"
27
28 /* Mutex to protect rdtgroup access. */
29 DEFINE_MUTEX(rdtgroup_mutex);
30
31 /*
32 * The cached resctrl_pqr_state is strictly per CPU and can never be
33 * updated from a remote CPU. Functions which modify the state
34 * are called with interrupts disabled and no preemption, which
35 * is sufficient for the protection.
36 */
37 DEFINE_PER_CPU(struct resctrl_pqr_state, pqr_state);
38
39 /*
40 * Used to store the max resource name width and max resource data width
41 * to display the schemata in a tabular format
42 */
43 int max_name_width, max_data_width;
44
45 /*
46 * Global boolean for rdt_alloc which is true if any
47 * resource allocation is enabled.
48 */
49 bool rdt_alloc_capable;
50
51 static void
52 mba_wrmsr_intel(struct rdt_domain *d, struct msr_param *m,
53 struct rdt_resource *r);
54 static void
55 cat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r);
56 static void
57 mba_wrmsr_amd(struct rdt_domain *d, struct msr_param *m,
58 struct rdt_resource *r);
59
60 #define domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].domains)
61
62 struct rdt_resource rdt_resources_all[] = {
63 [RDT_RESOURCE_L3] =
64 {
65 .rid = RDT_RESOURCE_L3,
66 .name = "L3",
67 .domains = domain_init(RDT_RESOURCE_L3),
68 .msr_base = MSR_IA32_L3_CBM_BASE,
69 .msr_update = cat_wrmsr,
70 .cache_level = 3,
71 .cache = {
72 .min_cbm_bits = 1,
73 .cbm_idx_mult = 1,
74 .cbm_idx_offset = 0,
75 },
76 .parse_ctrlval = parse_cbm,
77 .format_str = "%d=%0*x",
78 .fflags = RFTYPE_RES_CACHE,
79 },
80 [RDT_RESOURCE_L3DATA] =
81 {
82 .rid = RDT_RESOURCE_L3DATA,
83 .name = "L3DATA",
84 .domains = domain_init(RDT_RESOURCE_L3DATA),
85 .msr_base = MSR_IA32_L3_CBM_BASE,
86 .msr_update = cat_wrmsr,
87 .cache_level = 3,
88 .cache = {
89 .min_cbm_bits = 1,
90 .cbm_idx_mult = 2,
91 .cbm_idx_offset = 0,
92 },
93 .parse_ctrlval = parse_cbm,
94 .format_str = "%d=%0*x",
95 .fflags = RFTYPE_RES_CACHE,
96 },
97 [RDT_RESOURCE_L3CODE] =
98 {
99 .rid = RDT_RESOURCE_L3CODE,
100 .name = "L3CODE",
101 .domains = domain_init(RDT_RESOURCE_L3CODE),
102 .msr_base = MSR_IA32_L3_CBM_BASE,
103 .msr_update = cat_wrmsr,
104 .cache_level = 3,
105 .cache = {
106 .min_cbm_bits = 1,
107 .cbm_idx_mult = 2,
108 .cbm_idx_offset = 1,
109 },
110 .parse_ctrlval = parse_cbm,
111 .format_str = "%d=%0*x",
112 .fflags = RFTYPE_RES_CACHE,
113 },
114 [RDT_RESOURCE_L2] =
115 {
116 .rid = RDT_RESOURCE_L2,
117 .name = "L2",
118 .domains = domain_init(RDT_RESOURCE_L2),
119 .msr_base = MSR_IA32_L2_CBM_BASE,
120 .msr_update = cat_wrmsr,
121 .cache_level = 2,
122 .cache = {
123 .min_cbm_bits = 1,
124 .cbm_idx_mult = 1,
125 .cbm_idx_offset = 0,
126 },
127 .parse_ctrlval = parse_cbm,
128 .format_str = "%d=%0*x",
129 .fflags = RFTYPE_RES_CACHE,
130 },
131 [RDT_RESOURCE_L2DATA] =
132 {
133 .rid = RDT_RESOURCE_L2DATA,
134 .name = "L2DATA",
135 .domains = domain_init(RDT_RESOURCE_L2DATA),
136 .msr_base = MSR_IA32_L2_CBM_BASE,
137 .msr_update = cat_wrmsr,
138 .cache_level = 2,
139 .cache = {
140 .min_cbm_bits = 1,
141 .cbm_idx_mult = 2,
142 .cbm_idx_offset = 0,
143 },
144 .parse_ctrlval = parse_cbm,
145 .format_str = "%d=%0*x",
146 .fflags = RFTYPE_RES_CACHE,
147 },
148 [RDT_RESOURCE_L2CODE] =
149 {
150 .rid = RDT_RESOURCE_L2CODE,
151 .name = "L2CODE",
152 .domains = domain_init(RDT_RESOURCE_L2CODE),
153 .msr_base = MSR_IA32_L2_CBM_BASE,
154 .msr_update = cat_wrmsr,
155 .cache_level = 2,
156 .cache = {
157 .min_cbm_bits = 1,
158 .cbm_idx_mult = 2,
159 .cbm_idx_offset = 1,
160 },
161 .parse_ctrlval = parse_cbm,
162 .format_str = "%d=%0*x",
163 .fflags = RFTYPE_RES_CACHE,
164 },
165 [RDT_RESOURCE_MBA] =
166 {
167 .rid = RDT_RESOURCE_MBA,
168 .name = "MB",
169 .domains = domain_init(RDT_RESOURCE_MBA),
170 .cache_level = 3,
171 .parse_ctrlval = parse_bw,
172 .format_str = "%d=%*u",
173 .fflags = RFTYPE_RES_MB,
174 },
175 };
176
cbm_idx(struct rdt_resource * r,unsigned int closid)177 static unsigned int cbm_idx(struct rdt_resource *r, unsigned int closid)
178 {
179 return closid * r->cache.cbm_idx_mult + r->cache.cbm_idx_offset;
180 }
181
182 /*
183 * cache_alloc_hsw_probe() - Have to probe for Intel haswell server CPUs
184 * as they do not have CPUID enumeration support for Cache allocation.
185 * The check for Vendor/Family/Model is not enough to guarantee that
186 * the MSRs won't #GP fault because only the following SKUs support
187 * CAT:
188 * Intel(R) Xeon(R) CPU E5-2658 v3 @ 2.20GHz
189 * Intel(R) Xeon(R) CPU E5-2648L v3 @ 1.80GHz
190 * Intel(R) Xeon(R) CPU E5-2628L v3 @ 2.00GHz
191 * Intel(R) Xeon(R) CPU E5-2618L v3 @ 2.30GHz
192 * Intel(R) Xeon(R) CPU E5-2608L v3 @ 2.00GHz
193 * Intel(R) Xeon(R) CPU E5-2658A v3 @ 2.20GHz
194 *
195 * Probe by trying to write the first of the L3 cach mask registers
196 * and checking that the bits stick. Max CLOSids is always 4 and max cbm length
197 * is always 20 on hsw server parts. The minimum cache bitmask length
198 * allowed for HSW server is always 2 bits. Hardcode all of them.
199 */
cache_alloc_hsw_probe(void)200 static inline void cache_alloc_hsw_probe(void)
201 {
202 struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3];
203 u32 l, h, max_cbm = BIT_MASK(20) - 1;
204
205 if (wrmsr_safe(MSR_IA32_L3_CBM_BASE, max_cbm, 0))
206 return;
207
208 rdmsr(MSR_IA32_L3_CBM_BASE, l, h);
209
210 /* If all the bits were set in MSR, return success */
211 if (l != max_cbm)
212 return;
213
214 r->num_closid = 4;
215 r->default_ctrl = max_cbm;
216 r->cache.cbm_len = 20;
217 r->cache.shareable_bits = 0xc0000;
218 r->cache.min_cbm_bits = 2;
219 r->alloc_capable = true;
220 r->alloc_enabled = true;
221
222 rdt_alloc_capable = true;
223 }
224
is_mba_sc(struct rdt_resource * r)225 bool is_mba_sc(struct rdt_resource *r)
226 {
227 if (!r)
228 return rdt_resources_all[RDT_RESOURCE_MBA].membw.mba_sc;
229
230 return r->membw.mba_sc;
231 }
232
233 /*
234 * rdt_get_mb_table() - get a mapping of bandwidth(b/w) percentage values
235 * exposed to user interface and the h/w understandable delay values.
236 *
237 * The non-linear delay values have the granularity of power of two
238 * and also the h/w does not guarantee a curve for configured delay
239 * values vs. actual b/w enforced.
240 * Hence we need a mapping that is pre calibrated so the user can
241 * express the memory b/w as a percentage value.
242 */
rdt_get_mb_table(struct rdt_resource * r)243 static inline bool rdt_get_mb_table(struct rdt_resource *r)
244 {
245 /*
246 * There are no Intel SKUs as of now to support non-linear delay.
247 */
248 pr_info("MBA b/w map not implemented for cpu:%d, model:%d",
249 boot_cpu_data.x86, boot_cpu_data.x86_model);
250
251 return false;
252 }
253
__get_mem_config_intel(struct rdt_resource * r)254 static bool __get_mem_config_intel(struct rdt_resource *r)
255 {
256 union cpuid_0x10_3_eax eax;
257 union cpuid_0x10_x_edx edx;
258 u32 ebx, ecx, max_delay;
259
260 cpuid_count(0x00000010, 3, &eax.full, &ebx, &ecx, &edx.full);
261 r->num_closid = edx.split.cos_max + 1;
262 max_delay = eax.split.max_delay + 1;
263 r->default_ctrl = MAX_MBA_BW;
264 r->membw.arch_needs_linear = true;
265 if (ecx & MBA_IS_LINEAR) {
266 r->membw.delay_linear = true;
267 r->membw.min_bw = MAX_MBA_BW - max_delay;
268 r->membw.bw_gran = MAX_MBA_BW - max_delay;
269 } else {
270 if (!rdt_get_mb_table(r))
271 return false;
272 r->membw.arch_needs_linear = false;
273 }
274 r->data_width = 3;
275
276 if (boot_cpu_has(X86_FEATURE_PER_THREAD_MBA))
277 r->membw.throttle_mode = THREAD_THROTTLE_PER_THREAD;
278 else
279 r->membw.throttle_mode = THREAD_THROTTLE_MAX;
280 thread_throttle_mode_init();
281
282 r->alloc_capable = true;
283 r->alloc_enabled = true;
284
285 return true;
286 }
287
__rdt_get_mem_config_amd(struct rdt_resource * r)288 static bool __rdt_get_mem_config_amd(struct rdt_resource *r)
289 {
290 union cpuid_0x10_3_eax eax;
291 union cpuid_0x10_x_edx edx;
292 u32 ebx, ecx;
293
294 cpuid_count(0x80000020, 1, &eax.full, &ebx, &ecx, &edx.full);
295 r->num_closid = edx.split.cos_max + 1;
296 r->default_ctrl = MAX_MBA_BW_AMD;
297
298 /* AMD does not use delay */
299 r->membw.delay_linear = false;
300 r->membw.arch_needs_linear = false;
301
302 /*
303 * AMD does not use memory delay throttle model to control
304 * the allocation like Intel does.
305 */
306 r->membw.throttle_mode = THREAD_THROTTLE_UNDEFINED;
307 r->membw.min_bw = 0;
308 r->membw.bw_gran = 1;
309 /* Max value is 2048, Data width should be 4 in decimal */
310 r->data_width = 4;
311
312 r->alloc_capable = true;
313 r->alloc_enabled = true;
314
315 return true;
316 }
317
rdt_get_cache_alloc_cfg(int idx,struct rdt_resource * r)318 static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r)
319 {
320 union cpuid_0x10_1_eax eax;
321 union cpuid_0x10_x_edx edx;
322 u32 ebx, ecx;
323
324 cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx, &edx.full);
325 r->num_closid = edx.split.cos_max + 1;
326 r->cache.cbm_len = eax.split.cbm_len + 1;
327 r->default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1;
328 r->cache.shareable_bits = ebx & r->default_ctrl;
329 r->data_width = (r->cache.cbm_len + 3) / 4;
330 r->alloc_capable = true;
331 r->alloc_enabled = true;
332 }
333
rdt_get_cdp_config(int level,int type)334 static void rdt_get_cdp_config(int level, int type)
335 {
336 struct rdt_resource *r_l = &rdt_resources_all[level];
337 struct rdt_resource *r = &rdt_resources_all[type];
338
339 r->num_closid = r_l->num_closid / 2;
340 r->cache.cbm_len = r_l->cache.cbm_len;
341 r->default_ctrl = r_l->default_ctrl;
342 r->cache.shareable_bits = r_l->cache.shareable_bits;
343 r->data_width = (r->cache.cbm_len + 3) / 4;
344 r->alloc_capable = true;
345 /*
346 * By default, CDP is disabled. CDP can be enabled by mount parameter
347 * "cdp" during resctrl file system mount time.
348 */
349 r->alloc_enabled = false;
350 }
351
rdt_get_cdp_l3_config(void)352 static void rdt_get_cdp_l3_config(void)
353 {
354 rdt_get_cdp_config(RDT_RESOURCE_L3, RDT_RESOURCE_L3DATA);
355 rdt_get_cdp_config(RDT_RESOURCE_L3, RDT_RESOURCE_L3CODE);
356 }
357
rdt_get_cdp_l2_config(void)358 static void rdt_get_cdp_l2_config(void)
359 {
360 rdt_get_cdp_config(RDT_RESOURCE_L2, RDT_RESOURCE_L2DATA);
361 rdt_get_cdp_config(RDT_RESOURCE_L2, RDT_RESOURCE_L2CODE);
362 }
363
364 static void
mba_wrmsr_amd(struct rdt_domain * d,struct msr_param * m,struct rdt_resource * r)365 mba_wrmsr_amd(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r)
366 {
367 unsigned int i;
368
369 for (i = m->low; i < m->high; i++)
370 wrmsrl(r->msr_base + i, d->ctrl_val[i]);
371 }
372
373 /*
374 * Map the memory b/w percentage value to delay values
375 * that can be written to QOS_MSRs.
376 * There are currently no SKUs which support non linear delay values.
377 */
delay_bw_map(unsigned long bw,struct rdt_resource * r)378 u32 delay_bw_map(unsigned long bw, struct rdt_resource *r)
379 {
380 if (r->membw.delay_linear)
381 return MAX_MBA_BW - bw;
382
383 pr_warn_once("Non Linear delay-bw map not supported but queried\n");
384 return r->default_ctrl;
385 }
386
387 static void
mba_wrmsr_intel(struct rdt_domain * d,struct msr_param * m,struct rdt_resource * r)388 mba_wrmsr_intel(struct rdt_domain *d, struct msr_param *m,
389 struct rdt_resource *r)
390 {
391 unsigned int i;
392
393 /* Write the delay values for mba. */
394 for (i = m->low; i < m->high; i++)
395 wrmsrl(r->msr_base + i, delay_bw_map(d->ctrl_val[i], r));
396 }
397
398 static void
cat_wrmsr(struct rdt_domain * d,struct msr_param * m,struct rdt_resource * r)399 cat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r)
400 {
401 unsigned int i;
402
403 for (i = m->low; i < m->high; i++)
404 wrmsrl(r->msr_base + cbm_idx(r, i), d->ctrl_val[i]);
405 }
406
get_domain_from_cpu(int cpu,struct rdt_resource * r)407 struct rdt_domain *get_domain_from_cpu(int cpu, struct rdt_resource *r)
408 {
409 struct rdt_domain *d;
410
411 list_for_each_entry(d, &r->domains, list) {
412 /* Find the domain that contains this CPU */
413 if (cpumask_test_cpu(cpu, &d->cpu_mask))
414 return d;
415 }
416
417 return NULL;
418 }
419
rdt_ctrl_update(void * arg)420 void rdt_ctrl_update(void *arg)
421 {
422 struct msr_param *m = arg;
423 struct rdt_resource *r = m->res;
424 int cpu = smp_processor_id();
425 struct rdt_domain *d;
426
427 d = get_domain_from_cpu(cpu, r);
428 if (d) {
429 r->msr_update(d, m, r);
430 return;
431 }
432 pr_warn_once("cpu %d not found in any domain for resource %s\n",
433 cpu, r->name);
434 }
435
436 /*
437 * rdt_find_domain - Find a domain in a resource that matches input resource id
438 *
439 * Search resource r's domain list to find the resource id. If the resource
440 * id is found in a domain, return the domain. Otherwise, if requested by
441 * caller, return the first domain whose id is bigger than the input id.
442 * The domain list is sorted by id in ascending order.
443 */
rdt_find_domain(struct rdt_resource * r,int id,struct list_head ** pos)444 struct rdt_domain *rdt_find_domain(struct rdt_resource *r, int id,
445 struct list_head **pos)
446 {
447 struct rdt_domain *d;
448 struct list_head *l;
449
450 if (id < 0)
451 return ERR_PTR(-ENODEV);
452
453 list_for_each(l, &r->domains) {
454 d = list_entry(l, struct rdt_domain, list);
455 /* When id is found, return its domain. */
456 if (id == d->id)
457 return d;
458 /* Stop searching when finding id's position in sorted list. */
459 if (id < d->id)
460 break;
461 }
462
463 if (pos)
464 *pos = l;
465
466 return NULL;
467 }
468
setup_default_ctrlval(struct rdt_resource * r,u32 * dc,u32 * dm)469 void setup_default_ctrlval(struct rdt_resource *r, u32 *dc, u32 *dm)
470 {
471 int i;
472
473 /*
474 * Initialize the Control MSRs to having no control.
475 * For Cache Allocation: Set all bits in cbm
476 * For Memory Allocation: Set b/w requested to 100%
477 * and the bandwidth in MBps to U32_MAX
478 */
479 for (i = 0; i < r->num_closid; i++, dc++, dm++) {
480 *dc = r->default_ctrl;
481 *dm = MBA_MAX_MBPS;
482 }
483 }
484
domain_setup_ctrlval(struct rdt_resource * r,struct rdt_domain * d)485 static int domain_setup_ctrlval(struct rdt_resource *r, struct rdt_domain *d)
486 {
487 struct msr_param m;
488 u32 *dc, *dm;
489
490 dc = kmalloc_array(r->num_closid, sizeof(*d->ctrl_val), GFP_KERNEL);
491 if (!dc)
492 return -ENOMEM;
493
494 dm = kmalloc_array(r->num_closid, sizeof(*d->mbps_val), GFP_KERNEL);
495 if (!dm) {
496 kfree(dc);
497 return -ENOMEM;
498 }
499
500 d->ctrl_val = dc;
501 d->mbps_val = dm;
502 setup_default_ctrlval(r, dc, dm);
503
504 m.low = 0;
505 m.high = r->num_closid;
506 r->msr_update(d, &m, r);
507 return 0;
508 }
509
domain_setup_mon_state(struct rdt_resource * r,struct rdt_domain * d)510 static int domain_setup_mon_state(struct rdt_resource *r, struct rdt_domain *d)
511 {
512 size_t tsize;
513
514 if (is_llc_occupancy_enabled()) {
515 d->rmid_busy_llc = bitmap_zalloc(r->num_rmid, GFP_KERNEL);
516 if (!d->rmid_busy_llc)
517 return -ENOMEM;
518 INIT_DELAYED_WORK(&d->cqm_limbo, cqm_handle_limbo);
519 }
520 if (is_mbm_total_enabled()) {
521 tsize = sizeof(*d->mbm_total);
522 d->mbm_total = kcalloc(r->num_rmid, tsize, GFP_KERNEL);
523 if (!d->mbm_total) {
524 bitmap_free(d->rmid_busy_llc);
525 return -ENOMEM;
526 }
527 }
528 if (is_mbm_local_enabled()) {
529 tsize = sizeof(*d->mbm_local);
530 d->mbm_local = kcalloc(r->num_rmid, tsize, GFP_KERNEL);
531 if (!d->mbm_local) {
532 bitmap_free(d->rmid_busy_llc);
533 kfree(d->mbm_total);
534 return -ENOMEM;
535 }
536 }
537
538 if (is_mbm_enabled()) {
539 INIT_DELAYED_WORK(&d->mbm_over, mbm_handle_overflow);
540 mbm_setup_overflow_handler(d, MBM_OVERFLOW_INTERVAL);
541 }
542
543 return 0;
544 }
545
546 /*
547 * domain_add_cpu - Add a cpu to a resource's domain list.
548 *
549 * If an existing domain in the resource r's domain list matches the cpu's
550 * resource id, add the cpu in the domain.
551 *
552 * Otherwise, a new domain is allocated and inserted into the right position
553 * in the domain list sorted by id in ascending order.
554 *
555 * The order in the domain list is visible to users when we print entries
556 * in the schemata file and schemata input is validated to have the same order
557 * as this list.
558 */
domain_add_cpu(int cpu,struct rdt_resource * r)559 static void domain_add_cpu(int cpu, struct rdt_resource *r)
560 {
561 int id = get_cpu_cacheinfo_id(cpu, r->cache_level);
562 struct list_head *add_pos = NULL;
563 struct rdt_domain *d;
564
565 d = rdt_find_domain(r, id, &add_pos);
566 if (IS_ERR(d)) {
567 pr_warn("Couldn't find cache id for CPU %d\n", cpu);
568 return;
569 }
570
571 if (d) {
572 cpumask_set_cpu(cpu, &d->cpu_mask);
573 if (r->cache.arch_has_per_cpu_cfg)
574 rdt_domain_reconfigure_cdp(r);
575 return;
576 }
577
578 d = kzalloc_node(sizeof(*d), GFP_KERNEL, cpu_to_node(cpu));
579 if (!d)
580 return;
581
582 d->id = id;
583 cpumask_set_cpu(cpu, &d->cpu_mask);
584
585 rdt_domain_reconfigure_cdp(r);
586
587 if (r->alloc_capable && domain_setup_ctrlval(r, d)) {
588 kfree(d);
589 return;
590 }
591
592 if (r->mon_capable && domain_setup_mon_state(r, d)) {
593 kfree(d);
594 return;
595 }
596
597 list_add_tail(&d->list, add_pos);
598
599 /*
600 * If resctrl is mounted, add
601 * per domain monitor data directories.
602 */
603 if (static_branch_unlikely(&rdt_mon_enable_key))
604 mkdir_mondata_subdir_allrdtgrp(r, d);
605 }
606
domain_remove_cpu(int cpu,struct rdt_resource * r)607 static void domain_remove_cpu(int cpu, struct rdt_resource *r)
608 {
609 int id = get_cpu_cacheinfo_id(cpu, r->cache_level);
610 struct rdt_domain *d;
611
612 d = rdt_find_domain(r, id, NULL);
613 if (IS_ERR_OR_NULL(d)) {
614 pr_warn("Couldn't find cache id for CPU %d\n", cpu);
615 return;
616 }
617
618 cpumask_clear_cpu(cpu, &d->cpu_mask);
619 if (cpumask_empty(&d->cpu_mask)) {
620 /*
621 * If resctrl is mounted, remove all the
622 * per domain monitor data directories.
623 */
624 if (static_branch_unlikely(&rdt_mon_enable_key))
625 rmdir_mondata_subdir_allrdtgrp(r, d->id);
626 list_del(&d->list);
627 if (r->mon_capable && is_mbm_enabled())
628 cancel_delayed_work(&d->mbm_over);
629 if (is_llc_occupancy_enabled() && has_busy_rmid(r, d)) {
630 /*
631 * When a package is going down, forcefully
632 * decrement rmid->ebusy. There is no way to know
633 * that the L3 was flushed and hence may lead to
634 * incorrect counts in rare scenarios, but leaving
635 * the RMID as busy creates RMID leaks if the
636 * package never comes back.
637 */
638 __check_limbo(d, true);
639 cancel_delayed_work(&d->cqm_limbo);
640 }
641
642 /*
643 * rdt_domain "d" is going to be freed below, so clear
644 * its pointer from pseudo_lock_region struct.
645 */
646 if (d->plr)
647 d->plr->d = NULL;
648
649 kfree(d->ctrl_val);
650 kfree(d->mbps_val);
651 bitmap_free(d->rmid_busy_llc);
652 kfree(d->mbm_total);
653 kfree(d->mbm_local);
654 kfree(d);
655 return;
656 }
657
658 if (r == &rdt_resources_all[RDT_RESOURCE_L3]) {
659 if (is_mbm_enabled() && cpu == d->mbm_work_cpu) {
660 cancel_delayed_work(&d->mbm_over);
661 mbm_setup_overflow_handler(d, 0);
662 }
663 if (is_llc_occupancy_enabled() && cpu == d->cqm_work_cpu &&
664 has_busy_rmid(r, d)) {
665 cancel_delayed_work(&d->cqm_limbo);
666 cqm_setup_limbo_handler(d, 0);
667 }
668 }
669 }
670
clear_closid_rmid(int cpu)671 static void clear_closid_rmid(int cpu)
672 {
673 struct resctrl_pqr_state *state = this_cpu_ptr(&pqr_state);
674
675 state->default_closid = 0;
676 state->default_rmid = 0;
677 state->cur_closid = 0;
678 state->cur_rmid = 0;
679 wrmsr(IA32_PQR_ASSOC, 0, 0);
680 }
681
resctrl_online_cpu(unsigned int cpu)682 static int resctrl_online_cpu(unsigned int cpu)
683 {
684 struct rdt_resource *r;
685
686 mutex_lock(&rdtgroup_mutex);
687 for_each_capable_rdt_resource(r)
688 domain_add_cpu(cpu, r);
689 /* The cpu is set in default rdtgroup after online. */
690 cpumask_set_cpu(cpu, &rdtgroup_default.cpu_mask);
691 clear_closid_rmid(cpu);
692 mutex_unlock(&rdtgroup_mutex);
693
694 return 0;
695 }
696
clear_childcpus(struct rdtgroup * r,unsigned int cpu)697 static void clear_childcpus(struct rdtgroup *r, unsigned int cpu)
698 {
699 struct rdtgroup *cr;
700
701 list_for_each_entry(cr, &r->mon.crdtgrp_list, mon.crdtgrp_list) {
702 if (cpumask_test_and_clear_cpu(cpu, &cr->cpu_mask)) {
703 break;
704 }
705 }
706 }
707
resctrl_offline_cpu(unsigned int cpu)708 static int resctrl_offline_cpu(unsigned int cpu)
709 {
710 struct rdtgroup *rdtgrp;
711 struct rdt_resource *r;
712
713 mutex_lock(&rdtgroup_mutex);
714 for_each_capable_rdt_resource(r)
715 domain_remove_cpu(cpu, r);
716 list_for_each_entry(rdtgrp, &rdt_all_groups, rdtgroup_list) {
717 if (cpumask_test_and_clear_cpu(cpu, &rdtgrp->cpu_mask)) {
718 clear_childcpus(rdtgrp, cpu);
719 break;
720 }
721 }
722 clear_closid_rmid(cpu);
723 mutex_unlock(&rdtgroup_mutex);
724
725 return 0;
726 }
727
728 /*
729 * Choose a width for the resource name and resource data based on the
730 * resource that has widest name and cbm.
731 */
rdt_init_padding(void)732 static __init void rdt_init_padding(void)
733 {
734 struct rdt_resource *r;
735 int cl;
736
737 for_each_alloc_capable_rdt_resource(r) {
738 cl = strlen(r->name);
739 if (cl > max_name_width)
740 max_name_width = cl;
741
742 if (r->data_width > max_data_width)
743 max_data_width = r->data_width;
744 }
745 }
746
747 enum {
748 RDT_FLAG_CMT,
749 RDT_FLAG_MBM_TOTAL,
750 RDT_FLAG_MBM_LOCAL,
751 RDT_FLAG_L3_CAT,
752 RDT_FLAG_L3_CDP,
753 RDT_FLAG_L2_CAT,
754 RDT_FLAG_L2_CDP,
755 RDT_FLAG_MBA,
756 };
757
758 #define RDT_OPT(idx, n, f) \
759 [idx] = { \
760 .name = n, \
761 .flag = f \
762 }
763
764 struct rdt_options {
765 char *name;
766 int flag;
767 bool force_off, force_on;
768 };
769
770 static struct rdt_options rdt_options[] __initdata = {
771 RDT_OPT(RDT_FLAG_CMT, "cmt", X86_FEATURE_CQM_OCCUP_LLC),
772 RDT_OPT(RDT_FLAG_MBM_TOTAL, "mbmtotal", X86_FEATURE_CQM_MBM_TOTAL),
773 RDT_OPT(RDT_FLAG_MBM_LOCAL, "mbmlocal", X86_FEATURE_CQM_MBM_LOCAL),
774 RDT_OPT(RDT_FLAG_L3_CAT, "l3cat", X86_FEATURE_CAT_L3),
775 RDT_OPT(RDT_FLAG_L3_CDP, "l3cdp", X86_FEATURE_CDP_L3),
776 RDT_OPT(RDT_FLAG_L2_CAT, "l2cat", X86_FEATURE_CAT_L2),
777 RDT_OPT(RDT_FLAG_L2_CDP, "l2cdp", X86_FEATURE_CDP_L2),
778 RDT_OPT(RDT_FLAG_MBA, "mba", X86_FEATURE_MBA),
779 };
780 #define NUM_RDT_OPTIONS ARRAY_SIZE(rdt_options)
781
set_rdt_options(char * str)782 static int __init set_rdt_options(char *str)
783 {
784 struct rdt_options *o;
785 bool force_off;
786 char *tok;
787
788 if (*str == '=')
789 str++;
790 while ((tok = strsep(&str, ",")) != NULL) {
791 force_off = *tok == '!';
792 if (force_off)
793 tok++;
794 for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) {
795 if (strcmp(tok, o->name) == 0) {
796 if (force_off)
797 o->force_off = true;
798 else
799 o->force_on = true;
800 break;
801 }
802 }
803 }
804 return 1;
805 }
806 __setup("rdt", set_rdt_options);
807
rdt_cpu_has(int flag)808 static bool __init rdt_cpu_has(int flag)
809 {
810 bool ret = boot_cpu_has(flag);
811 struct rdt_options *o;
812
813 if (!ret)
814 return ret;
815
816 for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) {
817 if (flag == o->flag) {
818 if (o->force_off)
819 ret = false;
820 if (o->force_on)
821 ret = true;
822 break;
823 }
824 }
825 return ret;
826 }
827
get_mem_config(void)828 static __init bool get_mem_config(void)
829 {
830 if (!rdt_cpu_has(X86_FEATURE_MBA))
831 return false;
832
833 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
834 return __get_mem_config_intel(&rdt_resources_all[RDT_RESOURCE_MBA]);
835 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
836 return __rdt_get_mem_config_amd(&rdt_resources_all[RDT_RESOURCE_MBA]);
837
838 return false;
839 }
840
get_rdt_alloc_resources(void)841 static __init bool get_rdt_alloc_resources(void)
842 {
843 bool ret = false;
844
845 if (rdt_alloc_capable)
846 return true;
847
848 if (!boot_cpu_has(X86_FEATURE_RDT_A))
849 return false;
850
851 if (rdt_cpu_has(X86_FEATURE_CAT_L3)) {
852 rdt_get_cache_alloc_cfg(1, &rdt_resources_all[RDT_RESOURCE_L3]);
853 if (rdt_cpu_has(X86_FEATURE_CDP_L3))
854 rdt_get_cdp_l3_config();
855 ret = true;
856 }
857 if (rdt_cpu_has(X86_FEATURE_CAT_L2)) {
858 /* CPUID 0x10.2 fields are same format at 0x10.1 */
859 rdt_get_cache_alloc_cfg(2, &rdt_resources_all[RDT_RESOURCE_L2]);
860 if (rdt_cpu_has(X86_FEATURE_CDP_L2))
861 rdt_get_cdp_l2_config();
862 ret = true;
863 }
864
865 if (get_mem_config())
866 ret = true;
867
868 return ret;
869 }
870
get_rdt_mon_resources(void)871 static __init bool get_rdt_mon_resources(void)
872 {
873 if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC))
874 rdt_mon_features |= (1 << QOS_L3_OCCUP_EVENT_ID);
875 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL))
876 rdt_mon_features |= (1 << QOS_L3_MBM_TOTAL_EVENT_ID);
877 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL))
878 rdt_mon_features |= (1 << QOS_L3_MBM_LOCAL_EVENT_ID);
879
880 if (!rdt_mon_features)
881 return false;
882
883 return !rdt_get_mon_l3_config(&rdt_resources_all[RDT_RESOURCE_L3]);
884 }
885
__check_quirks_intel(void)886 static __init void __check_quirks_intel(void)
887 {
888 switch (boot_cpu_data.x86_model) {
889 case INTEL_FAM6_HASWELL_X:
890 if (!rdt_options[RDT_FLAG_L3_CAT].force_off)
891 cache_alloc_hsw_probe();
892 break;
893 case INTEL_FAM6_SKYLAKE_X:
894 if (boot_cpu_data.x86_stepping <= 4)
895 set_rdt_options("!cmt,!mbmtotal,!mbmlocal,!l3cat");
896 else
897 set_rdt_options("!l3cat");
898 }
899 }
900
check_quirks(void)901 static __init void check_quirks(void)
902 {
903 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
904 __check_quirks_intel();
905 }
906
get_rdt_resources(void)907 static __init bool get_rdt_resources(void)
908 {
909 rdt_alloc_capable = get_rdt_alloc_resources();
910 rdt_mon_capable = get_rdt_mon_resources();
911
912 return (rdt_mon_capable || rdt_alloc_capable);
913 }
914
rdt_init_res_defs_intel(void)915 static __init void rdt_init_res_defs_intel(void)
916 {
917 struct rdt_resource *r;
918
919 for_each_rdt_resource(r) {
920 if (r->rid == RDT_RESOURCE_L3 ||
921 r->rid == RDT_RESOURCE_L3DATA ||
922 r->rid == RDT_RESOURCE_L3CODE ||
923 r->rid == RDT_RESOURCE_L2 ||
924 r->rid == RDT_RESOURCE_L2DATA ||
925 r->rid == RDT_RESOURCE_L2CODE) {
926 r->cache.arch_has_sparse_bitmaps = false;
927 r->cache.arch_has_empty_bitmaps = false;
928 r->cache.arch_has_per_cpu_cfg = false;
929 } else if (r->rid == RDT_RESOURCE_MBA) {
930 r->msr_base = MSR_IA32_MBA_THRTL_BASE;
931 r->msr_update = mba_wrmsr_intel;
932 }
933 }
934 }
935
rdt_init_res_defs_amd(void)936 static __init void rdt_init_res_defs_amd(void)
937 {
938 struct rdt_resource *r;
939
940 for_each_rdt_resource(r) {
941 if (r->rid == RDT_RESOURCE_L3 ||
942 r->rid == RDT_RESOURCE_L3DATA ||
943 r->rid == RDT_RESOURCE_L3CODE ||
944 r->rid == RDT_RESOURCE_L2 ||
945 r->rid == RDT_RESOURCE_L2DATA ||
946 r->rid == RDT_RESOURCE_L2CODE) {
947 r->cache.arch_has_sparse_bitmaps = true;
948 r->cache.arch_has_empty_bitmaps = true;
949 r->cache.arch_has_per_cpu_cfg = true;
950 } else if (r->rid == RDT_RESOURCE_MBA) {
951 r->msr_base = MSR_IA32_MBA_BW_BASE;
952 r->msr_update = mba_wrmsr_amd;
953 }
954 }
955 }
956
rdt_init_res_defs(void)957 static __init void rdt_init_res_defs(void)
958 {
959 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
960 rdt_init_res_defs_intel();
961 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
962 rdt_init_res_defs_amd();
963 }
964
965 static enum cpuhp_state rdt_online;
966
967 /* Runs once on the BSP during boot. */
resctrl_cpu_detect(struct cpuinfo_x86 * c)968 void resctrl_cpu_detect(struct cpuinfo_x86 *c)
969 {
970 if (!cpu_has(c, X86_FEATURE_CQM_LLC)) {
971 c->x86_cache_max_rmid = -1;
972 c->x86_cache_occ_scale = -1;
973 c->x86_cache_mbm_width_offset = -1;
974 return;
975 }
976
977 /* will be overridden if occupancy monitoring exists */
978 c->x86_cache_max_rmid = cpuid_ebx(0xf);
979
980 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) ||
981 cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) ||
982 cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)) {
983 u32 eax, ebx, ecx, edx;
984
985 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
986 cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx);
987
988 c->x86_cache_max_rmid = ecx;
989 c->x86_cache_occ_scale = ebx;
990 c->x86_cache_mbm_width_offset = eax & 0xff;
991
992 if (c->x86_vendor == X86_VENDOR_AMD && !c->x86_cache_mbm_width_offset)
993 c->x86_cache_mbm_width_offset = MBM_CNTR_WIDTH_OFFSET_AMD;
994 }
995 }
996
resctrl_late_init(void)997 static int __init resctrl_late_init(void)
998 {
999 struct rdt_resource *r;
1000 int state, ret;
1001
1002 /*
1003 * Initialize functions(or definitions) that are different
1004 * between vendors here.
1005 */
1006 rdt_init_res_defs();
1007
1008 check_quirks();
1009
1010 if (!get_rdt_resources())
1011 return -ENODEV;
1012
1013 rdt_init_padding();
1014
1015 state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
1016 "x86/resctrl/cat:online:",
1017 resctrl_online_cpu, resctrl_offline_cpu);
1018 if (state < 0)
1019 return state;
1020
1021 ret = rdtgroup_init();
1022 if (ret) {
1023 cpuhp_remove_state(state);
1024 return ret;
1025 }
1026 rdt_online = state;
1027
1028 for_each_alloc_capable_rdt_resource(r)
1029 pr_info("%s allocation detected\n", r->name);
1030
1031 for_each_mon_capable_rdt_resource(r)
1032 pr_info("%s monitoring detected\n", r->name);
1033
1034 return 0;
1035 }
1036
1037 late_initcall(resctrl_late_init);
1038
resctrl_exit(void)1039 static void __exit resctrl_exit(void)
1040 {
1041 cpuhp_remove_state(rdt_online);
1042 rdtgroup_exit();
1043 }
1044
1045 __exitcall(resctrl_exit);
1046
