1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_
3 #define _ASM_POWERPC_BOOK3S_64_MMU_H_
4
5 #ifndef __ASSEMBLY__
6 /*
7 * Page size definition
8 *
9 * shift : is the "PAGE_SHIFT" value for that page size
10 * sllp : is a bit mask with the value of SLB L || LP to be or'ed
11 * directly to a slbmte "vsid" value
12 * penc : is the HPTE encoding mask for the "LP" field:
13 *
14 */
15 struct mmu_psize_def {
16 unsigned int shift; /* number of bits */
17 int penc[MMU_PAGE_COUNT]; /* HPTE encoding */
18 unsigned int tlbiel; /* tlbiel supported for that page size */
19 unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
20 union {
21 unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
22 unsigned long ap; /* Ap encoding used by PowerISA 3.0 */
23 };
24 };
25 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
26
27 #endif /* __ASSEMBLY__ */
28
29 /* 64-bit classic hash table MMU */
30 #include <asm/book3s/64/mmu-hash.h>
31
32 #ifndef __ASSEMBLY__
33 /*
34 * ISA 3.0 partition and process table entry format
35 */
36 struct prtb_entry {
37 __be64 prtb0;
38 __be64 prtb1;
39 };
40 extern struct prtb_entry *process_tb;
41
42 struct patb_entry {
43 __be64 patb0;
44 __be64 patb1;
45 };
46 extern struct patb_entry *partition_tb;
47
48 /* Bits in patb0 field */
49 #define PATB_HR (1UL << 63)
50 #define RPDB_MASK 0x0fffffffffffff00UL
51 #define RPDB_SHIFT (1UL << 8)
52 #define RTS1_SHIFT 61 /* top 2 bits of radix tree size */
53 #define RTS1_MASK (3UL << RTS1_SHIFT)
54 #define RTS2_SHIFT 5 /* bottom 3 bits of radix tree size */
55 #define RTS2_MASK (7UL << RTS2_SHIFT)
56 #define RPDS_MASK 0x1f /* root page dir. size field */
57
58 /* Bits in patb1 field */
59 #define PATB_GR (1UL << 63) /* guest uses radix; must match HR */
60 #define PRTS_MASK 0x1f /* process table size field */
61 #define PRTB_MASK 0x0ffffffffffff000UL
62
63 /* Number of supported PID bits */
64 extern unsigned int mmu_pid_bits;
65
66 /* Base PID to allocate from */
67 extern unsigned int mmu_base_pid;
68
69 #define PRTB_SIZE_SHIFT (mmu_pid_bits + 4)
70 #define PRTB_ENTRIES (1ul << mmu_pid_bits)
71
72 /*
73 * Power9 currently only support 64K partition table size.
74 */
75 #define PATB_SIZE_SHIFT 16
76
77 typedef unsigned long mm_context_id_t;
78 struct spinlock;
79
80 /* Maximum possible number of NPUs in a system. */
81 #define NV_MAX_NPUS 8
82
83 /*
84 * One bit per slice. We have lower slices which cover 256MB segments
85 * upto 4G range. That gets us 16 low slices. For the rest we track slices
86 * in 1TB size.
87 */
88 struct slice_mask {
89 u64 low_slices;
90 DECLARE_BITMAP(high_slices, SLICE_NUM_HIGH);
91 };
92
93 typedef struct {
94 union {
95 /*
96 * We use id as the PIDR content for radix. On hash we can use
97 * more than one id. The extended ids are used when we start
98 * having address above 512TB. We allocate one extended id
99 * for each 512TB. The new id is then used with the 49 bit
100 * EA to build a new VA. We always use ESID_BITS_1T_MASK bits
101 * from EA and new context ids to build the new VAs.
102 */
103 mm_context_id_t id;
104 mm_context_id_t extended_id[TASK_SIZE_USER64/TASK_CONTEXT_SIZE];
105 };
106 u16 user_psize; /* page size index */
107
108 /* Number of bits in the mm_cpumask */
109 atomic_t active_cpus;
110
111 /* Number of users of the external (Nest) MMU */
112 atomic_t copros;
113
114 /* NPU NMMU context */
115 struct npu_context *npu_context;
116
117 #ifdef CONFIG_PPC_MM_SLICES
118 /* SLB page size encodings*/
119 unsigned char low_slices_psize[BITS_PER_LONG / BITS_PER_BYTE];
120 unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
121 unsigned long slb_addr_limit;
122 # ifdef CONFIG_PPC_64K_PAGES
123 struct slice_mask mask_64k;
124 # endif
125 struct slice_mask mask_4k;
126 # ifdef CONFIG_HUGETLB_PAGE
127 struct slice_mask mask_16m;
128 struct slice_mask mask_16g;
129 # endif
130 #else
131 u16 sllp; /* SLB page size encoding */
132 #endif
133 unsigned long vdso_base;
134 #ifdef CONFIG_PPC_SUBPAGE_PROT
135 struct subpage_prot_table spt;
136 #endif /* CONFIG_PPC_SUBPAGE_PROT */
137 /*
138 * pagetable fragment support
139 */
140 void *pte_frag;
141 void *pmd_frag;
142 #ifdef CONFIG_SPAPR_TCE_IOMMU
143 struct list_head iommu_group_mem_list;
144 #endif
145
146 #ifdef CONFIG_PPC_MEM_KEYS
147 /*
148 * Each bit represents one protection key.
149 * bit set -> key allocated
150 * bit unset -> key available for allocation
151 */
152 u32 pkey_allocation_map;
153 s16 execute_only_pkey; /* key holding execute-only protection */
154 #endif
155 } mm_context_t;
156
157 /*
158 * The current system page and segment sizes
159 */
160 extern int mmu_linear_psize;
161 extern int mmu_virtual_psize;
162 extern int mmu_vmalloc_psize;
163 extern int mmu_vmemmap_psize;
164 extern int mmu_io_psize;
165
166 /* MMU initialization */
167 void mmu_early_init_devtree(void);
168 void hash__early_init_devtree(void);
169 void radix__early_init_devtree(void);
170 extern void radix_init_native(void);
171 extern void hash__early_init_mmu(void);
172 extern void radix__early_init_mmu(void);
early_init_mmu(void)173 static inline void early_init_mmu(void)
174 {
175 if (radix_enabled())
176 return radix__early_init_mmu();
177 return hash__early_init_mmu();
178 }
179 extern void hash__early_init_mmu_secondary(void);
180 extern void radix__early_init_mmu_secondary(void);
early_init_mmu_secondary(void)181 static inline void early_init_mmu_secondary(void)
182 {
183 if (radix_enabled())
184 return radix__early_init_mmu_secondary();
185 return hash__early_init_mmu_secondary();
186 }
187
188 extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
189 phys_addr_t first_memblock_size);
190 extern void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
191 phys_addr_t first_memblock_size);
setup_initial_memory_limit(phys_addr_t first_memblock_base,phys_addr_t first_memblock_size)192 static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
193 phys_addr_t first_memblock_size)
194 {
195 if (early_radix_enabled())
196 return radix__setup_initial_memory_limit(first_memblock_base,
197 first_memblock_size);
198 return hash__setup_initial_memory_limit(first_memblock_base,
199 first_memblock_size);
200 }
201
202 extern int (*register_process_table)(unsigned long base, unsigned long page_size,
203 unsigned long tbl_size);
204
205 #ifdef CONFIG_PPC_PSERIES
206 extern void radix_init_pseries(void);
207 #else
radix_init_pseries(void)208 static inline void radix_init_pseries(void) { };
209 #endif
210
get_ea_context(mm_context_t * ctx,unsigned long ea)211 static inline int get_ea_context(mm_context_t *ctx, unsigned long ea)
212 {
213 int index = ea >> MAX_EA_BITS_PER_CONTEXT;
214
215 if (likely(index < ARRAY_SIZE(ctx->extended_id)))
216 return ctx->extended_id[index];
217
218 /* should never happen */
219 WARN_ON(1);
220 return 0;
221 }
222
get_user_vsid(mm_context_t * ctx,unsigned long ea,int ssize)223 static inline unsigned long get_user_vsid(mm_context_t *ctx,
224 unsigned long ea, int ssize)
225 {
226 unsigned long context = get_ea_context(ctx, ea);
227
228 return get_vsid(context, ea, ssize);
229 }
230
231 #endif /* __ASSEMBLY__ */
232 #endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */
233
