1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * misc setup functions for MPC83xx
4 *
5 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
6 */
7
8 #include <linux/stddef.h>
9 #include <linux/kernel.h>
10 #include <linux/of_platform.h>
11 #include <linux/pci.h>
12
13 #include <asm/debug.h>
14 #include <asm/io.h>
15 #include <asm/hw_irq.h>
16 #include <asm/ipic.h>
17 #include <sysdev/fsl_soc.h>
18 #include <sysdev/fsl_pci.h>
19
20 #include <mm/mmu_decl.h>
21
22 #include "mpc83xx.h"
23
24 static __be32 __iomem *restart_reg_base;
25
mpc83xx_restart_init(void)26 static int __init mpc83xx_restart_init(void)
27 {
28 /* map reset restart_reg_baseister space */
29 restart_reg_base = ioremap(get_immrbase() + 0x900, 0xff);
30
31 return 0;
32 }
33
34 arch_initcall(mpc83xx_restart_init);
35
mpc83xx_restart(char * cmd)36 void __noreturn mpc83xx_restart(char *cmd)
37 {
38 #define RST_OFFSET 0x00000900
39 #define RST_PROT_REG 0x00000018
40 #define RST_CTRL_REG 0x0000001c
41
42 local_irq_disable();
43
44 if (restart_reg_base) {
45 /* enable software reset "RSTE" */
46 out_be32(restart_reg_base + (RST_PROT_REG >> 2), 0x52535445);
47
48 /* set software hard reset */
49 out_be32(restart_reg_base + (RST_CTRL_REG >> 2), 0x2);
50 } else {
51 printk (KERN_EMERG "Error: Restart registers not mapped, spinning!\n");
52 }
53
54 for (;;) ;
55 }
56
mpc83xx_time_init(void)57 long __init mpc83xx_time_init(void)
58 {
59 #define SPCR_OFFSET 0x00000110
60 #define SPCR_TBEN 0x00400000
61 __be32 __iomem *spcr = ioremap(get_immrbase() + SPCR_OFFSET, 4);
62 __be32 tmp;
63
64 tmp = in_be32(spcr);
65 out_be32(spcr, tmp | SPCR_TBEN);
66
67 iounmap(spcr);
68
69 return 0;
70 }
71
mpc83xx_ipic_init_IRQ(void)72 void __init mpc83xx_ipic_init_IRQ(void)
73 {
74 struct device_node *np;
75
76 /* looking for fsl,pq2pro-pic which is asl compatible with fsl,ipic */
77 np = of_find_compatible_node(NULL, NULL, "fsl,ipic");
78 if (!np)
79 np = of_find_node_by_type(NULL, "ipic");
80 if (!np)
81 return;
82
83 ipic_init(np, 0);
84
85 of_node_put(np);
86
87 /* Initialize the default interrupt mapping priorities,
88 * in case the boot rom changed something on us.
89 */
90 ipic_set_default_priority();
91 }
92
93 static const struct of_device_id of_bus_ids[] __initconst = {
94 { .type = "soc", },
95 { .compatible = "soc", },
96 { .compatible = "simple-bus" },
97 { .compatible = "gianfar" },
98 { .compatible = "gpio-leds", },
99 { .type = "qe", },
100 { .compatible = "fsl,qe", },
101 {},
102 };
103
mpc83xx_declare_of_platform_devices(void)104 int __init mpc83xx_declare_of_platform_devices(void)
105 {
106 of_platform_bus_probe(NULL, of_bus_ids, NULL);
107 return 0;
108 }
109
110 #ifdef CONFIG_PCI
mpc83xx_setup_pci(void)111 void __init mpc83xx_setup_pci(void)
112 {
113 struct device_node *np;
114
115 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
116 mpc83xx_add_bridge(np);
117 for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie")
118 mpc83xx_add_bridge(np);
119 }
120 #endif
121
mpc83xx_setup_arch(void)122 void __init mpc83xx_setup_arch(void)
123 {
124 if (ppc_md.progress)
125 ppc_md.progress("mpc83xx_setup_arch()", 0);
126
127 if (!__map_without_bats) {
128 phys_addr_t immrbase = get_immrbase();
129 int immrsize = IS_ALIGNED(immrbase, SZ_2M) ? SZ_2M : SZ_1M;
130 unsigned long va = fix_to_virt(FIX_IMMR_BASE);
131
132 setbat(-1, va, immrbase, immrsize, PAGE_KERNEL_NCG);
133 update_bats();
134 }
135
136 mpc83xx_setup_pci();
137 }
138
machine_check_83xx(struct pt_regs * regs)139 int machine_check_83xx(struct pt_regs *regs)
140 {
141 u32 mask = 1 << (31 - IPIC_MCP_WDT);
142
143 if (!(regs->msr & SRR1_MCE_MCP) || !(ipic_get_mcp_status() & mask))
144 return machine_check_generic(regs);
145 ipic_clear_mcp_status(mask);
146
147 if (debugger_fault_handler(regs))
148 return 1;
149
150 die("Watchdog NMI Reset", regs, 0);
151
152 return 1;
153 }
154
