1 // SPDX-License-Identifier: GPL-2.0
2 // CAN bus driver for Bosch M_CAN controller
3 // Copyright (C) 2014 Freescale Semiconductor, Inc.
4 // Dong Aisheng <b29396@freescale.com>
5 // Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/
6
7 /* Bosch M_CAN user manual can be obtained from:
8 * https://github.com/linux-can/can-doc/tree/master/m_can
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/netdevice.h>
17 #include <linux/of.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/iopoll.h>
22 #include <linux/can/dev.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/phy/phy.h>
25
26 #include "m_can.h"
27
28 /* registers definition */
29 enum m_can_reg {
30 M_CAN_CREL = 0x0,
31 M_CAN_ENDN = 0x4,
32 M_CAN_CUST = 0x8,
33 M_CAN_DBTP = 0xc,
34 M_CAN_TEST = 0x10,
35 M_CAN_RWD = 0x14,
36 M_CAN_CCCR = 0x18,
37 M_CAN_NBTP = 0x1c,
38 M_CAN_TSCC = 0x20,
39 M_CAN_TSCV = 0x24,
40 M_CAN_TOCC = 0x28,
41 M_CAN_TOCV = 0x2c,
42 M_CAN_ECR = 0x40,
43 M_CAN_PSR = 0x44,
44 /* TDCR Register only available for version >=3.1.x */
45 M_CAN_TDCR = 0x48,
46 M_CAN_IR = 0x50,
47 M_CAN_IE = 0x54,
48 M_CAN_ILS = 0x58,
49 M_CAN_ILE = 0x5c,
50 M_CAN_GFC = 0x80,
51 M_CAN_SIDFC = 0x84,
52 M_CAN_XIDFC = 0x88,
53 M_CAN_XIDAM = 0x90,
54 M_CAN_HPMS = 0x94,
55 M_CAN_NDAT1 = 0x98,
56 M_CAN_NDAT2 = 0x9c,
57 M_CAN_RXF0C = 0xa0,
58 M_CAN_RXF0S = 0xa4,
59 M_CAN_RXF0A = 0xa8,
60 M_CAN_RXBC = 0xac,
61 M_CAN_RXF1C = 0xb0,
62 M_CAN_RXF1S = 0xb4,
63 M_CAN_RXF1A = 0xb8,
64 M_CAN_RXESC = 0xbc,
65 M_CAN_TXBC = 0xc0,
66 M_CAN_TXFQS = 0xc4,
67 M_CAN_TXESC = 0xc8,
68 M_CAN_TXBRP = 0xcc,
69 M_CAN_TXBAR = 0xd0,
70 M_CAN_TXBCR = 0xd4,
71 M_CAN_TXBTO = 0xd8,
72 M_CAN_TXBCF = 0xdc,
73 M_CAN_TXBTIE = 0xe0,
74 M_CAN_TXBCIE = 0xe4,
75 M_CAN_TXEFC = 0xf0,
76 M_CAN_TXEFS = 0xf4,
77 M_CAN_TXEFA = 0xf8,
78 };
79
80 /* napi related */
81 #define M_CAN_NAPI_WEIGHT 64
82
83 /* message ram configuration data length */
84 #define MRAM_CFG_LEN 8
85
86 /* Core Release Register (CREL) */
87 #define CREL_REL_MASK GENMASK(31, 28)
88 #define CREL_STEP_MASK GENMASK(27, 24)
89 #define CREL_SUBSTEP_MASK GENMASK(23, 20)
90
91 /* Data Bit Timing & Prescaler Register (DBTP) */
92 #define DBTP_TDC BIT(23)
93 #define DBTP_DBRP_MASK GENMASK(20, 16)
94 #define DBTP_DTSEG1_MASK GENMASK(12, 8)
95 #define DBTP_DTSEG2_MASK GENMASK(7, 4)
96 #define DBTP_DSJW_MASK GENMASK(3, 0)
97
98 /* Transmitter Delay Compensation Register (TDCR) */
99 #define TDCR_TDCO_MASK GENMASK(14, 8)
100 #define TDCR_TDCF_MASK GENMASK(6, 0)
101
102 /* Test Register (TEST) */
103 #define TEST_LBCK BIT(4)
104
105 /* CC Control Register (CCCR) */
106 #define CCCR_TXP BIT(14)
107 #define CCCR_TEST BIT(7)
108 #define CCCR_DAR BIT(6)
109 #define CCCR_MON BIT(5)
110 #define CCCR_CSR BIT(4)
111 #define CCCR_CSA BIT(3)
112 #define CCCR_ASM BIT(2)
113 #define CCCR_CCE BIT(1)
114 #define CCCR_INIT BIT(0)
115 /* for version 3.0.x */
116 #define CCCR_CMR_MASK GENMASK(11, 10)
117 #define CCCR_CMR_CANFD 0x1
118 #define CCCR_CMR_CANFD_BRS 0x2
119 #define CCCR_CMR_CAN 0x3
120 #define CCCR_CME_MASK GENMASK(9, 8)
121 #define CCCR_CME_CAN 0
122 #define CCCR_CME_CANFD 0x1
123 #define CCCR_CME_CANFD_BRS 0x2
124 /* for version >=3.1.x */
125 #define CCCR_EFBI BIT(13)
126 #define CCCR_PXHD BIT(12)
127 #define CCCR_BRSE BIT(9)
128 #define CCCR_FDOE BIT(8)
129 /* for version >=3.2.x */
130 #define CCCR_NISO BIT(15)
131 /* for version >=3.3.x */
132 #define CCCR_WMM BIT(11)
133 #define CCCR_UTSU BIT(10)
134
135 /* Nominal Bit Timing & Prescaler Register (NBTP) */
136 #define NBTP_NSJW_MASK GENMASK(31, 25)
137 #define NBTP_NBRP_MASK GENMASK(24, 16)
138 #define NBTP_NTSEG1_MASK GENMASK(15, 8)
139 #define NBTP_NTSEG2_MASK GENMASK(6, 0)
140
141 /* Timestamp Counter Configuration Register (TSCC) */
142 #define TSCC_TCP_MASK GENMASK(19, 16)
143 #define TSCC_TSS_MASK GENMASK(1, 0)
144 #define TSCC_TSS_DISABLE 0x0
145 #define TSCC_TSS_INTERNAL 0x1
146 #define TSCC_TSS_EXTERNAL 0x2
147
148 /* Timestamp Counter Value Register (TSCV) */
149 #define TSCV_TSC_MASK GENMASK(15, 0)
150
151 /* Error Counter Register (ECR) */
152 #define ECR_RP BIT(15)
153 #define ECR_REC_MASK GENMASK(14, 8)
154 #define ECR_TEC_MASK GENMASK(7, 0)
155
156 /* Protocol Status Register (PSR) */
157 #define PSR_BO BIT(7)
158 #define PSR_EW BIT(6)
159 #define PSR_EP BIT(5)
160 #define PSR_LEC_MASK GENMASK(2, 0)
161
162 /* Interrupt Register (IR) */
163 #define IR_ALL_INT 0xffffffff
164
165 /* Renamed bits for versions > 3.1.x */
166 #define IR_ARA BIT(29)
167 #define IR_PED BIT(28)
168 #define IR_PEA BIT(27)
169
170 /* Bits for version 3.0.x */
171 #define IR_STE BIT(31)
172 #define IR_FOE BIT(30)
173 #define IR_ACKE BIT(29)
174 #define IR_BE BIT(28)
175 #define IR_CRCE BIT(27)
176 #define IR_WDI BIT(26)
177 #define IR_BO BIT(25)
178 #define IR_EW BIT(24)
179 #define IR_EP BIT(23)
180 #define IR_ELO BIT(22)
181 #define IR_BEU BIT(21)
182 #define IR_BEC BIT(20)
183 #define IR_DRX BIT(19)
184 #define IR_TOO BIT(18)
185 #define IR_MRAF BIT(17)
186 #define IR_TSW BIT(16)
187 #define IR_TEFL BIT(15)
188 #define IR_TEFF BIT(14)
189 #define IR_TEFW BIT(13)
190 #define IR_TEFN BIT(12)
191 #define IR_TFE BIT(11)
192 #define IR_TCF BIT(10)
193 #define IR_TC BIT(9)
194 #define IR_HPM BIT(8)
195 #define IR_RF1L BIT(7)
196 #define IR_RF1F BIT(6)
197 #define IR_RF1W BIT(5)
198 #define IR_RF1N BIT(4)
199 #define IR_RF0L BIT(3)
200 #define IR_RF0F BIT(2)
201 #define IR_RF0W BIT(1)
202 #define IR_RF0N BIT(0)
203 #define IR_ERR_STATE (IR_BO | IR_EW | IR_EP)
204
205 /* Interrupts for version 3.0.x */
206 #define IR_ERR_LEC_30X (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE)
207 #define IR_ERR_BUS_30X (IR_ERR_LEC_30X | IR_WDI | IR_ELO | IR_BEU | \
208 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \
209 IR_RF1L | IR_RF0L)
210 #define IR_ERR_ALL_30X (IR_ERR_STATE | IR_ERR_BUS_30X)
211
212 /* Interrupts for version >= 3.1.x */
213 #define IR_ERR_LEC_31X (IR_PED | IR_PEA)
214 #define IR_ERR_BUS_31X (IR_ERR_LEC_31X | IR_WDI | IR_ELO | IR_BEU | \
215 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \
216 IR_RF1L | IR_RF0L)
217 #define IR_ERR_ALL_31X (IR_ERR_STATE | IR_ERR_BUS_31X)
218
219 /* Interrupt Line Select (ILS) */
220 #define ILS_ALL_INT0 0x0
221 #define ILS_ALL_INT1 0xFFFFFFFF
222
223 /* Interrupt Line Enable (ILE) */
224 #define ILE_EINT1 BIT(1)
225 #define ILE_EINT0 BIT(0)
226
227 /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */
228 #define RXFC_FWM_MASK GENMASK(30, 24)
229 #define RXFC_FS_MASK GENMASK(22, 16)
230
231 /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */
232 #define RXFS_RFL BIT(25)
233 #define RXFS_FF BIT(24)
234 #define RXFS_FPI_MASK GENMASK(21, 16)
235 #define RXFS_FGI_MASK GENMASK(13, 8)
236 #define RXFS_FFL_MASK GENMASK(6, 0)
237
238 /* Rx Buffer / FIFO Element Size Configuration (RXESC) */
239 #define RXESC_RBDS_MASK GENMASK(10, 8)
240 #define RXESC_F1DS_MASK GENMASK(6, 4)
241 #define RXESC_F0DS_MASK GENMASK(2, 0)
242 #define RXESC_64B 0x7
243
244 /* Tx Buffer Configuration (TXBC) */
245 #define TXBC_TFQS_MASK GENMASK(29, 24)
246 #define TXBC_NDTB_MASK GENMASK(21, 16)
247
248 /* Tx FIFO/Queue Status (TXFQS) */
249 #define TXFQS_TFQF BIT(21)
250 #define TXFQS_TFQPI_MASK GENMASK(20, 16)
251 #define TXFQS_TFGI_MASK GENMASK(12, 8)
252 #define TXFQS_TFFL_MASK GENMASK(5, 0)
253
254 /* Tx Buffer Element Size Configuration (TXESC) */
255 #define TXESC_TBDS_MASK GENMASK(2, 0)
256 #define TXESC_TBDS_64B 0x7
257
258 /* Tx Event FIFO Configuration (TXEFC) */
259 #define TXEFC_EFS_MASK GENMASK(21, 16)
260
261 /* Tx Event FIFO Status (TXEFS) */
262 #define TXEFS_TEFL BIT(25)
263 #define TXEFS_EFF BIT(24)
264 #define TXEFS_EFGI_MASK GENMASK(12, 8)
265 #define TXEFS_EFFL_MASK GENMASK(5, 0)
266
267 /* Tx Event FIFO Acknowledge (TXEFA) */
268 #define TXEFA_EFAI_MASK GENMASK(4, 0)
269
270 /* Message RAM Configuration (in bytes) */
271 #define SIDF_ELEMENT_SIZE 4
272 #define XIDF_ELEMENT_SIZE 8
273 #define RXF0_ELEMENT_SIZE 72
274 #define RXF1_ELEMENT_SIZE 72
275 #define RXB_ELEMENT_SIZE 72
276 #define TXE_ELEMENT_SIZE 8
277 #define TXB_ELEMENT_SIZE 72
278
279 /* Message RAM Elements */
280 #define M_CAN_FIFO_ID 0x0
281 #define M_CAN_FIFO_DLC 0x4
282 #define M_CAN_FIFO_DATA 0x8
283
284 /* Rx Buffer Element */
285 /* R0 */
286 #define RX_BUF_ESI BIT(31)
287 #define RX_BUF_XTD BIT(30)
288 #define RX_BUF_RTR BIT(29)
289 /* R1 */
290 #define RX_BUF_ANMF BIT(31)
291 #define RX_BUF_FDF BIT(21)
292 #define RX_BUF_BRS BIT(20)
293 #define RX_BUF_RXTS_MASK GENMASK(15, 0)
294
295 /* Tx Buffer Element */
296 /* T0 */
297 #define TX_BUF_ESI BIT(31)
298 #define TX_BUF_XTD BIT(30)
299 #define TX_BUF_RTR BIT(29)
300 /* T1 */
301 #define TX_BUF_EFC BIT(23)
302 #define TX_BUF_FDF BIT(21)
303 #define TX_BUF_BRS BIT(20)
304 #define TX_BUF_MM_MASK GENMASK(31, 24)
305 #define TX_BUF_DLC_MASK GENMASK(19, 16)
306
307 /* Tx event FIFO Element */
308 /* E1 */
309 #define TX_EVENT_MM_MASK GENMASK(31, 24)
310 #define TX_EVENT_TXTS_MASK GENMASK(15, 0)
311
312 /* The ID and DLC registers are adjacent in M_CAN FIFO memory,
313 * and we can save a (potentially slow) bus round trip by combining
314 * reads and writes to them.
315 */
316 struct id_and_dlc {
317 u32 id;
318 u32 dlc;
319 };
320
m_can_read(struct m_can_classdev * cdev,enum m_can_reg reg)321 static inline u32 m_can_read(struct m_can_classdev *cdev, enum m_can_reg reg)
322 {
323 return cdev->ops->read_reg(cdev, reg);
324 }
325
m_can_write(struct m_can_classdev * cdev,enum m_can_reg reg,u32 val)326 static inline void m_can_write(struct m_can_classdev *cdev, enum m_can_reg reg,
327 u32 val)
328 {
329 cdev->ops->write_reg(cdev, reg, val);
330 }
331
332 static int
m_can_fifo_read(struct m_can_classdev * cdev,u32 fgi,unsigned int offset,void * val,size_t val_count)333 m_can_fifo_read(struct m_can_classdev *cdev,
334 u32 fgi, unsigned int offset, void *val, size_t val_count)
335 {
336 u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE +
337 offset;
338
339 return cdev->ops->read_fifo(cdev, addr_offset, val, val_count);
340 }
341
342 static int
m_can_fifo_write(struct m_can_classdev * cdev,u32 fpi,unsigned int offset,const void * val,size_t val_count)343 m_can_fifo_write(struct m_can_classdev *cdev,
344 u32 fpi, unsigned int offset, const void *val, size_t val_count)
345 {
346 u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE +
347 offset;
348
349 return cdev->ops->write_fifo(cdev, addr_offset, val, val_count);
350 }
351
m_can_fifo_write_no_off(struct m_can_classdev * cdev,u32 fpi,u32 val)352 static inline int m_can_fifo_write_no_off(struct m_can_classdev *cdev,
353 u32 fpi, u32 val)
354 {
355 return cdev->ops->write_fifo(cdev, fpi, &val, 1);
356 }
357
358 static int
m_can_txe_fifo_read(struct m_can_classdev * cdev,u32 fgi,u32 offset,u32 * val)359 m_can_txe_fifo_read(struct m_can_classdev *cdev, u32 fgi, u32 offset, u32 *val)
360 {
361 u32 addr_offset = cdev->mcfg[MRAM_TXE].off + fgi * TXE_ELEMENT_SIZE +
362 offset;
363
364 return cdev->ops->read_fifo(cdev, addr_offset, val, 1);
365 }
366
m_can_tx_fifo_full(struct m_can_classdev * cdev)367 static inline bool m_can_tx_fifo_full(struct m_can_classdev *cdev)
368 {
369 return !!(m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQF);
370 }
371
m_can_config_endisable(struct m_can_classdev * cdev,bool enable)372 static void m_can_config_endisable(struct m_can_classdev *cdev, bool enable)
373 {
374 u32 cccr = m_can_read(cdev, M_CAN_CCCR);
375 u32 timeout = 10;
376 u32 val = 0;
377
378 /* Clear the Clock stop request if it was set */
379 if (cccr & CCCR_CSR)
380 cccr &= ~CCCR_CSR;
381
382 if (enable) {
383 /* enable m_can configuration */
384 m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT);
385 udelay(5);
386 /* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */
387 m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE);
388 } else {
389 m_can_write(cdev, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE));
390 }
391
392 /* there's a delay for module initialization */
393 if (enable)
394 val = CCCR_INIT | CCCR_CCE;
395
396 while ((m_can_read(cdev, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) {
397 if (timeout == 0) {
398 netdev_warn(cdev->net, "Failed to init module\n");
399 return;
400 }
401 timeout--;
402 udelay(1);
403 }
404 }
405
m_can_enable_all_interrupts(struct m_can_classdev * cdev)406 static inline void m_can_enable_all_interrupts(struct m_can_classdev *cdev)
407 {
408 /* Only interrupt line 0 is used in this driver */
409 m_can_write(cdev, M_CAN_ILE, ILE_EINT0);
410 }
411
m_can_disable_all_interrupts(struct m_can_classdev * cdev)412 static inline void m_can_disable_all_interrupts(struct m_can_classdev *cdev)
413 {
414 m_can_write(cdev, M_CAN_ILE, 0x0);
415 }
416
417 /* Retrieve internal timestamp counter from TSCV.TSC, and shift it to 32-bit
418 * width.
419 */
m_can_get_timestamp(struct m_can_classdev * cdev)420 static u32 m_can_get_timestamp(struct m_can_classdev *cdev)
421 {
422 u32 tscv;
423 u32 tsc;
424
425 tscv = m_can_read(cdev, M_CAN_TSCV);
426 tsc = FIELD_GET(TSCV_TSC_MASK, tscv);
427
428 return (tsc << 16);
429 }
430
m_can_clean(struct net_device * net)431 static void m_can_clean(struct net_device *net)
432 {
433 struct m_can_classdev *cdev = netdev_priv(net);
434
435 if (cdev->tx_skb) {
436 int putidx = 0;
437
438 net->stats.tx_errors++;
439 if (cdev->version > 30)
440 putidx = FIELD_GET(TXFQS_TFQPI_MASK,
441 m_can_read(cdev, M_CAN_TXFQS));
442
443 can_free_echo_skb(cdev->net, putidx, NULL);
444 cdev->tx_skb = NULL;
445 }
446 }
447
448 /* For peripherals, pass skb to rx-offload, which will push skb from
449 * napi. For non-peripherals, RX is done in napi already, so push
450 * directly. timestamp is used to ensure good skb ordering in
451 * rx-offload and is ignored for non-peripherals.
452 */
m_can_receive_skb(struct m_can_classdev * cdev,struct sk_buff * skb,u32 timestamp)453 static void m_can_receive_skb(struct m_can_classdev *cdev,
454 struct sk_buff *skb,
455 u32 timestamp)
456 {
457 if (cdev->is_peripheral) {
458 struct net_device_stats *stats = &cdev->net->stats;
459 int err;
460
461 err = can_rx_offload_queue_sorted(&cdev->offload, skb,
462 timestamp);
463 if (err)
464 stats->rx_fifo_errors++;
465 } else {
466 netif_receive_skb(skb);
467 }
468 }
469
m_can_read_fifo(struct net_device * dev,u32 rxfs)470 static int m_can_read_fifo(struct net_device *dev, u32 rxfs)
471 {
472 struct net_device_stats *stats = &dev->stats;
473 struct m_can_classdev *cdev = netdev_priv(dev);
474 struct canfd_frame *cf;
475 struct sk_buff *skb;
476 struct id_and_dlc fifo_header;
477 u32 fgi;
478 u32 timestamp = 0;
479 int err;
480
481 /* calculate the fifo get index for where to read data */
482 fgi = FIELD_GET(RXFS_FGI_MASK, rxfs);
483 err = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_ID, &fifo_header, 2);
484 if (err)
485 goto out_fail;
486
487 if (fifo_header.dlc & RX_BUF_FDF)
488 skb = alloc_canfd_skb(dev, &cf);
489 else
490 skb = alloc_can_skb(dev, (struct can_frame **)&cf);
491 if (!skb) {
492 stats->rx_dropped++;
493 return 0;
494 }
495
496 if (fifo_header.dlc & RX_BUF_FDF)
497 cf->len = can_fd_dlc2len((fifo_header.dlc >> 16) & 0x0F);
498 else
499 cf->len = can_cc_dlc2len((fifo_header.dlc >> 16) & 0x0F);
500
501 if (fifo_header.id & RX_BUF_XTD)
502 cf->can_id = (fifo_header.id & CAN_EFF_MASK) | CAN_EFF_FLAG;
503 else
504 cf->can_id = (fifo_header.id >> 18) & CAN_SFF_MASK;
505
506 if (fifo_header.id & RX_BUF_ESI) {
507 cf->flags |= CANFD_ESI;
508 netdev_dbg(dev, "ESI Error\n");
509 }
510
511 if (!(fifo_header.dlc & RX_BUF_FDF) && (fifo_header.id & RX_BUF_RTR)) {
512 cf->can_id |= CAN_RTR_FLAG;
513 } else {
514 if (fifo_header.dlc & RX_BUF_BRS)
515 cf->flags |= CANFD_BRS;
516
517 err = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_DATA,
518 cf->data, DIV_ROUND_UP(cf->len, 4));
519 if (err)
520 goto out_fail;
521 }
522
523 /* acknowledge rx fifo 0 */
524 m_can_write(cdev, M_CAN_RXF0A, fgi);
525
526 stats->rx_packets++;
527 stats->rx_bytes += cf->len;
528
529 timestamp = FIELD_GET(RX_BUF_RXTS_MASK, fifo_header.dlc);
530
531 m_can_receive_skb(cdev, skb, timestamp);
532
533 return 0;
534
535 out_fail:
536 netdev_err(dev, "FIFO read returned %d\n", err);
537 return err;
538 }
539
m_can_do_rx_poll(struct net_device * dev,int quota)540 static int m_can_do_rx_poll(struct net_device *dev, int quota)
541 {
542 struct m_can_classdev *cdev = netdev_priv(dev);
543 u32 pkts = 0;
544 u32 rxfs;
545 int err;
546
547 rxfs = m_can_read(cdev, M_CAN_RXF0S);
548 if (!(rxfs & RXFS_FFL_MASK)) {
549 netdev_dbg(dev, "no messages in fifo0\n");
550 return 0;
551 }
552
553 while ((rxfs & RXFS_FFL_MASK) && (quota > 0)) {
554 err = m_can_read_fifo(dev, rxfs);
555 if (err)
556 return err;
557
558 quota--;
559 pkts++;
560 rxfs = m_can_read(cdev, M_CAN_RXF0S);
561 }
562
563 if (pkts)
564 can_led_event(dev, CAN_LED_EVENT_RX);
565
566 return pkts;
567 }
568
m_can_handle_lost_msg(struct net_device * dev)569 static int m_can_handle_lost_msg(struct net_device *dev)
570 {
571 struct m_can_classdev *cdev = netdev_priv(dev);
572 struct net_device_stats *stats = &dev->stats;
573 struct sk_buff *skb;
574 struct can_frame *frame;
575 u32 timestamp = 0;
576
577 netdev_err(dev, "msg lost in rxf0\n");
578
579 stats->rx_errors++;
580 stats->rx_over_errors++;
581
582 skb = alloc_can_err_skb(dev, &frame);
583 if (unlikely(!skb))
584 return 0;
585
586 frame->can_id |= CAN_ERR_CRTL;
587 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
588
589 if (cdev->is_peripheral)
590 timestamp = m_can_get_timestamp(cdev);
591
592 m_can_receive_skb(cdev, skb, timestamp);
593
594 return 1;
595 }
596
m_can_handle_lec_err(struct net_device * dev,enum m_can_lec_type lec_type)597 static int m_can_handle_lec_err(struct net_device *dev,
598 enum m_can_lec_type lec_type)
599 {
600 struct m_can_classdev *cdev = netdev_priv(dev);
601 struct net_device_stats *stats = &dev->stats;
602 struct can_frame *cf;
603 struct sk_buff *skb;
604 u32 timestamp = 0;
605
606 cdev->can.can_stats.bus_error++;
607 stats->rx_errors++;
608
609 /* propagate the error condition to the CAN stack */
610 skb = alloc_can_err_skb(dev, &cf);
611 if (unlikely(!skb))
612 return 0;
613
614 /* check for 'last error code' which tells us the
615 * type of the last error to occur on the CAN bus
616 */
617 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
618
619 switch (lec_type) {
620 case LEC_STUFF_ERROR:
621 netdev_dbg(dev, "stuff error\n");
622 cf->data[2] |= CAN_ERR_PROT_STUFF;
623 break;
624 case LEC_FORM_ERROR:
625 netdev_dbg(dev, "form error\n");
626 cf->data[2] |= CAN_ERR_PROT_FORM;
627 break;
628 case LEC_ACK_ERROR:
629 netdev_dbg(dev, "ack error\n");
630 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
631 break;
632 case LEC_BIT1_ERROR:
633 netdev_dbg(dev, "bit1 error\n");
634 cf->data[2] |= CAN_ERR_PROT_BIT1;
635 break;
636 case LEC_BIT0_ERROR:
637 netdev_dbg(dev, "bit0 error\n");
638 cf->data[2] |= CAN_ERR_PROT_BIT0;
639 break;
640 case LEC_CRC_ERROR:
641 netdev_dbg(dev, "CRC error\n");
642 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
643 break;
644 default:
645 break;
646 }
647
648 stats->rx_packets++;
649 stats->rx_bytes += cf->len;
650
651 if (cdev->is_peripheral)
652 timestamp = m_can_get_timestamp(cdev);
653
654 m_can_receive_skb(cdev, skb, timestamp);
655
656 return 1;
657 }
658
__m_can_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)659 static int __m_can_get_berr_counter(const struct net_device *dev,
660 struct can_berr_counter *bec)
661 {
662 struct m_can_classdev *cdev = netdev_priv(dev);
663 unsigned int ecr;
664
665 ecr = m_can_read(cdev, M_CAN_ECR);
666 bec->rxerr = FIELD_GET(ECR_REC_MASK, ecr);
667 bec->txerr = FIELD_GET(ECR_TEC_MASK, ecr);
668
669 return 0;
670 }
671
m_can_clk_start(struct m_can_classdev * cdev)672 static int m_can_clk_start(struct m_can_classdev *cdev)
673 {
674 if (cdev->pm_clock_support == 0)
675 return 0;
676
677 return pm_runtime_resume_and_get(cdev->dev);
678 }
679
m_can_clk_stop(struct m_can_classdev * cdev)680 static void m_can_clk_stop(struct m_can_classdev *cdev)
681 {
682 if (cdev->pm_clock_support)
683 pm_runtime_put_sync(cdev->dev);
684 }
685
m_can_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)686 static int m_can_get_berr_counter(const struct net_device *dev,
687 struct can_berr_counter *bec)
688 {
689 struct m_can_classdev *cdev = netdev_priv(dev);
690 int err;
691
692 err = m_can_clk_start(cdev);
693 if (err)
694 return err;
695
696 __m_can_get_berr_counter(dev, bec);
697
698 m_can_clk_stop(cdev);
699
700 return 0;
701 }
702
m_can_handle_state_change(struct net_device * dev,enum can_state new_state)703 static int m_can_handle_state_change(struct net_device *dev,
704 enum can_state new_state)
705 {
706 struct m_can_classdev *cdev = netdev_priv(dev);
707 struct net_device_stats *stats = &dev->stats;
708 struct can_frame *cf;
709 struct sk_buff *skb;
710 struct can_berr_counter bec;
711 unsigned int ecr;
712 u32 timestamp = 0;
713
714 switch (new_state) {
715 case CAN_STATE_ERROR_WARNING:
716 /* error warning state */
717 cdev->can.can_stats.error_warning++;
718 cdev->can.state = CAN_STATE_ERROR_WARNING;
719 break;
720 case CAN_STATE_ERROR_PASSIVE:
721 /* error passive state */
722 cdev->can.can_stats.error_passive++;
723 cdev->can.state = CAN_STATE_ERROR_PASSIVE;
724 break;
725 case CAN_STATE_BUS_OFF:
726 /* bus-off state */
727 cdev->can.state = CAN_STATE_BUS_OFF;
728 m_can_disable_all_interrupts(cdev);
729 cdev->can.can_stats.bus_off++;
730 can_bus_off(dev);
731 break;
732 default:
733 break;
734 }
735
736 /* propagate the error condition to the CAN stack */
737 skb = alloc_can_err_skb(dev, &cf);
738 if (unlikely(!skb))
739 return 0;
740
741 __m_can_get_berr_counter(dev, &bec);
742
743 switch (new_state) {
744 case CAN_STATE_ERROR_WARNING:
745 /* error warning state */
746 cf->can_id |= CAN_ERR_CRTL;
747 cf->data[1] = (bec.txerr > bec.rxerr) ?
748 CAN_ERR_CRTL_TX_WARNING :
749 CAN_ERR_CRTL_RX_WARNING;
750 cf->data[6] = bec.txerr;
751 cf->data[7] = bec.rxerr;
752 break;
753 case CAN_STATE_ERROR_PASSIVE:
754 /* error passive state */
755 cf->can_id |= CAN_ERR_CRTL;
756 ecr = m_can_read(cdev, M_CAN_ECR);
757 if (ecr & ECR_RP)
758 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
759 if (bec.txerr > 127)
760 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
761 cf->data[6] = bec.txerr;
762 cf->data[7] = bec.rxerr;
763 break;
764 case CAN_STATE_BUS_OFF:
765 /* bus-off state */
766 cf->can_id |= CAN_ERR_BUSOFF;
767 break;
768 default:
769 break;
770 }
771
772 stats->rx_packets++;
773 stats->rx_bytes += cf->len;
774
775 if (cdev->is_peripheral)
776 timestamp = m_can_get_timestamp(cdev);
777
778 m_can_receive_skb(cdev, skb, timestamp);
779
780 return 1;
781 }
782
m_can_handle_state_errors(struct net_device * dev,u32 psr)783 static int m_can_handle_state_errors(struct net_device *dev, u32 psr)
784 {
785 struct m_can_classdev *cdev = netdev_priv(dev);
786 int work_done = 0;
787
788 if (psr & PSR_EW && cdev->can.state != CAN_STATE_ERROR_WARNING) {
789 netdev_dbg(dev, "entered error warning state\n");
790 work_done += m_can_handle_state_change(dev,
791 CAN_STATE_ERROR_WARNING);
792 }
793
794 if (psr & PSR_EP && cdev->can.state != CAN_STATE_ERROR_PASSIVE) {
795 netdev_dbg(dev, "entered error passive state\n");
796 work_done += m_can_handle_state_change(dev,
797 CAN_STATE_ERROR_PASSIVE);
798 }
799
800 if (psr & PSR_BO && cdev->can.state != CAN_STATE_BUS_OFF) {
801 netdev_dbg(dev, "entered error bus off state\n");
802 work_done += m_can_handle_state_change(dev,
803 CAN_STATE_BUS_OFF);
804 }
805
806 return work_done;
807 }
808
m_can_handle_other_err(struct net_device * dev,u32 irqstatus)809 static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus)
810 {
811 if (irqstatus & IR_WDI)
812 netdev_err(dev, "Message RAM Watchdog event due to missing READY\n");
813 if (irqstatus & IR_ELO)
814 netdev_err(dev, "Error Logging Overflow\n");
815 if (irqstatus & IR_BEU)
816 netdev_err(dev, "Bit Error Uncorrected\n");
817 if (irqstatus & IR_BEC)
818 netdev_err(dev, "Bit Error Corrected\n");
819 if (irqstatus & IR_TOO)
820 netdev_err(dev, "Timeout reached\n");
821 if (irqstatus & IR_MRAF)
822 netdev_err(dev, "Message RAM access failure occurred\n");
823 }
824
is_lec_err(u32 psr)825 static inline bool is_lec_err(u32 psr)
826 {
827 psr &= LEC_UNUSED;
828
829 return psr && (psr != LEC_UNUSED);
830 }
831
m_can_is_protocol_err(u32 irqstatus)832 static inline bool m_can_is_protocol_err(u32 irqstatus)
833 {
834 return irqstatus & IR_ERR_LEC_31X;
835 }
836
m_can_handle_protocol_error(struct net_device * dev,u32 irqstatus)837 static int m_can_handle_protocol_error(struct net_device *dev, u32 irqstatus)
838 {
839 struct net_device_stats *stats = &dev->stats;
840 struct m_can_classdev *cdev = netdev_priv(dev);
841 struct can_frame *cf;
842 struct sk_buff *skb;
843 u32 timestamp = 0;
844
845 /* propagate the error condition to the CAN stack */
846 skb = alloc_can_err_skb(dev, &cf);
847
848 /* update tx error stats since there is protocol error */
849 stats->tx_errors++;
850
851 /* update arbitration lost status */
852 if (cdev->version >= 31 && (irqstatus & IR_PEA)) {
853 netdev_dbg(dev, "Protocol error in Arbitration fail\n");
854 cdev->can.can_stats.arbitration_lost++;
855 if (skb) {
856 cf->can_id |= CAN_ERR_LOSTARB;
857 cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
858 }
859 }
860
861 if (unlikely(!skb)) {
862 netdev_dbg(dev, "allocation of skb failed\n");
863 return 0;
864 }
865
866 if (cdev->is_peripheral)
867 timestamp = m_can_get_timestamp(cdev);
868
869 m_can_receive_skb(cdev, skb, timestamp);
870
871 return 1;
872 }
873
m_can_handle_bus_errors(struct net_device * dev,u32 irqstatus,u32 psr)874 static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus,
875 u32 psr)
876 {
877 struct m_can_classdev *cdev = netdev_priv(dev);
878 int work_done = 0;
879
880 if (irqstatus & IR_RF0L)
881 work_done += m_can_handle_lost_msg(dev);
882
883 /* handle lec errors on the bus */
884 if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
885 is_lec_err(psr))
886 work_done += m_can_handle_lec_err(dev, psr & LEC_UNUSED);
887
888 /* handle protocol errors in arbitration phase */
889 if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
890 m_can_is_protocol_err(irqstatus))
891 work_done += m_can_handle_protocol_error(dev, irqstatus);
892
893 /* other unproccessed error interrupts */
894 m_can_handle_other_err(dev, irqstatus);
895
896 return work_done;
897 }
898
m_can_rx_handler(struct net_device * dev,int quota)899 static int m_can_rx_handler(struct net_device *dev, int quota)
900 {
901 struct m_can_classdev *cdev = netdev_priv(dev);
902 int rx_work_or_err;
903 int work_done = 0;
904 u32 irqstatus, psr;
905
906 irqstatus = cdev->irqstatus | m_can_read(cdev, M_CAN_IR);
907 if (!irqstatus)
908 goto end;
909
910 /* Errata workaround for issue "Needless activation of MRAF irq"
911 * During frame reception while the MCAN is in Error Passive state
912 * and the Receive Error Counter has the value MCAN_ECR.REC = 127,
913 * it may happen that MCAN_IR.MRAF is set although there was no
914 * Message RAM access failure.
915 * If MCAN_IR.MRAF is enabled, an interrupt to the Host CPU is generated
916 * The Message RAM Access Failure interrupt routine needs to check
917 * whether MCAN_ECR.RP = ’1’ and MCAN_ECR.REC = 127.
918 * In this case, reset MCAN_IR.MRAF. No further action is required.
919 */
920 if (cdev->version <= 31 && irqstatus & IR_MRAF &&
921 m_can_read(cdev, M_CAN_ECR) & ECR_RP) {
922 struct can_berr_counter bec;
923
924 __m_can_get_berr_counter(dev, &bec);
925 if (bec.rxerr == 127) {
926 m_can_write(cdev, M_CAN_IR, IR_MRAF);
927 irqstatus &= ~IR_MRAF;
928 }
929 }
930
931 psr = m_can_read(cdev, M_CAN_PSR);
932
933 if (irqstatus & IR_ERR_STATE)
934 work_done += m_can_handle_state_errors(dev, psr);
935
936 if (irqstatus & IR_ERR_BUS_30X)
937 work_done += m_can_handle_bus_errors(dev, irqstatus, psr);
938
939 if (irqstatus & IR_RF0N) {
940 rx_work_or_err = m_can_do_rx_poll(dev, (quota - work_done));
941 if (rx_work_or_err < 0)
942 return rx_work_or_err;
943
944 work_done += rx_work_or_err;
945 }
946 end:
947 return work_done;
948 }
949
m_can_rx_peripheral(struct net_device * dev)950 static int m_can_rx_peripheral(struct net_device *dev)
951 {
952 struct m_can_classdev *cdev = netdev_priv(dev);
953 int work_done;
954
955 work_done = m_can_rx_handler(dev, M_CAN_NAPI_WEIGHT);
956
957 /* Don't re-enable interrupts if the driver had a fatal error
958 * (e.g., FIFO read failure).
959 */
960 if (work_done >= 0)
961 m_can_enable_all_interrupts(cdev);
962
963 return work_done;
964 }
965
m_can_poll(struct napi_struct * napi,int quota)966 static int m_can_poll(struct napi_struct *napi, int quota)
967 {
968 struct net_device *dev = napi->dev;
969 struct m_can_classdev *cdev = netdev_priv(dev);
970 int work_done;
971
972 work_done = m_can_rx_handler(dev, quota);
973
974 /* Don't re-enable interrupts if the driver had a fatal error
975 * (e.g., FIFO read failure).
976 */
977 if (work_done >= 0 && work_done < quota) {
978 napi_complete_done(napi, work_done);
979 m_can_enable_all_interrupts(cdev);
980 }
981
982 return work_done;
983 }
984
985 /* Echo tx skb and update net stats. Peripherals use rx-offload for
986 * echo. timestamp is used for peripherals to ensure correct ordering
987 * by rx-offload, and is ignored for non-peripherals.
988 */
m_can_tx_update_stats(struct m_can_classdev * cdev,unsigned int msg_mark,u32 timestamp)989 static void m_can_tx_update_stats(struct m_can_classdev *cdev,
990 unsigned int msg_mark,
991 u32 timestamp)
992 {
993 struct net_device *dev = cdev->net;
994 struct net_device_stats *stats = &dev->stats;
995
996 if (cdev->is_peripheral)
997 stats->tx_bytes +=
998 can_rx_offload_get_echo_skb(&cdev->offload,
999 msg_mark,
1000 timestamp,
1001 NULL);
1002 else
1003 stats->tx_bytes += can_get_echo_skb(dev, msg_mark, NULL);
1004
1005 stats->tx_packets++;
1006 }
1007
m_can_echo_tx_event(struct net_device * dev)1008 static int m_can_echo_tx_event(struct net_device *dev)
1009 {
1010 u32 txe_count = 0;
1011 u32 m_can_txefs;
1012 u32 fgi = 0;
1013 int i = 0;
1014 unsigned int msg_mark;
1015
1016 struct m_can_classdev *cdev = netdev_priv(dev);
1017
1018 /* read tx event fifo status */
1019 m_can_txefs = m_can_read(cdev, M_CAN_TXEFS);
1020
1021 /* Get Tx Event fifo element count */
1022 txe_count = FIELD_GET(TXEFS_EFFL_MASK, m_can_txefs);
1023
1024 /* Get and process all sent elements */
1025 for (i = 0; i < txe_count; i++) {
1026 u32 txe, timestamp = 0;
1027 int err;
1028
1029 /* retrieve get index */
1030 fgi = FIELD_GET(TXEFS_EFGI_MASK, m_can_read(cdev, M_CAN_TXEFS));
1031
1032 /* get message marker, timestamp */
1033 err = m_can_txe_fifo_read(cdev, fgi, 4, &txe);
1034 if (err) {
1035 netdev_err(dev, "TXE FIFO read returned %d\n", err);
1036 return err;
1037 }
1038
1039 msg_mark = FIELD_GET(TX_EVENT_MM_MASK, txe);
1040 timestamp = FIELD_GET(TX_EVENT_TXTS_MASK, txe);
1041
1042 /* ack txe element */
1043 m_can_write(cdev, M_CAN_TXEFA, FIELD_PREP(TXEFA_EFAI_MASK,
1044 fgi));
1045
1046 /* update stats */
1047 m_can_tx_update_stats(cdev, msg_mark, timestamp);
1048 }
1049
1050 return 0;
1051 }
1052
m_can_isr(int irq,void * dev_id)1053 static irqreturn_t m_can_isr(int irq, void *dev_id)
1054 {
1055 struct net_device *dev = (struct net_device *)dev_id;
1056 struct m_can_classdev *cdev = netdev_priv(dev);
1057 u32 ir;
1058
1059 if (pm_runtime_suspended(cdev->dev))
1060 return IRQ_NONE;
1061 ir = m_can_read(cdev, M_CAN_IR);
1062 if (!ir)
1063 return IRQ_NONE;
1064
1065 /* ACK all irqs */
1066 if (ir & IR_ALL_INT)
1067 m_can_write(cdev, M_CAN_IR, ir);
1068
1069 if (cdev->ops->clear_interrupts)
1070 cdev->ops->clear_interrupts(cdev);
1071
1072 /* schedule NAPI in case of
1073 * - rx IRQ
1074 * - state change IRQ
1075 * - bus error IRQ and bus error reporting
1076 */
1077 if ((ir & IR_RF0N) || (ir & IR_ERR_ALL_30X)) {
1078 cdev->irqstatus = ir;
1079 m_can_disable_all_interrupts(cdev);
1080 if (!cdev->is_peripheral)
1081 napi_schedule(&cdev->napi);
1082 else if (m_can_rx_peripheral(dev) < 0)
1083 goto out_fail;
1084 }
1085
1086 if (cdev->version == 30) {
1087 if (ir & IR_TC) {
1088 /* Transmission Complete Interrupt*/
1089 u32 timestamp = 0;
1090
1091 if (cdev->is_peripheral)
1092 timestamp = m_can_get_timestamp(cdev);
1093 m_can_tx_update_stats(cdev, 0, timestamp);
1094
1095 can_led_event(dev, CAN_LED_EVENT_TX);
1096 netif_wake_queue(dev);
1097 }
1098 } else {
1099 if (ir & IR_TEFN) {
1100 /* New TX FIFO Element arrived */
1101 if (m_can_echo_tx_event(dev) != 0)
1102 goto out_fail;
1103
1104 can_led_event(dev, CAN_LED_EVENT_TX);
1105 if (netif_queue_stopped(dev) &&
1106 !m_can_tx_fifo_full(cdev))
1107 netif_wake_queue(dev);
1108 }
1109 }
1110
1111 if (cdev->is_peripheral)
1112 can_rx_offload_threaded_irq_finish(&cdev->offload);
1113
1114 return IRQ_HANDLED;
1115
1116 out_fail:
1117 m_can_disable_all_interrupts(cdev);
1118 return IRQ_HANDLED;
1119 }
1120
1121 static const struct can_bittiming_const m_can_bittiming_const_30X = {
1122 .name = KBUILD_MODNAME,
1123 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
1124 .tseg1_max = 64,
1125 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
1126 .tseg2_max = 16,
1127 .sjw_max = 16,
1128 .brp_min = 1,
1129 .brp_max = 1024,
1130 .brp_inc = 1,
1131 };
1132
1133 static const struct can_bittiming_const m_can_data_bittiming_const_30X = {
1134 .name = KBUILD_MODNAME,
1135 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
1136 .tseg1_max = 16,
1137 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
1138 .tseg2_max = 8,
1139 .sjw_max = 4,
1140 .brp_min = 1,
1141 .brp_max = 32,
1142 .brp_inc = 1,
1143 };
1144
1145 static const struct can_bittiming_const m_can_bittiming_const_31X = {
1146 .name = KBUILD_MODNAME,
1147 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
1148 .tseg1_max = 256,
1149 .tseg2_min = 2, /* Time segment 2 = phase_seg2 */
1150 .tseg2_max = 128,
1151 .sjw_max = 128,
1152 .brp_min = 1,
1153 .brp_max = 512,
1154 .brp_inc = 1,
1155 };
1156
1157 static const struct can_bittiming_const m_can_data_bittiming_const_31X = {
1158 .name = KBUILD_MODNAME,
1159 .tseg1_min = 1, /* Time segment 1 = prop_seg + phase_seg1 */
1160 .tseg1_max = 32,
1161 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
1162 .tseg2_max = 16,
1163 .sjw_max = 16,
1164 .brp_min = 1,
1165 .brp_max = 32,
1166 .brp_inc = 1,
1167 };
1168
m_can_set_bittiming(struct net_device * dev)1169 static int m_can_set_bittiming(struct net_device *dev)
1170 {
1171 struct m_can_classdev *cdev = netdev_priv(dev);
1172 const struct can_bittiming *bt = &cdev->can.bittiming;
1173 const struct can_bittiming *dbt = &cdev->can.data_bittiming;
1174 u16 brp, sjw, tseg1, tseg2;
1175 u32 reg_btp;
1176
1177 brp = bt->brp - 1;
1178 sjw = bt->sjw - 1;
1179 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
1180 tseg2 = bt->phase_seg2 - 1;
1181 reg_btp = FIELD_PREP(NBTP_NBRP_MASK, brp) |
1182 FIELD_PREP(NBTP_NSJW_MASK, sjw) |
1183 FIELD_PREP(NBTP_NTSEG1_MASK, tseg1) |
1184 FIELD_PREP(NBTP_NTSEG2_MASK, tseg2);
1185 m_can_write(cdev, M_CAN_NBTP, reg_btp);
1186
1187 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) {
1188 reg_btp = 0;
1189 brp = dbt->brp - 1;
1190 sjw = dbt->sjw - 1;
1191 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
1192 tseg2 = dbt->phase_seg2 - 1;
1193
1194 /* TDC is only needed for bitrates beyond 2.5 MBit/s.
1195 * This is mentioned in the "Bit Time Requirements for CAN FD"
1196 * paper presented at the International CAN Conference 2013
1197 */
1198 if (dbt->bitrate > 2500000) {
1199 u32 tdco, ssp;
1200
1201 /* Use the same value of secondary sampling point
1202 * as the data sampling point
1203 */
1204 ssp = dbt->sample_point;
1205
1206 /* Equation based on Bosch's M_CAN User Manual's
1207 * Transmitter Delay Compensation Section
1208 */
1209 tdco = (cdev->can.clock.freq / 1000) *
1210 ssp / dbt->bitrate;
1211
1212 /* Max valid TDCO value is 127 */
1213 if (tdco > 127) {
1214 netdev_warn(dev, "TDCO value of %u is beyond maximum. Using maximum possible value\n",
1215 tdco);
1216 tdco = 127;
1217 }
1218
1219 reg_btp |= DBTP_TDC;
1220 m_can_write(cdev, M_CAN_TDCR,
1221 FIELD_PREP(TDCR_TDCO_MASK, tdco));
1222 }
1223
1224 reg_btp |= FIELD_PREP(DBTP_DBRP_MASK, brp) |
1225 FIELD_PREP(DBTP_DSJW_MASK, sjw) |
1226 FIELD_PREP(DBTP_DTSEG1_MASK, tseg1) |
1227 FIELD_PREP(DBTP_DTSEG2_MASK, tseg2);
1228
1229 m_can_write(cdev, M_CAN_DBTP, reg_btp);
1230 }
1231
1232 return 0;
1233 }
1234
1235 /* Configure M_CAN chip:
1236 * - set rx buffer/fifo element size
1237 * - configure rx fifo
1238 * - accept non-matching frame into fifo 0
1239 * - configure tx buffer
1240 * - >= v3.1.x: TX FIFO is used
1241 * - configure mode
1242 * - setup bittiming
1243 * - configure timestamp generation
1244 */
m_can_chip_config(struct net_device * dev)1245 static void m_can_chip_config(struct net_device *dev)
1246 {
1247 struct m_can_classdev *cdev = netdev_priv(dev);
1248 u32 cccr, test;
1249
1250 m_can_config_endisable(cdev, true);
1251
1252 /* RX Buffer/FIFO Element Size 64 bytes data field */
1253 m_can_write(cdev, M_CAN_RXESC,
1254 FIELD_PREP(RXESC_RBDS_MASK, RXESC_64B) |
1255 FIELD_PREP(RXESC_F1DS_MASK, RXESC_64B) |
1256 FIELD_PREP(RXESC_F0DS_MASK, RXESC_64B));
1257
1258 /* Accept Non-matching Frames Into FIFO 0 */
1259 m_can_write(cdev, M_CAN_GFC, 0x0);
1260
1261 if (cdev->version == 30) {
1262 /* only support one Tx Buffer currently */
1263 m_can_write(cdev, M_CAN_TXBC, FIELD_PREP(TXBC_NDTB_MASK, 1) |
1264 cdev->mcfg[MRAM_TXB].off);
1265 } else {
1266 /* TX FIFO is used for newer IP Core versions */
1267 m_can_write(cdev, M_CAN_TXBC,
1268 FIELD_PREP(TXBC_TFQS_MASK,
1269 cdev->mcfg[MRAM_TXB].num) |
1270 cdev->mcfg[MRAM_TXB].off);
1271 }
1272
1273 /* support 64 bytes payload */
1274 m_can_write(cdev, M_CAN_TXESC,
1275 FIELD_PREP(TXESC_TBDS_MASK, TXESC_TBDS_64B));
1276
1277 /* TX Event FIFO */
1278 if (cdev->version == 30) {
1279 m_can_write(cdev, M_CAN_TXEFC,
1280 FIELD_PREP(TXEFC_EFS_MASK, 1) |
1281 cdev->mcfg[MRAM_TXE].off);
1282 } else {
1283 /* Full TX Event FIFO is used */
1284 m_can_write(cdev, M_CAN_TXEFC,
1285 FIELD_PREP(TXEFC_EFS_MASK,
1286 cdev->mcfg[MRAM_TXE].num) |
1287 cdev->mcfg[MRAM_TXE].off);
1288 }
1289
1290 /* rx fifo configuration, blocking mode, fifo size 1 */
1291 m_can_write(cdev, M_CAN_RXF0C,
1292 FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF0].num) |
1293 cdev->mcfg[MRAM_RXF0].off);
1294
1295 m_can_write(cdev, M_CAN_RXF1C,
1296 FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF1].num) |
1297 cdev->mcfg[MRAM_RXF1].off);
1298
1299 cccr = m_can_read(cdev, M_CAN_CCCR);
1300 test = m_can_read(cdev, M_CAN_TEST);
1301 test &= ~TEST_LBCK;
1302 if (cdev->version == 30) {
1303 /* Version 3.0.x */
1304
1305 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_DAR |
1306 FIELD_PREP(CCCR_CMR_MASK, FIELD_MAX(CCCR_CMR_MASK)) |
1307 FIELD_PREP(CCCR_CME_MASK, FIELD_MAX(CCCR_CME_MASK)));
1308
1309 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD)
1310 cccr |= FIELD_PREP(CCCR_CME_MASK, CCCR_CME_CANFD_BRS);
1311
1312 } else {
1313 /* Version 3.1.x or 3.2.x */
1314 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_BRSE | CCCR_FDOE |
1315 CCCR_NISO | CCCR_DAR);
1316
1317 /* Only 3.2.x has NISO Bit implemented */
1318 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)
1319 cccr |= CCCR_NISO;
1320
1321 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD)
1322 cccr |= (CCCR_BRSE | CCCR_FDOE);
1323 }
1324
1325 /* Loopback Mode */
1326 if (cdev->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
1327 cccr |= CCCR_TEST | CCCR_MON;
1328 test |= TEST_LBCK;
1329 }
1330
1331 /* Enable Monitoring (all versions) */
1332 if (cdev->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1333 cccr |= CCCR_MON;
1334
1335 /* Disable Auto Retransmission (all versions) */
1336 if (cdev->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
1337 cccr |= CCCR_DAR;
1338
1339 /* Write config */
1340 m_can_write(cdev, M_CAN_CCCR, cccr);
1341 m_can_write(cdev, M_CAN_TEST, test);
1342
1343 /* Enable interrupts */
1344 m_can_write(cdev, M_CAN_IR, IR_ALL_INT);
1345 if (!(cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
1346 if (cdev->version == 30)
1347 m_can_write(cdev, M_CAN_IE, IR_ALL_INT &
1348 ~(IR_ERR_LEC_30X));
1349 else
1350 m_can_write(cdev, M_CAN_IE, IR_ALL_INT &
1351 ~(IR_ERR_LEC_31X));
1352 else
1353 m_can_write(cdev, M_CAN_IE, IR_ALL_INT);
1354
1355 /* route all interrupts to INT0 */
1356 m_can_write(cdev, M_CAN_ILS, ILS_ALL_INT0);
1357
1358 /* set bittiming params */
1359 m_can_set_bittiming(dev);
1360
1361 /* enable internal timestamp generation, with a prescalar of 16. The
1362 * prescalar is applied to the nominal bit timing
1363 */
1364 m_can_write(cdev, M_CAN_TSCC, FIELD_PREP(TSCC_TCP_MASK, 0xf));
1365
1366 m_can_config_endisable(cdev, false);
1367
1368 if (cdev->ops->init)
1369 cdev->ops->init(cdev);
1370 }
1371
m_can_start(struct net_device * dev)1372 static void m_can_start(struct net_device *dev)
1373 {
1374 struct m_can_classdev *cdev = netdev_priv(dev);
1375
1376 /* basic m_can configuration */
1377 m_can_chip_config(dev);
1378
1379 cdev->can.state = CAN_STATE_ERROR_ACTIVE;
1380
1381 m_can_enable_all_interrupts(cdev);
1382 }
1383
m_can_set_mode(struct net_device * dev,enum can_mode mode)1384 static int m_can_set_mode(struct net_device *dev, enum can_mode mode)
1385 {
1386 switch (mode) {
1387 case CAN_MODE_START:
1388 m_can_clean(dev);
1389 m_can_start(dev);
1390 netif_wake_queue(dev);
1391 break;
1392 default:
1393 return -EOPNOTSUPP;
1394 }
1395
1396 return 0;
1397 }
1398
1399 /* Checks core release number of M_CAN
1400 * returns 0 if an unsupported device is detected
1401 * else it returns the release and step coded as:
1402 * return value = 10 * <release> + 1 * <step>
1403 */
m_can_check_core_release(struct m_can_classdev * cdev)1404 static int m_can_check_core_release(struct m_can_classdev *cdev)
1405 {
1406 u32 crel_reg;
1407 u8 rel;
1408 u8 step;
1409 int res;
1410
1411 /* Read Core Release Version and split into version number
1412 * Example: Version 3.2.1 => rel = 3; step = 2; substep = 1;
1413 */
1414 crel_reg = m_can_read(cdev, M_CAN_CREL);
1415 rel = (u8)FIELD_GET(CREL_REL_MASK, crel_reg);
1416 step = (u8)FIELD_GET(CREL_STEP_MASK, crel_reg);
1417
1418 if (rel == 3) {
1419 /* M_CAN v3.x.y: create return value */
1420 res = 30 + step;
1421 } else {
1422 /* Unsupported M_CAN version */
1423 res = 0;
1424 }
1425
1426 return res;
1427 }
1428
1429 /* Selectable Non ISO support only in version 3.2.x
1430 * This function checks if the bit is writable.
1431 */
m_can_niso_supported(struct m_can_classdev * cdev)1432 static bool m_can_niso_supported(struct m_can_classdev *cdev)
1433 {
1434 u32 cccr_reg, cccr_poll = 0;
1435 int niso_timeout = -ETIMEDOUT;
1436 int i;
1437
1438 m_can_config_endisable(cdev, true);
1439 cccr_reg = m_can_read(cdev, M_CAN_CCCR);
1440 cccr_reg |= CCCR_NISO;
1441 m_can_write(cdev, M_CAN_CCCR, cccr_reg);
1442
1443 for (i = 0; i <= 10; i++) {
1444 cccr_poll = m_can_read(cdev, M_CAN_CCCR);
1445 if (cccr_poll == cccr_reg) {
1446 niso_timeout = 0;
1447 break;
1448 }
1449
1450 usleep_range(1, 5);
1451 }
1452
1453 /* Clear NISO */
1454 cccr_reg &= ~(CCCR_NISO);
1455 m_can_write(cdev, M_CAN_CCCR, cccr_reg);
1456
1457 m_can_config_endisable(cdev, false);
1458
1459 /* return false if time out (-ETIMEDOUT), else return true */
1460 return !niso_timeout;
1461 }
1462
m_can_dev_setup(struct m_can_classdev * cdev)1463 static int m_can_dev_setup(struct m_can_classdev *cdev)
1464 {
1465 struct net_device *dev = cdev->net;
1466 int m_can_version;
1467
1468 m_can_version = m_can_check_core_release(cdev);
1469 /* return if unsupported version */
1470 if (!m_can_version) {
1471 dev_err(cdev->dev, "Unsupported version number: %2d",
1472 m_can_version);
1473 return -EINVAL;
1474 }
1475
1476 if (!cdev->is_peripheral)
1477 netif_napi_add(dev, &cdev->napi,
1478 m_can_poll, M_CAN_NAPI_WEIGHT);
1479
1480 /* Shared properties of all M_CAN versions */
1481 cdev->version = m_can_version;
1482 cdev->can.do_set_mode = m_can_set_mode;
1483 cdev->can.do_get_berr_counter = m_can_get_berr_counter;
1484
1485 /* Set M_CAN supported operations */
1486 cdev->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1487 CAN_CTRLMODE_LISTENONLY |
1488 CAN_CTRLMODE_BERR_REPORTING |
1489 CAN_CTRLMODE_FD |
1490 CAN_CTRLMODE_ONE_SHOT;
1491
1492 /* Set properties depending on M_CAN version */
1493 switch (cdev->version) {
1494 case 30:
1495 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */
1496 can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
1497 cdev->can.bittiming_const = &m_can_bittiming_const_30X;
1498 cdev->can.data_bittiming_const = &m_can_data_bittiming_const_30X;
1499 break;
1500 case 31:
1501 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */
1502 can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
1503 cdev->can.bittiming_const = &m_can_bittiming_const_31X;
1504 cdev->can.data_bittiming_const = &m_can_data_bittiming_const_31X;
1505 break;
1506 case 32:
1507 case 33:
1508 /* Support both MCAN version v3.2.x and v3.3.0 */
1509 cdev->can.bittiming_const = &m_can_bittiming_const_31X;
1510 cdev->can.data_bittiming_const = &m_can_data_bittiming_const_31X;
1511
1512 cdev->can.ctrlmode_supported |=
1513 (m_can_niso_supported(cdev) ?
1514 CAN_CTRLMODE_FD_NON_ISO : 0);
1515 break;
1516 default:
1517 dev_err(cdev->dev, "Unsupported version number: %2d",
1518 cdev->version);
1519 return -EINVAL;
1520 }
1521
1522 if (cdev->ops->init)
1523 cdev->ops->init(cdev);
1524
1525 return 0;
1526 }
1527
m_can_stop(struct net_device * dev)1528 static void m_can_stop(struct net_device *dev)
1529 {
1530 struct m_can_classdev *cdev = netdev_priv(dev);
1531
1532 /* disable all interrupts */
1533 m_can_disable_all_interrupts(cdev);
1534
1535 /* Set init mode to disengage from the network */
1536 m_can_config_endisable(cdev, true);
1537
1538 /* set the state as STOPPED */
1539 cdev->can.state = CAN_STATE_STOPPED;
1540 }
1541
m_can_close(struct net_device * dev)1542 static int m_can_close(struct net_device *dev)
1543 {
1544 struct m_can_classdev *cdev = netdev_priv(dev);
1545
1546 netif_stop_queue(dev);
1547
1548 if (!cdev->is_peripheral)
1549 napi_disable(&cdev->napi);
1550
1551 m_can_stop(dev);
1552 m_can_clk_stop(cdev);
1553 free_irq(dev->irq, dev);
1554
1555 if (cdev->is_peripheral) {
1556 cdev->tx_skb = NULL;
1557 destroy_workqueue(cdev->tx_wq);
1558 cdev->tx_wq = NULL;
1559 }
1560
1561 if (cdev->is_peripheral)
1562 can_rx_offload_disable(&cdev->offload);
1563
1564 close_candev(dev);
1565 can_led_event(dev, CAN_LED_EVENT_STOP);
1566
1567 phy_power_off(cdev->transceiver);
1568
1569 return 0;
1570 }
1571
m_can_next_echo_skb_occupied(struct net_device * dev,int putidx)1572 static int m_can_next_echo_skb_occupied(struct net_device *dev, int putidx)
1573 {
1574 struct m_can_classdev *cdev = netdev_priv(dev);
1575 /*get wrap around for loopback skb index */
1576 unsigned int wrap = cdev->can.echo_skb_max;
1577 int next_idx;
1578
1579 /* calculate next index */
1580 next_idx = (++putidx >= wrap ? 0 : putidx);
1581
1582 /* check if occupied */
1583 return !!cdev->can.echo_skb[next_idx];
1584 }
1585
m_can_tx_handler(struct m_can_classdev * cdev)1586 static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev)
1587 {
1588 struct canfd_frame *cf = (struct canfd_frame *)cdev->tx_skb->data;
1589 struct net_device *dev = cdev->net;
1590 struct sk_buff *skb = cdev->tx_skb;
1591 struct id_and_dlc fifo_header;
1592 u32 cccr, fdflags;
1593 int err;
1594 int putidx;
1595
1596 cdev->tx_skb = NULL;
1597
1598 /* Generate ID field for TX buffer Element */
1599 /* Common to all supported M_CAN versions */
1600 if (cf->can_id & CAN_EFF_FLAG) {
1601 fifo_header.id = cf->can_id & CAN_EFF_MASK;
1602 fifo_header.id |= TX_BUF_XTD;
1603 } else {
1604 fifo_header.id = ((cf->can_id & CAN_SFF_MASK) << 18);
1605 }
1606
1607 if (cf->can_id & CAN_RTR_FLAG)
1608 fifo_header.id |= TX_BUF_RTR;
1609
1610 if (cdev->version == 30) {
1611 netif_stop_queue(dev);
1612
1613 fifo_header.dlc = can_fd_len2dlc(cf->len) << 16;
1614
1615 /* Write the frame ID, DLC, and payload to the FIFO element. */
1616 err = m_can_fifo_write(cdev, 0, M_CAN_FIFO_ID, &fifo_header, 2);
1617 if (err)
1618 goto out_fail;
1619
1620 err = m_can_fifo_write(cdev, 0, M_CAN_FIFO_DATA,
1621 cf->data, DIV_ROUND_UP(cf->len, 4));
1622 if (err)
1623 goto out_fail;
1624
1625 can_put_echo_skb(skb, dev, 0, 0);
1626
1627 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) {
1628 cccr = m_can_read(cdev, M_CAN_CCCR);
1629 cccr &= ~CCCR_CMR_MASK;
1630 if (can_is_canfd_skb(skb)) {
1631 if (cf->flags & CANFD_BRS)
1632 cccr |= FIELD_PREP(CCCR_CMR_MASK,
1633 CCCR_CMR_CANFD_BRS);
1634 else
1635 cccr |= FIELD_PREP(CCCR_CMR_MASK,
1636 CCCR_CMR_CANFD);
1637 } else {
1638 cccr |= FIELD_PREP(CCCR_CMR_MASK, CCCR_CMR_CAN);
1639 }
1640 m_can_write(cdev, M_CAN_CCCR, cccr);
1641 }
1642 m_can_write(cdev, M_CAN_TXBTIE, 0x1);
1643 m_can_write(cdev, M_CAN_TXBAR, 0x1);
1644 /* End of xmit function for version 3.0.x */
1645 } else {
1646 /* Transmit routine for version >= v3.1.x */
1647
1648 /* Check if FIFO full */
1649 if (m_can_tx_fifo_full(cdev)) {
1650 /* This shouldn't happen */
1651 netif_stop_queue(dev);
1652 netdev_warn(dev,
1653 "TX queue active although FIFO is full.");
1654
1655 if (cdev->is_peripheral) {
1656 kfree_skb(skb);
1657 dev->stats.tx_dropped++;
1658 return NETDEV_TX_OK;
1659 } else {
1660 return NETDEV_TX_BUSY;
1661 }
1662 }
1663
1664 /* get put index for frame */
1665 putidx = FIELD_GET(TXFQS_TFQPI_MASK,
1666 m_can_read(cdev, M_CAN_TXFQS));
1667
1668 /* Construct DLC Field, with CAN-FD configuration.
1669 * Use the put index of the fifo as the message marker,
1670 * used in the TX interrupt for sending the correct echo frame.
1671 */
1672
1673 /* get CAN FD configuration of frame */
1674 fdflags = 0;
1675 if (can_is_canfd_skb(skb)) {
1676 fdflags |= TX_BUF_FDF;
1677 if (cf->flags & CANFD_BRS)
1678 fdflags |= TX_BUF_BRS;
1679 }
1680
1681 fifo_header.dlc = FIELD_PREP(TX_BUF_MM_MASK, putidx) |
1682 FIELD_PREP(TX_BUF_DLC_MASK, can_fd_len2dlc(cf->len)) |
1683 fdflags | TX_BUF_EFC;
1684 err = m_can_fifo_write(cdev, putidx, M_CAN_FIFO_ID, &fifo_header, 2);
1685 if (err)
1686 goto out_fail;
1687
1688 err = m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DATA,
1689 cf->data, DIV_ROUND_UP(cf->len, 4));
1690 if (err)
1691 goto out_fail;
1692
1693 /* Push loopback echo.
1694 * Will be looped back on TX interrupt based on message marker
1695 */
1696 can_put_echo_skb(skb, dev, putidx, 0);
1697
1698 /* Enable TX FIFO element to start transfer */
1699 m_can_write(cdev, M_CAN_TXBAR, (1 << putidx));
1700
1701 /* stop network queue if fifo full */
1702 if (m_can_tx_fifo_full(cdev) ||
1703 m_can_next_echo_skb_occupied(dev, putidx))
1704 netif_stop_queue(dev);
1705 }
1706
1707 return NETDEV_TX_OK;
1708
1709 out_fail:
1710 netdev_err(dev, "FIFO write returned %d\n", err);
1711 m_can_disable_all_interrupts(cdev);
1712 return NETDEV_TX_BUSY;
1713 }
1714
m_can_tx_work_queue(struct work_struct * ws)1715 static void m_can_tx_work_queue(struct work_struct *ws)
1716 {
1717 struct m_can_classdev *cdev = container_of(ws, struct m_can_classdev,
1718 tx_work);
1719
1720 m_can_tx_handler(cdev);
1721 }
1722
m_can_start_xmit(struct sk_buff * skb,struct net_device * dev)1723 static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
1724 struct net_device *dev)
1725 {
1726 struct m_can_classdev *cdev = netdev_priv(dev);
1727
1728 if (can_dropped_invalid_skb(dev, skb))
1729 return NETDEV_TX_OK;
1730
1731 if (cdev->is_peripheral) {
1732 if (cdev->tx_skb) {
1733 netdev_err(dev, "hard_xmit called while tx busy\n");
1734 return NETDEV_TX_BUSY;
1735 }
1736
1737 if (cdev->can.state == CAN_STATE_BUS_OFF) {
1738 m_can_clean(dev);
1739 } else {
1740 /* Need to stop the queue to avoid numerous requests
1741 * from being sent. Suggested improvement is to create
1742 * a queueing mechanism that will queue the skbs and
1743 * process them in order.
1744 */
1745 cdev->tx_skb = skb;
1746 netif_stop_queue(cdev->net);
1747 queue_work(cdev->tx_wq, &cdev->tx_work);
1748 }
1749 } else {
1750 cdev->tx_skb = skb;
1751 return m_can_tx_handler(cdev);
1752 }
1753
1754 return NETDEV_TX_OK;
1755 }
1756
m_can_open(struct net_device * dev)1757 static int m_can_open(struct net_device *dev)
1758 {
1759 struct m_can_classdev *cdev = netdev_priv(dev);
1760 int err;
1761
1762 err = phy_power_on(cdev->transceiver);
1763 if (err)
1764 return err;
1765
1766 err = m_can_clk_start(cdev);
1767 if (err)
1768 goto out_phy_power_off;
1769
1770 /* open the can device */
1771 err = open_candev(dev);
1772 if (err) {
1773 netdev_err(dev, "failed to open can device\n");
1774 goto exit_disable_clks;
1775 }
1776
1777 if (cdev->is_peripheral)
1778 can_rx_offload_enable(&cdev->offload);
1779
1780 /* register interrupt handler */
1781 if (cdev->is_peripheral) {
1782 cdev->tx_skb = NULL;
1783 cdev->tx_wq = alloc_workqueue("mcan_wq",
1784 WQ_FREEZABLE | WQ_MEM_RECLAIM, 0);
1785 if (!cdev->tx_wq) {
1786 err = -ENOMEM;
1787 goto out_wq_fail;
1788 }
1789
1790 INIT_WORK(&cdev->tx_work, m_can_tx_work_queue);
1791
1792 err = request_threaded_irq(dev->irq, NULL, m_can_isr,
1793 IRQF_ONESHOT,
1794 dev->name, dev);
1795 } else {
1796 err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name,
1797 dev);
1798 }
1799
1800 if (err < 0) {
1801 netdev_err(dev, "failed to request interrupt\n");
1802 goto exit_irq_fail;
1803 }
1804
1805 /* start the m_can controller */
1806 m_can_start(dev);
1807
1808 can_led_event(dev, CAN_LED_EVENT_OPEN);
1809
1810 if (!cdev->is_peripheral)
1811 napi_enable(&cdev->napi);
1812
1813 netif_start_queue(dev);
1814
1815 return 0;
1816
1817 exit_irq_fail:
1818 if (cdev->is_peripheral)
1819 destroy_workqueue(cdev->tx_wq);
1820 out_wq_fail:
1821 if (cdev->is_peripheral)
1822 can_rx_offload_disable(&cdev->offload);
1823 close_candev(dev);
1824 exit_disable_clks:
1825 m_can_clk_stop(cdev);
1826 out_phy_power_off:
1827 phy_power_off(cdev->transceiver);
1828 return err;
1829 }
1830
1831 static const struct net_device_ops m_can_netdev_ops = {
1832 .ndo_open = m_can_open,
1833 .ndo_stop = m_can_close,
1834 .ndo_start_xmit = m_can_start_xmit,
1835 .ndo_change_mtu = can_change_mtu,
1836 };
1837
register_m_can_dev(struct net_device * dev)1838 static int register_m_can_dev(struct net_device *dev)
1839 {
1840 dev->flags |= IFF_ECHO; /* we support local echo */
1841 dev->netdev_ops = &m_can_netdev_ops;
1842
1843 return register_candev(dev);
1844 }
1845
m_can_of_parse_mram(struct m_can_classdev * cdev,const u32 * mram_config_vals)1846 static void m_can_of_parse_mram(struct m_can_classdev *cdev,
1847 const u32 *mram_config_vals)
1848 {
1849 cdev->mcfg[MRAM_SIDF].off = mram_config_vals[0];
1850 cdev->mcfg[MRAM_SIDF].num = mram_config_vals[1];
1851 cdev->mcfg[MRAM_XIDF].off = cdev->mcfg[MRAM_SIDF].off +
1852 cdev->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE;
1853 cdev->mcfg[MRAM_XIDF].num = mram_config_vals[2];
1854 cdev->mcfg[MRAM_RXF0].off = cdev->mcfg[MRAM_XIDF].off +
1855 cdev->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE;
1856 cdev->mcfg[MRAM_RXF0].num = mram_config_vals[3] &
1857 FIELD_MAX(RXFC_FS_MASK);
1858 cdev->mcfg[MRAM_RXF1].off = cdev->mcfg[MRAM_RXF0].off +
1859 cdev->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE;
1860 cdev->mcfg[MRAM_RXF1].num = mram_config_vals[4] &
1861 FIELD_MAX(RXFC_FS_MASK);
1862 cdev->mcfg[MRAM_RXB].off = cdev->mcfg[MRAM_RXF1].off +
1863 cdev->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE;
1864 cdev->mcfg[MRAM_RXB].num = mram_config_vals[5];
1865 cdev->mcfg[MRAM_TXE].off = cdev->mcfg[MRAM_RXB].off +
1866 cdev->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE;
1867 cdev->mcfg[MRAM_TXE].num = mram_config_vals[6];
1868 cdev->mcfg[MRAM_TXB].off = cdev->mcfg[MRAM_TXE].off +
1869 cdev->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE;
1870 cdev->mcfg[MRAM_TXB].num = mram_config_vals[7] &
1871 FIELD_MAX(TXBC_NDTB_MASK);
1872
1873 dev_dbg(cdev->dev,
1874 "sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
1875 cdev->mcfg[MRAM_SIDF].off, cdev->mcfg[MRAM_SIDF].num,
1876 cdev->mcfg[MRAM_XIDF].off, cdev->mcfg[MRAM_XIDF].num,
1877 cdev->mcfg[MRAM_RXF0].off, cdev->mcfg[MRAM_RXF0].num,
1878 cdev->mcfg[MRAM_RXF1].off, cdev->mcfg[MRAM_RXF1].num,
1879 cdev->mcfg[MRAM_RXB].off, cdev->mcfg[MRAM_RXB].num,
1880 cdev->mcfg[MRAM_TXE].off, cdev->mcfg[MRAM_TXE].num,
1881 cdev->mcfg[MRAM_TXB].off, cdev->mcfg[MRAM_TXB].num);
1882 }
1883
m_can_init_ram(struct m_can_classdev * cdev)1884 int m_can_init_ram(struct m_can_classdev *cdev)
1885 {
1886 int end, i, start;
1887 int err = 0;
1888
1889 /* initialize the entire Message RAM in use to avoid possible
1890 * ECC/parity checksum errors when reading an uninitialized buffer
1891 */
1892 start = cdev->mcfg[MRAM_SIDF].off;
1893 end = cdev->mcfg[MRAM_TXB].off +
1894 cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE;
1895
1896 for (i = start; i < end; i += 4) {
1897 err = m_can_fifo_write_no_off(cdev, i, 0x0);
1898 if (err)
1899 break;
1900 }
1901
1902 return err;
1903 }
1904 EXPORT_SYMBOL_GPL(m_can_init_ram);
1905
m_can_class_get_clocks(struct m_can_classdev * cdev)1906 int m_can_class_get_clocks(struct m_can_classdev *cdev)
1907 {
1908 int ret = 0;
1909
1910 cdev->hclk = devm_clk_get(cdev->dev, "hclk");
1911 cdev->cclk = devm_clk_get(cdev->dev, "cclk");
1912
1913 if (IS_ERR(cdev->cclk)) {
1914 dev_err(cdev->dev, "no clock found\n");
1915 ret = -ENODEV;
1916 }
1917
1918 return ret;
1919 }
1920 EXPORT_SYMBOL_GPL(m_can_class_get_clocks);
1921
m_can_class_allocate_dev(struct device * dev,int sizeof_priv)1922 struct m_can_classdev *m_can_class_allocate_dev(struct device *dev,
1923 int sizeof_priv)
1924 {
1925 struct m_can_classdev *class_dev = NULL;
1926 u32 mram_config_vals[MRAM_CFG_LEN];
1927 struct net_device *net_dev;
1928 u32 tx_fifo_size;
1929 int ret;
1930
1931 ret = fwnode_property_read_u32_array(dev_fwnode(dev),
1932 "bosch,mram-cfg",
1933 mram_config_vals,
1934 sizeof(mram_config_vals) / 4);
1935 if (ret) {
1936 dev_err(dev, "Could not get Message RAM configuration.");
1937 goto out;
1938 }
1939
1940 /* Get TX FIFO size
1941 * Defines the total amount of echo buffers for loopback
1942 */
1943 tx_fifo_size = mram_config_vals[7];
1944
1945 /* allocate the m_can device */
1946 net_dev = alloc_candev(sizeof_priv, tx_fifo_size);
1947 if (!net_dev) {
1948 dev_err(dev, "Failed to allocate CAN device");
1949 goto out;
1950 }
1951
1952 class_dev = netdev_priv(net_dev);
1953 class_dev->net = net_dev;
1954 class_dev->dev = dev;
1955 SET_NETDEV_DEV(net_dev, dev);
1956
1957 m_can_of_parse_mram(class_dev, mram_config_vals);
1958 out:
1959 return class_dev;
1960 }
1961 EXPORT_SYMBOL_GPL(m_can_class_allocate_dev);
1962
m_can_class_free_dev(struct net_device * net)1963 void m_can_class_free_dev(struct net_device *net)
1964 {
1965 free_candev(net);
1966 }
1967 EXPORT_SYMBOL_GPL(m_can_class_free_dev);
1968
m_can_class_register(struct m_can_classdev * cdev)1969 int m_can_class_register(struct m_can_classdev *cdev)
1970 {
1971 int ret;
1972
1973 if (cdev->pm_clock_support) {
1974 ret = m_can_clk_start(cdev);
1975 if (ret)
1976 return ret;
1977 }
1978
1979 if (cdev->is_peripheral) {
1980 ret = can_rx_offload_add_manual(cdev->net, &cdev->offload,
1981 M_CAN_NAPI_WEIGHT);
1982 if (ret)
1983 goto clk_disable;
1984 }
1985
1986 ret = m_can_dev_setup(cdev);
1987 if (ret)
1988 goto rx_offload_del;
1989
1990 ret = register_m_can_dev(cdev->net);
1991 if (ret) {
1992 dev_err(cdev->dev, "registering %s failed (err=%d)\n",
1993 cdev->net->name, ret);
1994 goto rx_offload_del;
1995 }
1996
1997 devm_can_led_init(cdev->net);
1998
1999 of_can_transceiver(cdev->net);
2000
2001 dev_info(cdev->dev, "%s device registered (irq=%d, version=%d)\n",
2002 KBUILD_MODNAME, cdev->net->irq, cdev->version);
2003
2004 /* Probe finished
2005 * Stop clocks. They will be reactivated once the M_CAN device is opened
2006 */
2007 m_can_clk_stop(cdev);
2008
2009 return 0;
2010
2011 rx_offload_del:
2012 if (cdev->is_peripheral)
2013 can_rx_offload_del(&cdev->offload);
2014 clk_disable:
2015 m_can_clk_stop(cdev);
2016
2017 return ret;
2018 }
2019 EXPORT_SYMBOL_GPL(m_can_class_register);
2020
m_can_class_unregister(struct m_can_classdev * cdev)2021 void m_can_class_unregister(struct m_can_classdev *cdev)
2022 {
2023 if (cdev->is_peripheral)
2024 can_rx_offload_del(&cdev->offload);
2025 unregister_candev(cdev->net);
2026 }
2027 EXPORT_SYMBOL_GPL(m_can_class_unregister);
2028
m_can_class_suspend(struct device * dev)2029 int m_can_class_suspend(struct device *dev)
2030 {
2031 struct m_can_classdev *cdev = dev_get_drvdata(dev);
2032 struct net_device *ndev = cdev->net;
2033
2034 if (netif_running(ndev)) {
2035 netif_stop_queue(ndev);
2036 netif_device_detach(ndev);
2037 m_can_stop(ndev);
2038 m_can_clk_stop(cdev);
2039 }
2040
2041 pinctrl_pm_select_sleep_state(dev);
2042
2043 cdev->can.state = CAN_STATE_SLEEPING;
2044
2045 return 0;
2046 }
2047 EXPORT_SYMBOL_GPL(m_can_class_suspend);
2048
m_can_class_resume(struct device * dev)2049 int m_can_class_resume(struct device *dev)
2050 {
2051 struct m_can_classdev *cdev = dev_get_drvdata(dev);
2052 struct net_device *ndev = cdev->net;
2053
2054 pinctrl_pm_select_default_state(dev);
2055
2056 cdev->can.state = CAN_STATE_ERROR_ACTIVE;
2057
2058 if (netif_running(ndev)) {
2059 int ret;
2060
2061 ret = m_can_clk_start(cdev);
2062 if (ret)
2063 return ret;
2064
2065 m_can_init_ram(cdev);
2066 m_can_start(ndev);
2067 netif_device_attach(ndev);
2068 netif_start_queue(ndev);
2069 }
2070
2071 return 0;
2072 }
2073 EXPORT_SYMBOL_GPL(m_can_class_resume);
2074
2075 MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>");
2076 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
2077 MODULE_LICENSE("GPL v2");
2078 MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller");
2079
