1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #include <linux/dma-mapping.h>
5 #include <linux/etherdevice.h>
6 #include <linux/interrupt.h>
7 #ifdef CONFIG_RFS_ACCEL
8 #include <linux/cpu_rmap.h>
9 #endif
10 #include <linux/if_vlan.h>
11 #include <linux/irq.h>
12 #include <linux/ip.h>
13 #include <linux/ipv6.h>
14 #include <linux/module.h>
15 #include <linux/pci.h>
16 #include <linux/skbuff.h>
17 #include <linux/sctp.h>
18 #include <net/gre.h>
19 #include <net/gro.h>
20 #include <net/ip6_checksum.h>
21 #include <net/page_pool/helpers.h>
22 #include <net/pkt_cls.h>
23 #include <net/pkt_sched.h>
24 #include <net/tcp.h>
25 #include <net/vxlan.h>
26 #include <net/geneve.h>
27
28 #include "hnae3.h"
29 #include "hns3_enet.h"
30 /* All hns3 tracepoints are defined by the include below, which
31 * must be included exactly once across the whole kernel with
32 * CREATE_TRACE_POINTS defined
33 */
34 #define CREATE_TRACE_POINTS
35 #include "hns3_trace.h"
36
37 #define hns3_set_field(origin, shift, val) ((origin) |= (val) << (shift))
38 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
39
40 #define hns3_rl_err(fmt, ...) \
41 do { \
42 if (net_ratelimit()) \
43 netdev_err(fmt, ##__VA_ARGS__); \
44 } while (0)
45
46 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
47
48 static const char hns3_driver_name[] = "hns3";
49 static const char hns3_driver_string[] =
50 "Hisilicon Ethernet Network Driver for Hip08 Family";
51 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
52 static struct hnae3_client client;
53
54 static int debug = -1;
55 module_param(debug, int, 0);
56 MODULE_PARM_DESC(debug, " Network interface message level setting");
57
58 static unsigned int tx_sgl = 1;
59 module_param(tx_sgl, uint, 0600);
60 MODULE_PARM_DESC(tx_sgl, "Minimum number of frags when using dma_map_sg() to optimize the IOMMU mapping");
61
62 static bool page_pool_enabled = true;
63 module_param(page_pool_enabled, bool, 0400);
64
65 #define HNS3_SGL_SIZE(nfrag) (sizeof(struct scatterlist) * (nfrag) + \
66 sizeof(struct sg_table))
67 #define HNS3_MAX_SGL_SIZE ALIGN(HNS3_SGL_SIZE(HNS3_MAX_TSO_BD_NUM), \
68 dma_get_cache_alignment())
69
70 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
71 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
72
73 #define HNS3_INNER_VLAN_TAG 1
74 #define HNS3_OUTER_VLAN_TAG 2
75
76 #define HNS3_MIN_TX_LEN 33U
77 #define HNS3_MIN_TUN_PKT_LEN 65U
78
79 /* hns3_pci_tbl - PCI Device ID Table
80 *
81 * Last entry must be all 0s
82 *
83 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
84 * Class, Class Mask, private data (not used) }
85 */
86 static const struct pci_device_id hns3_pci_tbl[] = {
87 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
88 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
89 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
90 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
91 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
92 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
93 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
94 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
95 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
96 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
97 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
98 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
99 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA),
100 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
101 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},
102 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
103 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
104 /* required last entry */
105 {0,}
106 };
107 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
108
109 #define HNS3_RX_PTYPE_ENTRY(ptype, l, s, t, h) \
110 { ptype, \
111 l, \
112 CHECKSUM_##s, \
113 HNS3_L3_TYPE_##t, \
114 1, \
115 h}
116
117 #define HNS3_RX_PTYPE_UNUSED_ENTRY(ptype) \
118 { ptype, 0, CHECKSUM_NONE, HNS3_L3_TYPE_PARSE_FAIL, 0, \
119 PKT_HASH_TYPE_NONE }
120
121 static const struct hns3_rx_ptype hns3_rx_ptype_tbl[] = {
122 HNS3_RX_PTYPE_UNUSED_ENTRY(0),
123 HNS3_RX_PTYPE_ENTRY(1, 0, COMPLETE, ARP, PKT_HASH_TYPE_NONE),
124 HNS3_RX_PTYPE_ENTRY(2, 0, COMPLETE, RARP, PKT_HASH_TYPE_NONE),
125 HNS3_RX_PTYPE_ENTRY(3, 0, COMPLETE, LLDP, PKT_HASH_TYPE_NONE),
126 HNS3_RX_PTYPE_ENTRY(4, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
127 HNS3_RX_PTYPE_ENTRY(5, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
128 HNS3_RX_PTYPE_ENTRY(6, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
129 HNS3_RX_PTYPE_ENTRY(7, 0, COMPLETE, CNM, PKT_HASH_TYPE_NONE),
130 HNS3_RX_PTYPE_ENTRY(8, 0, NONE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
131 HNS3_RX_PTYPE_UNUSED_ENTRY(9),
132 HNS3_RX_PTYPE_UNUSED_ENTRY(10),
133 HNS3_RX_PTYPE_UNUSED_ENTRY(11),
134 HNS3_RX_PTYPE_UNUSED_ENTRY(12),
135 HNS3_RX_PTYPE_UNUSED_ENTRY(13),
136 HNS3_RX_PTYPE_UNUSED_ENTRY(14),
137 HNS3_RX_PTYPE_UNUSED_ENTRY(15),
138 HNS3_RX_PTYPE_ENTRY(16, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
139 HNS3_RX_PTYPE_ENTRY(17, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE),
140 HNS3_RX_PTYPE_ENTRY(18, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE),
141 HNS3_RX_PTYPE_ENTRY(19, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
142 HNS3_RX_PTYPE_ENTRY(20, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
143 HNS3_RX_PTYPE_ENTRY(21, 0, NONE, IPV4, PKT_HASH_TYPE_NONE),
144 HNS3_RX_PTYPE_ENTRY(22, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
145 HNS3_RX_PTYPE_ENTRY(23, 0, NONE, IPV4, PKT_HASH_TYPE_L3),
146 HNS3_RX_PTYPE_ENTRY(24, 0, NONE, IPV4, PKT_HASH_TYPE_L3),
147 HNS3_RX_PTYPE_ENTRY(25, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
148 HNS3_RX_PTYPE_UNUSED_ENTRY(26),
149 HNS3_RX_PTYPE_UNUSED_ENTRY(27),
150 HNS3_RX_PTYPE_UNUSED_ENTRY(28),
151 HNS3_RX_PTYPE_ENTRY(29, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
152 HNS3_RX_PTYPE_ENTRY(30, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
153 HNS3_RX_PTYPE_ENTRY(31, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
154 HNS3_RX_PTYPE_ENTRY(32, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
155 HNS3_RX_PTYPE_ENTRY(33, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
156 HNS3_RX_PTYPE_ENTRY(34, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
157 HNS3_RX_PTYPE_ENTRY(35, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
158 HNS3_RX_PTYPE_ENTRY(36, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
159 HNS3_RX_PTYPE_ENTRY(37, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
160 HNS3_RX_PTYPE_UNUSED_ENTRY(38),
161 HNS3_RX_PTYPE_ENTRY(39, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
162 HNS3_RX_PTYPE_ENTRY(40, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
163 HNS3_RX_PTYPE_ENTRY(41, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
164 HNS3_RX_PTYPE_ENTRY(42, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
165 HNS3_RX_PTYPE_ENTRY(43, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
166 HNS3_RX_PTYPE_ENTRY(44, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
167 HNS3_RX_PTYPE_ENTRY(45, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
168 HNS3_RX_PTYPE_UNUSED_ENTRY(46),
169 HNS3_RX_PTYPE_UNUSED_ENTRY(47),
170 HNS3_RX_PTYPE_UNUSED_ENTRY(48),
171 HNS3_RX_PTYPE_UNUSED_ENTRY(49),
172 HNS3_RX_PTYPE_UNUSED_ENTRY(50),
173 HNS3_RX_PTYPE_UNUSED_ENTRY(51),
174 HNS3_RX_PTYPE_UNUSED_ENTRY(52),
175 HNS3_RX_PTYPE_UNUSED_ENTRY(53),
176 HNS3_RX_PTYPE_UNUSED_ENTRY(54),
177 HNS3_RX_PTYPE_UNUSED_ENTRY(55),
178 HNS3_RX_PTYPE_UNUSED_ENTRY(56),
179 HNS3_RX_PTYPE_UNUSED_ENTRY(57),
180 HNS3_RX_PTYPE_UNUSED_ENTRY(58),
181 HNS3_RX_PTYPE_UNUSED_ENTRY(59),
182 HNS3_RX_PTYPE_UNUSED_ENTRY(60),
183 HNS3_RX_PTYPE_UNUSED_ENTRY(61),
184 HNS3_RX_PTYPE_UNUSED_ENTRY(62),
185 HNS3_RX_PTYPE_UNUSED_ENTRY(63),
186 HNS3_RX_PTYPE_UNUSED_ENTRY(64),
187 HNS3_RX_PTYPE_UNUSED_ENTRY(65),
188 HNS3_RX_PTYPE_UNUSED_ENTRY(66),
189 HNS3_RX_PTYPE_UNUSED_ENTRY(67),
190 HNS3_RX_PTYPE_UNUSED_ENTRY(68),
191 HNS3_RX_PTYPE_UNUSED_ENTRY(69),
192 HNS3_RX_PTYPE_UNUSED_ENTRY(70),
193 HNS3_RX_PTYPE_UNUSED_ENTRY(71),
194 HNS3_RX_PTYPE_UNUSED_ENTRY(72),
195 HNS3_RX_PTYPE_UNUSED_ENTRY(73),
196 HNS3_RX_PTYPE_UNUSED_ENTRY(74),
197 HNS3_RX_PTYPE_UNUSED_ENTRY(75),
198 HNS3_RX_PTYPE_UNUSED_ENTRY(76),
199 HNS3_RX_PTYPE_UNUSED_ENTRY(77),
200 HNS3_RX_PTYPE_UNUSED_ENTRY(78),
201 HNS3_RX_PTYPE_UNUSED_ENTRY(79),
202 HNS3_RX_PTYPE_UNUSED_ENTRY(80),
203 HNS3_RX_PTYPE_UNUSED_ENTRY(81),
204 HNS3_RX_PTYPE_UNUSED_ENTRY(82),
205 HNS3_RX_PTYPE_UNUSED_ENTRY(83),
206 HNS3_RX_PTYPE_UNUSED_ENTRY(84),
207 HNS3_RX_PTYPE_UNUSED_ENTRY(85),
208 HNS3_RX_PTYPE_UNUSED_ENTRY(86),
209 HNS3_RX_PTYPE_UNUSED_ENTRY(87),
210 HNS3_RX_PTYPE_UNUSED_ENTRY(88),
211 HNS3_RX_PTYPE_UNUSED_ENTRY(89),
212 HNS3_RX_PTYPE_UNUSED_ENTRY(90),
213 HNS3_RX_PTYPE_UNUSED_ENTRY(91),
214 HNS3_RX_PTYPE_UNUSED_ENTRY(92),
215 HNS3_RX_PTYPE_UNUSED_ENTRY(93),
216 HNS3_RX_PTYPE_UNUSED_ENTRY(94),
217 HNS3_RX_PTYPE_UNUSED_ENTRY(95),
218 HNS3_RX_PTYPE_UNUSED_ENTRY(96),
219 HNS3_RX_PTYPE_UNUSED_ENTRY(97),
220 HNS3_RX_PTYPE_UNUSED_ENTRY(98),
221 HNS3_RX_PTYPE_UNUSED_ENTRY(99),
222 HNS3_RX_PTYPE_UNUSED_ENTRY(100),
223 HNS3_RX_PTYPE_UNUSED_ENTRY(101),
224 HNS3_RX_PTYPE_UNUSED_ENTRY(102),
225 HNS3_RX_PTYPE_UNUSED_ENTRY(103),
226 HNS3_RX_PTYPE_UNUSED_ENTRY(104),
227 HNS3_RX_PTYPE_UNUSED_ENTRY(105),
228 HNS3_RX_PTYPE_UNUSED_ENTRY(106),
229 HNS3_RX_PTYPE_UNUSED_ENTRY(107),
230 HNS3_RX_PTYPE_UNUSED_ENTRY(108),
231 HNS3_RX_PTYPE_UNUSED_ENTRY(109),
232 HNS3_RX_PTYPE_UNUSED_ENTRY(110),
233 HNS3_RX_PTYPE_ENTRY(111, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
234 HNS3_RX_PTYPE_ENTRY(112, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
235 HNS3_RX_PTYPE_ENTRY(113, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
236 HNS3_RX_PTYPE_ENTRY(114, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
237 HNS3_RX_PTYPE_ENTRY(115, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
238 HNS3_RX_PTYPE_ENTRY(116, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
239 HNS3_RX_PTYPE_ENTRY(117, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
240 HNS3_RX_PTYPE_ENTRY(118, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
241 HNS3_RX_PTYPE_ENTRY(119, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
242 HNS3_RX_PTYPE_UNUSED_ENTRY(120),
243 HNS3_RX_PTYPE_UNUSED_ENTRY(121),
244 HNS3_RX_PTYPE_UNUSED_ENTRY(122),
245 HNS3_RX_PTYPE_ENTRY(123, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
246 HNS3_RX_PTYPE_ENTRY(124, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
247 HNS3_RX_PTYPE_ENTRY(125, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
248 HNS3_RX_PTYPE_ENTRY(126, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
249 HNS3_RX_PTYPE_ENTRY(127, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
250 HNS3_RX_PTYPE_ENTRY(128, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
251 HNS3_RX_PTYPE_ENTRY(129, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
252 HNS3_RX_PTYPE_ENTRY(130, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
253 HNS3_RX_PTYPE_ENTRY(131, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
254 HNS3_RX_PTYPE_UNUSED_ENTRY(132),
255 HNS3_RX_PTYPE_ENTRY(133, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
256 HNS3_RX_PTYPE_ENTRY(134, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
257 HNS3_RX_PTYPE_ENTRY(135, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
258 HNS3_RX_PTYPE_ENTRY(136, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
259 HNS3_RX_PTYPE_ENTRY(137, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
260 HNS3_RX_PTYPE_ENTRY(138, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
261 HNS3_RX_PTYPE_ENTRY(139, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
262 HNS3_RX_PTYPE_UNUSED_ENTRY(140),
263 HNS3_RX_PTYPE_UNUSED_ENTRY(141),
264 HNS3_RX_PTYPE_UNUSED_ENTRY(142),
265 HNS3_RX_PTYPE_UNUSED_ENTRY(143),
266 HNS3_RX_PTYPE_UNUSED_ENTRY(144),
267 HNS3_RX_PTYPE_UNUSED_ENTRY(145),
268 HNS3_RX_PTYPE_UNUSED_ENTRY(146),
269 HNS3_RX_PTYPE_UNUSED_ENTRY(147),
270 HNS3_RX_PTYPE_UNUSED_ENTRY(148),
271 HNS3_RX_PTYPE_UNUSED_ENTRY(149),
272 HNS3_RX_PTYPE_UNUSED_ENTRY(150),
273 HNS3_RX_PTYPE_UNUSED_ENTRY(151),
274 HNS3_RX_PTYPE_UNUSED_ENTRY(152),
275 HNS3_RX_PTYPE_UNUSED_ENTRY(153),
276 HNS3_RX_PTYPE_UNUSED_ENTRY(154),
277 HNS3_RX_PTYPE_UNUSED_ENTRY(155),
278 HNS3_RX_PTYPE_UNUSED_ENTRY(156),
279 HNS3_RX_PTYPE_UNUSED_ENTRY(157),
280 HNS3_RX_PTYPE_UNUSED_ENTRY(158),
281 HNS3_RX_PTYPE_UNUSED_ENTRY(159),
282 HNS3_RX_PTYPE_UNUSED_ENTRY(160),
283 HNS3_RX_PTYPE_UNUSED_ENTRY(161),
284 HNS3_RX_PTYPE_UNUSED_ENTRY(162),
285 HNS3_RX_PTYPE_UNUSED_ENTRY(163),
286 HNS3_RX_PTYPE_UNUSED_ENTRY(164),
287 HNS3_RX_PTYPE_UNUSED_ENTRY(165),
288 HNS3_RX_PTYPE_UNUSED_ENTRY(166),
289 HNS3_RX_PTYPE_UNUSED_ENTRY(167),
290 HNS3_RX_PTYPE_UNUSED_ENTRY(168),
291 HNS3_RX_PTYPE_UNUSED_ENTRY(169),
292 HNS3_RX_PTYPE_UNUSED_ENTRY(170),
293 HNS3_RX_PTYPE_UNUSED_ENTRY(171),
294 HNS3_RX_PTYPE_UNUSED_ENTRY(172),
295 HNS3_RX_PTYPE_UNUSED_ENTRY(173),
296 HNS3_RX_PTYPE_UNUSED_ENTRY(174),
297 HNS3_RX_PTYPE_UNUSED_ENTRY(175),
298 HNS3_RX_PTYPE_UNUSED_ENTRY(176),
299 HNS3_RX_PTYPE_UNUSED_ENTRY(177),
300 HNS3_RX_PTYPE_UNUSED_ENTRY(178),
301 HNS3_RX_PTYPE_UNUSED_ENTRY(179),
302 HNS3_RX_PTYPE_UNUSED_ENTRY(180),
303 HNS3_RX_PTYPE_UNUSED_ENTRY(181),
304 HNS3_RX_PTYPE_UNUSED_ENTRY(182),
305 HNS3_RX_PTYPE_UNUSED_ENTRY(183),
306 HNS3_RX_PTYPE_UNUSED_ENTRY(184),
307 HNS3_RX_PTYPE_UNUSED_ENTRY(185),
308 HNS3_RX_PTYPE_UNUSED_ENTRY(186),
309 HNS3_RX_PTYPE_UNUSED_ENTRY(187),
310 HNS3_RX_PTYPE_UNUSED_ENTRY(188),
311 HNS3_RX_PTYPE_UNUSED_ENTRY(189),
312 HNS3_RX_PTYPE_UNUSED_ENTRY(190),
313 HNS3_RX_PTYPE_UNUSED_ENTRY(191),
314 HNS3_RX_PTYPE_UNUSED_ENTRY(192),
315 HNS3_RX_PTYPE_UNUSED_ENTRY(193),
316 HNS3_RX_PTYPE_UNUSED_ENTRY(194),
317 HNS3_RX_PTYPE_UNUSED_ENTRY(195),
318 HNS3_RX_PTYPE_UNUSED_ENTRY(196),
319 HNS3_RX_PTYPE_UNUSED_ENTRY(197),
320 HNS3_RX_PTYPE_UNUSED_ENTRY(198),
321 HNS3_RX_PTYPE_UNUSED_ENTRY(199),
322 HNS3_RX_PTYPE_UNUSED_ENTRY(200),
323 HNS3_RX_PTYPE_UNUSED_ENTRY(201),
324 HNS3_RX_PTYPE_UNUSED_ENTRY(202),
325 HNS3_RX_PTYPE_UNUSED_ENTRY(203),
326 HNS3_RX_PTYPE_UNUSED_ENTRY(204),
327 HNS3_RX_PTYPE_UNUSED_ENTRY(205),
328 HNS3_RX_PTYPE_UNUSED_ENTRY(206),
329 HNS3_RX_PTYPE_UNUSED_ENTRY(207),
330 HNS3_RX_PTYPE_UNUSED_ENTRY(208),
331 HNS3_RX_PTYPE_UNUSED_ENTRY(209),
332 HNS3_RX_PTYPE_UNUSED_ENTRY(210),
333 HNS3_RX_PTYPE_UNUSED_ENTRY(211),
334 HNS3_RX_PTYPE_UNUSED_ENTRY(212),
335 HNS3_RX_PTYPE_UNUSED_ENTRY(213),
336 HNS3_RX_PTYPE_UNUSED_ENTRY(214),
337 HNS3_RX_PTYPE_UNUSED_ENTRY(215),
338 HNS3_RX_PTYPE_UNUSED_ENTRY(216),
339 HNS3_RX_PTYPE_UNUSED_ENTRY(217),
340 HNS3_RX_PTYPE_UNUSED_ENTRY(218),
341 HNS3_RX_PTYPE_UNUSED_ENTRY(219),
342 HNS3_RX_PTYPE_UNUSED_ENTRY(220),
343 HNS3_RX_PTYPE_UNUSED_ENTRY(221),
344 HNS3_RX_PTYPE_UNUSED_ENTRY(222),
345 HNS3_RX_PTYPE_UNUSED_ENTRY(223),
346 HNS3_RX_PTYPE_UNUSED_ENTRY(224),
347 HNS3_RX_PTYPE_UNUSED_ENTRY(225),
348 HNS3_RX_PTYPE_UNUSED_ENTRY(226),
349 HNS3_RX_PTYPE_UNUSED_ENTRY(227),
350 HNS3_RX_PTYPE_UNUSED_ENTRY(228),
351 HNS3_RX_PTYPE_UNUSED_ENTRY(229),
352 HNS3_RX_PTYPE_UNUSED_ENTRY(230),
353 HNS3_RX_PTYPE_UNUSED_ENTRY(231),
354 HNS3_RX_PTYPE_UNUSED_ENTRY(232),
355 HNS3_RX_PTYPE_UNUSED_ENTRY(233),
356 HNS3_RX_PTYPE_UNUSED_ENTRY(234),
357 HNS3_RX_PTYPE_UNUSED_ENTRY(235),
358 HNS3_RX_PTYPE_UNUSED_ENTRY(236),
359 HNS3_RX_PTYPE_UNUSED_ENTRY(237),
360 HNS3_RX_PTYPE_UNUSED_ENTRY(238),
361 HNS3_RX_PTYPE_UNUSED_ENTRY(239),
362 HNS3_RX_PTYPE_UNUSED_ENTRY(240),
363 HNS3_RX_PTYPE_UNUSED_ENTRY(241),
364 HNS3_RX_PTYPE_UNUSED_ENTRY(242),
365 HNS3_RX_PTYPE_UNUSED_ENTRY(243),
366 HNS3_RX_PTYPE_UNUSED_ENTRY(244),
367 HNS3_RX_PTYPE_UNUSED_ENTRY(245),
368 HNS3_RX_PTYPE_UNUSED_ENTRY(246),
369 HNS3_RX_PTYPE_UNUSED_ENTRY(247),
370 HNS3_RX_PTYPE_UNUSED_ENTRY(248),
371 HNS3_RX_PTYPE_UNUSED_ENTRY(249),
372 HNS3_RX_PTYPE_UNUSED_ENTRY(250),
373 HNS3_RX_PTYPE_UNUSED_ENTRY(251),
374 HNS3_RX_PTYPE_UNUSED_ENTRY(252),
375 HNS3_RX_PTYPE_UNUSED_ENTRY(253),
376 HNS3_RX_PTYPE_UNUSED_ENTRY(254),
377 HNS3_RX_PTYPE_UNUSED_ENTRY(255),
378 };
379
380 #define HNS3_INVALID_PTYPE \
381 ARRAY_SIZE(hns3_rx_ptype_tbl)
382
hns3_irq_handle(int irq,void * vector)383 static irqreturn_t hns3_irq_handle(int irq, void *vector)
384 {
385 struct hns3_enet_tqp_vector *tqp_vector = vector;
386
387 napi_schedule_irqoff(&tqp_vector->napi);
388 tqp_vector->event_cnt++;
389
390 return IRQ_HANDLED;
391 }
392
hns3_nic_uninit_irq(struct hns3_nic_priv * priv)393 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
394 {
395 struct hns3_enet_tqp_vector *tqp_vectors;
396 unsigned int i;
397
398 for (i = 0; i < priv->vector_num; i++) {
399 tqp_vectors = &priv->tqp_vector[i];
400
401 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
402 continue;
403
404 /* clear the affinity mask */
405 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
406
407 /* release the irq resource */
408 free_irq(tqp_vectors->vector_irq, tqp_vectors);
409 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
410 }
411 }
412
hns3_nic_init_irq(struct hns3_nic_priv * priv)413 static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
414 {
415 struct hns3_enet_tqp_vector *tqp_vectors;
416 int txrx_int_idx = 0;
417 int rx_int_idx = 0;
418 int tx_int_idx = 0;
419 unsigned int i;
420 int ret;
421
422 for (i = 0; i < priv->vector_num; i++) {
423 tqp_vectors = &priv->tqp_vector[i];
424
425 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
426 continue;
427
428 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
429 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
430 "%s-%s-%s-%d", hns3_driver_name,
431 pci_name(priv->ae_handle->pdev),
432 "TxRx", txrx_int_idx++);
433 txrx_int_idx++;
434 } else if (tqp_vectors->rx_group.ring) {
435 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
436 "%s-%s-%s-%d", hns3_driver_name,
437 pci_name(priv->ae_handle->pdev),
438 "Rx", rx_int_idx++);
439 } else if (tqp_vectors->tx_group.ring) {
440 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
441 "%s-%s-%s-%d", hns3_driver_name,
442 pci_name(priv->ae_handle->pdev),
443 "Tx", tx_int_idx++);
444 } else {
445 /* Skip this unused q_vector */
446 continue;
447 }
448
449 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
450
451 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN);
452 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
453 tqp_vectors->name, tqp_vectors);
454 if (ret) {
455 netdev_err(priv->netdev, "request irq(%d) fail\n",
456 tqp_vectors->vector_irq);
457 hns3_nic_uninit_irq(priv);
458 return ret;
459 }
460
461 irq_set_affinity_hint(tqp_vectors->vector_irq,
462 &tqp_vectors->affinity_mask);
463
464 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
465 }
466
467 return 0;
468 }
469
hns3_mask_vector_irq(struct hns3_enet_tqp_vector * tqp_vector,u32 mask_en)470 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
471 u32 mask_en)
472 {
473 writel(mask_en, tqp_vector->mask_addr);
474 }
475
hns3_vector_enable(struct hns3_enet_tqp_vector * tqp_vector)476 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
477 {
478 napi_enable(&tqp_vector->napi);
479 enable_irq(tqp_vector->vector_irq);
480
481 /* enable vector */
482 hns3_mask_vector_irq(tqp_vector, 1);
483 }
484
hns3_vector_disable(struct hns3_enet_tqp_vector * tqp_vector)485 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
486 {
487 /* disable vector */
488 hns3_mask_vector_irq(tqp_vector, 0);
489
490 disable_irq(tqp_vector->vector_irq);
491 napi_disable(&tqp_vector->napi);
492 cancel_work_sync(&tqp_vector->rx_group.dim.work);
493 cancel_work_sync(&tqp_vector->tx_group.dim.work);
494 }
495
hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector * tqp_vector,u32 rl_value)496 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
497 u32 rl_value)
498 {
499 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
500
501 /* this defines the configuration for RL (Interrupt Rate Limiter).
502 * Rl defines rate of interrupts i.e. number of interrupts-per-second
503 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
504 */
505 if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable &&
506 !tqp_vector->rx_group.coal.adapt_enable)
507 /* According to the hardware, the range of rl_reg is
508 * 0-59 and the unit is 4.
509 */
510 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
511
512 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
513 }
514
hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector * tqp_vector,u32 gl_value)515 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
516 u32 gl_value)
517 {
518 u32 new_val;
519
520 if (tqp_vector->rx_group.coal.unit_1us)
521 new_val = gl_value | HNS3_INT_GL_1US;
522 else
523 new_val = hns3_gl_usec_to_reg(gl_value);
524
525 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
526 }
527
hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector * tqp_vector,u32 gl_value)528 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
529 u32 gl_value)
530 {
531 u32 new_val;
532
533 if (tqp_vector->tx_group.coal.unit_1us)
534 new_val = gl_value | HNS3_INT_GL_1US;
535 else
536 new_val = hns3_gl_usec_to_reg(gl_value);
537
538 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
539 }
540
hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector * tqp_vector,u32 ql_value)541 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
542 u32 ql_value)
543 {
544 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET);
545 }
546
hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector * tqp_vector,u32 ql_value)547 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector,
548 u32 ql_value)
549 {
550 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET);
551 }
552
hns3_vector_coalesce_init(struct hns3_enet_tqp_vector * tqp_vector,struct hns3_nic_priv * priv)553 static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector,
554 struct hns3_nic_priv *priv)
555 {
556 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
557 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
558 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
559 struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal;
560 struct hns3_enet_coalesce *prx_coal = &priv->rx_coal;
561
562 tx_coal->adapt_enable = ptx_coal->adapt_enable;
563 rx_coal->adapt_enable = prx_coal->adapt_enable;
564
565 tx_coal->int_gl = ptx_coal->int_gl;
566 rx_coal->int_gl = prx_coal->int_gl;
567
568 rx_coal->flow_level = prx_coal->flow_level;
569 tx_coal->flow_level = ptx_coal->flow_level;
570
571 /* device version above V3(include V3), GL can configure 1us
572 * unit, so uses 1us unit.
573 */
574 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
575 tx_coal->unit_1us = 1;
576 rx_coal->unit_1us = 1;
577 }
578
579 if (ae_dev->dev_specs.int_ql_max) {
580 tx_coal->ql_enable = 1;
581 rx_coal->ql_enable = 1;
582 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
583 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
584 tx_coal->int_ql = ptx_coal->int_ql;
585 rx_coal->int_ql = prx_coal->int_ql;
586 }
587 }
588
589 static void
hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector * tqp_vector,struct hns3_nic_priv * priv)590 hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
591 struct hns3_nic_priv *priv)
592 {
593 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
594 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
595 struct hnae3_handle *h = priv->ae_handle;
596
597 hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl);
598 hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl);
599 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
600
601 if (tx_coal->ql_enable)
602 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql);
603
604 if (rx_coal->ql_enable)
605 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql);
606 }
607
hns3_nic_set_real_num_queue(struct net_device * netdev)608 static int hns3_nic_set_real_num_queue(struct net_device *netdev)
609 {
610 struct hnae3_handle *h = hns3_get_handle(netdev);
611 struct hnae3_knic_private_info *kinfo = &h->kinfo;
612 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
613 unsigned int queue_size = kinfo->num_tqps;
614 int i, ret;
615
616 if (tc_info->num_tc <= 1 && !tc_info->mqprio_active) {
617 netdev_reset_tc(netdev);
618 } else {
619 ret = netdev_set_num_tc(netdev, tc_info->num_tc);
620 if (ret) {
621 netdev_err(netdev,
622 "netdev_set_num_tc fail, ret=%d!\n", ret);
623 return ret;
624 }
625
626 for (i = 0; i < tc_info->num_tc; i++)
627 netdev_set_tc_queue(netdev, i, tc_info->tqp_count[i],
628 tc_info->tqp_offset[i]);
629 }
630
631 ret = netif_set_real_num_tx_queues(netdev, queue_size);
632 if (ret) {
633 netdev_err(netdev,
634 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
635 return ret;
636 }
637
638 ret = netif_set_real_num_rx_queues(netdev, queue_size);
639 if (ret) {
640 netdev_err(netdev,
641 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
642 return ret;
643 }
644
645 return 0;
646 }
647
hns3_get_max_available_channels(struct hnae3_handle * h)648 u16 hns3_get_max_available_channels(struct hnae3_handle *h)
649 {
650 u16 alloc_tqps, max_rss_size, rss_size;
651
652 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
653 rss_size = alloc_tqps / h->kinfo.tc_info.num_tc;
654
655 return min_t(u16, rss_size, max_rss_size);
656 }
657
hns3_tqp_enable(struct hnae3_queue * tqp)658 static void hns3_tqp_enable(struct hnae3_queue *tqp)
659 {
660 u32 rcb_reg;
661
662 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
663 rcb_reg |= BIT(HNS3_RING_EN_B);
664 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
665 }
666
hns3_tqp_disable(struct hnae3_queue * tqp)667 static void hns3_tqp_disable(struct hnae3_queue *tqp)
668 {
669 u32 rcb_reg;
670
671 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
672 rcb_reg &= ~BIT(HNS3_RING_EN_B);
673 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
674 }
675
hns3_free_rx_cpu_rmap(struct net_device * netdev)676 static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
677 {
678 #ifdef CONFIG_RFS_ACCEL
679 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
680 netdev->rx_cpu_rmap = NULL;
681 #endif
682 }
683
hns3_set_rx_cpu_rmap(struct net_device * netdev)684 static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
685 {
686 #ifdef CONFIG_RFS_ACCEL
687 struct hns3_nic_priv *priv = netdev_priv(netdev);
688 struct hns3_enet_tqp_vector *tqp_vector;
689 int i, ret;
690
691 if (!netdev->rx_cpu_rmap) {
692 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
693 if (!netdev->rx_cpu_rmap)
694 return -ENOMEM;
695 }
696
697 for (i = 0; i < priv->vector_num; i++) {
698 tqp_vector = &priv->tqp_vector[i];
699 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
700 tqp_vector->vector_irq);
701 if (ret) {
702 hns3_free_rx_cpu_rmap(netdev);
703 return ret;
704 }
705 }
706 #endif
707 return 0;
708 }
709
hns3_nic_net_up(struct net_device * netdev)710 static int hns3_nic_net_up(struct net_device *netdev)
711 {
712 struct hns3_nic_priv *priv = netdev_priv(netdev);
713 struct hnae3_handle *h = priv->ae_handle;
714 int i, j;
715 int ret;
716
717 ret = hns3_nic_reset_all_ring(h);
718 if (ret)
719 return ret;
720
721 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
722
723 /* enable the vectors */
724 for (i = 0; i < priv->vector_num; i++)
725 hns3_vector_enable(&priv->tqp_vector[i]);
726
727 /* enable rcb */
728 for (j = 0; j < h->kinfo.num_tqps; j++)
729 hns3_tqp_enable(h->kinfo.tqp[j]);
730
731 /* start the ae_dev */
732 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
733 if (ret) {
734 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
735 while (j--)
736 hns3_tqp_disable(h->kinfo.tqp[j]);
737
738 for (j = i - 1; j >= 0; j--)
739 hns3_vector_disable(&priv->tqp_vector[j]);
740 }
741
742 return ret;
743 }
744
hns3_config_xps(struct hns3_nic_priv * priv)745 static void hns3_config_xps(struct hns3_nic_priv *priv)
746 {
747 int i;
748
749 for (i = 0; i < priv->vector_num; i++) {
750 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
751 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
752
753 while (ring) {
754 int ret;
755
756 ret = netif_set_xps_queue(priv->netdev,
757 &tqp_vector->affinity_mask,
758 ring->tqp->tqp_index);
759 if (ret)
760 netdev_warn(priv->netdev,
761 "set xps queue failed: %d", ret);
762
763 ring = ring->next;
764 }
765 }
766 }
767
hns3_nic_net_open(struct net_device * netdev)768 static int hns3_nic_net_open(struct net_device *netdev)
769 {
770 struct hns3_nic_priv *priv = netdev_priv(netdev);
771 struct hnae3_handle *h = hns3_get_handle(netdev);
772 struct hnae3_knic_private_info *kinfo;
773 int i, ret;
774
775 if (hns3_nic_resetting(netdev))
776 return -EBUSY;
777
778 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
779 netdev_warn(netdev, "net open repeatedly!\n");
780 return 0;
781 }
782
783 netif_carrier_off(netdev);
784
785 ret = hns3_nic_set_real_num_queue(netdev);
786 if (ret)
787 return ret;
788
789 ret = hns3_nic_net_up(netdev);
790 if (ret) {
791 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
792 return ret;
793 }
794
795 kinfo = &h->kinfo;
796 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
797 netdev_set_prio_tc_map(netdev, i, kinfo->tc_info.prio_tc[i]);
798
799 if (h->ae_algo->ops->set_timer_task)
800 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
801
802 hns3_config_xps(priv);
803
804 netif_dbg(h, drv, netdev, "net open\n");
805
806 return 0;
807 }
808
hns3_reset_tx_queue(struct hnae3_handle * h)809 static void hns3_reset_tx_queue(struct hnae3_handle *h)
810 {
811 struct net_device *ndev = h->kinfo.netdev;
812 struct hns3_nic_priv *priv = netdev_priv(ndev);
813 struct netdev_queue *dev_queue;
814 u32 i;
815
816 for (i = 0; i < h->kinfo.num_tqps; i++) {
817 dev_queue = netdev_get_tx_queue(ndev,
818 priv->ring[i].queue_index);
819 netdev_tx_reset_queue(dev_queue);
820 }
821 }
822
hns3_nic_net_down(struct net_device * netdev)823 static void hns3_nic_net_down(struct net_device *netdev)
824 {
825 struct hns3_nic_priv *priv = netdev_priv(netdev);
826 struct hnae3_handle *h = hns3_get_handle(netdev);
827 const struct hnae3_ae_ops *ops;
828 int i;
829
830 /* disable vectors */
831 for (i = 0; i < priv->vector_num; i++)
832 hns3_vector_disable(&priv->tqp_vector[i]);
833
834 /* disable rcb */
835 for (i = 0; i < h->kinfo.num_tqps; i++)
836 hns3_tqp_disable(h->kinfo.tqp[i]);
837
838 /* stop ae_dev */
839 ops = priv->ae_handle->ae_algo->ops;
840 if (ops->stop)
841 ops->stop(priv->ae_handle);
842
843 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
844 * during reset process, because driver may not be able
845 * to disable the ring through firmware when downing the netdev.
846 */
847 if (!hns3_nic_resetting(netdev))
848 hns3_clear_all_ring(priv->ae_handle, false);
849
850 hns3_reset_tx_queue(priv->ae_handle);
851 }
852
hns3_nic_net_stop(struct net_device * netdev)853 static int hns3_nic_net_stop(struct net_device *netdev)
854 {
855 struct hns3_nic_priv *priv = netdev_priv(netdev);
856 struct hnae3_handle *h = hns3_get_handle(netdev);
857
858 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
859 return 0;
860
861 netif_dbg(h, drv, netdev, "net stop\n");
862
863 if (h->ae_algo->ops->set_timer_task)
864 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
865
866 netif_carrier_off(netdev);
867 netif_tx_disable(netdev);
868
869 hns3_nic_net_down(netdev);
870
871 return 0;
872 }
873
hns3_nic_uc_sync(struct net_device * netdev,const unsigned char * addr)874 static int hns3_nic_uc_sync(struct net_device *netdev,
875 const unsigned char *addr)
876 {
877 struct hnae3_handle *h = hns3_get_handle(netdev);
878
879 if (h->ae_algo->ops->add_uc_addr)
880 return h->ae_algo->ops->add_uc_addr(h, addr);
881
882 return 0;
883 }
884
hns3_nic_uc_unsync(struct net_device * netdev,const unsigned char * addr)885 static int hns3_nic_uc_unsync(struct net_device *netdev,
886 const unsigned char *addr)
887 {
888 struct hnae3_handle *h = hns3_get_handle(netdev);
889
890 /* need ignore the request of removing device address, because
891 * we store the device address and other addresses of uc list
892 * in the function's mac filter list.
893 */
894 if (ether_addr_equal(addr, netdev->dev_addr))
895 return 0;
896
897 if (h->ae_algo->ops->rm_uc_addr)
898 return h->ae_algo->ops->rm_uc_addr(h, addr);
899
900 return 0;
901 }
902
hns3_nic_mc_sync(struct net_device * netdev,const unsigned char * addr)903 static int hns3_nic_mc_sync(struct net_device *netdev,
904 const unsigned char *addr)
905 {
906 struct hnae3_handle *h = hns3_get_handle(netdev);
907
908 if (h->ae_algo->ops->add_mc_addr)
909 return h->ae_algo->ops->add_mc_addr(h, addr);
910
911 return 0;
912 }
913
hns3_nic_mc_unsync(struct net_device * netdev,const unsigned char * addr)914 static int hns3_nic_mc_unsync(struct net_device *netdev,
915 const unsigned char *addr)
916 {
917 struct hnae3_handle *h = hns3_get_handle(netdev);
918
919 if (h->ae_algo->ops->rm_mc_addr)
920 return h->ae_algo->ops->rm_mc_addr(h, addr);
921
922 return 0;
923 }
924
hns3_get_netdev_flags(struct net_device * netdev)925 static u8 hns3_get_netdev_flags(struct net_device *netdev)
926 {
927 u8 flags = 0;
928
929 if (netdev->flags & IFF_PROMISC)
930 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
931 else if (netdev->flags & IFF_ALLMULTI)
932 flags = HNAE3_USER_MPE;
933
934 return flags;
935 }
936
hns3_nic_set_rx_mode(struct net_device * netdev)937 static void hns3_nic_set_rx_mode(struct net_device *netdev)
938 {
939 struct hnae3_handle *h = hns3_get_handle(netdev);
940 u8 new_flags;
941
942 new_flags = hns3_get_netdev_flags(netdev);
943
944 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
945 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync);
946
947 /* User mode Promisc mode enable and vlan filtering is disabled to
948 * let all packets in.
949 */
950 h->netdev_flags = new_flags;
951 hns3_request_update_promisc_mode(h);
952 }
953
hns3_request_update_promisc_mode(struct hnae3_handle * handle)954 void hns3_request_update_promisc_mode(struct hnae3_handle *handle)
955 {
956 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
957
958 if (ops->request_update_promisc_mode)
959 ops->request_update_promisc_mode(handle);
960 }
961
hns3_tx_spare_space(struct hns3_enet_ring * ring)962 static u32 hns3_tx_spare_space(struct hns3_enet_ring *ring)
963 {
964 struct hns3_tx_spare *tx_spare = ring->tx_spare;
965 u32 ntc, ntu;
966
967 /* This smp_load_acquire() pairs with smp_store_release() in
968 * hns3_tx_spare_update() called in tx desc cleaning process.
969 */
970 ntc = smp_load_acquire(&tx_spare->last_to_clean);
971 ntu = tx_spare->next_to_use;
972
973 if (ntc > ntu)
974 return ntc - ntu - 1;
975
976 /* The free tx buffer is divided into two part, so pick the
977 * larger one.
978 */
979 return max(ntc, tx_spare->len - ntu) - 1;
980 }
981
hns3_tx_spare_update(struct hns3_enet_ring * ring)982 static void hns3_tx_spare_update(struct hns3_enet_ring *ring)
983 {
984 struct hns3_tx_spare *tx_spare = ring->tx_spare;
985
986 if (!tx_spare ||
987 tx_spare->last_to_clean == tx_spare->next_to_clean)
988 return;
989
990 /* This smp_store_release() pairs with smp_load_acquire() in
991 * hns3_tx_spare_space() called in xmit process.
992 */
993 smp_store_release(&tx_spare->last_to_clean,
994 tx_spare->next_to_clean);
995 }
996
hns3_can_use_tx_bounce(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 space)997 static bool hns3_can_use_tx_bounce(struct hns3_enet_ring *ring,
998 struct sk_buff *skb,
999 u32 space)
1000 {
1001 u32 len = skb->len <= ring->tx_copybreak ? skb->len :
1002 skb_headlen(skb);
1003
1004 if (len > ring->tx_copybreak)
1005 return false;
1006
1007 if (ALIGN(len, dma_get_cache_alignment()) > space) {
1008 hns3_ring_stats_update(ring, tx_spare_full);
1009 return false;
1010 }
1011
1012 return true;
1013 }
1014
hns3_can_use_tx_sgl(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 space)1015 static bool hns3_can_use_tx_sgl(struct hns3_enet_ring *ring,
1016 struct sk_buff *skb,
1017 u32 space)
1018 {
1019 if (skb->len <= ring->tx_copybreak || !tx_sgl ||
1020 (!skb_has_frag_list(skb) &&
1021 skb_shinfo(skb)->nr_frags < tx_sgl))
1022 return false;
1023
1024 if (space < HNS3_MAX_SGL_SIZE) {
1025 hns3_ring_stats_update(ring, tx_spare_full);
1026 return false;
1027 }
1028
1029 return true;
1030 }
1031
hns3_init_tx_spare_buffer(struct hns3_enet_ring * ring)1032 static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring)
1033 {
1034 u32 alloc_size = ring->tqp->handle->kinfo.tx_spare_buf_size;
1035 struct hns3_tx_spare *tx_spare;
1036 struct page *page;
1037 dma_addr_t dma;
1038 int order;
1039
1040 if (!alloc_size)
1041 return;
1042
1043 order = get_order(alloc_size);
1044 if (order > MAX_ORDER) {
1045 if (net_ratelimit())
1046 dev_warn(ring_to_dev(ring), "failed to allocate tx spare buffer, exceed to max order\n");
1047 return;
1048 }
1049
1050 tx_spare = devm_kzalloc(ring_to_dev(ring), sizeof(*tx_spare),
1051 GFP_KERNEL);
1052 if (!tx_spare) {
1053 /* The driver still work without the tx spare buffer */
1054 dev_warn(ring_to_dev(ring), "failed to allocate hns3_tx_spare\n");
1055 goto devm_kzalloc_error;
1056 }
1057
1058 page = alloc_pages_node(dev_to_node(ring_to_dev(ring)),
1059 GFP_KERNEL, order);
1060 if (!page) {
1061 dev_warn(ring_to_dev(ring), "failed to allocate tx spare pages\n");
1062 goto alloc_pages_error;
1063 }
1064
1065 dma = dma_map_page(ring_to_dev(ring), page, 0,
1066 PAGE_SIZE << order, DMA_TO_DEVICE);
1067 if (dma_mapping_error(ring_to_dev(ring), dma)) {
1068 dev_warn(ring_to_dev(ring), "failed to map pages for tx spare\n");
1069 goto dma_mapping_error;
1070 }
1071
1072 tx_spare->dma = dma;
1073 tx_spare->buf = page_address(page);
1074 tx_spare->len = PAGE_SIZE << order;
1075 ring->tx_spare = tx_spare;
1076 return;
1077
1078 dma_mapping_error:
1079 put_page(page);
1080 alloc_pages_error:
1081 devm_kfree(ring_to_dev(ring), tx_spare);
1082 devm_kzalloc_error:
1083 ring->tqp->handle->kinfo.tx_spare_buf_size = 0;
1084 }
1085
1086 /* Use hns3_tx_spare_space() to make sure there is enough buffer
1087 * before calling below function to allocate tx buffer.
1088 */
hns3_tx_spare_alloc(struct hns3_enet_ring * ring,unsigned int size,dma_addr_t * dma,u32 * cb_len)1089 static void *hns3_tx_spare_alloc(struct hns3_enet_ring *ring,
1090 unsigned int size, dma_addr_t *dma,
1091 u32 *cb_len)
1092 {
1093 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1094 u32 ntu = tx_spare->next_to_use;
1095
1096 size = ALIGN(size, dma_get_cache_alignment());
1097 *cb_len = size;
1098
1099 /* Tx spare buffer wraps back here because the end of
1100 * freed tx buffer is not enough.
1101 */
1102 if (ntu + size > tx_spare->len) {
1103 *cb_len += (tx_spare->len - ntu);
1104 ntu = 0;
1105 }
1106
1107 tx_spare->next_to_use = ntu + size;
1108 if (tx_spare->next_to_use == tx_spare->len)
1109 tx_spare->next_to_use = 0;
1110
1111 *dma = tx_spare->dma + ntu;
1112
1113 return tx_spare->buf + ntu;
1114 }
1115
hns3_tx_spare_rollback(struct hns3_enet_ring * ring,u32 len)1116 static void hns3_tx_spare_rollback(struct hns3_enet_ring *ring, u32 len)
1117 {
1118 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1119
1120 if (len > tx_spare->next_to_use) {
1121 len -= tx_spare->next_to_use;
1122 tx_spare->next_to_use = tx_spare->len - len;
1123 } else {
1124 tx_spare->next_to_use -= len;
1125 }
1126 }
1127
hns3_tx_spare_reclaim_cb(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)1128 static void hns3_tx_spare_reclaim_cb(struct hns3_enet_ring *ring,
1129 struct hns3_desc_cb *cb)
1130 {
1131 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1132 u32 ntc = tx_spare->next_to_clean;
1133 u32 len = cb->length;
1134
1135 tx_spare->next_to_clean += len;
1136
1137 if (tx_spare->next_to_clean >= tx_spare->len) {
1138 tx_spare->next_to_clean -= tx_spare->len;
1139
1140 if (tx_spare->next_to_clean) {
1141 ntc = 0;
1142 len = tx_spare->next_to_clean;
1143 }
1144 }
1145
1146 /* This tx spare buffer is only really reclaimed after calling
1147 * hns3_tx_spare_update(), so it is still safe to use the info in
1148 * the tx buffer to do the dma sync or sg unmapping after
1149 * tx_spare->next_to_clean is moved forword.
1150 */
1151 if (cb->type & (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) {
1152 dma_addr_t dma = tx_spare->dma + ntc;
1153
1154 dma_sync_single_for_cpu(ring_to_dev(ring), dma, len,
1155 DMA_TO_DEVICE);
1156 } else {
1157 struct sg_table *sgt = tx_spare->buf + ntc;
1158
1159 dma_unmap_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
1160 DMA_TO_DEVICE);
1161 }
1162 }
1163
hns3_set_tso(struct sk_buff * skb,u32 * paylen_fdop_ol4cs,u16 * mss,u32 * type_cs_vlan_tso,u32 * send_bytes)1164 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs,
1165 u16 *mss, u32 *type_cs_vlan_tso, u32 *send_bytes)
1166 {
1167 u32 l4_offset, hdr_len;
1168 union l3_hdr_info l3;
1169 union l4_hdr_info l4;
1170 u32 l4_paylen;
1171 int ret;
1172
1173 if (!skb_is_gso(skb))
1174 return 0;
1175
1176 ret = skb_cow_head(skb, 0);
1177 if (unlikely(ret < 0))
1178 return ret;
1179
1180 l3.hdr = skb_network_header(skb);
1181 l4.hdr = skb_transport_header(skb);
1182
1183 /* Software should clear the IPv4's checksum field when tso is
1184 * needed.
1185 */
1186 if (l3.v4->version == 4)
1187 l3.v4->check = 0;
1188
1189 /* tunnel packet */
1190 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
1191 SKB_GSO_GRE_CSUM |
1192 SKB_GSO_UDP_TUNNEL |
1193 SKB_GSO_UDP_TUNNEL_CSUM)) {
1194 /* reset l3&l4 pointers from outer to inner headers */
1195 l3.hdr = skb_inner_network_header(skb);
1196 l4.hdr = skb_inner_transport_header(skb);
1197
1198 /* Software should clear the IPv4's checksum field when
1199 * tso is needed.
1200 */
1201 if (l3.v4->version == 4)
1202 l3.v4->check = 0;
1203 }
1204
1205 /* normal or tunnel packet */
1206 l4_offset = l4.hdr - skb->data;
1207
1208 /* remove payload length from inner pseudo checksum when tso */
1209 l4_paylen = skb->len - l4_offset;
1210
1211 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
1212 hdr_len = sizeof(*l4.udp) + l4_offset;
1213 csum_replace_by_diff(&l4.udp->check,
1214 (__force __wsum)htonl(l4_paylen));
1215 } else {
1216 hdr_len = (l4.tcp->doff << 2) + l4_offset;
1217 csum_replace_by_diff(&l4.tcp->check,
1218 (__force __wsum)htonl(l4_paylen));
1219 }
1220
1221 *send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len;
1222
1223 /* find the txbd field values */
1224 *paylen_fdop_ol4cs = skb->len - hdr_len;
1225 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
1226
1227 /* offload outer UDP header checksum */
1228 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)
1229 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1);
1230
1231 /* get MSS for TSO */
1232 *mss = skb_shinfo(skb)->gso_size;
1233
1234 trace_hns3_tso(skb);
1235
1236 return 0;
1237 }
1238
hns3_get_l4_protocol(struct sk_buff * skb,u8 * ol4_proto,u8 * il4_proto)1239 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
1240 u8 *il4_proto)
1241 {
1242 union l3_hdr_info l3;
1243 unsigned char *l4_hdr;
1244 unsigned char *exthdr;
1245 u8 l4_proto_tmp;
1246 __be16 frag_off;
1247
1248 /* find outer header point */
1249 l3.hdr = skb_network_header(skb);
1250 l4_hdr = skb_transport_header(skb);
1251
1252 if (skb->protocol == htons(ETH_P_IPV6)) {
1253 exthdr = l3.hdr + sizeof(*l3.v6);
1254 l4_proto_tmp = l3.v6->nexthdr;
1255 if (l4_hdr != exthdr)
1256 ipv6_skip_exthdr(skb, exthdr - skb->data,
1257 &l4_proto_tmp, &frag_off);
1258 } else if (skb->protocol == htons(ETH_P_IP)) {
1259 l4_proto_tmp = l3.v4->protocol;
1260 } else {
1261 return -EINVAL;
1262 }
1263
1264 *ol4_proto = l4_proto_tmp;
1265
1266 /* tunnel packet */
1267 if (!skb->encapsulation) {
1268 *il4_proto = 0;
1269 return 0;
1270 }
1271
1272 /* find inner header point */
1273 l3.hdr = skb_inner_network_header(skb);
1274 l4_hdr = skb_inner_transport_header(skb);
1275
1276 if (l3.v6->version == 6) {
1277 exthdr = l3.hdr + sizeof(*l3.v6);
1278 l4_proto_tmp = l3.v6->nexthdr;
1279 if (l4_hdr != exthdr)
1280 ipv6_skip_exthdr(skb, exthdr - skb->data,
1281 &l4_proto_tmp, &frag_off);
1282 } else if (l3.v4->version == 4) {
1283 l4_proto_tmp = l3.v4->protocol;
1284 }
1285
1286 *il4_proto = l4_proto_tmp;
1287
1288 return 0;
1289 }
1290
1291 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
1292 * and it is udp packet, which has a dest port as the IANA assigned.
1293 * the hardware is expected to do the checksum offload, but the
1294 * hardware will not do the checksum offload when udp dest port is
1295 * 4789, 4790 or 6081.
1296 */
hns3_tunnel_csum_bug(struct sk_buff * skb)1297 static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
1298 {
1299 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1300 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
1301 union l4_hdr_info l4;
1302
1303 /* device version above V3(include V3), the hardware can
1304 * do this checksum offload.
1305 */
1306 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
1307 return false;
1308
1309 l4.hdr = skb_transport_header(skb);
1310
1311 if (!(!skb->encapsulation &&
1312 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) ||
1313 l4.udp->dest == htons(GENEVE_UDP_PORT) ||
1314 l4.udp->dest == htons(IANA_VXLAN_GPE_UDP_PORT))))
1315 return false;
1316
1317 return true;
1318 }
1319
hns3_set_outer_l2l3l4(struct sk_buff * skb,u8 ol4_proto,u32 * ol_type_vlan_len_msec)1320 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1321 u32 *ol_type_vlan_len_msec)
1322 {
1323 u32 l2_len, l3_len, l4_len;
1324 unsigned char *il2_hdr;
1325 union l3_hdr_info l3;
1326 union l4_hdr_info l4;
1327
1328 l3.hdr = skb_network_header(skb);
1329 l4.hdr = skb_transport_header(skb);
1330
1331 /* compute OL2 header size, defined in 2 Bytes */
1332 l2_len = l3.hdr - skb->data;
1333 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
1334
1335 /* compute OL3 header size, defined in 4 Bytes */
1336 l3_len = l4.hdr - l3.hdr;
1337 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
1338
1339 il2_hdr = skb_inner_mac_header(skb);
1340 /* compute OL4 header size, defined in 4 Bytes */
1341 l4_len = il2_hdr - l4.hdr;
1342 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
1343
1344 /* define outer network header type */
1345 if (skb->protocol == htons(ETH_P_IP)) {
1346 if (skb_is_gso(skb))
1347 hns3_set_field(*ol_type_vlan_len_msec,
1348 HNS3_TXD_OL3T_S,
1349 HNS3_OL3T_IPV4_CSUM);
1350 else
1351 hns3_set_field(*ol_type_vlan_len_msec,
1352 HNS3_TXD_OL3T_S,
1353 HNS3_OL3T_IPV4_NO_CSUM);
1354 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1355 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
1356 HNS3_OL3T_IPV6);
1357 }
1358
1359 if (ol4_proto == IPPROTO_UDP)
1360 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1361 HNS3_TUN_MAC_IN_UDP);
1362 else if (ol4_proto == IPPROTO_GRE)
1363 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1364 HNS3_TUN_NVGRE);
1365 }
1366
hns3_set_l3_type(struct sk_buff * skb,union l3_hdr_info l3,u32 * type_cs_vlan_tso)1367 static void hns3_set_l3_type(struct sk_buff *skb, union l3_hdr_info l3,
1368 u32 *type_cs_vlan_tso)
1369 {
1370 if (l3.v4->version == 4) {
1371 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1372 HNS3_L3T_IPV4);
1373
1374 /* the stack computes the IP header already, the only time we
1375 * need the hardware to recompute it is in the case of TSO.
1376 */
1377 if (skb_is_gso(skb))
1378 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
1379 } else if (l3.v6->version == 6) {
1380 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1381 HNS3_L3T_IPV6);
1382 }
1383 }
1384
hns3_set_l4_csum_length(struct sk_buff * skb,union l4_hdr_info l4,u32 l4_proto,u32 * type_cs_vlan_tso)1385 static int hns3_set_l4_csum_length(struct sk_buff *skb, union l4_hdr_info l4,
1386 u32 l4_proto, u32 *type_cs_vlan_tso)
1387 {
1388 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
1389 switch (l4_proto) {
1390 case IPPROTO_TCP:
1391 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1392 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1393 HNS3_L4T_TCP);
1394 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1395 l4.tcp->doff);
1396 break;
1397 case IPPROTO_UDP:
1398 if (hns3_tunnel_csum_bug(skb)) {
1399 int ret = skb_put_padto(skb, HNS3_MIN_TUN_PKT_LEN);
1400
1401 return ret ? ret : skb_checksum_help(skb);
1402 }
1403
1404 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1405 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1406 HNS3_L4T_UDP);
1407 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1408 (sizeof(struct udphdr) >> 2));
1409 break;
1410 case IPPROTO_SCTP:
1411 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1412 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1413 HNS3_L4T_SCTP);
1414 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1415 (sizeof(struct sctphdr) >> 2));
1416 break;
1417 default:
1418 /* drop the skb tunnel packet if hardware don't support,
1419 * because hardware can't calculate csum when TSO.
1420 */
1421 if (skb_is_gso(skb))
1422 return -EDOM;
1423
1424 /* the stack computes the IP header already,
1425 * driver calculate l4 checksum when not TSO.
1426 */
1427 return skb_checksum_help(skb);
1428 }
1429
1430 return 0;
1431 }
1432
hns3_set_l2l3l4(struct sk_buff * skb,u8 ol4_proto,u8 il4_proto,u32 * type_cs_vlan_tso,u32 * ol_type_vlan_len_msec)1433 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1434 u8 il4_proto, u32 *type_cs_vlan_tso,
1435 u32 *ol_type_vlan_len_msec)
1436 {
1437 unsigned char *l2_hdr = skb->data;
1438 u32 l4_proto = ol4_proto;
1439 union l4_hdr_info l4;
1440 union l3_hdr_info l3;
1441 u32 l2_len, l3_len;
1442
1443 l4.hdr = skb_transport_header(skb);
1444 l3.hdr = skb_network_header(skb);
1445
1446 /* handle encapsulation skb */
1447 if (skb->encapsulation) {
1448 /* If this is a not UDP/GRE encapsulation skb */
1449 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
1450 /* drop the skb tunnel packet if hardware don't support,
1451 * because hardware can't calculate csum when TSO.
1452 */
1453 if (skb_is_gso(skb))
1454 return -EDOM;
1455
1456 /* the stack computes the IP header already,
1457 * driver calculate l4 checksum when not TSO.
1458 */
1459 return skb_checksum_help(skb);
1460 }
1461
1462 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
1463
1464 /* switch to inner header */
1465 l2_hdr = skb_inner_mac_header(skb);
1466 l3.hdr = skb_inner_network_header(skb);
1467 l4.hdr = skb_inner_transport_header(skb);
1468 l4_proto = il4_proto;
1469 }
1470
1471 hns3_set_l3_type(skb, l3, type_cs_vlan_tso);
1472
1473 /* compute inner(/normal) L2 header size, defined in 2 Bytes */
1474 l2_len = l3.hdr - l2_hdr;
1475 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
1476
1477 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
1478 l3_len = l4.hdr - l3.hdr;
1479 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
1480
1481 return hns3_set_l4_csum_length(skb, l4, l4_proto, type_cs_vlan_tso);
1482 }
1483
hns3_handle_vtags(struct hns3_enet_ring * tx_ring,struct sk_buff * skb)1484 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
1485 struct sk_buff *skb)
1486 {
1487 struct hnae3_handle *handle = tx_ring->tqp->handle;
1488 struct hnae3_ae_dev *ae_dev;
1489 struct vlan_ethhdr *vhdr;
1490 int rc;
1491
1492 if (!(skb->protocol == htons(ETH_P_8021Q) ||
1493 skb_vlan_tag_present(skb)))
1494 return 0;
1495
1496 /* For HW limitation on HNAE3_DEVICE_VERSION_V2, if port based insert
1497 * VLAN enabled, only one VLAN header is allowed in skb, otherwise it
1498 * will cause RAS error.
1499 */
1500 ae_dev = pci_get_drvdata(handle->pdev);
1501 if (unlikely(skb_vlan_tagged_multi(skb) &&
1502 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 &&
1503 handle->port_base_vlan_state ==
1504 HNAE3_PORT_BASE_VLAN_ENABLE))
1505 return -EINVAL;
1506
1507 if (skb->protocol == htons(ETH_P_8021Q) &&
1508 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1509 /* When HW VLAN acceleration is turned off, and the stack
1510 * sets the protocol to 802.1q, the driver just need to
1511 * set the protocol to the encapsulated ethertype.
1512 */
1513 skb->protocol = vlan_get_protocol(skb);
1514 return 0;
1515 }
1516
1517 if (skb_vlan_tag_present(skb)) {
1518 /* Based on hw strategy, use out_vtag in two layer tag case,
1519 * and use inner_vtag in one tag case.
1520 */
1521 if (skb->protocol == htons(ETH_P_8021Q) &&
1522 handle->port_base_vlan_state ==
1523 HNAE3_PORT_BASE_VLAN_DISABLE)
1524 rc = HNS3_OUTER_VLAN_TAG;
1525 else
1526 rc = HNS3_INNER_VLAN_TAG;
1527
1528 skb->protocol = vlan_get_protocol(skb);
1529 return rc;
1530 }
1531
1532 rc = skb_cow_head(skb, 0);
1533 if (unlikely(rc < 0))
1534 return rc;
1535
1536 vhdr = skb_vlan_eth_hdr(skb);
1537 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
1538 & VLAN_PRIO_MASK);
1539
1540 skb->protocol = vlan_get_protocol(skb);
1541 return 0;
1542 }
1543
1544 /* check if the hardware is capable of checksum offloading */
hns3_check_hw_tx_csum(struct sk_buff * skb)1545 static bool hns3_check_hw_tx_csum(struct sk_buff *skb)
1546 {
1547 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1548
1549 /* Kindly note, due to backward compatibility of the TX descriptor,
1550 * HW checksum of the non-IP packets and GSO packets is handled at
1551 * different place in the following code
1552 */
1553 if (skb_csum_is_sctp(skb) || skb_is_gso(skb) ||
1554 !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state))
1555 return false;
1556
1557 return true;
1558 }
1559
1560 struct hns3_desc_param {
1561 u32 paylen_ol4cs;
1562 u32 ol_type_vlan_len_msec;
1563 u32 type_cs_vlan_tso;
1564 u16 mss_hw_csum;
1565 u16 inner_vtag;
1566 u16 out_vtag;
1567 };
1568
hns3_init_desc_data(struct sk_buff * skb,struct hns3_desc_param * pa)1569 static void hns3_init_desc_data(struct sk_buff *skb, struct hns3_desc_param *pa)
1570 {
1571 pa->paylen_ol4cs = skb->len;
1572 pa->ol_type_vlan_len_msec = 0;
1573 pa->type_cs_vlan_tso = 0;
1574 pa->mss_hw_csum = 0;
1575 pa->inner_vtag = 0;
1576 pa->out_vtag = 0;
1577 }
1578
hns3_handle_vlan_info(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_param * param)1579 static int hns3_handle_vlan_info(struct hns3_enet_ring *ring,
1580 struct sk_buff *skb,
1581 struct hns3_desc_param *param)
1582 {
1583 int ret;
1584
1585 ret = hns3_handle_vtags(ring, skb);
1586 if (unlikely(ret < 0)) {
1587 hns3_ring_stats_update(ring, tx_vlan_err);
1588 return ret;
1589 } else if (ret == HNS3_INNER_VLAN_TAG) {
1590 param->inner_vtag = skb_vlan_tag_get(skb);
1591 param->inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1592 VLAN_PRIO_MASK;
1593 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1594 } else if (ret == HNS3_OUTER_VLAN_TAG) {
1595 param->out_vtag = skb_vlan_tag_get(skb);
1596 param->out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1597 VLAN_PRIO_MASK;
1598 hns3_set_field(param->ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1599 1);
1600 }
1601 return 0;
1602 }
1603
hns3_handle_csum_partial(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_cb * desc_cb,struct hns3_desc_param * param)1604 static int hns3_handle_csum_partial(struct hns3_enet_ring *ring,
1605 struct sk_buff *skb,
1606 struct hns3_desc_cb *desc_cb,
1607 struct hns3_desc_param *param)
1608 {
1609 u8 ol4_proto, il4_proto;
1610 int ret;
1611
1612 if (hns3_check_hw_tx_csum(skb)) {
1613 /* set checksum start and offset, defined in 2 Bytes */
1614 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_CSUM_START_S,
1615 skb_checksum_start_offset(skb) >> 1);
1616 hns3_set_field(param->ol_type_vlan_len_msec,
1617 HNS3_TXD_CSUM_OFFSET_S,
1618 skb->csum_offset >> 1);
1619 param->mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B);
1620 return 0;
1621 }
1622
1623 skb_reset_mac_len(skb);
1624
1625 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1626 if (unlikely(ret < 0)) {
1627 hns3_ring_stats_update(ring, tx_l4_proto_err);
1628 return ret;
1629 }
1630
1631 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1632 ¶m->type_cs_vlan_tso,
1633 ¶m->ol_type_vlan_len_msec);
1634 if (unlikely(ret < 0)) {
1635 hns3_ring_stats_update(ring, tx_l2l3l4_err);
1636 return ret;
1637 }
1638
1639 ret = hns3_set_tso(skb, ¶m->paylen_ol4cs, ¶m->mss_hw_csum,
1640 ¶m->type_cs_vlan_tso, &desc_cb->send_bytes);
1641 if (unlikely(ret < 0)) {
1642 hns3_ring_stats_update(ring, tx_tso_err);
1643 return ret;
1644 }
1645 return 0;
1646 }
1647
hns3_fill_skb_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc * desc,struct hns3_desc_cb * desc_cb)1648 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
1649 struct sk_buff *skb, struct hns3_desc *desc,
1650 struct hns3_desc_cb *desc_cb)
1651 {
1652 struct hns3_desc_param param;
1653 int ret;
1654
1655 hns3_init_desc_data(skb, ¶m);
1656 ret = hns3_handle_vlan_info(ring, skb, ¶m);
1657 if (unlikely(ret < 0))
1658 return ret;
1659
1660 desc_cb->send_bytes = skb->len;
1661
1662 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1663 ret = hns3_handle_csum_partial(ring, skb, desc_cb, ¶m);
1664 if (ret)
1665 return ret;
1666 }
1667
1668 /* Set txbd */
1669 desc->tx.ol_type_vlan_len_msec =
1670 cpu_to_le32(param.ol_type_vlan_len_msec);
1671 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(param.type_cs_vlan_tso);
1672 desc->tx.paylen_ol4cs = cpu_to_le32(param.paylen_ol4cs);
1673 desc->tx.mss_hw_csum = cpu_to_le16(param.mss_hw_csum);
1674 desc->tx.vlan_tag = cpu_to_le16(param.inner_vtag);
1675 desc->tx.outer_vlan_tag = cpu_to_le16(param.out_vtag);
1676
1677 return 0;
1678 }
1679
hns3_fill_desc(struct hns3_enet_ring * ring,dma_addr_t dma,unsigned int size)1680 static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma,
1681 unsigned int size)
1682 {
1683 #define HNS3_LIKELY_BD_NUM 1
1684
1685 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1686 unsigned int frag_buf_num;
1687 int k, sizeoflast;
1688
1689 if (likely(size <= HNS3_MAX_BD_SIZE)) {
1690 desc->addr = cpu_to_le64(dma);
1691 desc->tx.send_size = cpu_to_le16(size);
1692 desc->tx.bdtp_fe_sc_vld_ra_ri =
1693 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1694
1695 trace_hns3_tx_desc(ring, ring->next_to_use);
1696 ring_ptr_move_fw(ring, next_to_use);
1697 return HNS3_LIKELY_BD_NUM;
1698 }
1699
1700 frag_buf_num = hns3_tx_bd_count(size);
1701 sizeoflast = size % HNS3_MAX_BD_SIZE;
1702 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1703
1704 /* When frag size is bigger than hardware limit, split this frag */
1705 for (k = 0; k < frag_buf_num; k++) {
1706 /* now, fill the descriptor */
1707 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
1708 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1709 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1710 desc->tx.bdtp_fe_sc_vld_ra_ri =
1711 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1712
1713 trace_hns3_tx_desc(ring, ring->next_to_use);
1714 /* move ring pointer to next */
1715 ring_ptr_move_fw(ring, next_to_use);
1716
1717 desc = &ring->desc[ring->next_to_use];
1718 }
1719
1720 return frag_buf_num;
1721 }
1722
hns3_map_and_fill_desc(struct hns3_enet_ring * ring,void * priv,unsigned int type)1723 static int hns3_map_and_fill_desc(struct hns3_enet_ring *ring, void *priv,
1724 unsigned int type)
1725 {
1726 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1727 struct device *dev = ring_to_dev(ring);
1728 unsigned int size;
1729 dma_addr_t dma;
1730
1731 if (type & (DESC_TYPE_FRAGLIST_SKB | DESC_TYPE_SKB)) {
1732 struct sk_buff *skb = (struct sk_buff *)priv;
1733
1734 size = skb_headlen(skb);
1735 if (!size)
1736 return 0;
1737
1738 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1739 } else if (type & DESC_TYPE_BOUNCE_HEAD) {
1740 /* Head data has been filled in hns3_handle_tx_bounce(),
1741 * just return 0 here.
1742 */
1743 return 0;
1744 } else {
1745 skb_frag_t *frag = (skb_frag_t *)priv;
1746
1747 size = skb_frag_size(frag);
1748 if (!size)
1749 return 0;
1750
1751 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1752 }
1753
1754 if (unlikely(dma_mapping_error(dev, dma))) {
1755 hns3_ring_stats_update(ring, sw_err_cnt);
1756 return -ENOMEM;
1757 }
1758
1759 desc_cb->priv = priv;
1760 desc_cb->length = size;
1761 desc_cb->dma = dma;
1762 desc_cb->type = type;
1763
1764 return hns3_fill_desc(ring, dma, size);
1765 }
1766
hns3_skb_bd_num(struct sk_buff * skb,unsigned int * bd_size,unsigned int bd_num)1767 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1768 unsigned int bd_num)
1769 {
1770 unsigned int size;
1771 int i;
1772
1773 size = skb_headlen(skb);
1774 while (size > HNS3_MAX_BD_SIZE) {
1775 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1776 size -= HNS3_MAX_BD_SIZE;
1777
1778 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1779 return bd_num;
1780 }
1781
1782 if (size) {
1783 bd_size[bd_num++] = size;
1784 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1785 return bd_num;
1786 }
1787
1788 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1789 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1790 size = skb_frag_size(frag);
1791 if (!size)
1792 continue;
1793
1794 while (size > HNS3_MAX_BD_SIZE) {
1795 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1796 size -= HNS3_MAX_BD_SIZE;
1797
1798 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1799 return bd_num;
1800 }
1801
1802 bd_size[bd_num++] = size;
1803 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1804 return bd_num;
1805 }
1806
1807 return bd_num;
1808 }
1809
hns3_tx_bd_num(struct sk_buff * skb,unsigned int * bd_size,u8 max_non_tso_bd_num,unsigned int bd_num,unsigned int recursion_level)1810 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1811 u8 max_non_tso_bd_num, unsigned int bd_num,
1812 unsigned int recursion_level)
1813 {
1814 #define HNS3_MAX_RECURSION_LEVEL 24
1815
1816 struct sk_buff *frag_skb;
1817
1818 /* If the total len is within the max bd limit */
1819 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !recursion_level &&
1820 !skb_has_frag_list(skb) &&
1821 skb_shinfo(skb)->nr_frags < max_non_tso_bd_num))
1822 return skb_shinfo(skb)->nr_frags + 1U;
1823
1824 if (unlikely(recursion_level >= HNS3_MAX_RECURSION_LEVEL))
1825 return UINT_MAX;
1826
1827 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
1828 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1829 return bd_num;
1830
1831 skb_walk_frags(skb, frag_skb) {
1832 bd_num = hns3_tx_bd_num(frag_skb, bd_size, max_non_tso_bd_num,
1833 bd_num, recursion_level + 1);
1834 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1835 return bd_num;
1836 }
1837
1838 return bd_num;
1839 }
1840
hns3_gso_hdr_len(struct sk_buff * skb)1841 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1842 {
1843 if (!skb->encapsulation)
1844 return skb_tcp_all_headers(skb);
1845
1846 return skb_inner_tcp_all_headers(skb);
1847 }
1848
1849 /* HW need every continuous max_non_tso_bd_num buffer data to be larger
1850 * than MSS, we simplify it by ensuring skb_headlen + the first continuous
1851 * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss,
1852 * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger
1853 * than MSS except the last max_non_tso_bd_num - 1 frags.
1854 */
hns3_skb_need_linearized(struct sk_buff * skb,unsigned int * bd_size,unsigned int bd_num,u8 max_non_tso_bd_num)1855 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
1856 unsigned int bd_num, u8 max_non_tso_bd_num)
1857 {
1858 unsigned int tot_len = 0;
1859 int i;
1860
1861 for (i = 0; i < max_non_tso_bd_num - 1U; i++)
1862 tot_len += bd_size[i];
1863
1864 /* ensure the first max_non_tso_bd_num frags is greater than
1865 * mss + header
1866 */
1867 if (tot_len + bd_size[max_non_tso_bd_num - 1U] <
1868 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
1869 return true;
1870
1871 /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater
1872 * than mss except the last one.
1873 */
1874 for (i = 0; i < bd_num - max_non_tso_bd_num; i++) {
1875 tot_len -= bd_size[i];
1876 tot_len += bd_size[i + max_non_tso_bd_num - 1U];
1877
1878 if (tot_len < skb_shinfo(skb)->gso_size)
1879 return true;
1880 }
1881
1882 return false;
1883 }
1884
hns3_shinfo_pack(struct skb_shared_info * shinfo,__u32 * size)1885 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
1886 {
1887 int i;
1888
1889 for (i = 0; i < MAX_SKB_FRAGS; i++)
1890 size[i] = skb_frag_size(&shinfo->frags[i]);
1891 }
1892
hns3_skb_linearize(struct hns3_enet_ring * ring,struct sk_buff * skb,unsigned int bd_num)1893 static int hns3_skb_linearize(struct hns3_enet_ring *ring,
1894 struct sk_buff *skb,
1895 unsigned int bd_num)
1896 {
1897 /* 'bd_num == UINT_MAX' means the skb' fraglist has a
1898 * recursion level of over HNS3_MAX_RECURSION_LEVEL.
1899 */
1900 if (bd_num == UINT_MAX) {
1901 hns3_ring_stats_update(ring, over_max_recursion);
1902 return -ENOMEM;
1903 }
1904
1905 /* The skb->len has exceeded the hw limitation, linearization
1906 * will not help.
1907 */
1908 if (skb->len > HNS3_MAX_TSO_SIZE ||
1909 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)) {
1910 hns3_ring_stats_update(ring, hw_limitation);
1911 return -ENOMEM;
1912 }
1913
1914 if (__skb_linearize(skb)) {
1915 hns3_ring_stats_update(ring, sw_err_cnt);
1916 return -ENOMEM;
1917 }
1918
1919 return 0;
1920 }
1921
hns3_nic_maybe_stop_tx(struct hns3_enet_ring * ring,struct net_device * netdev,struct sk_buff * skb)1922 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
1923 struct net_device *netdev,
1924 struct sk_buff *skb)
1925 {
1926 struct hns3_nic_priv *priv = netdev_priv(netdev);
1927 u8 max_non_tso_bd_num = priv->max_non_tso_bd_num;
1928 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
1929 unsigned int bd_num;
1930
1931 bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num, 0, 0);
1932 if (unlikely(bd_num > max_non_tso_bd_num)) {
1933 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
1934 !hns3_skb_need_linearized(skb, bd_size, bd_num,
1935 max_non_tso_bd_num)) {
1936 trace_hns3_over_max_bd(skb);
1937 goto out;
1938 }
1939
1940 if (hns3_skb_linearize(ring, skb, bd_num))
1941 return -ENOMEM;
1942
1943 bd_num = hns3_tx_bd_count(skb->len);
1944
1945 hns3_ring_stats_update(ring, tx_copy);
1946 }
1947
1948 out:
1949 if (likely(ring_space(ring) >= bd_num))
1950 return bd_num;
1951
1952 netif_stop_subqueue(netdev, ring->queue_index);
1953 smp_mb(); /* Memory barrier before checking ring_space */
1954
1955 /* Start queue in case hns3_clean_tx_ring has just made room
1956 * available and has not seen the queue stopped state performed
1957 * by netif_stop_subqueue above.
1958 */
1959 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) &&
1960 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
1961 netif_start_subqueue(netdev, ring->queue_index);
1962 return bd_num;
1963 }
1964
1965 hns3_ring_stats_update(ring, tx_busy);
1966
1967 return -EBUSY;
1968 }
1969
hns3_clear_desc(struct hns3_enet_ring * ring,int next_to_use_orig)1970 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
1971 {
1972 struct device *dev = ring_to_dev(ring);
1973 unsigned int i;
1974
1975 for (i = 0; i < ring->desc_num; i++) {
1976 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1977 struct hns3_desc_cb *desc_cb;
1978
1979 memset(desc, 0, sizeof(*desc));
1980
1981 /* check if this is where we started */
1982 if (ring->next_to_use == next_to_use_orig)
1983 break;
1984
1985 /* rollback one */
1986 ring_ptr_move_bw(ring, next_to_use);
1987
1988 desc_cb = &ring->desc_cb[ring->next_to_use];
1989
1990 if (!desc_cb->dma)
1991 continue;
1992
1993 /* unmap the descriptor dma address */
1994 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
1995 dma_unmap_single(dev, desc_cb->dma, desc_cb->length,
1996 DMA_TO_DEVICE);
1997 else if (desc_cb->type &
1998 (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL))
1999 hns3_tx_spare_rollback(ring, desc_cb->length);
2000 else if (desc_cb->length)
2001 dma_unmap_page(dev, desc_cb->dma, desc_cb->length,
2002 DMA_TO_DEVICE);
2003
2004 desc_cb->length = 0;
2005 desc_cb->dma = 0;
2006 desc_cb->type = DESC_TYPE_UNKNOWN;
2007 }
2008 }
2009
hns3_fill_skb_to_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,unsigned int type)2010 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
2011 struct sk_buff *skb, unsigned int type)
2012 {
2013 struct sk_buff *frag_skb;
2014 int i, ret, bd_num = 0;
2015
2016 ret = hns3_map_and_fill_desc(ring, skb, type);
2017 if (unlikely(ret < 0))
2018 return ret;
2019
2020 bd_num += ret;
2021
2022 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2023 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2024
2025 ret = hns3_map_and_fill_desc(ring, frag, DESC_TYPE_PAGE);
2026 if (unlikely(ret < 0))
2027 return ret;
2028
2029 bd_num += ret;
2030 }
2031
2032 skb_walk_frags(skb, frag_skb) {
2033 ret = hns3_fill_skb_to_desc(ring, frag_skb,
2034 DESC_TYPE_FRAGLIST_SKB);
2035 if (unlikely(ret < 0))
2036 return ret;
2037
2038 bd_num += ret;
2039 }
2040
2041 return bd_num;
2042 }
2043
hns3_tx_push_bd(struct hns3_enet_ring * ring,int num)2044 static void hns3_tx_push_bd(struct hns3_enet_ring *ring, int num)
2045 {
2046 #define HNS3_BYTES_PER_64BIT 8
2047
2048 struct hns3_desc desc[HNS3_MAX_PUSH_BD_NUM] = {};
2049 int offset = 0;
2050
2051 /* make sure everything is visible to device before
2052 * excuting tx push or updating doorbell
2053 */
2054 dma_wmb();
2055
2056 do {
2057 int idx = (ring->next_to_use - num + ring->desc_num) %
2058 ring->desc_num;
2059
2060 u64_stats_update_begin(&ring->syncp);
2061 ring->stats.tx_push++;
2062 u64_stats_update_end(&ring->syncp);
2063 memcpy(&desc[offset], &ring->desc[idx],
2064 sizeof(struct hns3_desc));
2065 offset++;
2066 } while (--num);
2067
2068 __iowrite64_copy(ring->tqp->mem_base, desc,
2069 (sizeof(struct hns3_desc) * HNS3_MAX_PUSH_BD_NUM) /
2070 HNS3_BYTES_PER_64BIT);
2071
2072 io_stop_wc();
2073 }
2074
hns3_tx_mem_doorbell(struct hns3_enet_ring * ring)2075 static void hns3_tx_mem_doorbell(struct hns3_enet_ring *ring)
2076 {
2077 #define HNS3_MEM_DOORBELL_OFFSET 64
2078
2079 __le64 bd_num = cpu_to_le64((u64)ring->pending_buf);
2080
2081 /* make sure everything is visible to device before
2082 * excuting tx push or updating doorbell
2083 */
2084 dma_wmb();
2085
2086 __iowrite64_copy(ring->tqp->mem_base + HNS3_MEM_DOORBELL_OFFSET,
2087 &bd_num, 1);
2088 u64_stats_update_begin(&ring->syncp);
2089 ring->stats.tx_mem_doorbell += ring->pending_buf;
2090 u64_stats_update_end(&ring->syncp);
2091
2092 io_stop_wc();
2093 }
2094
hns3_tx_doorbell(struct hns3_enet_ring * ring,int num,bool doorbell)2095 static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num,
2096 bool doorbell)
2097 {
2098 struct net_device *netdev = ring_to_netdev(ring);
2099 struct hns3_nic_priv *priv = netdev_priv(netdev);
2100
2101 /* when tx push is enabled, the packet whose number of BD below
2102 * HNS3_MAX_PUSH_BD_NUM can be pushed directly.
2103 */
2104 if (test_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state) && num &&
2105 !ring->pending_buf && num <= HNS3_MAX_PUSH_BD_NUM && doorbell) {
2106 /* This smp_store_release() pairs with smp_load_aquire() in
2107 * hns3_nic_reclaim_desc(). Ensure that the BD valid bit
2108 * is updated.
2109 */
2110 smp_store_release(&ring->last_to_use, ring->next_to_use);
2111 hns3_tx_push_bd(ring, num);
2112 return;
2113 }
2114
2115 ring->pending_buf += num;
2116
2117 if (!doorbell) {
2118 hns3_ring_stats_update(ring, tx_more);
2119 return;
2120 }
2121
2122 /* This smp_store_release() pairs with smp_load_aquire() in
2123 * hns3_nic_reclaim_desc(). Ensure that the BD valid bit is updated.
2124 */
2125 smp_store_release(&ring->last_to_use, ring->next_to_use);
2126
2127 if (ring->tqp->mem_base)
2128 hns3_tx_mem_doorbell(ring);
2129 else
2130 writel(ring->pending_buf,
2131 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG);
2132
2133 ring->pending_buf = 0;
2134 }
2135
hns3_tsyn(struct net_device * netdev,struct sk_buff * skb,struct hns3_desc * desc)2136 static void hns3_tsyn(struct net_device *netdev, struct sk_buff *skb,
2137 struct hns3_desc *desc)
2138 {
2139 struct hnae3_handle *h = hns3_get_handle(netdev);
2140
2141 if (!(h->ae_algo->ops->set_tx_hwts_info &&
2142 h->ae_algo->ops->set_tx_hwts_info(h, skb)))
2143 return;
2144
2145 desc->tx.bdtp_fe_sc_vld_ra_ri |= cpu_to_le16(BIT(HNS3_TXD_TSYN_B));
2146 }
2147
hns3_handle_tx_bounce(struct hns3_enet_ring * ring,struct sk_buff * skb)2148 static int hns3_handle_tx_bounce(struct hns3_enet_ring *ring,
2149 struct sk_buff *skb)
2150 {
2151 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2152 unsigned int type = DESC_TYPE_BOUNCE_HEAD;
2153 unsigned int size = skb_headlen(skb);
2154 dma_addr_t dma;
2155 int bd_num = 0;
2156 u32 cb_len;
2157 void *buf;
2158 int ret;
2159
2160 if (skb->len <= ring->tx_copybreak) {
2161 size = skb->len;
2162 type = DESC_TYPE_BOUNCE_ALL;
2163 }
2164
2165 /* hns3_can_use_tx_bounce() is called to ensure the below
2166 * function can always return the tx buffer.
2167 */
2168 buf = hns3_tx_spare_alloc(ring, size, &dma, &cb_len);
2169
2170 ret = skb_copy_bits(skb, 0, buf, size);
2171 if (unlikely(ret < 0)) {
2172 hns3_tx_spare_rollback(ring, cb_len);
2173 hns3_ring_stats_update(ring, copy_bits_err);
2174 return ret;
2175 }
2176
2177 desc_cb->priv = skb;
2178 desc_cb->length = cb_len;
2179 desc_cb->dma = dma;
2180 desc_cb->type = type;
2181
2182 bd_num += hns3_fill_desc(ring, dma, size);
2183
2184 if (type == DESC_TYPE_BOUNCE_HEAD) {
2185 ret = hns3_fill_skb_to_desc(ring, skb,
2186 DESC_TYPE_BOUNCE_HEAD);
2187 if (unlikely(ret < 0))
2188 return ret;
2189
2190 bd_num += ret;
2191 }
2192
2193 dma_sync_single_for_device(ring_to_dev(ring), dma, size,
2194 DMA_TO_DEVICE);
2195
2196 hns3_ring_stats_update(ring, tx_bounce);
2197
2198 return bd_num;
2199 }
2200
hns3_handle_tx_sgl(struct hns3_enet_ring * ring,struct sk_buff * skb)2201 static int hns3_handle_tx_sgl(struct hns3_enet_ring *ring,
2202 struct sk_buff *skb)
2203 {
2204 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2205 u32 nfrag = skb_shinfo(skb)->nr_frags + 1;
2206 struct sg_table *sgt;
2207 int i, bd_num = 0;
2208 dma_addr_t dma;
2209 u32 cb_len;
2210 int nents;
2211
2212 if (skb_has_frag_list(skb))
2213 nfrag = HNS3_MAX_TSO_BD_NUM;
2214
2215 /* hns3_can_use_tx_sgl() is called to ensure the below
2216 * function can always return the tx buffer.
2217 */
2218 sgt = hns3_tx_spare_alloc(ring, HNS3_SGL_SIZE(nfrag),
2219 &dma, &cb_len);
2220
2221 /* scatterlist follows by the sg table */
2222 sgt->sgl = (struct scatterlist *)(sgt + 1);
2223 sg_init_table(sgt->sgl, nfrag);
2224 nents = skb_to_sgvec(skb, sgt->sgl, 0, skb->len);
2225 if (unlikely(nents < 0)) {
2226 hns3_tx_spare_rollback(ring, cb_len);
2227 hns3_ring_stats_update(ring, skb2sgl_err);
2228 return -ENOMEM;
2229 }
2230
2231 sgt->orig_nents = nents;
2232 sgt->nents = dma_map_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
2233 DMA_TO_DEVICE);
2234 if (unlikely(!sgt->nents)) {
2235 hns3_tx_spare_rollback(ring, cb_len);
2236 hns3_ring_stats_update(ring, map_sg_err);
2237 return -ENOMEM;
2238 }
2239
2240 desc_cb->priv = skb;
2241 desc_cb->length = cb_len;
2242 desc_cb->dma = dma;
2243 desc_cb->type = DESC_TYPE_SGL_SKB;
2244
2245 for (i = 0; i < sgt->nents; i++)
2246 bd_num += hns3_fill_desc(ring, sg_dma_address(sgt->sgl + i),
2247 sg_dma_len(sgt->sgl + i));
2248 hns3_ring_stats_update(ring, tx_sgl);
2249
2250 return bd_num;
2251 }
2252
hns3_handle_desc_filling(struct hns3_enet_ring * ring,struct sk_buff * skb)2253 static int hns3_handle_desc_filling(struct hns3_enet_ring *ring,
2254 struct sk_buff *skb)
2255 {
2256 u32 space;
2257
2258 if (!ring->tx_spare)
2259 goto out;
2260
2261 space = hns3_tx_spare_space(ring);
2262
2263 if (hns3_can_use_tx_sgl(ring, skb, space))
2264 return hns3_handle_tx_sgl(ring, skb);
2265
2266 if (hns3_can_use_tx_bounce(ring, skb, space))
2267 return hns3_handle_tx_bounce(ring, skb);
2268
2269 out:
2270 return hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
2271 }
2272
hns3_handle_skb_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_cb * desc_cb,int next_to_use_head)2273 static int hns3_handle_skb_desc(struct hns3_enet_ring *ring,
2274 struct sk_buff *skb,
2275 struct hns3_desc_cb *desc_cb,
2276 int next_to_use_head)
2277 {
2278 int ret;
2279
2280 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use],
2281 desc_cb);
2282 if (unlikely(ret < 0))
2283 goto fill_err;
2284
2285 /* 'ret < 0' means filling error, 'ret == 0' means skb->len is
2286 * zero, which is unlikely, and 'ret > 0' means how many tx desc
2287 * need to be notified to the hw.
2288 */
2289 ret = hns3_handle_desc_filling(ring, skb);
2290 if (likely(ret > 0))
2291 return ret;
2292
2293 fill_err:
2294 hns3_clear_desc(ring, next_to_use_head);
2295 return ret;
2296 }
2297
hns3_nic_net_xmit(struct sk_buff * skb,struct net_device * netdev)2298 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
2299 {
2300 struct hns3_nic_priv *priv = netdev_priv(netdev);
2301 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
2302 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2303 struct netdev_queue *dev_queue;
2304 int pre_ntu, ret;
2305 bool doorbell;
2306
2307 /* Hardware can only handle short frames above 32 bytes */
2308 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) {
2309 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
2310
2311 hns3_ring_stats_update(ring, sw_err_cnt);
2312
2313 return NETDEV_TX_OK;
2314 }
2315
2316 /* Prefetch the data used later */
2317 prefetch(skb->data);
2318
2319 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb);
2320 if (unlikely(ret <= 0)) {
2321 if (ret == -EBUSY) {
2322 hns3_tx_doorbell(ring, 0, true);
2323 return NETDEV_TX_BUSY;
2324 }
2325
2326 hns3_rl_err(netdev, "xmit error: %d!\n", ret);
2327 goto out_err_tx_ok;
2328 }
2329
2330 ret = hns3_handle_skb_desc(ring, skb, desc_cb, ring->next_to_use);
2331 if (unlikely(ret <= 0))
2332 goto out_err_tx_ok;
2333
2334 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
2335 (ring->desc_num - 1);
2336
2337 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
2338 hns3_tsyn(netdev, skb, &ring->desc[pre_ntu]);
2339
2340 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
2341 cpu_to_le16(BIT(HNS3_TXD_FE_B));
2342 trace_hns3_tx_desc(ring, pre_ntu);
2343
2344 skb_tx_timestamp(skb);
2345
2346 /* Complete translate all packets */
2347 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
2348 doorbell = __netdev_tx_sent_queue(dev_queue, desc_cb->send_bytes,
2349 netdev_xmit_more());
2350 hns3_tx_doorbell(ring, ret, doorbell);
2351
2352 return NETDEV_TX_OK;
2353
2354 out_err_tx_ok:
2355 dev_kfree_skb_any(skb);
2356 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
2357 return NETDEV_TX_OK;
2358 }
2359
hns3_nic_net_set_mac_address(struct net_device * netdev,void * p)2360 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
2361 {
2362 char format_mac_addr_perm[HNAE3_FORMAT_MAC_ADDR_LEN];
2363 char format_mac_addr_sa[HNAE3_FORMAT_MAC_ADDR_LEN];
2364 struct hnae3_handle *h = hns3_get_handle(netdev);
2365 struct sockaddr *mac_addr = p;
2366 int ret;
2367
2368 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
2369 return -EADDRNOTAVAIL;
2370
2371 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
2372 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data);
2373 netdev_info(netdev, "already using mac address %s\n",
2374 format_mac_addr_sa);
2375 return 0;
2376 }
2377
2378 /* For VF device, if there is a perm_addr, then the user will not
2379 * be allowed to change the address.
2380 */
2381 if (!hns3_is_phys_func(h->pdev) &&
2382 !is_zero_ether_addr(netdev->perm_addr)) {
2383 hnae3_format_mac_addr(format_mac_addr_perm, netdev->perm_addr);
2384 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data);
2385 netdev_err(netdev, "has permanent MAC %s, user MAC %s not allow\n",
2386 format_mac_addr_perm, format_mac_addr_sa);
2387 return -EPERM;
2388 }
2389
2390 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
2391 if (ret) {
2392 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
2393 return ret;
2394 }
2395
2396 eth_hw_addr_set(netdev, mac_addr->sa_data);
2397
2398 return 0;
2399 }
2400
hns3_nic_do_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)2401 static int hns3_nic_do_ioctl(struct net_device *netdev,
2402 struct ifreq *ifr, int cmd)
2403 {
2404 struct hnae3_handle *h = hns3_get_handle(netdev);
2405
2406 if (!netif_running(netdev))
2407 return -EINVAL;
2408
2409 if (!h->ae_algo->ops->do_ioctl)
2410 return -EOPNOTSUPP;
2411
2412 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
2413 }
2414
hns3_nic_set_features(struct net_device * netdev,netdev_features_t features)2415 static int hns3_nic_set_features(struct net_device *netdev,
2416 netdev_features_t features)
2417 {
2418 netdev_features_t changed = netdev->features ^ features;
2419 struct hns3_nic_priv *priv = netdev_priv(netdev);
2420 struct hnae3_handle *h = priv->ae_handle;
2421 bool enable;
2422 int ret;
2423
2424 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
2425 enable = !!(features & NETIF_F_GRO_HW);
2426 ret = h->ae_algo->ops->set_gro_en(h, enable);
2427 if (ret)
2428 return ret;
2429 }
2430
2431 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
2432 h->ae_algo->ops->enable_hw_strip_rxvtag) {
2433 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
2434 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
2435 if (ret)
2436 return ret;
2437 }
2438
2439 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
2440 enable = !!(features & NETIF_F_NTUPLE);
2441 h->ae_algo->ops->enable_fd(h, enable);
2442 }
2443
2444 if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) &&
2445 h->ae_algo->ops->cls_flower_active(h)) {
2446 netdev_err(netdev,
2447 "there are offloaded TC filters active, cannot disable HW TC offload");
2448 return -EINVAL;
2449 }
2450
2451 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
2452 h->ae_algo->ops->enable_vlan_filter) {
2453 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
2454 ret = h->ae_algo->ops->enable_vlan_filter(h, enable);
2455 if (ret)
2456 return ret;
2457 }
2458
2459 netdev->features = features;
2460 return 0;
2461 }
2462
hns3_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)2463 static netdev_features_t hns3_features_check(struct sk_buff *skb,
2464 struct net_device *dev,
2465 netdev_features_t features)
2466 {
2467 #define HNS3_MAX_HDR_LEN 480U
2468 #define HNS3_MAX_L4_HDR_LEN 60U
2469
2470 size_t len;
2471
2472 if (skb->ip_summed != CHECKSUM_PARTIAL)
2473 return features;
2474
2475 if (skb->encapsulation)
2476 len = skb_inner_transport_header(skb) - skb->data;
2477 else
2478 len = skb_transport_header(skb) - skb->data;
2479
2480 /* Assume L4 is 60 byte as TCP is the only protocol with a
2481 * a flexible value, and it's max len is 60 bytes.
2482 */
2483 len += HNS3_MAX_L4_HDR_LEN;
2484
2485 /* Hardware only supports checksum on the skb with a max header
2486 * len of 480 bytes.
2487 */
2488 if (len > HNS3_MAX_HDR_LEN)
2489 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2490
2491 return features;
2492 }
2493
hns3_fetch_stats(struct rtnl_link_stats64 * stats,struct hns3_enet_ring * ring,bool is_tx)2494 static void hns3_fetch_stats(struct rtnl_link_stats64 *stats,
2495 struct hns3_enet_ring *ring, bool is_tx)
2496 {
2497 unsigned int start;
2498
2499 do {
2500 start = u64_stats_fetch_begin(&ring->syncp);
2501 if (is_tx) {
2502 stats->tx_bytes += ring->stats.tx_bytes;
2503 stats->tx_packets += ring->stats.tx_pkts;
2504 stats->tx_dropped += ring->stats.sw_err_cnt;
2505 stats->tx_dropped += ring->stats.tx_vlan_err;
2506 stats->tx_dropped += ring->stats.tx_l4_proto_err;
2507 stats->tx_dropped += ring->stats.tx_l2l3l4_err;
2508 stats->tx_dropped += ring->stats.tx_tso_err;
2509 stats->tx_dropped += ring->stats.over_max_recursion;
2510 stats->tx_dropped += ring->stats.hw_limitation;
2511 stats->tx_dropped += ring->stats.copy_bits_err;
2512 stats->tx_dropped += ring->stats.skb2sgl_err;
2513 stats->tx_dropped += ring->stats.map_sg_err;
2514 stats->tx_errors += ring->stats.sw_err_cnt;
2515 stats->tx_errors += ring->stats.tx_vlan_err;
2516 stats->tx_errors += ring->stats.tx_l4_proto_err;
2517 stats->tx_errors += ring->stats.tx_l2l3l4_err;
2518 stats->tx_errors += ring->stats.tx_tso_err;
2519 stats->tx_errors += ring->stats.over_max_recursion;
2520 stats->tx_errors += ring->stats.hw_limitation;
2521 stats->tx_errors += ring->stats.copy_bits_err;
2522 stats->tx_errors += ring->stats.skb2sgl_err;
2523 stats->tx_errors += ring->stats.map_sg_err;
2524 } else {
2525 stats->rx_bytes += ring->stats.rx_bytes;
2526 stats->rx_packets += ring->stats.rx_pkts;
2527 stats->rx_dropped += ring->stats.l2_err;
2528 stats->rx_errors += ring->stats.l2_err;
2529 stats->rx_errors += ring->stats.l3l4_csum_err;
2530 stats->rx_crc_errors += ring->stats.l2_err;
2531 stats->multicast += ring->stats.rx_multicast;
2532 stats->rx_length_errors += ring->stats.err_pkt_len;
2533 }
2534 } while (u64_stats_fetch_retry(&ring->syncp, start));
2535 }
2536
hns3_nic_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)2537 static void hns3_nic_get_stats64(struct net_device *netdev,
2538 struct rtnl_link_stats64 *stats)
2539 {
2540 struct hns3_nic_priv *priv = netdev_priv(netdev);
2541 int queue_num = priv->ae_handle->kinfo.num_tqps;
2542 struct hnae3_handle *handle = priv->ae_handle;
2543 struct rtnl_link_stats64 ring_total_stats;
2544 struct hns3_enet_ring *ring;
2545 unsigned int idx;
2546
2547 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
2548 return;
2549
2550 handle->ae_algo->ops->update_stats(handle);
2551
2552 memset(&ring_total_stats, 0, sizeof(ring_total_stats));
2553 for (idx = 0; idx < queue_num; idx++) {
2554 /* fetch the tx stats */
2555 ring = &priv->ring[idx];
2556 hns3_fetch_stats(&ring_total_stats, ring, true);
2557
2558 /* fetch the rx stats */
2559 ring = &priv->ring[idx + queue_num];
2560 hns3_fetch_stats(&ring_total_stats, ring, false);
2561 }
2562
2563 stats->tx_bytes = ring_total_stats.tx_bytes;
2564 stats->tx_packets = ring_total_stats.tx_packets;
2565 stats->rx_bytes = ring_total_stats.rx_bytes;
2566 stats->rx_packets = ring_total_stats.rx_packets;
2567
2568 stats->rx_errors = ring_total_stats.rx_errors;
2569 stats->multicast = ring_total_stats.multicast;
2570 stats->rx_length_errors = ring_total_stats.rx_length_errors;
2571 stats->rx_crc_errors = ring_total_stats.rx_crc_errors;
2572 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
2573
2574 stats->tx_errors = ring_total_stats.tx_errors;
2575 stats->rx_dropped = ring_total_stats.rx_dropped;
2576 stats->tx_dropped = ring_total_stats.tx_dropped;
2577 stats->collisions = netdev->stats.collisions;
2578 stats->rx_over_errors = netdev->stats.rx_over_errors;
2579 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
2580 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
2581 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
2582 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
2583 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
2584 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
2585 stats->tx_window_errors = netdev->stats.tx_window_errors;
2586 stats->rx_compressed = netdev->stats.rx_compressed;
2587 stats->tx_compressed = netdev->stats.tx_compressed;
2588 }
2589
hns3_setup_tc(struct net_device * netdev,void * type_data)2590 static int hns3_setup_tc(struct net_device *netdev, void *type_data)
2591 {
2592 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
2593 struct hnae3_knic_private_info *kinfo;
2594 u8 tc = mqprio_qopt->qopt.num_tc;
2595 u16 mode = mqprio_qopt->mode;
2596 u8 hw = mqprio_qopt->qopt.hw;
2597 struct hnae3_handle *h;
2598
2599 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
2600 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
2601 return -EOPNOTSUPP;
2602
2603 if (tc > HNAE3_MAX_TC)
2604 return -EINVAL;
2605
2606 if (!netdev)
2607 return -EINVAL;
2608
2609 h = hns3_get_handle(netdev);
2610 kinfo = &h->kinfo;
2611
2612 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
2613
2614 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
2615 kinfo->dcb_ops->setup_tc(h, mqprio_qopt) : -EOPNOTSUPP;
2616 }
2617
hns3_setup_tc_cls_flower(struct hns3_nic_priv * priv,struct flow_cls_offload * flow)2618 static int hns3_setup_tc_cls_flower(struct hns3_nic_priv *priv,
2619 struct flow_cls_offload *flow)
2620 {
2621 int tc = tc_classid_to_hwtc(priv->netdev, flow->classid);
2622 struct hnae3_handle *h = hns3_get_handle(priv->netdev);
2623
2624 switch (flow->command) {
2625 case FLOW_CLS_REPLACE:
2626 if (h->ae_algo->ops->add_cls_flower)
2627 return h->ae_algo->ops->add_cls_flower(h, flow, tc);
2628 break;
2629 case FLOW_CLS_DESTROY:
2630 if (h->ae_algo->ops->del_cls_flower)
2631 return h->ae_algo->ops->del_cls_flower(h, flow);
2632 break;
2633 default:
2634 break;
2635 }
2636
2637 return -EOPNOTSUPP;
2638 }
2639
hns3_setup_tc_block_cb(enum tc_setup_type type,void * type_data,void * cb_priv)2640 static int hns3_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2641 void *cb_priv)
2642 {
2643 struct hns3_nic_priv *priv = cb_priv;
2644
2645 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
2646 return -EOPNOTSUPP;
2647
2648 switch (type) {
2649 case TC_SETUP_CLSFLOWER:
2650 return hns3_setup_tc_cls_flower(priv, type_data);
2651 default:
2652 return -EOPNOTSUPP;
2653 }
2654 }
2655
2656 static LIST_HEAD(hns3_block_cb_list);
2657
hns3_nic_setup_tc(struct net_device * dev,enum tc_setup_type type,void * type_data)2658 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
2659 void *type_data)
2660 {
2661 struct hns3_nic_priv *priv = netdev_priv(dev);
2662 int ret;
2663
2664 switch (type) {
2665 case TC_SETUP_QDISC_MQPRIO:
2666 ret = hns3_setup_tc(dev, type_data);
2667 break;
2668 case TC_SETUP_BLOCK:
2669 ret = flow_block_cb_setup_simple(type_data,
2670 &hns3_block_cb_list,
2671 hns3_setup_tc_block_cb,
2672 priv, priv, true);
2673 break;
2674 default:
2675 return -EOPNOTSUPP;
2676 }
2677
2678 return ret;
2679 }
2680
hns3_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)2681 static int hns3_vlan_rx_add_vid(struct net_device *netdev,
2682 __be16 proto, u16 vid)
2683 {
2684 struct hnae3_handle *h = hns3_get_handle(netdev);
2685 int ret = -EIO;
2686
2687 if (h->ae_algo->ops->set_vlan_filter)
2688 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
2689
2690 return ret;
2691 }
2692
hns3_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)2693 static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
2694 __be16 proto, u16 vid)
2695 {
2696 struct hnae3_handle *h = hns3_get_handle(netdev);
2697 int ret = -EIO;
2698
2699 if (h->ae_algo->ops->set_vlan_filter)
2700 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
2701
2702 return ret;
2703 }
2704
hns3_ndo_set_vf_vlan(struct net_device * netdev,int vf,u16 vlan,u8 qos,__be16 vlan_proto)2705 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
2706 u8 qos, __be16 vlan_proto)
2707 {
2708 struct hnae3_handle *h = hns3_get_handle(netdev);
2709 int ret = -EIO;
2710
2711 netif_dbg(h, drv, netdev,
2712 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
2713 vf, vlan, qos, ntohs(vlan_proto));
2714
2715 if (h->ae_algo->ops->set_vf_vlan_filter)
2716 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
2717 qos, vlan_proto);
2718
2719 return ret;
2720 }
2721
hns3_set_vf_spoofchk(struct net_device * netdev,int vf,bool enable)2722 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
2723 {
2724 struct hnae3_handle *handle = hns3_get_handle(netdev);
2725
2726 if (hns3_nic_resetting(netdev))
2727 return -EBUSY;
2728
2729 if (!handle->ae_algo->ops->set_vf_spoofchk)
2730 return -EOPNOTSUPP;
2731
2732 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
2733 }
2734
hns3_set_vf_trust(struct net_device * netdev,int vf,bool enable)2735 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
2736 {
2737 struct hnae3_handle *handle = hns3_get_handle(netdev);
2738
2739 if (!handle->ae_algo->ops->set_vf_trust)
2740 return -EOPNOTSUPP;
2741
2742 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
2743 }
2744
hns3_nic_change_mtu(struct net_device * netdev,int new_mtu)2745 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
2746 {
2747 struct hnae3_handle *h = hns3_get_handle(netdev);
2748 int ret;
2749
2750 if (hns3_nic_resetting(netdev))
2751 return -EBUSY;
2752
2753 if (!h->ae_algo->ops->set_mtu)
2754 return -EOPNOTSUPP;
2755
2756 netif_dbg(h, drv, netdev,
2757 "change mtu from %u to %d\n", netdev->mtu, new_mtu);
2758
2759 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
2760 if (ret)
2761 netdev_err(netdev, "failed to change MTU in hardware %d\n",
2762 ret);
2763 else
2764 netdev->mtu = new_mtu;
2765
2766 return ret;
2767 }
2768
hns3_get_timeout_queue(struct net_device * ndev)2769 static int hns3_get_timeout_queue(struct net_device *ndev)
2770 {
2771 int i;
2772
2773 /* Find the stopped queue the same way the stack does */
2774 for (i = 0; i < ndev->num_tx_queues; i++) {
2775 struct netdev_queue *q;
2776 unsigned long trans_start;
2777
2778 q = netdev_get_tx_queue(ndev, i);
2779 trans_start = READ_ONCE(q->trans_start);
2780 if (netif_xmit_stopped(q) &&
2781 time_after(jiffies,
2782 (trans_start + ndev->watchdog_timeo))) {
2783 #ifdef CONFIG_BQL
2784 struct dql *dql = &q->dql;
2785
2786 netdev_info(ndev, "DQL info last_cnt: %u, queued: %u, adj_limit: %u, completed: %u\n",
2787 dql->last_obj_cnt, dql->num_queued,
2788 dql->adj_limit, dql->num_completed);
2789 #endif
2790 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
2791 q->state,
2792 jiffies_to_msecs(jiffies - trans_start));
2793 break;
2794 }
2795 }
2796
2797 return i;
2798 }
2799
hns3_dump_queue_stats(struct net_device * ndev,struct hns3_enet_ring * tx_ring,int timeout_queue)2800 static void hns3_dump_queue_stats(struct net_device *ndev,
2801 struct hns3_enet_ring *tx_ring,
2802 int timeout_queue)
2803 {
2804 struct napi_struct *napi = &tx_ring->tqp_vector->napi;
2805 struct hns3_nic_priv *priv = netdev_priv(ndev);
2806
2807 netdev_info(ndev,
2808 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
2809 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
2810 tx_ring->next_to_clean, napi->state);
2811
2812 netdev_info(ndev,
2813 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n",
2814 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
2815 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf);
2816
2817 netdev_info(ndev,
2818 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n",
2819 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more,
2820 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
2821
2822 netdev_info(ndev, "tx_push: %llu, tx_mem_doorbell: %llu\n",
2823 tx_ring->stats.tx_push, tx_ring->stats.tx_mem_doorbell);
2824 }
2825
hns3_dump_queue_reg(struct net_device * ndev,struct hns3_enet_ring * tx_ring)2826 static void hns3_dump_queue_reg(struct net_device *ndev,
2827 struct hns3_enet_ring *tx_ring)
2828 {
2829 netdev_info(ndev,
2830 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
2831 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_NUM_REG),
2832 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_HEAD_REG),
2833 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TAIL_REG),
2834 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_ERR_REG),
2835 readl(tx_ring->tqp_vector->mask_addr));
2836 netdev_info(ndev,
2837 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
2838 hns3_tqp_read_reg(tx_ring, HNS3_RING_EN_REG),
2839 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TC_REG),
2840 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_FBDNUM_REG),
2841 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_OFFSET_REG),
2842 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_EBDNUM_REG),
2843 hns3_tqp_read_reg(tx_ring,
2844 HNS3_RING_TX_RING_EBD_OFFSET_REG));
2845 }
2846
hns3_get_tx_timeo_queue_info(struct net_device * ndev)2847 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
2848 {
2849 struct hns3_nic_priv *priv = netdev_priv(ndev);
2850 struct hnae3_handle *h = hns3_get_handle(ndev);
2851 struct hns3_enet_ring *tx_ring;
2852 int timeout_queue;
2853
2854 timeout_queue = hns3_get_timeout_queue(ndev);
2855 if (timeout_queue >= ndev->num_tx_queues) {
2856 netdev_info(ndev,
2857 "no netdev TX timeout queue found, timeout count: %llu\n",
2858 priv->tx_timeout_count);
2859 return false;
2860 }
2861
2862 priv->tx_timeout_count++;
2863
2864 tx_ring = &priv->ring[timeout_queue];
2865 hns3_dump_queue_stats(ndev, tx_ring, timeout_queue);
2866
2867 /* When mac received many pause frames continuous, it's unable to send
2868 * packets, which may cause tx timeout
2869 */
2870 if (h->ae_algo->ops->get_mac_stats) {
2871 struct hns3_mac_stats mac_stats;
2872
2873 h->ae_algo->ops->get_mac_stats(h, &mac_stats);
2874 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
2875 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
2876 }
2877
2878 hns3_dump_queue_reg(ndev, tx_ring);
2879
2880 return true;
2881 }
2882
hns3_nic_net_timeout(struct net_device * ndev,unsigned int txqueue)2883 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue)
2884 {
2885 struct hns3_nic_priv *priv = netdev_priv(ndev);
2886 struct hnae3_handle *h = priv->ae_handle;
2887
2888 if (!hns3_get_tx_timeo_queue_info(ndev))
2889 return;
2890
2891 /* request the reset, and let the hclge to determine
2892 * which reset level should be done
2893 */
2894 if (h->ae_algo->ops->reset_event)
2895 h->ae_algo->ops->reset_event(h->pdev, h);
2896 }
2897
2898 #ifdef CONFIG_RFS_ACCEL
hns3_rx_flow_steer(struct net_device * dev,const struct sk_buff * skb,u16 rxq_index,u32 flow_id)2899 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
2900 u16 rxq_index, u32 flow_id)
2901 {
2902 struct hnae3_handle *h = hns3_get_handle(dev);
2903 struct flow_keys fkeys;
2904
2905 if (!h->ae_algo->ops->add_arfs_entry)
2906 return -EOPNOTSUPP;
2907
2908 if (skb->encapsulation)
2909 return -EPROTONOSUPPORT;
2910
2911 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
2912 return -EPROTONOSUPPORT;
2913
2914 if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
2915 fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
2916 (fkeys.basic.ip_proto != IPPROTO_TCP &&
2917 fkeys.basic.ip_proto != IPPROTO_UDP))
2918 return -EPROTONOSUPPORT;
2919
2920 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
2921 }
2922 #endif
2923
hns3_nic_get_vf_config(struct net_device * ndev,int vf,struct ifla_vf_info * ivf)2924 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
2925 struct ifla_vf_info *ivf)
2926 {
2927 struct hnae3_handle *h = hns3_get_handle(ndev);
2928
2929 if (!h->ae_algo->ops->get_vf_config)
2930 return -EOPNOTSUPP;
2931
2932 return h->ae_algo->ops->get_vf_config(h, vf, ivf);
2933 }
2934
hns3_nic_set_vf_link_state(struct net_device * ndev,int vf,int link_state)2935 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
2936 int link_state)
2937 {
2938 struct hnae3_handle *h = hns3_get_handle(ndev);
2939
2940 if (!h->ae_algo->ops->set_vf_link_state)
2941 return -EOPNOTSUPP;
2942
2943 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
2944 }
2945
hns3_nic_set_vf_rate(struct net_device * ndev,int vf,int min_tx_rate,int max_tx_rate)2946 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
2947 int min_tx_rate, int max_tx_rate)
2948 {
2949 struct hnae3_handle *h = hns3_get_handle(ndev);
2950
2951 if (!h->ae_algo->ops->set_vf_rate)
2952 return -EOPNOTSUPP;
2953
2954 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
2955 false);
2956 }
2957
hns3_nic_set_vf_mac(struct net_device * netdev,int vf_id,u8 * mac)2958 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
2959 {
2960 struct hnae3_handle *h = hns3_get_handle(netdev);
2961 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
2962
2963 if (!h->ae_algo->ops->set_vf_mac)
2964 return -EOPNOTSUPP;
2965
2966 if (is_multicast_ether_addr(mac)) {
2967 hnae3_format_mac_addr(format_mac_addr, mac);
2968 netdev_err(netdev,
2969 "Invalid MAC:%s specified. Could not set MAC\n",
2970 format_mac_addr);
2971 return -EINVAL;
2972 }
2973
2974 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
2975 }
2976
2977 #define HNS3_INVALID_DSCP 0xff
2978 #define HNS3_DSCP_SHIFT 2
2979
hns3_get_skb_dscp(struct sk_buff * skb)2980 static u8 hns3_get_skb_dscp(struct sk_buff *skb)
2981 {
2982 __be16 protocol = skb->protocol;
2983 u8 dscp = HNS3_INVALID_DSCP;
2984
2985 if (protocol == htons(ETH_P_8021Q))
2986 protocol = vlan_get_protocol(skb);
2987
2988 if (protocol == htons(ETH_P_IP))
2989 dscp = ipv4_get_dsfield(ip_hdr(skb)) >> HNS3_DSCP_SHIFT;
2990 else if (protocol == htons(ETH_P_IPV6))
2991 dscp = ipv6_get_dsfield(ipv6_hdr(skb)) >> HNS3_DSCP_SHIFT;
2992
2993 return dscp;
2994 }
2995
hns3_nic_select_queue(struct net_device * netdev,struct sk_buff * skb,struct net_device * sb_dev)2996 static u16 hns3_nic_select_queue(struct net_device *netdev,
2997 struct sk_buff *skb,
2998 struct net_device *sb_dev)
2999 {
3000 struct hnae3_handle *h = hns3_get_handle(netdev);
3001 u8 dscp;
3002
3003 if (h->kinfo.tc_map_mode != HNAE3_TC_MAP_MODE_DSCP ||
3004 !h->ae_algo->ops->get_dscp_prio)
3005 goto out;
3006
3007 dscp = hns3_get_skb_dscp(skb);
3008 if (unlikely(dscp >= HNAE3_MAX_DSCP))
3009 goto out;
3010
3011 skb->priority = h->kinfo.dscp_prio[dscp];
3012 if (skb->priority == HNAE3_PRIO_ID_INVALID)
3013 skb->priority = 0;
3014
3015 out:
3016 return netdev_pick_tx(netdev, skb, sb_dev);
3017 }
3018
3019 static const struct net_device_ops hns3_nic_netdev_ops = {
3020 .ndo_open = hns3_nic_net_open,
3021 .ndo_stop = hns3_nic_net_stop,
3022 .ndo_start_xmit = hns3_nic_net_xmit,
3023 .ndo_tx_timeout = hns3_nic_net_timeout,
3024 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
3025 .ndo_eth_ioctl = hns3_nic_do_ioctl,
3026 .ndo_change_mtu = hns3_nic_change_mtu,
3027 .ndo_set_features = hns3_nic_set_features,
3028 .ndo_features_check = hns3_features_check,
3029 .ndo_get_stats64 = hns3_nic_get_stats64,
3030 .ndo_setup_tc = hns3_nic_setup_tc,
3031 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
3032 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
3033 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
3034 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
3035 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk,
3036 .ndo_set_vf_trust = hns3_set_vf_trust,
3037 #ifdef CONFIG_RFS_ACCEL
3038 .ndo_rx_flow_steer = hns3_rx_flow_steer,
3039 #endif
3040 .ndo_get_vf_config = hns3_nic_get_vf_config,
3041 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state,
3042 .ndo_set_vf_rate = hns3_nic_set_vf_rate,
3043 .ndo_set_vf_mac = hns3_nic_set_vf_mac,
3044 .ndo_select_queue = hns3_nic_select_queue,
3045 };
3046
hns3_is_phys_func(struct pci_dev * pdev)3047 bool hns3_is_phys_func(struct pci_dev *pdev)
3048 {
3049 u32 dev_id = pdev->device;
3050
3051 switch (dev_id) {
3052 case HNAE3_DEV_ID_GE:
3053 case HNAE3_DEV_ID_25GE:
3054 case HNAE3_DEV_ID_25GE_RDMA:
3055 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
3056 case HNAE3_DEV_ID_50GE_RDMA:
3057 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
3058 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
3059 case HNAE3_DEV_ID_200G_RDMA:
3060 return true;
3061 case HNAE3_DEV_ID_VF:
3062 case HNAE3_DEV_ID_RDMA_DCB_PFC_VF:
3063 return false;
3064 default:
3065 dev_warn(&pdev->dev, "un-recognized pci device-id %u",
3066 dev_id);
3067 }
3068
3069 return false;
3070 }
3071
hns3_disable_sriov(struct pci_dev * pdev)3072 static void hns3_disable_sriov(struct pci_dev *pdev)
3073 {
3074 /* If our VFs are assigned we cannot shut down SR-IOV
3075 * without causing issues, so just leave the hardware
3076 * available but disabled
3077 */
3078 if (pci_vfs_assigned(pdev)) {
3079 dev_warn(&pdev->dev,
3080 "disabling driver while VFs are assigned\n");
3081 return;
3082 }
3083
3084 pci_disable_sriov(pdev);
3085 }
3086
3087 /* hns3_probe - Device initialization routine
3088 * @pdev: PCI device information struct
3089 * @ent: entry in hns3_pci_tbl
3090 *
3091 * hns3_probe initializes a PF identified by a pci_dev structure.
3092 * The OS initialization, configuring of the PF private structure,
3093 * and a hardware reset occur.
3094 *
3095 * Returns 0 on success, negative on failure
3096 */
hns3_probe(struct pci_dev * pdev,const struct pci_device_id * ent)3097 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3098 {
3099 struct hnae3_ae_dev *ae_dev;
3100 int ret;
3101
3102 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
3103 if (!ae_dev)
3104 return -ENOMEM;
3105
3106 ae_dev->pdev = pdev;
3107 ae_dev->flag = ent->driver_data;
3108 pci_set_drvdata(pdev, ae_dev);
3109
3110 ret = hnae3_register_ae_dev(ae_dev);
3111 if (ret)
3112 pci_set_drvdata(pdev, NULL);
3113
3114 return ret;
3115 }
3116
3117 /**
3118 * hns3_clean_vf_config
3119 * @pdev: pointer to a pci_dev structure
3120 * @num_vfs: number of VFs allocated
3121 *
3122 * Clean residual vf config after disable sriov
3123 **/
hns3_clean_vf_config(struct pci_dev * pdev,int num_vfs)3124 static void hns3_clean_vf_config(struct pci_dev *pdev, int num_vfs)
3125 {
3126 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3127
3128 if (ae_dev->ops->clean_vf_config)
3129 ae_dev->ops->clean_vf_config(ae_dev, num_vfs);
3130 }
3131
3132 /* hns3_remove - Device removal routine
3133 * @pdev: PCI device information struct
3134 */
hns3_remove(struct pci_dev * pdev)3135 static void hns3_remove(struct pci_dev *pdev)
3136 {
3137 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3138
3139 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
3140 hns3_disable_sriov(pdev);
3141
3142 hnae3_unregister_ae_dev(ae_dev);
3143 pci_set_drvdata(pdev, NULL);
3144 }
3145
3146 /**
3147 * hns3_pci_sriov_configure
3148 * @pdev: pointer to a pci_dev structure
3149 * @num_vfs: number of VFs to allocate
3150 *
3151 * Enable or change the number of VFs. Called when the user updates the number
3152 * of VFs in sysfs.
3153 **/
hns3_pci_sriov_configure(struct pci_dev * pdev,int num_vfs)3154 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
3155 {
3156 int ret;
3157
3158 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
3159 dev_warn(&pdev->dev, "Can not config SRIOV\n");
3160 return -EINVAL;
3161 }
3162
3163 if (num_vfs) {
3164 ret = pci_enable_sriov(pdev, num_vfs);
3165 if (ret)
3166 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
3167 else
3168 return num_vfs;
3169 } else if (!pci_vfs_assigned(pdev)) {
3170 int num_vfs_pre = pci_num_vf(pdev);
3171
3172 pci_disable_sriov(pdev);
3173 hns3_clean_vf_config(pdev, num_vfs_pre);
3174 } else {
3175 dev_warn(&pdev->dev,
3176 "Unable to free VFs because some are assigned to VMs.\n");
3177 }
3178
3179 return 0;
3180 }
3181
hns3_shutdown(struct pci_dev * pdev)3182 static void hns3_shutdown(struct pci_dev *pdev)
3183 {
3184 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3185
3186 hnae3_unregister_ae_dev(ae_dev);
3187 pci_set_drvdata(pdev, NULL);
3188
3189 if (system_state == SYSTEM_POWER_OFF)
3190 pci_set_power_state(pdev, PCI_D3hot);
3191 }
3192
hns3_suspend(struct device * dev)3193 static int __maybe_unused hns3_suspend(struct device *dev)
3194 {
3195 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3196
3197 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
3198 dev_info(dev, "Begin to suspend.\n");
3199 if (ae_dev->ops && ae_dev->ops->reset_prepare)
3200 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FUNC_RESET);
3201 }
3202
3203 return 0;
3204 }
3205
hns3_resume(struct device * dev)3206 static int __maybe_unused hns3_resume(struct device *dev)
3207 {
3208 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3209
3210 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
3211 dev_info(dev, "Begin to resume.\n");
3212 if (ae_dev->ops && ae_dev->ops->reset_done)
3213 ae_dev->ops->reset_done(ae_dev);
3214 }
3215
3216 return 0;
3217 }
3218
hns3_error_detected(struct pci_dev * pdev,pci_channel_state_t state)3219 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
3220 pci_channel_state_t state)
3221 {
3222 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3223 pci_ers_result_t ret;
3224
3225 dev_info(&pdev->dev, "PCI error detected, state(=%u)!!\n", state);
3226
3227 if (state == pci_channel_io_perm_failure)
3228 return PCI_ERS_RESULT_DISCONNECT;
3229
3230 if (!ae_dev || !ae_dev->ops) {
3231 dev_err(&pdev->dev,
3232 "Can't recover - error happened before device initialized\n");
3233 return PCI_ERS_RESULT_NONE;
3234 }
3235
3236 if (ae_dev->ops->handle_hw_ras_error)
3237 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
3238 else
3239 return PCI_ERS_RESULT_NONE;
3240
3241 return ret;
3242 }
3243
hns3_slot_reset(struct pci_dev * pdev)3244 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
3245 {
3246 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3247 const struct hnae3_ae_ops *ops;
3248 enum hnae3_reset_type reset_type;
3249 struct device *dev = &pdev->dev;
3250
3251 if (!ae_dev || !ae_dev->ops)
3252 return PCI_ERS_RESULT_NONE;
3253
3254 ops = ae_dev->ops;
3255 /* request the reset */
3256 if (ops->reset_event && ops->get_reset_level &&
3257 ops->set_default_reset_request) {
3258 if (ae_dev->hw_err_reset_req) {
3259 reset_type = ops->get_reset_level(ae_dev,
3260 &ae_dev->hw_err_reset_req);
3261 ops->set_default_reset_request(ae_dev, reset_type);
3262 dev_info(dev, "requesting reset due to PCI error\n");
3263 ops->reset_event(pdev, NULL);
3264 }
3265
3266 return PCI_ERS_RESULT_RECOVERED;
3267 }
3268
3269 return PCI_ERS_RESULT_DISCONNECT;
3270 }
3271
hns3_reset_prepare(struct pci_dev * pdev)3272 static void hns3_reset_prepare(struct pci_dev *pdev)
3273 {
3274 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3275
3276 dev_info(&pdev->dev, "FLR prepare\n");
3277 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_prepare)
3278 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FLR_RESET);
3279 }
3280
hns3_reset_done(struct pci_dev * pdev)3281 static void hns3_reset_done(struct pci_dev *pdev)
3282 {
3283 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3284
3285 dev_info(&pdev->dev, "FLR done\n");
3286 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_done)
3287 ae_dev->ops->reset_done(ae_dev);
3288 }
3289
3290 static const struct pci_error_handlers hns3_err_handler = {
3291 .error_detected = hns3_error_detected,
3292 .slot_reset = hns3_slot_reset,
3293 .reset_prepare = hns3_reset_prepare,
3294 .reset_done = hns3_reset_done,
3295 };
3296
3297 static SIMPLE_DEV_PM_OPS(hns3_pm_ops, hns3_suspend, hns3_resume);
3298
3299 static struct pci_driver hns3_driver = {
3300 .name = hns3_driver_name,
3301 .id_table = hns3_pci_tbl,
3302 .probe = hns3_probe,
3303 .remove = hns3_remove,
3304 .shutdown = hns3_shutdown,
3305 .driver.pm = &hns3_pm_ops,
3306 .sriov_configure = hns3_pci_sriov_configure,
3307 .err_handler = &hns3_err_handler,
3308 };
3309
3310 /* set default feature to hns3 */
hns3_set_default_feature(struct net_device * netdev)3311 static void hns3_set_default_feature(struct net_device *netdev)
3312 {
3313 struct hnae3_handle *h = hns3_get_handle(netdev);
3314 struct pci_dev *pdev = h->pdev;
3315 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3316
3317 netdev->priv_flags |= IFF_UNICAST_FLT;
3318
3319 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
3320 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
3321 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
3322 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
3323 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
3324 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST;
3325
3326 if (hnae3_ae_dev_gro_supported(ae_dev))
3327 netdev->features |= NETIF_F_GRO_HW;
3328
3329 if (hnae3_ae_dev_fd_supported(ae_dev))
3330 netdev->features |= NETIF_F_NTUPLE;
3331
3332 if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps))
3333 netdev->features |= NETIF_F_GSO_UDP_L4;
3334
3335 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
3336 netdev->features |= NETIF_F_HW_CSUM;
3337 else
3338 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
3339
3340 if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps))
3341 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
3342
3343 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps))
3344 netdev->features |= NETIF_F_HW_TC;
3345
3346 netdev->hw_features |= netdev->features;
3347 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
3348 netdev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
3349
3350 netdev->vlan_features |= netdev->features &
3351 ~(NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX |
3352 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_GRO_HW | NETIF_F_NTUPLE |
3353 NETIF_F_HW_TC);
3354
3355 netdev->hw_enc_features |= netdev->vlan_features | NETIF_F_TSO_MANGLEID;
3356
3357 /* The device_version V3 hardware can't offload the checksum for IP in
3358 * GRE packets, but can do it for NvGRE. So default to disable the
3359 * checksum and GSO offload for GRE.
3360 */
3361 if (ae_dev->dev_version > HNAE3_DEVICE_VERSION_V2) {
3362 netdev->features &= ~NETIF_F_GSO_GRE;
3363 netdev->features &= ~NETIF_F_GSO_GRE_CSUM;
3364 }
3365 }
3366
hns3_alloc_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3367 static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
3368 struct hns3_desc_cb *cb)
3369 {
3370 unsigned int order = hns3_page_order(ring);
3371 struct page *p;
3372
3373 if (ring->page_pool) {
3374 p = page_pool_dev_alloc_frag(ring->page_pool,
3375 &cb->page_offset,
3376 hns3_buf_size(ring));
3377 if (unlikely(!p))
3378 return -ENOMEM;
3379
3380 cb->priv = p;
3381 cb->buf = page_address(p);
3382 cb->dma = page_pool_get_dma_addr(p);
3383 cb->type = DESC_TYPE_PP_FRAG;
3384 cb->reuse_flag = 0;
3385 return 0;
3386 }
3387
3388 p = dev_alloc_pages(order);
3389 if (!p)
3390 return -ENOMEM;
3391
3392 cb->priv = p;
3393 cb->page_offset = 0;
3394 cb->reuse_flag = 0;
3395 cb->buf = page_address(p);
3396 cb->length = hns3_page_size(ring);
3397 cb->type = DESC_TYPE_PAGE;
3398 page_ref_add(p, USHRT_MAX - 1);
3399 cb->pagecnt_bias = USHRT_MAX;
3400
3401 return 0;
3402 }
3403
hns3_free_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb,int budget)3404 static void hns3_free_buffer(struct hns3_enet_ring *ring,
3405 struct hns3_desc_cb *cb, int budget)
3406 {
3407 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_HEAD |
3408 DESC_TYPE_BOUNCE_ALL | DESC_TYPE_SGL_SKB))
3409 napi_consume_skb(cb->priv, budget);
3410 else if (!HNAE3_IS_TX_RING(ring)) {
3411 if (cb->type & DESC_TYPE_PAGE && cb->pagecnt_bias)
3412 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias);
3413 else if (cb->type & DESC_TYPE_PP_FRAG)
3414 page_pool_put_full_page(ring->page_pool, cb->priv,
3415 false);
3416 }
3417 memset(cb, 0, sizeof(*cb));
3418 }
3419
hns3_map_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3420 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
3421 {
3422 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
3423 cb->length, ring_to_dma_dir(ring));
3424
3425 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
3426 return -EIO;
3427
3428 return 0;
3429 }
3430
hns3_unmap_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3431 static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
3432 struct hns3_desc_cb *cb)
3433 {
3434 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
3435 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
3436 ring_to_dma_dir(ring));
3437 else if ((cb->type & DESC_TYPE_PAGE) && cb->length)
3438 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
3439 ring_to_dma_dir(ring));
3440 else if (cb->type & (DESC_TYPE_BOUNCE_ALL | DESC_TYPE_BOUNCE_HEAD |
3441 DESC_TYPE_SGL_SKB))
3442 hns3_tx_spare_reclaim_cb(ring, cb);
3443 }
3444
hns3_buffer_detach(struct hns3_enet_ring * ring,int i)3445 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
3446 {
3447 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3448 ring->desc[i].addr = 0;
3449 ring->desc_cb[i].refill = 0;
3450 }
3451
hns3_free_buffer_detach(struct hns3_enet_ring * ring,int i,int budget)3452 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i,
3453 int budget)
3454 {
3455 struct hns3_desc_cb *cb = &ring->desc_cb[i];
3456
3457 if (!ring->desc_cb[i].dma)
3458 return;
3459
3460 hns3_buffer_detach(ring, i);
3461 hns3_free_buffer(ring, cb, budget);
3462 }
3463
hns3_free_buffers(struct hns3_enet_ring * ring)3464 static void hns3_free_buffers(struct hns3_enet_ring *ring)
3465 {
3466 int i;
3467
3468 for (i = 0; i < ring->desc_num; i++)
3469 hns3_free_buffer_detach(ring, i, 0);
3470 }
3471
3472 /* free desc along with its attached buffer */
hns3_free_desc(struct hns3_enet_ring * ring)3473 static void hns3_free_desc(struct hns3_enet_ring *ring)
3474 {
3475 int size = ring->desc_num * sizeof(ring->desc[0]);
3476
3477 hns3_free_buffers(ring);
3478
3479 if (ring->desc) {
3480 dma_free_coherent(ring_to_dev(ring), size,
3481 ring->desc, ring->desc_dma_addr);
3482 ring->desc = NULL;
3483 }
3484 }
3485
hns3_alloc_desc(struct hns3_enet_ring * ring)3486 static int hns3_alloc_desc(struct hns3_enet_ring *ring)
3487 {
3488 int size = ring->desc_num * sizeof(ring->desc[0]);
3489
3490 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
3491 &ring->desc_dma_addr, GFP_KERNEL);
3492 if (!ring->desc)
3493 return -ENOMEM;
3494
3495 return 0;
3496 }
3497
hns3_alloc_and_map_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3498 static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring,
3499 struct hns3_desc_cb *cb)
3500 {
3501 int ret;
3502
3503 ret = hns3_alloc_buffer(ring, cb);
3504 if (ret || ring->page_pool)
3505 goto out;
3506
3507 ret = hns3_map_buffer(ring, cb);
3508 if (ret)
3509 goto out_with_buf;
3510
3511 return 0;
3512
3513 out_with_buf:
3514 hns3_free_buffer(ring, cb, 0);
3515 out:
3516 return ret;
3517 }
3518
hns3_alloc_and_attach_buffer(struct hns3_enet_ring * ring,int i)3519 static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i)
3520 {
3521 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]);
3522
3523 if (ret)
3524 return ret;
3525
3526 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3527 ring->desc_cb[i].page_offset);
3528 ring->desc_cb[i].refill = 1;
3529
3530 return 0;
3531 }
3532
3533 /* Allocate memory for raw pkg, and map with dma */
hns3_alloc_ring_buffers(struct hns3_enet_ring * ring)3534 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
3535 {
3536 int i, j, ret;
3537
3538 for (i = 0; i < ring->desc_num; i++) {
3539 ret = hns3_alloc_and_attach_buffer(ring, i);
3540 if (ret)
3541 goto out_buffer_fail;
3542 }
3543
3544 return 0;
3545
3546 out_buffer_fail:
3547 for (j = i - 1; j >= 0; j--)
3548 hns3_free_buffer_detach(ring, j, 0);
3549 return ret;
3550 }
3551
3552 /* detach a in-used buffer and replace with a reserved one */
hns3_replace_buffer(struct hns3_enet_ring * ring,int i,struct hns3_desc_cb * res_cb)3553 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
3554 struct hns3_desc_cb *res_cb)
3555 {
3556 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3557 ring->desc_cb[i] = *res_cb;
3558 ring->desc_cb[i].refill = 1;
3559 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3560 ring->desc_cb[i].page_offset);
3561 ring->desc[i].rx.bd_base_info = 0;
3562 }
3563
hns3_reuse_buffer(struct hns3_enet_ring * ring,int i)3564 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
3565 {
3566 ring->desc_cb[i].reuse_flag = 0;
3567 ring->desc_cb[i].refill = 1;
3568 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3569 ring->desc_cb[i].page_offset);
3570 ring->desc[i].rx.bd_base_info = 0;
3571
3572 dma_sync_single_for_device(ring_to_dev(ring),
3573 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset,
3574 hns3_buf_size(ring),
3575 DMA_FROM_DEVICE);
3576 }
3577
hns3_nic_reclaim_desc(struct hns3_enet_ring * ring,int * bytes,int * pkts,int budget)3578 static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring,
3579 int *bytes, int *pkts, int budget)
3580 {
3581 /* This smp_load_acquire() pairs with smp_store_release() in
3582 * hns3_tx_doorbell().
3583 */
3584 int ltu = smp_load_acquire(&ring->last_to_use);
3585 int ntc = ring->next_to_clean;
3586 struct hns3_desc_cb *desc_cb;
3587 bool reclaimed = false;
3588 struct hns3_desc *desc;
3589
3590 while (ltu != ntc) {
3591 desc = &ring->desc[ntc];
3592
3593 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) &
3594 BIT(HNS3_TXD_VLD_B))
3595 break;
3596
3597 desc_cb = &ring->desc_cb[ntc];
3598
3599 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_ALL |
3600 DESC_TYPE_BOUNCE_HEAD |
3601 DESC_TYPE_SGL_SKB)) {
3602 (*pkts)++;
3603 (*bytes) += desc_cb->send_bytes;
3604 }
3605
3606 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
3607 hns3_free_buffer_detach(ring, ntc, budget);
3608
3609 if (++ntc == ring->desc_num)
3610 ntc = 0;
3611
3612 /* Issue prefetch for next Tx descriptor */
3613 prefetch(&ring->desc_cb[ntc]);
3614 reclaimed = true;
3615 }
3616
3617 if (unlikely(!reclaimed))
3618 return false;
3619
3620 /* This smp_store_release() pairs with smp_load_acquire() in
3621 * ring_space called by hns3_nic_net_xmit.
3622 */
3623 smp_store_release(&ring->next_to_clean, ntc);
3624
3625 hns3_tx_spare_update(ring);
3626
3627 return true;
3628 }
3629
hns3_clean_tx_ring(struct hns3_enet_ring * ring,int budget)3630 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget)
3631 {
3632 struct net_device *netdev = ring_to_netdev(ring);
3633 struct hns3_nic_priv *priv = netdev_priv(netdev);
3634 struct netdev_queue *dev_queue;
3635 int bytes, pkts;
3636
3637 bytes = 0;
3638 pkts = 0;
3639
3640 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget)))
3641 return;
3642
3643 ring->tqp_vector->tx_group.total_bytes += bytes;
3644 ring->tqp_vector->tx_group.total_packets += pkts;
3645
3646 u64_stats_update_begin(&ring->syncp);
3647 ring->stats.tx_bytes += bytes;
3648 ring->stats.tx_pkts += pkts;
3649 u64_stats_update_end(&ring->syncp);
3650
3651 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
3652 netdev_tx_completed_queue(dev_queue, pkts, bytes);
3653
3654 if (unlikely(netif_carrier_ok(netdev) &&
3655 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
3656 /* Make sure that anybody stopping the queue after this
3657 * sees the new next_to_clean.
3658 */
3659 smp_mb();
3660 if (netif_tx_queue_stopped(dev_queue) &&
3661 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
3662 netif_tx_wake_queue(dev_queue);
3663 ring->stats.restart_queue++;
3664 }
3665 }
3666 }
3667
hns3_desc_unused(struct hns3_enet_ring * ring)3668 static int hns3_desc_unused(struct hns3_enet_ring *ring)
3669 {
3670 int ntc = ring->next_to_clean;
3671 int ntu = ring->next_to_use;
3672
3673 if (unlikely(ntc == ntu && !ring->desc_cb[ntc].refill))
3674 return ring->desc_num;
3675
3676 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
3677 }
3678
3679 /* Return true if there is any allocation failure */
hns3_nic_alloc_rx_buffers(struct hns3_enet_ring * ring,int cleand_count)3680 static bool hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
3681 int cleand_count)
3682 {
3683 struct hns3_desc_cb *desc_cb;
3684 struct hns3_desc_cb res_cbs;
3685 int i, ret;
3686
3687 for (i = 0; i < cleand_count; i++) {
3688 desc_cb = &ring->desc_cb[ring->next_to_use];
3689 if (desc_cb->reuse_flag) {
3690 hns3_ring_stats_update(ring, reuse_pg_cnt);
3691
3692 hns3_reuse_buffer(ring, ring->next_to_use);
3693 } else {
3694 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
3695 if (ret) {
3696 hns3_ring_stats_update(ring, sw_err_cnt);
3697
3698 hns3_rl_err(ring_to_netdev(ring),
3699 "alloc rx buffer failed: %d\n",
3700 ret);
3701
3702 writel(i, ring->tqp->io_base +
3703 HNS3_RING_RX_RING_HEAD_REG);
3704 return true;
3705 }
3706 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
3707
3708 hns3_ring_stats_update(ring, non_reuse_pg);
3709 }
3710
3711 ring_ptr_move_fw(ring, next_to_use);
3712 }
3713
3714 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
3715 return false;
3716 }
3717
hns3_can_reuse_page(struct hns3_desc_cb * cb)3718 static bool hns3_can_reuse_page(struct hns3_desc_cb *cb)
3719 {
3720 return page_count(cb->priv) == cb->pagecnt_bias;
3721 }
3722
hns3_handle_rx_copybreak(struct sk_buff * skb,int i,struct hns3_enet_ring * ring,int pull_len,struct hns3_desc_cb * desc_cb)3723 static int hns3_handle_rx_copybreak(struct sk_buff *skb, int i,
3724 struct hns3_enet_ring *ring,
3725 int pull_len,
3726 struct hns3_desc_cb *desc_cb)
3727 {
3728 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
3729 u32 frag_offset = desc_cb->page_offset + pull_len;
3730 int size = le16_to_cpu(desc->rx.size);
3731 u32 frag_size = size - pull_len;
3732 void *frag = napi_alloc_frag(frag_size);
3733
3734 if (unlikely(!frag)) {
3735 hns3_ring_stats_update(ring, frag_alloc_err);
3736
3737 hns3_rl_err(ring_to_netdev(ring),
3738 "failed to allocate rx frag\n");
3739 return -ENOMEM;
3740 }
3741
3742 desc_cb->reuse_flag = 1;
3743 memcpy(frag, desc_cb->buf + frag_offset, frag_size);
3744 skb_add_rx_frag(skb, i, virt_to_page(frag),
3745 offset_in_page(frag), frag_size, frag_size);
3746
3747 hns3_ring_stats_update(ring, frag_alloc);
3748 return 0;
3749 }
3750
hns3_nic_reuse_page(struct sk_buff * skb,int i,struct hns3_enet_ring * ring,int pull_len,struct hns3_desc_cb * desc_cb)3751 static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
3752 struct hns3_enet_ring *ring, int pull_len,
3753 struct hns3_desc_cb *desc_cb)
3754 {
3755 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
3756 u32 frag_offset = desc_cb->page_offset + pull_len;
3757 int size = le16_to_cpu(desc->rx.size);
3758 u32 truesize = hns3_buf_size(ring);
3759 u32 frag_size = size - pull_len;
3760 int ret = 0;
3761 bool reused;
3762
3763 if (ring->page_pool) {
3764 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3765 frag_size, truesize);
3766 return;
3767 }
3768
3769 /* Avoid re-using remote or pfmem page */
3770 if (unlikely(!dev_page_is_reusable(desc_cb->priv)))
3771 goto out;
3772
3773 reused = hns3_can_reuse_page(desc_cb);
3774
3775 /* Rx page can be reused when:
3776 * 1. Rx page is only owned by the driver when page_offset
3777 * is zero, which means 0 @ truesize will be used by
3778 * stack after skb_add_rx_frag() is called, and the rest
3779 * of rx page can be reused by driver.
3780 * Or
3781 * 2. Rx page is only owned by the driver when page_offset
3782 * is non-zero, which means page_offset @ truesize will
3783 * be used by stack after skb_add_rx_frag() is called,
3784 * and 0 @ truesize can be reused by driver.
3785 */
3786 if ((!desc_cb->page_offset && reused) ||
3787 ((desc_cb->page_offset + truesize + truesize) <=
3788 hns3_page_size(ring) && desc_cb->page_offset)) {
3789 desc_cb->page_offset += truesize;
3790 desc_cb->reuse_flag = 1;
3791 } else if (desc_cb->page_offset && reused) {
3792 desc_cb->page_offset = 0;
3793 desc_cb->reuse_flag = 1;
3794 } else if (frag_size <= ring->rx_copybreak) {
3795 ret = hns3_handle_rx_copybreak(skb, i, ring, pull_len, desc_cb);
3796 if (!ret)
3797 return;
3798 }
3799
3800 out:
3801 desc_cb->pagecnt_bias--;
3802
3803 if (unlikely(!desc_cb->pagecnt_bias)) {
3804 page_ref_add(desc_cb->priv, USHRT_MAX);
3805 desc_cb->pagecnt_bias = USHRT_MAX;
3806 }
3807
3808 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3809 frag_size, truesize);
3810
3811 if (unlikely(!desc_cb->reuse_flag))
3812 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias);
3813 }
3814
hns3_gro_complete(struct sk_buff * skb,u32 l234info)3815 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
3816 {
3817 __be16 type = skb->protocol;
3818 struct tcphdr *th;
3819 int depth = 0;
3820
3821 while (eth_type_vlan(type)) {
3822 struct vlan_hdr *vh;
3823
3824 if ((depth + VLAN_HLEN) > skb_headlen(skb))
3825 return -EFAULT;
3826
3827 vh = (struct vlan_hdr *)(skb->data + depth);
3828 type = vh->h_vlan_encapsulated_proto;
3829 depth += VLAN_HLEN;
3830 }
3831
3832 skb_set_network_header(skb, depth);
3833
3834 if (type == htons(ETH_P_IP)) {
3835 const struct iphdr *iph = ip_hdr(skb);
3836
3837 depth += sizeof(struct iphdr);
3838 skb_set_transport_header(skb, depth);
3839 th = tcp_hdr(skb);
3840 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
3841 iph->daddr, 0);
3842 } else if (type == htons(ETH_P_IPV6)) {
3843 const struct ipv6hdr *iph = ipv6_hdr(skb);
3844
3845 depth += sizeof(struct ipv6hdr);
3846 skb_set_transport_header(skb, depth);
3847 th = tcp_hdr(skb);
3848 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
3849 &iph->daddr, 0);
3850 } else {
3851 hns3_rl_err(skb->dev,
3852 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
3853 be16_to_cpu(type), depth);
3854 return -EFAULT;
3855 }
3856
3857 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
3858 if (th->cwr)
3859 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
3860
3861 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
3862 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
3863
3864 skb->csum_start = (unsigned char *)th - skb->head;
3865 skb->csum_offset = offsetof(struct tcphdr, check);
3866 skb->ip_summed = CHECKSUM_PARTIAL;
3867
3868 trace_hns3_gro(skb);
3869
3870 return 0;
3871 }
3872
hns3_checksum_complete(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 ptype,u16 csum)3873 static void hns3_checksum_complete(struct hns3_enet_ring *ring,
3874 struct sk_buff *skb, u32 ptype, u16 csum)
3875 {
3876 if (ptype == HNS3_INVALID_PTYPE ||
3877 hns3_rx_ptype_tbl[ptype].ip_summed != CHECKSUM_COMPLETE)
3878 return;
3879
3880 hns3_ring_stats_update(ring, csum_complete);
3881 skb->ip_summed = CHECKSUM_COMPLETE;
3882 skb->csum = csum_unfold((__force __sum16)csum);
3883 }
3884
hns3_rx_handle_csum(struct sk_buff * skb,u32 l234info,u32 ol_info,u32 ptype)3885 static void hns3_rx_handle_csum(struct sk_buff *skb, u32 l234info,
3886 u32 ol_info, u32 ptype)
3887 {
3888 int l3_type, l4_type;
3889 int ol4_type;
3890
3891 if (ptype != HNS3_INVALID_PTYPE) {
3892 skb->csum_level = hns3_rx_ptype_tbl[ptype].csum_level;
3893 skb->ip_summed = hns3_rx_ptype_tbl[ptype].ip_summed;
3894
3895 return;
3896 }
3897
3898 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
3899 HNS3_RXD_OL4ID_S);
3900 switch (ol4_type) {
3901 case HNS3_OL4_TYPE_MAC_IN_UDP:
3902 case HNS3_OL4_TYPE_NVGRE:
3903 skb->csum_level = 1;
3904 fallthrough;
3905 case HNS3_OL4_TYPE_NO_TUN:
3906 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
3907 HNS3_RXD_L3ID_S);
3908 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
3909 HNS3_RXD_L4ID_S);
3910 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
3911 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
3912 l3_type == HNS3_L3_TYPE_IPV6) &&
3913 (l4_type == HNS3_L4_TYPE_UDP ||
3914 l4_type == HNS3_L4_TYPE_TCP ||
3915 l4_type == HNS3_L4_TYPE_SCTP))
3916 skb->ip_summed = CHECKSUM_UNNECESSARY;
3917 break;
3918 default:
3919 break;
3920 }
3921 }
3922
hns3_rx_checksum(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 l234info,u32 bd_base_info,u32 ol_info,u16 csum)3923 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
3924 u32 l234info, u32 bd_base_info, u32 ol_info,
3925 u16 csum)
3926 {
3927 struct net_device *netdev = ring_to_netdev(ring);
3928 struct hns3_nic_priv *priv = netdev_priv(netdev);
3929 u32 ptype = HNS3_INVALID_PTYPE;
3930
3931 skb->ip_summed = CHECKSUM_NONE;
3932
3933 skb_checksum_none_assert(skb);
3934
3935 if (!(netdev->features & NETIF_F_RXCSUM))
3936 return;
3937
3938 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state))
3939 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
3940 HNS3_RXD_PTYPE_S);
3941
3942 hns3_checksum_complete(ring, skb, ptype, csum);
3943
3944 /* check if hardware has done checksum */
3945 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
3946 return;
3947
3948 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
3949 BIT(HNS3_RXD_OL3E_B) |
3950 BIT(HNS3_RXD_OL4E_B)))) {
3951 skb->ip_summed = CHECKSUM_NONE;
3952 hns3_ring_stats_update(ring, l3l4_csum_err);
3953
3954 return;
3955 }
3956
3957 hns3_rx_handle_csum(skb, l234info, ol_info, ptype);
3958 }
3959
hns3_rx_skb(struct hns3_enet_ring * ring,struct sk_buff * skb)3960 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
3961 {
3962 if (skb_has_frag_list(skb))
3963 napi_gro_flush(&ring->tqp_vector->napi, false);
3964
3965 napi_gro_receive(&ring->tqp_vector->napi, skb);
3966 }
3967
hns3_parse_vlan_tag(struct hns3_enet_ring * ring,struct hns3_desc * desc,u32 l234info,u16 * vlan_tag)3968 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
3969 struct hns3_desc *desc, u32 l234info,
3970 u16 *vlan_tag)
3971 {
3972 struct hnae3_handle *handle = ring->tqp->handle;
3973 struct pci_dev *pdev = ring->tqp->handle->pdev;
3974 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3975
3976 if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) {
3977 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3978 if (!(*vlan_tag & VLAN_VID_MASK))
3979 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
3980
3981 return (*vlan_tag != 0);
3982 }
3983
3984 #define HNS3_STRP_OUTER_VLAN 0x1
3985 #define HNS3_STRP_INNER_VLAN 0x2
3986 #define HNS3_STRP_BOTH 0x3
3987
3988 /* Hardware always insert VLAN tag into RX descriptor when
3989 * remove the tag from packet, driver needs to determine
3990 * reporting which tag to stack.
3991 */
3992 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
3993 HNS3_RXD_STRP_TAGP_S)) {
3994 case HNS3_STRP_OUTER_VLAN:
3995 if (handle->port_base_vlan_state !=
3996 HNAE3_PORT_BASE_VLAN_DISABLE)
3997 return false;
3998
3999 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
4000 return true;
4001 case HNS3_STRP_INNER_VLAN:
4002 if (handle->port_base_vlan_state !=
4003 HNAE3_PORT_BASE_VLAN_DISABLE)
4004 return false;
4005
4006 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
4007 return true;
4008 case HNS3_STRP_BOTH:
4009 if (handle->port_base_vlan_state ==
4010 HNAE3_PORT_BASE_VLAN_DISABLE)
4011 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
4012 else
4013 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
4014
4015 return true;
4016 default:
4017 return false;
4018 }
4019 }
4020
hns3_rx_ring_move_fw(struct hns3_enet_ring * ring)4021 static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring)
4022 {
4023 ring->desc[ring->next_to_clean].rx.bd_base_info &=
4024 cpu_to_le32(~BIT(HNS3_RXD_VLD_B));
4025 ring->desc_cb[ring->next_to_clean].refill = 0;
4026 ring->next_to_clean += 1;
4027
4028 if (unlikely(ring->next_to_clean == ring->desc_num))
4029 ring->next_to_clean = 0;
4030 }
4031
hns3_alloc_skb(struct hns3_enet_ring * ring,unsigned int length,unsigned char * va)4032 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
4033 unsigned char *va)
4034 {
4035 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
4036 struct net_device *netdev = ring_to_netdev(ring);
4037 struct sk_buff *skb;
4038
4039 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
4040 skb = ring->skb;
4041 if (unlikely(!skb)) {
4042 hns3_rl_err(netdev, "alloc rx skb fail\n");
4043 hns3_ring_stats_update(ring, sw_err_cnt);
4044
4045 return -ENOMEM;
4046 }
4047
4048 trace_hns3_rx_desc(ring);
4049 prefetchw(skb->data);
4050
4051 ring->pending_buf = 1;
4052 ring->frag_num = 0;
4053 ring->tail_skb = NULL;
4054 if (length <= HNS3_RX_HEAD_SIZE) {
4055 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
4056
4057 /* We can reuse buffer as-is, just make sure it is reusable */
4058 if (dev_page_is_reusable(desc_cb->priv))
4059 desc_cb->reuse_flag = 1;
4060 else if (desc_cb->type & DESC_TYPE_PP_FRAG)
4061 page_pool_put_full_page(ring->page_pool, desc_cb->priv,
4062 false);
4063 else /* This page cannot be reused so discard it */
4064 __page_frag_cache_drain(desc_cb->priv,
4065 desc_cb->pagecnt_bias);
4066
4067 hns3_rx_ring_move_fw(ring);
4068 return 0;
4069 }
4070
4071 if (ring->page_pool)
4072 skb_mark_for_recycle(skb);
4073
4074 hns3_ring_stats_update(ring, seg_pkt_cnt);
4075
4076 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
4077 __skb_put(skb, ring->pull_len);
4078 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
4079 desc_cb);
4080 hns3_rx_ring_move_fw(ring);
4081
4082 return 0;
4083 }
4084
hns3_add_frag(struct hns3_enet_ring * ring)4085 static int hns3_add_frag(struct hns3_enet_ring *ring)
4086 {
4087 struct sk_buff *skb = ring->skb;
4088 struct sk_buff *head_skb = skb;
4089 struct sk_buff *new_skb;
4090 struct hns3_desc_cb *desc_cb;
4091 struct hns3_desc *desc;
4092 u32 bd_base_info;
4093
4094 do {
4095 desc = &ring->desc[ring->next_to_clean];
4096 desc_cb = &ring->desc_cb[ring->next_to_clean];
4097 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4098 /* make sure HW write desc complete */
4099 dma_rmb();
4100 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
4101 return -ENXIO;
4102
4103 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
4104 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0);
4105 if (unlikely(!new_skb)) {
4106 hns3_rl_err(ring_to_netdev(ring),
4107 "alloc rx fraglist skb fail\n");
4108 return -ENXIO;
4109 }
4110
4111 if (ring->page_pool)
4112 skb_mark_for_recycle(new_skb);
4113
4114 ring->frag_num = 0;
4115
4116 if (ring->tail_skb) {
4117 ring->tail_skb->next = new_skb;
4118 ring->tail_skb = new_skb;
4119 } else {
4120 skb_shinfo(skb)->frag_list = new_skb;
4121 ring->tail_skb = new_skb;
4122 }
4123 }
4124
4125 if (ring->tail_skb) {
4126 head_skb->truesize += hns3_buf_size(ring);
4127 head_skb->data_len += le16_to_cpu(desc->rx.size);
4128 head_skb->len += le16_to_cpu(desc->rx.size);
4129 skb = ring->tail_skb;
4130 }
4131
4132 dma_sync_single_for_cpu(ring_to_dev(ring),
4133 desc_cb->dma + desc_cb->page_offset,
4134 hns3_buf_size(ring),
4135 DMA_FROM_DEVICE);
4136
4137 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
4138 trace_hns3_rx_desc(ring);
4139 hns3_rx_ring_move_fw(ring);
4140 ring->pending_buf++;
4141 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B)));
4142
4143 return 0;
4144 }
4145
hns3_set_gro_and_checksum(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 l234info,u32 bd_base_info,u32 ol_info,u16 csum)4146 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
4147 struct sk_buff *skb, u32 l234info,
4148 u32 bd_base_info, u32 ol_info, u16 csum)
4149 {
4150 struct net_device *netdev = ring_to_netdev(ring);
4151 struct hns3_nic_priv *priv = netdev_priv(netdev);
4152 u32 l3_type;
4153
4154 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
4155 HNS3_RXD_GRO_SIZE_M,
4156 HNS3_RXD_GRO_SIZE_S);
4157 /* if there is no HW GRO, do not set gro params */
4158 if (!skb_shinfo(skb)->gso_size) {
4159 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info,
4160 csum);
4161 return 0;
4162 }
4163
4164 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
4165 HNS3_RXD_GRO_COUNT_M,
4166 HNS3_RXD_GRO_COUNT_S);
4167
4168 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
4169 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
4170 HNS3_RXD_PTYPE_S);
4171
4172 l3_type = hns3_rx_ptype_tbl[ptype].l3_type;
4173 } else {
4174 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
4175 HNS3_RXD_L3ID_S);
4176 }
4177
4178 if (l3_type == HNS3_L3_TYPE_IPV4)
4179 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
4180 else if (l3_type == HNS3_L3_TYPE_IPV6)
4181 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
4182 else
4183 return -EFAULT;
4184
4185 return hns3_gro_complete(skb, l234info);
4186 }
4187
hns3_set_rx_skb_rss_type(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 rss_hash,u32 l234info,u32 ol_info)4188 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
4189 struct sk_buff *skb, u32 rss_hash,
4190 u32 l234info, u32 ol_info)
4191 {
4192 enum pkt_hash_types rss_type = PKT_HASH_TYPE_NONE;
4193 struct net_device *netdev = ring_to_netdev(ring);
4194 struct hns3_nic_priv *priv = netdev_priv(netdev);
4195
4196 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
4197 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
4198 HNS3_RXD_PTYPE_S);
4199
4200 rss_type = hns3_rx_ptype_tbl[ptype].hash_type;
4201 } else {
4202 int l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
4203 HNS3_RXD_L3ID_S);
4204 int l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
4205 HNS3_RXD_L4ID_S);
4206
4207 if (l3_type == HNS3_L3_TYPE_IPV4 ||
4208 l3_type == HNS3_L3_TYPE_IPV6) {
4209 if (l4_type == HNS3_L4_TYPE_UDP ||
4210 l4_type == HNS3_L4_TYPE_TCP ||
4211 l4_type == HNS3_L4_TYPE_SCTP)
4212 rss_type = PKT_HASH_TYPE_L4;
4213 else if (l4_type == HNS3_L4_TYPE_IGMP ||
4214 l4_type == HNS3_L4_TYPE_ICMP)
4215 rss_type = PKT_HASH_TYPE_L3;
4216 }
4217 }
4218
4219 skb_set_hash(skb, rss_hash, rss_type);
4220 }
4221
hns3_handle_rx_ts_info(struct net_device * netdev,struct hns3_desc * desc,struct sk_buff * skb,u32 bd_base_info)4222 static void hns3_handle_rx_ts_info(struct net_device *netdev,
4223 struct hns3_desc *desc, struct sk_buff *skb,
4224 u32 bd_base_info)
4225 {
4226 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) {
4227 struct hnae3_handle *h = hns3_get_handle(netdev);
4228 u32 nsec = le32_to_cpu(desc->ts_nsec);
4229 u32 sec = le32_to_cpu(desc->ts_sec);
4230
4231 if (h->ae_algo->ops->get_rx_hwts)
4232 h->ae_algo->ops->get_rx_hwts(h, skb, nsec, sec);
4233 }
4234 }
4235
hns3_handle_rx_vlan_tag(struct hns3_enet_ring * ring,struct hns3_desc * desc,struct sk_buff * skb,u32 l234info)4236 static void hns3_handle_rx_vlan_tag(struct hns3_enet_ring *ring,
4237 struct hns3_desc *desc, struct sk_buff *skb,
4238 u32 l234info)
4239 {
4240 struct net_device *netdev = ring_to_netdev(ring);
4241
4242 /* Based on hw strategy, the tag offloaded will be stored at
4243 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
4244 * in one layer tag case.
4245 */
4246 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
4247 u16 vlan_tag;
4248
4249 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
4250 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
4251 vlan_tag);
4252 }
4253 }
4254
hns3_handle_bdinfo(struct hns3_enet_ring * ring,struct sk_buff * skb)4255 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
4256 {
4257 struct net_device *netdev = ring_to_netdev(ring);
4258 enum hns3_pkt_l2t_type l2_frame_type;
4259 u32 bd_base_info, l234info, ol_info;
4260 struct hns3_desc *desc;
4261 unsigned int len;
4262 int pre_ntc, ret;
4263 u16 csum;
4264
4265 /* bdinfo handled below is only valid on the last BD of the
4266 * current packet, and ring->next_to_clean indicates the first
4267 * descriptor of next packet, so need - 1 below.
4268 */
4269 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
4270 (ring->desc_num - 1);
4271 desc = &ring->desc[pre_ntc];
4272 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4273 l234info = le32_to_cpu(desc->rx.l234_info);
4274 ol_info = le32_to_cpu(desc->rx.ol_info);
4275 csum = le16_to_cpu(desc->csum);
4276
4277 hns3_handle_rx_ts_info(netdev, desc, skb, bd_base_info);
4278
4279 hns3_handle_rx_vlan_tag(ring, desc, skb, l234info);
4280
4281 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
4282 BIT(HNS3_RXD_L2E_B))))) {
4283 u64_stats_update_begin(&ring->syncp);
4284 if (l234info & BIT(HNS3_RXD_L2E_B))
4285 ring->stats.l2_err++;
4286 else
4287 ring->stats.err_pkt_len++;
4288 u64_stats_update_end(&ring->syncp);
4289
4290 return -EFAULT;
4291 }
4292
4293 len = skb->len;
4294
4295 /* Do update ip stack process */
4296 skb->protocol = eth_type_trans(skb, netdev);
4297
4298 /* This is needed in order to enable forwarding support */
4299 ret = hns3_set_gro_and_checksum(ring, skb, l234info,
4300 bd_base_info, ol_info, csum);
4301 if (unlikely(ret)) {
4302 hns3_ring_stats_update(ring, rx_err_cnt);
4303 return ret;
4304 }
4305
4306 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
4307 HNS3_RXD_DMAC_S);
4308
4309 u64_stats_update_begin(&ring->syncp);
4310 ring->stats.rx_pkts++;
4311 ring->stats.rx_bytes += len;
4312
4313 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
4314 ring->stats.rx_multicast++;
4315
4316 u64_stats_update_end(&ring->syncp);
4317
4318 ring->tqp_vector->rx_group.total_bytes += len;
4319
4320 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash),
4321 l234info, ol_info);
4322 return 0;
4323 }
4324
hns3_handle_rx_bd(struct hns3_enet_ring * ring)4325 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
4326 {
4327 struct sk_buff *skb = ring->skb;
4328 struct hns3_desc_cb *desc_cb;
4329 struct hns3_desc *desc;
4330 unsigned int length;
4331 u32 bd_base_info;
4332 int ret;
4333
4334 desc = &ring->desc[ring->next_to_clean];
4335 desc_cb = &ring->desc_cb[ring->next_to_clean];
4336
4337 prefetch(desc);
4338
4339 if (!skb) {
4340 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4341 /* Check valid BD */
4342 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
4343 return -ENXIO;
4344
4345 dma_rmb();
4346 length = le16_to_cpu(desc->rx.size);
4347
4348 ring->va = desc_cb->buf + desc_cb->page_offset;
4349
4350 dma_sync_single_for_cpu(ring_to_dev(ring),
4351 desc_cb->dma + desc_cb->page_offset,
4352 hns3_buf_size(ring),
4353 DMA_FROM_DEVICE);
4354
4355 /* Prefetch first cache line of first page.
4356 * Idea is to cache few bytes of the header of the packet.
4357 * Our L1 Cache line size is 64B so need to prefetch twice to make
4358 * it 128B. But in actual we can have greater size of caches with
4359 * 128B Level 1 cache lines. In such a case, single fetch would
4360 * suffice to cache in the relevant part of the header.
4361 */
4362 net_prefetch(ring->va);
4363
4364 ret = hns3_alloc_skb(ring, length, ring->va);
4365 skb = ring->skb;
4366
4367 if (ret < 0) /* alloc buffer fail */
4368 return ret;
4369 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */
4370 ret = hns3_add_frag(ring);
4371 if (ret)
4372 return ret;
4373 }
4374 } else {
4375 ret = hns3_add_frag(ring);
4376 if (ret)
4377 return ret;
4378 }
4379
4380 /* As the head data may be changed when GRO enable, copy
4381 * the head data in after other data rx completed
4382 */
4383 if (skb->len > HNS3_RX_HEAD_SIZE)
4384 memcpy(skb->data, ring->va,
4385 ALIGN(ring->pull_len, sizeof(long)));
4386
4387 ret = hns3_handle_bdinfo(ring, skb);
4388 if (unlikely(ret)) {
4389 dev_kfree_skb_any(skb);
4390 return ret;
4391 }
4392
4393 skb_record_rx_queue(skb, ring->tqp->tqp_index);
4394 return 0;
4395 }
4396
hns3_clean_rx_ring(struct hns3_enet_ring * ring,int budget,void (* rx_fn)(struct hns3_enet_ring *,struct sk_buff *))4397 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
4398 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
4399 {
4400 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
4401 int unused_count = hns3_desc_unused(ring);
4402 bool failure = false;
4403 int recv_pkts = 0;
4404 int err;
4405
4406 unused_count -= ring->pending_buf;
4407
4408 while (recv_pkts < budget) {
4409 /* Reuse or realloc buffers */
4410 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
4411 failure = failure ||
4412 hns3_nic_alloc_rx_buffers(ring, unused_count);
4413 unused_count = 0;
4414 }
4415
4416 /* Poll one pkt */
4417 err = hns3_handle_rx_bd(ring);
4418 /* Do not get FE for the packet or failed to alloc skb */
4419 if (unlikely(!ring->skb || err == -ENXIO)) {
4420 goto out;
4421 } else if (likely(!err)) {
4422 rx_fn(ring, ring->skb);
4423 recv_pkts++;
4424 }
4425
4426 unused_count += ring->pending_buf;
4427 ring->skb = NULL;
4428 ring->pending_buf = 0;
4429 }
4430
4431 out:
4432 /* sync head pointer before exiting, since hardware will calculate
4433 * FBD number with head pointer
4434 */
4435 if (unused_count > 0)
4436 failure = failure ||
4437 hns3_nic_alloc_rx_buffers(ring, unused_count);
4438
4439 return failure ? budget : recv_pkts;
4440 }
4441
hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector * tqp_vector)4442 static void hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
4443 {
4444 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
4445 struct dim_sample sample = {};
4446
4447 if (!rx_group->coal.adapt_enable)
4448 return;
4449
4450 dim_update_sample(tqp_vector->event_cnt, rx_group->total_packets,
4451 rx_group->total_bytes, &sample);
4452 net_dim(&rx_group->dim, sample);
4453 }
4454
hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector * tqp_vector)4455 static void hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
4456 {
4457 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
4458 struct dim_sample sample = {};
4459
4460 if (!tx_group->coal.adapt_enable)
4461 return;
4462
4463 dim_update_sample(tqp_vector->event_cnt, tx_group->total_packets,
4464 tx_group->total_bytes, &sample);
4465 net_dim(&tx_group->dim, sample);
4466 }
4467
hns3_nic_common_poll(struct napi_struct * napi,int budget)4468 static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
4469 {
4470 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
4471 struct hns3_enet_ring *ring;
4472 int rx_pkt_total = 0;
4473
4474 struct hns3_enet_tqp_vector *tqp_vector =
4475 container_of(napi, struct hns3_enet_tqp_vector, napi);
4476 bool clean_complete = true;
4477 int rx_budget = budget;
4478
4479 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4480 napi_complete(napi);
4481 return 0;
4482 }
4483
4484 /* Since the actual Tx work is minimal, we can give the Tx a larger
4485 * budget and be more aggressive about cleaning up the Tx descriptors.
4486 */
4487 hns3_for_each_ring(ring, tqp_vector->tx_group)
4488 hns3_clean_tx_ring(ring, budget);
4489
4490 /* make sure rx ring budget not smaller than 1 */
4491 if (tqp_vector->num_tqps > 1)
4492 rx_budget = max(budget / tqp_vector->num_tqps, 1);
4493
4494 hns3_for_each_ring(ring, tqp_vector->rx_group) {
4495 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
4496 hns3_rx_skb);
4497 if (rx_cleaned >= rx_budget)
4498 clean_complete = false;
4499
4500 rx_pkt_total += rx_cleaned;
4501 }
4502
4503 tqp_vector->rx_group.total_packets += rx_pkt_total;
4504
4505 if (!clean_complete)
4506 return budget;
4507
4508 if (napi_complete(napi) &&
4509 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4510 hns3_update_rx_int_coalesce(tqp_vector);
4511 hns3_update_tx_int_coalesce(tqp_vector);
4512
4513 hns3_mask_vector_irq(tqp_vector, 1);
4514 }
4515
4516 return rx_pkt_total;
4517 }
4518
hns3_create_ring_chain(struct hns3_enet_tqp_vector * tqp_vector,struct hnae3_ring_chain_node ** head,bool is_tx)4519 static int hns3_create_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4520 struct hnae3_ring_chain_node **head,
4521 bool is_tx)
4522 {
4523 u32 bit_value = is_tx ? HNAE3_RING_TYPE_TX : HNAE3_RING_TYPE_RX;
4524 u32 field_value = is_tx ? HNAE3_RING_GL_TX : HNAE3_RING_GL_RX;
4525 struct hnae3_ring_chain_node *cur_chain = *head;
4526 struct pci_dev *pdev = tqp_vector->handle->pdev;
4527 struct hnae3_ring_chain_node *chain;
4528 struct hns3_enet_ring *ring;
4529
4530 ring = is_tx ? tqp_vector->tx_group.ring : tqp_vector->rx_group.ring;
4531
4532 if (cur_chain) {
4533 while (cur_chain->next)
4534 cur_chain = cur_chain->next;
4535 }
4536
4537 while (ring) {
4538 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
4539 if (!chain)
4540 return -ENOMEM;
4541 if (cur_chain)
4542 cur_chain->next = chain;
4543 else
4544 *head = chain;
4545 chain->tqp_index = ring->tqp->tqp_index;
4546 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
4547 bit_value);
4548 hnae3_set_field(chain->int_gl_idx,
4549 HNAE3_RING_GL_IDX_M,
4550 HNAE3_RING_GL_IDX_S, field_value);
4551
4552 cur_chain = chain;
4553
4554 ring = ring->next;
4555 }
4556
4557 return 0;
4558 }
4559
4560 static struct hnae3_ring_chain_node *
hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector * tqp_vector)4561 hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector)
4562 {
4563 struct pci_dev *pdev = tqp_vector->handle->pdev;
4564 struct hnae3_ring_chain_node *cur_chain = NULL;
4565 struct hnae3_ring_chain_node *chain;
4566
4567 if (hns3_create_ring_chain(tqp_vector, &cur_chain, true))
4568 goto err_free_chain;
4569
4570 if (hns3_create_ring_chain(tqp_vector, &cur_chain, false))
4571 goto err_free_chain;
4572
4573 return cur_chain;
4574
4575 err_free_chain:
4576 while (cur_chain) {
4577 chain = cur_chain->next;
4578 devm_kfree(&pdev->dev, cur_chain);
4579 cur_chain = chain;
4580 }
4581
4582 return NULL;
4583 }
4584
hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector * tqp_vector,struct hnae3_ring_chain_node * head)4585 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4586 struct hnae3_ring_chain_node *head)
4587 {
4588 struct pci_dev *pdev = tqp_vector->handle->pdev;
4589 struct hnae3_ring_chain_node *chain_tmp, *chain;
4590
4591 chain = head;
4592
4593 while (chain) {
4594 chain_tmp = chain->next;
4595 devm_kfree(&pdev->dev, chain);
4596 chain = chain_tmp;
4597 }
4598 }
4599
hns3_add_ring_to_group(struct hns3_enet_ring_group * group,struct hns3_enet_ring * ring)4600 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
4601 struct hns3_enet_ring *ring)
4602 {
4603 ring->next = group->ring;
4604 group->ring = ring;
4605
4606 group->count++;
4607 }
4608
hns3_nic_set_cpumask(struct hns3_nic_priv * priv)4609 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
4610 {
4611 struct pci_dev *pdev = priv->ae_handle->pdev;
4612 struct hns3_enet_tqp_vector *tqp_vector;
4613 int num_vectors = priv->vector_num;
4614 int numa_node;
4615 int vector_i;
4616
4617 numa_node = dev_to_node(&pdev->dev);
4618
4619 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
4620 tqp_vector = &priv->tqp_vector[vector_i];
4621 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
4622 &tqp_vector->affinity_mask);
4623 }
4624 }
4625
hns3_rx_dim_work(struct work_struct * work)4626 static void hns3_rx_dim_work(struct work_struct *work)
4627 {
4628 struct dim *dim = container_of(work, struct dim, work);
4629 struct hns3_enet_ring_group *group = container_of(dim,
4630 struct hns3_enet_ring_group, dim);
4631 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4632 struct dim_cq_moder cur_moder =
4633 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
4634
4635 hns3_set_vector_coalesce_rx_gl(group->ring->tqp_vector, cur_moder.usec);
4636 tqp_vector->rx_group.coal.int_gl = cur_moder.usec;
4637
4638 if (cur_moder.pkts < tqp_vector->rx_group.coal.int_ql_max) {
4639 hns3_set_vector_coalesce_rx_ql(tqp_vector, cur_moder.pkts);
4640 tqp_vector->rx_group.coal.int_ql = cur_moder.pkts;
4641 }
4642
4643 dim->state = DIM_START_MEASURE;
4644 }
4645
hns3_tx_dim_work(struct work_struct * work)4646 static void hns3_tx_dim_work(struct work_struct *work)
4647 {
4648 struct dim *dim = container_of(work, struct dim, work);
4649 struct hns3_enet_ring_group *group = container_of(dim,
4650 struct hns3_enet_ring_group, dim);
4651 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4652 struct dim_cq_moder cur_moder =
4653 net_dim_get_tx_moderation(dim->mode, dim->profile_ix);
4654
4655 hns3_set_vector_coalesce_tx_gl(tqp_vector, cur_moder.usec);
4656 tqp_vector->tx_group.coal.int_gl = cur_moder.usec;
4657
4658 if (cur_moder.pkts < tqp_vector->tx_group.coal.int_ql_max) {
4659 hns3_set_vector_coalesce_tx_ql(tqp_vector, cur_moder.pkts);
4660 tqp_vector->tx_group.coal.int_ql = cur_moder.pkts;
4661 }
4662
4663 dim->state = DIM_START_MEASURE;
4664 }
4665
hns3_nic_init_dim(struct hns3_enet_tqp_vector * tqp_vector)4666 static void hns3_nic_init_dim(struct hns3_enet_tqp_vector *tqp_vector)
4667 {
4668 INIT_WORK(&tqp_vector->rx_group.dim.work, hns3_rx_dim_work);
4669 INIT_WORK(&tqp_vector->tx_group.dim.work, hns3_tx_dim_work);
4670 }
4671
hns3_nic_init_vector_data(struct hns3_nic_priv * priv)4672 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
4673 {
4674 struct hnae3_handle *h = priv->ae_handle;
4675 struct hns3_enet_tqp_vector *tqp_vector;
4676 int ret;
4677 int i;
4678
4679 hns3_nic_set_cpumask(priv);
4680
4681 for (i = 0; i < priv->vector_num; i++) {
4682 tqp_vector = &priv->tqp_vector[i];
4683 hns3_vector_coalesce_init_hw(tqp_vector, priv);
4684 tqp_vector->num_tqps = 0;
4685 hns3_nic_init_dim(tqp_vector);
4686 }
4687
4688 for (i = 0; i < h->kinfo.num_tqps; i++) {
4689 u16 vector_i = i % priv->vector_num;
4690 u16 tqp_num = h->kinfo.num_tqps;
4691
4692 tqp_vector = &priv->tqp_vector[vector_i];
4693
4694 hns3_add_ring_to_group(&tqp_vector->tx_group,
4695 &priv->ring[i]);
4696
4697 hns3_add_ring_to_group(&tqp_vector->rx_group,
4698 &priv->ring[i + tqp_num]);
4699
4700 priv->ring[i].tqp_vector = tqp_vector;
4701 priv->ring[i + tqp_num].tqp_vector = tqp_vector;
4702 tqp_vector->num_tqps++;
4703 }
4704
4705 for (i = 0; i < priv->vector_num; i++) {
4706 struct hnae3_ring_chain_node *vector_ring_chain;
4707
4708 tqp_vector = &priv->tqp_vector[i];
4709
4710 tqp_vector->rx_group.total_bytes = 0;
4711 tqp_vector->rx_group.total_packets = 0;
4712 tqp_vector->tx_group.total_bytes = 0;
4713 tqp_vector->tx_group.total_packets = 0;
4714 tqp_vector->handle = h;
4715
4716 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector);
4717 if (!vector_ring_chain) {
4718 ret = -ENOMEM;
4719 goto map_ring_fail;
4720 }
4721
4722 ret = h->ae_algo->ops->map_ring_to_vector(h,
4723 tqp_vector->vector_irq, vector_ring_chain);
4724
4725 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain);
4726
4727 if (ret)
4728 goto map_ring_fail;
4729
4730 netif_napi_add(priv->netdev, &tqp_vector->napi,
4731 hns3_nic_common_poll);
4732 }
4733
4734 return 0;
4735
4736 map_ring_fail:
4737 while (i--)
4738 netif_napi_del(&priv->tqp_vector[i].napi);
4739
4740 return ret;
4741 }
4742
hns3_nic_init_coal_cfg(struct hns3_nic_priv * priv)4743 static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv)
4744 {
4745 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
4746 struct hns3_enet_coalesce *tx_coal = &priv->tx_coal;
4747 struct hns3_enet_coalesce *rx_coal = &priv->rx_coal;
4748
4749 /* initialize the configuration for interrupt coalescing.
4750 * 1. GL (Interrupt Gap Limiter)
4751 * 2. RL (Interrupt Rate Limiter)
4752 * 3. QL (Interrupt Quantity Limiter)
4753 *
4754 * Default: enable interrupt coalescing self-adaptive and GL
4755 */
4756 tx_coal->adapt_enable = 1;
4757 rx_coal->adapt_enable = 1;
4758
4759 tx_coal->int_gl = HNS3_INT_GL_50K;
4760 rx_coal->int_gl = HNS3_INT_GL_50K;
4761
4762 rx_coal->flow_level = HNS3_FLOW_LOW;
4763 tx_coal->flow_level = HNS3_FLOW_LOW;
4764
4765 if (ae_dev->dev_specs.int_ql_max) {
4766 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4767 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4768 }
4769 }
4770
hns3_nic_alloc_vector_data(struct hns3_nic_priv * priv)4771 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
4772 {
4773 struct hnae3_handle *h = priv->ae_handle;
4774 struct hns3_enet_tqp_vector *tqp_vector;
4775 struct hnae3_vector_info *vector;
4776 struct pci_dev *pdev = h->pdev;
4777 u16 tqp_num = h->kinfo.num_tqps;
4778 u16 vector_num;
4779 int ret = 0;
4780 u16 i;
4781
4782 /* RSS size, cpu online and vector_num should be the same */
4783 /* Should consider 2p/4p later */
4784 vector_num = min_t(u16, num_online_cpus(), tqp_num);
4785
4786 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
4787 GFP_KERNEL);
4788 if (!vector)
4789 return -ENOMEM;
4790
4791 /* save the actual available vector number */
4792 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
4793
4794 priv->vector_num = vector_num;
4795 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
4796 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
4797 GFP_KERNEL);
4798 if (!priv->tqp_vector) {
4799 ret = -ENOMEM;
4800 goto out;
4801 }
4802
4803 for (i = 0; i < priv->vector_num; i++) {
4804 tqp_vector = &priv->tqp_vector[i];
4805 tqp_vector->idx = i;
4806 tqp_vector->mask_addr = vector[i].io_addr;
4807 tqp_vector->vector_irq = vector[i].vector;
4808 hns3_vector_coalesce_init(tqp_vector, priv);
4809 }
4810
4811 out:
4812 devm_kfree(&pdev->dev, vector);
4813 return ret;
4814 }
4815
hns3_clear_ring_group(struct hns3_enet_ring_group * group)4816 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
4817 {
4818 group->ring = NULL;
4819 group->count = 0;
4820 }
4821
hns3_nic_uninit_vector_data(struct hns3_nic_priv * priv)4822 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
4823 {
4824 struct hnae3_ring_chain_node *vector_ring_chain;
4825 struct hnae3_handle *h = priv->ae_handle;
4826 struct hns3_enet_tqp_vector *tqp_vector;
4827 int i;
4828
4829 for (i = 0; i < priv->vector_num; i++) {
4830 tqp_vector = &priv->tqp_vector[i];
4831
4832 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
4833 continue;
4834
4835 /* Since the mapping can be overwritten, when fail to get the
4836 * chain between vector and ring, we should go on to deal with
4837 * the remaining options.
4838 */
4839 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector);
4840 if (!vector_ring_chain)
4841 dev_warn(priv->dev, "failed to get ring chain\n");
4842
4843 h->ae_algo->ops->unmap_ring_from_vector(h,
4844 tqp_vector->vector_irq, vector_ring_chain);
4845
4846 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain);
4847
4848 hns3_clear_ring_group(&tqp_vector->rx_group);
4849 hns3_clear_ring_group(&tqp_vector->tx_group);
4850 netif_napi_del(&priv->tqp_vector[i].napi);
4851 }
4852 }
4853
hns3_nic_dealloc_vector_data(struct hns3_nic_priv * priv)4854 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
4855 {
4856 struct hnae3_handle *h = priv->ae_handle;
4857 struct pci_dev *pdev = h->pdev;
4858 int i, ret;
4859
4860 for (i = 0; i < priv->vector_num; i++) {
4861 struct hns3_enet_tqp_vector *tqp_vector;
4862
4863 tqp_vector = &priv->tqp_vector[i];
4864 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
4865 if (ret)
4866 return;
4867 }
4868
4869 devm_kfree(&pdev->dev, priv->tqp_vector);
4870 }
4871
hns3_ring_get_cfg(struct hnae3_queue * q,struct hns3_nic_priv * priv,unsigned int ring_type)4872 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
4873 unsigned int ring_type)
4874 {
4875 int queue_num = priv->ae_handle->kinfo.num_tqps;
4876 struct hns3_enet_ring *ring;
4877 int desc_num;
4878
4879 if (ring_type == HNAE3_RING_TYPE_TX) {
4880 ring = &priv->ring[q->tqp_index];
4881 desc_num = priv->ae_handle->kinfo.num_tx_desc;
4882 ring->queue_index = q->tqp_index;
4883 ring->tx_copybreak = priv->tx_copybreak;
4884 ring->last_to_use = 0;
4885 } else {
4886 ring = &priv->ring[q->tqp_index + queue_num];
4887 desc_num = priv->ae_handle->kinfo.num_rx_desc;
4888 ring->queue_index = q->tqp_index;
4889 ring->rx_copybreak = priv->rx_copybreak;
4890 }
4891
4892 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
4893
4894 ring->tqp = q;
4895 ring->desc = NULL;
4896 ring->desc_cb = NULL;
4897 ring->dev = priv->dev;
4898 ring->desc_dma_addr = 0;
4899 ring->buf_size = q->buf_size;
4900 ring->desc_num = desc_num;
4901 ring->next_to_use = 0;
4902 ring->next_to_clean = 0;
4903 }
4904
hns3_queue_to_ring(struct hnae3_queue * tqp,struct hns3_nic_priv * priv)4905 static void hns3_queue_to_ring(struct hnae3_queue *tqp,
4906 struct hns3_nic_priv *priv)
4907 {
4908 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
4909 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
4910 }
4911
hns3_get_ring_config(struct hns3_nic_priv * priv)4912 static int hns3_get_ring_config(struct hns3_nic_priv *priv)
4913 {
4914 struct hnae3_handle *h = priv->ae_handle;
4915 struct pci_dev *pdev = h->pdev;
4916 int i;
4917
4918 priv->ring = devm_kzalloc(&pdev->dev,
4919 array3_size(h->kinfo.num_tqps,
4920 sizeof(*priv->ring), 2),
4921 GFP_KERNEL);
4922 if (!priv->ring)
4923 return -ENOMEM;
4924
4925 for (i = 0; i < h->kinfo.num_tqps; i++)
4926 hns3_queue_to_ring(h->kinfo.tqp[i], priv);
4927
4928 return 0;
4929 }
4930
hns3_put_ring_config(struct hns3_nic_priv * priv)4931 static void hns3_put_ring_config(struct hns3_nic_priv *priv)
4932 {
4933 if (!priv->ring)
4934 return;
4935
4936 devm_kfree(priv->dev, priv->ring);
4937 priv->ring = NULL;
4938 }
4939
hns3_alloc_page_pool(struct hns3_enet_ring * ring)4940 static void hns3_alloc_page_pool(struct hns3_enet_ring *ring)
4941 {
4942 struct page_pool_params pp_params = {
4943 .flags = PP_FLAG_DMA_MAP | PP_FLAG_PAGE_FRAG |
4944 PP_FLAG_DMA_SYNC_DEV,
4945 .order = hns3_page_order(ring),
4946 .pool_size = ring->desc_num * hns3_buf_size(ring) /
4947 (PAGE_SIZE << hns3_page_order(ring)),
4948 .nid = dev_to_node(ring_to_dev(ring)),
4949 .dev = ring_to_dev(ring),
4950 .dma_dir = DMA_FROM_DEVICE,
4951 .offset = 0,
4952 .max_len = PAGE_SIZE << hns3_page_order(ring),
4953 };
4954
4955 ring->page_pool = page_pool_create(&pp_params);
4956 if (IS_ERR(ring->page_pool)) {
4957 dev_warn(ring_to_dev(ring), "page pool creation failed: %ld\n",
4958 PTR_ERR(ring->page_pool));
4959 ring->page_pool = NULL;
4960 }
4961 }
4962
hns3_alloc_ring_memory(struct hns3_enet_ring * ring)4963 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
4964 {
4965 int ret;
4966
4967 if (ring->desc_num <= 0 || ring->buf_size <= 0)
4968 return -EINVAL;
4969
4970 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
4971 sizeof(ring->desc_cb[0]), GFP_KERNEL);
4972 if (!ring->desc_cb) {
4973 ret = -ENOMEM;
4974 goto out;
4975 }
4976
4977 ret = hns3_alloc_desc(ring);
4978 if (ret)
4979 goto out_with_desc_cb;
4980
4981 if (!HNAE3_IS_TX_RING(ring)) {
4982 if (page_pool_enabled)
4983 hns3_alloc_page_pool(ring);
4984
4985 ret = hns3_alloc_ring_buffers(ring);
4986 if (ret)
4987 goto out_with_desc;
4988 } else {
4989 hns3_init_tx_spare_buffer(ring);
4990 }
4991
4992 return 0;
4993
4994 out_with_desc:
4995 hns3_free_desc(ring);
4996 out_with_desc_cb:
4997 devm_kfree(ring_to_dev(ring), ring->desc_cb);
4998 ring->desc_cb = NULL;
4999 out:
5000 return ret;
5001 }
5002
hns3_fini_ring(struct hns3_enet_ring * ring)5003 void hns3_fini_ring(struct hns3_enet_ring *ring)
5004 {
5005 hns3_free_desc(ring);
5006 devm_kfree(ring_to_dev(ring), ring->desc_cb);
5007 ring->desc_cb = NULL;
5008 ring->next_to_clean = 0;
5009 ring->next_to_use = 0;
5010 ring->last_to_use = 0;
5011 ring->pending_buf = 0;
5012 if (!HNAE3_IS_TX_RING(ring) && ring->skb) {
5013 dev_kfree_skb_any(ring->skb);
5014 ring->skb = NULL;
5015 } else if (HNAE3_IS_TX_RING(ring) && ring->tx_spare) {
5016 struct hns3_tx_spare *tx_spare = ring->tx_spare;
5017
5018 dma_unmap_page(ring_to_dev(ring), tx_spare->dma, tx_spare->len,
5019 DMA_TO_DEVICE);
5020 free_pages((unsigned long)tx_spare->buf,
5021 get_order(tx_spare->len));
5022 devm_kfree(ring_to_dev(ring), tx_spare);
5023 ring->tx_spare = NULL;
5024 }
5025
5026 if (!HNAE3_IS_TX_RING(ring) && ring->page_pool) {
5027 page_pool_destroy(ring->page_pool);
5028 ring->page_pool = NULL;
5029 }
5030 }
5031
hns3_buf_size2type(u32 buf_size)5032 static int hns3_buf_size2type(u32 buf_size)
5033 {
5034 int bd_size_type;
5035
5036 switch (buf_size) {
5037 case 512:
5038 bd_size_type = HNS3_BD_SIZE_512_TYPE;
5039 break;
5040 case 1024:
5041 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
5042 break;
5043 case 2048:
5044 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
5045 break;
5046 case 4096:
5047 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
5048 break;
5049 default:
5050 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
5051 }
5052
5053 return bd_size_type;
5054 }
5055
hns3_init_ring_hw(struct hns3_enet_ring * ring)5056 static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
5057 {
5058 dma_addr_t dma = ring->desc_dma_addr;
5059 struct hnae3_queue *q = ring->tqp;
5060
5061 if (!HNAE3_IS_TX_RING(ring)) {
5062 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
5063 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
5064 (u32)((dma >> 31) >> 1));
5065
5066 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
5067 hns3_buf_size2type(ring->buf_size));
5068 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
5069 ring->desc_num / 8 - 1);
5070 } else {
5071 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
5072 (u32)dma);
5073 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
5074 (u32)((dma >> 31) >> 1));
5075
5076 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
5077 ring->desc_num / 8 - 1);
5078 }
5079 }
5080
hns3_init_tx_ring_tc(struct hns3_nic_priv * priv)5081 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
5082 {
5083 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
5084 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
5085 int i;
5086
5087 for (i = 0; i < tc_info->num_tc; i++) {
5088 int j;
5089
5090 for (j = 0; j < tc_info->tqp_count[i]; j++) {
5091 struct hnae3_queue *q;
5092
5093 q = priv->ring[tc_info->tqp_offset[i] + j].tqp;
5094 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, i);
5095 }
5096 }
5097 }
5098
hns3_init_all_ring(struct hns3_nic_priv * priv)5099 int hns3_init_all_ring(struct hns3_nic_priv *priv)
5100 {
5101 struct hnae3_handle *h = priv->ae_handle;
5102 int ring_num = h->kinfo.num_tqps * 2;
5103 int i, j;
5104 int ret;
5105
5106 for (i = 0; i < ring_num; i++) {
5107 ret = hns3_alloc_ring_memory(&priv->ring[i]);
5108 if (ret) {
5109 dev_err(priv->dev,
5110 "Alloc ring memory fail! ret=%d\n", ret);
5111 goto out_when_alloc_ring_memory;
5112 }
5113
5114 u64_stats_init(&priv->ring[i].syncp);
5115 }
5116
5117 return 0;
5118
5119 out_when_alloc_ring_memory:
5120 for (j = i - 1; j >= 0; j--)
5121 hns3_fini_ring(&priv->ring[j]);
5122
5123 return -ENOMEM;
5124 }
5125
hns3_uninit_all_ring(struct hns3_nic_priv * priv)5126 static void hns3_uninit_all_ring(struct hns3_nic_priv *priv)
5127 {
5128 struct hnae3_handle *h = priv->ae_handle;
5129 int i;
5130
5131 for (i = 0; i < h->kinfo.num_tqps; i++) {
5132 hns3_fini_ring(&priv->ring[i]);
5133 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
5134 }
5135 }
5136
5137 /* Set mac addr if it is configured. or leave it to the AE driver */
hns3_init_mac_addr(struct net_device * netdev)5138 static int hns3_init_mac_addr(struct net_device *netdev)
5139 {
5140 struct hns3_nic_priv *priv = netdev_priv(netdev);
5141 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
5142 struct hnae3_handle *h = priv->ae_handle;
5143 u8 mac_addr_temp[ETH_ALEN];
5144 int ret = 0;
5145
5146 if (h->ae_algo->ops->get_mac_addr)
5147 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
5148
5149 /* Check if the MAC address is valid, if not get a random one */
5150 if (!is_valid_ether_addr(mac_addr_temp)) {
5151 eth_hw_addr_random(netdev);
5152 hnae3_format_mac_addr(format_mac_addr, netdev->dev_addr);
5153 dev_warn(priv->dev, "using random MAC address %s\n",
5154 format_mac_addr);
5155 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) {
5156 eth_hw_addr_set(netdev, mac_addr_temp);
5157 ether_addr_copy(netdev->perm_addr, mac_addr_temp);
5158 } else {
5159 return 0;
5160 }
5161
5162 if (h->ae_algo->ops->set_mac_addr)
5163 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
5164
5165 return ret;
5166 }
5167
hns3_init_phy(struct net_device * netdev)5168 static int hns3_init_phy(struct net_device *netdev)
5169 {
5170 struct hnae3_handle *h = hns3_get_handle(netdev);
5171 int ret = 0;
5172
5173 if (h->ae_algo->ops->mac_connect_phy)
5174 ret = h->ae_algo->ops->mac_connect_phy(h);
5175
5176 return ret;
5177 }
5178
hns3_uninit_phy(struct net_device * netdev)5179 static void hns3_uninit_phy(struct net_device *netdev)
5180 {
5181 struct hnae3_handle *h = hns3_get_handle(netdev);
5182
5183 if (h->ae_algo->ops->mac_disconnect_phy)
5184 h->ae_algo->ops->mac_disconnect_phy(h);
5185 }
5186
hns3_client_start(struct hnae3_handle * handle)5187 static int hns3_client_start(struct hnae3_handle *handle)
5188 {
5189 if (!handle->ae_algo->ops->client_start)
5190 return 0;
5191
5192 return handle->ae_algo->ops->client_start(handle);
5193 }
5194
hns3_client_stop(struct hnae3_handle * handle)5195 static void hns3_client_stop(struct hnae3_handle *handle)
5196 {
5197 if (!handle->ae_algo->ops->client_stop)
5198 return;
5199
5200 handle->ae_algo->ops->client_stop(handle);
5201 }
5202
hns3_info_show(struct hns3_nic_priv * priv)5203 static void hns3_info_show(struct hns3_nic_priv *priv)
5204 {
5205 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
5206 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
5207
5208 hnae3_format_mac_addr(format_mac_addr, priv->netdev->dev_addr);
5209 dev_info(priv->dev, "MAC address: %s\n", format_mac_addr);
5210 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
5211 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
5212 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
5213 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
5214 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
5215 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
5216 dev_info(priv->dev, "Total number of enabled TCs: %u\n",
5217 kinfo->tc_info.num_tc);
5218 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
5219 }
5220
hns3_set_cq_period_mode(struct hns3_nic_priv * priv,enum dim_cq_period_mode mode,bool is_tx)5221 static void hns3_set_cq_period_mode(struct hns3_nic_priv *priv,
5222 enum dim_cq_period_mode mode, bool is_tx)
5223 {
5224 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
5225 struct hnae3_handle *handle = priv->ae_handle;
5226 int i;
5227
5228 if (is_tx) {
5229 priv->tx_cqe_mode = mode;
5230
5231 for (i = 0; i < priv->vector_num; i++)
5232 priv->tqp_vector[i].tx_group.dim.mode = mode;
5233 } else {
5234 priv->rx_cqe_mode = mode;
5235
5236 for (i = 0; i < priv->vector_num; i++)
5237 priv->tqp_vector[i].rx_group.dim.mode = mode;
5238 }
5239
5240 if (hnae3_ae_dev_cq_supported(ae_dev)) {
5241 u32 new_mode;
5242 u64 reg;
5243
5244 new_mode = (mode == DIM_CQ_PERIOD_MODE_START_FROM_CQE) ?
5245 HNS3_CQ_MODE_CQE : HNS3_CQ_MODE_EQE;
5246 reg = is_tx ? HNS3_GL1_CQ_MODE_REG : HNS3_GL0_CQ_MODE_REG;
5247
5248 writel(new_mode, handle->kinfo.io_base + reg);
5249 }
5250 }
5251
hns3_cq_period_mode_init(struct hns3_nic_priv * priv,enum dim_cq_period_mode tx_mode,enum dim_cq_period_mode rx_mode)5252 void hns3_cq_period_mode_init(struct hns3_nic_priv *priv,
5253 enum dim_cq_period_mode tx_mode,
5254 enum dim_cq_period_mode rx_mode)
5255 {
5256 hns3_set_cq_period_mode(priv, tx_mode, true);
5257 hns3_set_cq_period_mode(priv, rx_mode, false);
5258 }
5259
hns3_state_init(struct hnae3_handle * handle)5260 static void hns3_state_init(struct hnae3_handle *handle)
5261 {
5262 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
5263 struct net_device *netdev = handle->kinfo.netdev;
5264 struct hns3_nic_priv *priv = netdev_priv(netdev);
5265
5266 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5267
5268 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps))
5269 set_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state);
5270
5271 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
5272 set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags);
5273
5274 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
5275 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state);
5276
5277 if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev))
5278 set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state);
5279 }
5280
hns3_state_uninit(struct hnae3_handle * handle)5281 static void hns3_state_uninit(struct hnae3_handle *handle)
5282 {
5283 struct hns3_nic_priv *priv = handle->priv;
5284
5285 clear_bit(HNS3_NIC_STATE_INITED, &priv->state);
5286 }
5287
hns3_client_init(struct hnae3_handle * handle)5288 static int hns3_client_init(struct hnae3_handle *handle)
5289 {
5290 struct pci_dev *pdev = handle->pdev;
5291 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
5292 u16 alloc_tqps, max_rss_size;
5293 struct hns3_nic_priv *priv;
5294 struct net_device *netdev;
5295 int ret;
5296
5297 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
5298 &max_rss_size);
5299 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
5300 if (!netdev)
5301 return -ENOMEM;
5302
5303 priv = netdev_priv(netdev);
5304 priv->dev = &pdev->dev;
5305 priv->netdev = netdev;
5306 priv->ae_handle = handle;
5307 priv->tx_timeout_count = 0;
5308 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num;
5309 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
5310
5311 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
5312
5313 handle->kinfo.netdev = netdev;
5314 handle->priv = (void *)priv;
5315
5316 hns3_init_mac_addr(netdev);
5317
5318 hns3_set_default_feature(netdev);
5319
5320 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
5321 netdev->priv_flags |= IFF_UNICAST_FLT;
5322 netdev->netdev_ops = &hns3_nic_netdev_ops;
5323 SET_NETDEV_DEV(netdev, &pdev->dev);
5324 hns3_ethtool_set_ops(netdev);
5325
5326 /* Carrier off reporting is important to ethtool even BEFORE open */
5327 netif_carrier_off(netdev);
5328
5329 ret = hns3_get_ring_config(priv);
5330 if (ret) {
5331 ret = -ENOMEM;
5332 goto out_get_ring_cfg;
5333 }
5334
5335 hns3_nic_init_coal_cfg(priv);
5336
5337 ret = hns3_nic_alloc_vector_data(priv);
5338 if (ret) {
5339 ret = -ENOMEM;
5340 goto out_alloc_vector_data;
5341 }
5342
5343 ret = hns3_nic_init_vector_data(priv);
5344 if (ret) {
5345 ret = -ENOMEM;
5346 goto out_init_vector_data;
5347 }
5348
5349 ret = hns3_init_all_ring(priv);
5350 if (ret) {
5351 ret = -ENOMEM;
5352 goto out_init_ring;
5353 }
5354
5355 hns3_cq_period_mode_init(priv, DIM_CQ_PERIOD_MODE_START_FROM_EQE,
5356 DIM_CQ_PERIOD_MODE_START_FROM_EQE);
5357
5358 ret = hns3_init_phy(netdev);
5359 if (ret)
5360 goto out_init_phy;
5361
5362 /* the device can work without cpu rmap, only aRFS needs it */
5363 ret = hns3_set_rx_cpu_rmap(netdev);
5364 if (ret)
5365 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5366
5367 ret = hns3_nic_init_irq(priv);
5368 if (ret) {
5369 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5370 hns3_free_rx_cpu_rmap(netdev);
5371 goto out_init_irq_fail;
5372 }
5373
5374 ret = hns3_client_start(handle);
5375 if (ret) {
5376 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
5377 goto out_client_start;
5378 }
5379
5380 hns3_dcbnl_setup(handle);
5381
5382 ret = hns3_dbg_init(handle);
5383 if (ret) {
5384 dev_err(priv->dev, "failed to init debugfs, ret = %d\n",
5385 ret);
5386 goto out_client_start;
5387 }
5388
5389 netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size);
5390
5391 hns3_state_init(handle);
5392
5393 ret = register_netdev(netdev);
5394 if (ret) {
5395 dev_err(priv->dev, "probe register netdev fail!\n");
5396 goto out_reg_netdev_fail;
5397 }
5398
5399 if (netif_msg_drv(handle))
5400 hns3_info_show(priv);
5401
5402 return ret;
5403
5404 out_reg_netdev_fail:
5405 hns3_state_uninit(handle);
5406 hns3_dbg_uninit(handle);
5407 hns3_client_stop(handle);
5408 out_client_start:
5409 hns3_free_rx_cpu_rmap(netdev);
5410 hns3_nic_uninit_irq(priv);
5411 out_init_irq_fail:
5412 hns3_uninit_phy(netdev);
5413 out_init_phy:
5414 hns3_uninit_all_ring(priv);
5415 out_init_ring:
5416 hns3_nic_uninit_vector_data(priv);
5417 out_init_vector_data:
5418 hns3_nic_dealloc_vector_data(priv);
5419 out_alloc_vector_data:
5420 priv->ring = NULL;
5421 out_get_ring_cfg:
5422 priv->ae_handle = NULL;
5423 free_netdev(netdev);
5424 return ret;
5425 }
5426
hns3_client_uninit(struct hnae3_handle * handle,bool reset)5427 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
5428 {
5429 struct net_device *netdev = handle->kinfo.netdev;
5430 struct hns3_nic_priv *priv = netdev_priv(netdev);
5431
5432 if (netdev->reg_state != NETREG_UNINITIALIZED)
5433 unregister_netdev(netdev);
5434
5435 hns3_client_stop(handle);
5436
5437 hns3_uninit_phy(netdev);
5438
5439 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5440 netdev_warn(netdev, "already uninitialized\n");
5441 goto out_netdev_free;
5442 }
5443
5444 hns3_free_rx_cpu_rmap(netdev);
5445
5446 hns3_nic_uninit_irq(priv);
5447
5448 hns3_clear_all_ring(handle, true);
5449
5450 hns3_nic_uninit_vector_data(priv);
5451
5452 hns3_nic_dealloc_vector_data(priv);
5453
5454 hns3_uninit_all_ring(priv);
5455
5456 hns3_put_ring_config(priv);
5457
5458 out_netdev_free:
5459 hns3_dbg_uninit(handle);
5460 free_netdev(netdev);
5461 }
5462
hns3_link_status_change(struct hnae3_handle * handle,bool linkup)5463 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
5464 {
5465 struct net_device *netdev = handle->kinfo.netdev;
5466
5467 if (!netdev)
5468 return;
5469
5470 if (linkup) {
5471 netif_tx_wake_all_queues(netdev);
5472 netif_carrier_on(netdev);
5473 if (netif_msg_link(handle))
5474 netdev_info(netdev, "link up\n");
5475 } else {
5476 netif_carrier_off(netdev);
5477 netif_tx_stop_all_queues(netdev);
5478 if (netif_msg_link(handle))
5479 netdev_info(netdev, "link down\n");
5480 }
5481 }
5482
hns3_clear_tx_ring(struct hns3_enet_ring * ring)5483 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
5484 {
5485 while (ring->next_to_clean != ring->next_to_use) {
5486 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
5487 hns3_free_buffer_detach(ring, ring->next_to_clean, 0);
5488 ring_ptr_move_fw(ring, next_to_clean);
5489 }
5490
5491 ring->pending_buf = 0;
5492 }
5493
hns3_clear_rx_ring(struct hns3_enet_ring * ring)5494 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
5495 {
5496 struct hns3_desc_cb res_cbs;
5497 int ret;
5498
5499 while (ring->next_to_use != ring->next_to_clean) {
5500 /* When a buffer is not reused, it's memory has been
5501 * freed in hns3_handle_rx_bd or will be freed by
5502 * stack, so we need to replace the buffer here.
5503 */
5504 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5505 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
5506 if (ret) {
5507 hns3_ring_stats_update(ring, sw_err_cnt);
5508 /* if alloc new buffer fail, exit directly
5509 * and reclear in up flow.
5510 */
5511 netdev_warn(ring_to_netdev(ring),
5512 "reserve buffer map failed, ret = %d\n",
5513 ret);
5514 return ret;
5515 }
5516 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
5517 }
5518 ring_ptr_move_fw(ring, next_to_use);
5519 }
5520
5521 /* Free the pending skb in rx ring */
5522 if (ring->skb) {
5523 dev_kfree_skb_any(ring->skb);
5524 ring->skb = NULL;
5525 ring->pending_buf = 0;
5526 }
5527
5528 return 0;
5529 }
5530
hns3_force_clear_rx_ring(struct hns3_enet_ring * ring)5531 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
5532 {
5533 while (ring->next_to_use != ring->next_to_clean) {
5534 /* When a buffer is not reused, it's memory has been
5535 * freed in hns3_handle_rx_bd or will be freed by
5536 * stack, so only need to unmap the buffer here.
5537 */
5538 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5539 hns3_unmap_buffer(ring,
5540 &ring->desc_cb[ring->next_to_use]);
5541 ring->desc_cb[ring->next_to_use].dma = 0;
5542 }
5543
5544 ring_ptr_move_fw(ring, next_to_use);
5545 }
5546 }
5547
hns3_clear_all_ring(struct hnae3_handle * h,bool force)5548 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
5549 {
5550 struct net_device *ndev = h->kinfo.netdev;
5551 struct hns3_nic_priv *priv = netdev_priv(ndev);
5552 u32 i;
5553
5554 for (i = 0; i < h->kinfo.num_tqps; i++) {
5555 struct hns3_enet_ring *ring;
5556
5557 ring = &priv->ring[i];
5558 hns3_clear_tx_ring(ring);
5559
5560 ring = &priv->ring[i + h->kinfo.num_tqps];
5561 /* Continue to clear other rings even if clearing some
5562 * rings failed.
5563 */
5564 if (force)
5565 hns3_force_clear_rx_ring(ring);
5566 else
5567 hns3_clear_rx_ring(ring);
5568 }
5569 }
5570
hns3_nic_reset_all_ring(struct hnae3_handle * h)5571 int hns3_nic_reset_all_ring(struct hnae3_handle *h)
5572 {
5573 struct net_device *ndev = h->kinfo.netdev;
5574 struct hns3_nic_priv *priv = netdev_priv(ndev);
5575 struct hns3_enet_ring *rx_ring;
5576 int i, j;
5577 int ret;
5578
5579 ret = h->ae_algo->ops->reset_queue(h);
5580 if (ret)
5581 return ret;
5582
5583 for (i = 0; i < h->kinfo.num_tqps; i++) {
5584 hns3_init_ring_hw(&priv->ring[i]);
5585
5586 /* We need to clear tx ring here because self test will
5587 * use the ring and will not run down before up
5588 */
5589 hns3_clear_tx_ring(&priv->ring[i]);
5590 priv->ring[i].next_to_clean = 0;
5591 priv->ring[i].next_to_use = 0;
5592 priv->ring[i].last_to_use = 0;
5593
5594 rx_ring = &priv->ring[i + h->kinfo.num_tqps];
5595 hns3_init_ring_hw(rx_ring);
5596 ret = hns3_clear_rx_ring(rx_ring);
5597 if (ret)
5598 return ret;
5599
5600 /* We can not know the hardware head and tail when this
5601 * function is called in reset flow, so we reuse all desc.
5602 */
5603 for (j = 0; j < rx_ring->desc_num; j++)
5604 hns3_reuse_buffer(rx_ring, j);
5605
5606 rx_ring->next_to_clean = 0;
5607 rx_ring->next_to_use = 0;
5608 }
5609
5610 hns3_init_tx_ring_tc(priv);
5611
5612 return 0;
5613 }
5614
hns3_reset_notify_down_enet(struct hnae3_handle * handle)5615 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
5616 {
5617 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5618 struct net_device *ndev = kinfo->netdev;
5619 struct hns3_nic_priv *priv = netdev_priv(ndev);
5620
5621 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
5622 return 0;
5623
5624 if (!netif_running(ndev))
5625 return 0;
5626
5627 return hns3_nic_net_stop(ndev);
5628 }
5629
hns3_reset_notify_up_enet(struct hnae3_handle * handle)5630 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
5631 {
5632 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5633 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
5634 int ret = 0;
5635
5636 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5637 netdev_err(kinfo->netdev, "device is not initialized yet\n");
5638 return -EFAULT;
5639 }
5640
5641 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5642
5643 if (netif_running(kinfo->netdev)) {
5644 ret = hns3_nic_net_open(kinfo->netdev);
5645 if (ret) {
5646 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5647 netdev_err(kinfo->netdev,
5648 "net up fail, ret=%d!\n", ret);
5649 return ret;
5650 }
5651 }
5652
5653 return ret;
5654 }
5655
hns3_reset_notify_init_enet(struct hnae3_handle * handle)5656 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
5657 {
5658 struct net_device *netdev = handle->kinfo.netdev;
5659 struct hns3_nic_priv *priv = netdev_priv(netdev);
5660 int ret;
5661
5662 /* Carrier off reporting is important to ethtool even BEFORE open */
5663 netif_carrier_off(netdev);
5664
5665 ret = hns3_get_ring_config(priv);
5666 if (ret)
5667 return ret;
5668
5669 ret = hns3_nic_alloc_vector_data(priv);
5670 if (ret)
5671 goto err_put_ring;
5672
5673 ret = hns3_nic_init_vector_data(priv);
5674 if (ret)
5675 goto err_dealloc_vector;
5676
5677 ret = hns3_init_all_ring(priv);
5678 if (ret)
5679 goto err_uninit_vector;
5680
5681 hns3_cq_period_mode_init(priv, priv->tx_cqe_mode, priv->rx_cqe_mode);
5682
5683 /* the device can work without cpu rmap, only aRFS needs it */
5684 ret = hns3_set_rx_cpu_rmap(netdev);
5685 if (ret)
5686 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5687
5688 ret = hns3_nic_init_irq(priv);
5689 if (ret) {
5690 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5691 hns3_free_rx_cpu_rmap(netdev);
5692 goto err_init_irq_fail;
5693 }
5694
5695 if (!hns3_is_phys_func(handle->pdev))
5696 hns3_init_mac_addr(netdev);
5697
5698 ret = hns3_client_start(handle);
5699 if (ret) {
5700 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
5701 goto err_client_start_fail;
5702 }
5703
5704 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5705
5706 return ret;
5707
5708 err_client_start_fail:
5709 hns3_free_rx_cpu_rmap(netdev);
5710 hns3_nic_uninit_irq(priv);
5711 err_init_irq_fail:
5712 hns3_uninit_all_ring(priv);
5713 err_uninit_vector:
5714 hns3_nic_uninit_vector_data(priv);
5715 err_dealloc_vector:
5716 hns3_nic_dealloc_vector_data(priv);
5717 err_put_ring:
5718 hns3_put_ring_config(priv);
5719
5720 return ret;
5721 }
5722
hns3_reset_notify_uninit_enet(struct hnae3_handle * handle)5723 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
5724 {
5725 struct net_device *netdev = handle->kinfo.netdev;
5726 struct hns3_nic_priv *priv = netdev_priv(netdev);
5727
5728 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5729 netdev_warn(netdev, "already uninitialized\n");
5730 return 0;
5731 }
5732
5733 hns3_free_rx_cpu_rmap(netdev);
5734 hns3_nic_uninit_irq(priv);
5735 hns3_clear_all_ring(handle, true);
5736 hns3_reset_tx_queue(priv->ae_handle);
5737
5738 hns3_nic_uninit_vector_data(priv);
5739
5740 hns3_nic_dealloc_vector_data(priv);
5741
5742 hns3_uninit_all_ring(priv);
5743
5744 hns3_put_ring_config(priv);
5745
5746 return 0;
5747 }
5748
hns3_reset_notify(struct hnae3_handle * handle,enum hnae3_reset_notify_type type)5749 int hns3_reset_notify(struct hnae3_handle *handle,
5750 enum hnae3_reset_notify_type type)
5751 {
5752 int ret = 0;
5753
5754 switch (type) {
5755 case HNAE3_UP_CLIENT:
5756 ret = hns3_reset_notify_up_enet(handle);
5757 break;
5758 case HNAE3_DOWN_CLIENT:
5759 ret = hns3_reset_notify_down_enet(handle);
5760 break;
5761 case HNAE3_INIT_CLIENT:
5762 ret = hns3_reset_notify_init_enet(handle);
5763 break;
5764 case HNAE3_UNINIT_CLIENT:
5765 ret = hns3_reset_notify_uninit_enet(handle);
5766 break;
5767 default:
5768 break;
5769 }
5770
5771 return ret;
5772 }
5773
hns3_change_channels(struct hnae3_handle * handle,u32 new_tqp_num,bool rxfh_configured)5774 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
5775 bool rxfh_configured)
5776 {
5777 int ret;
5778
5779 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
5780 rxfh_configured);
5781 if (ret) {
5782 dev_err(&handle->pdev->dev,
5783 "Change tqp num(%u) fail.\n", new_tqp_num);
5784 return ret;
5785 }
5786
5787 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
5788 if (ret)
5789 return ret;
5790
5791 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT);
5792 if (ret)
5793 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
5794
5795 return ret;
5796 }
5797
hns3_set_channels(struct net_device * netdev,struct ethtool_channels * ch)5798 int hns3_set_channels(struct net_device *netdev,
5799 struct ethtool_channels *ch)
5800 {
5801 struct hnae3_handle *h = hns3_get_handle(netdev);
5802 struct hnae3_knic_private_info *kinfo = &h->kinfo;
5803 bool rxfh_configured = netif_is_rxfh_configured(netdev);
5804 u32 new_tqp_num = ch->combined_count;
5805 u16 org_tqp_num;
5806 int ret;
5807
5808 if (hns3_nic_resetting(netdev))
5809 return -EBUSY;
5810
5811 if (ch->rx_count || ch->tx_count)
5812 return -EINVAL;
5813
5814 if (kinfo->tc_info.mqprio_active) {
5815 dev_err(&netdev->dev,
5816 "it's not allowed to set channels via ethtool when MQPRIO mode is on\n");
5817 return -EINVAL;
5818 }
5819
5820 if (new_tqp_num > hns3_get_max_available_channels(h) ||
5821 new_tqp_num < 1) {
5822 dev_err(&netdev->dev,
5823 "Change tqps fail, the tqp range is from 1 to %u",
5824 hns3_get_max_available_channels(h));
5825 return -EINVAL;
5826 }
5827
5828 if (kinfo->rss_size == new_tqp_num)
5829 return 0;
5830
5831 netif_dbg(h, drv, netdev,
5832 "set channels: tqp_num=%u, rxfh=%d\n",
5833 new_tqp_num, rxfh_configured);
5834
5835 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
5836 if (ret)
5837 return ret;
5838
5839 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
5840 if (ret)
5841 return ret;
5842
5843 org_tqp_num = h->kinfo.num_tqps;
5844 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
5845 if (ret) {
5846 int ret1;
5847
5848 netdev_warn(netdev,
5849 "Change channels fail, revert to old value\n");
5850 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
5851 if (ret1) {
5852 netdev_err(netdev,
5853 "revert to old channel fail\n");
5854 return ret1;
5855 }
5856
5857 return ret;
5858 }
5859
5860 return 0;
5861 }
5862
hns3_external_lb_prepare(struct net_device * ndev,bool if_running)5863 void hns3_external_lb_prepare(struct net_device *ndev, bool if_running)
5864 {
5865 struct hns3_nic_priv *priv = netdev_priv(ndev);
5866 struct hnae3_handle *h = priv->ae_handle;
5867 int i;
5868
5869 if (!if_running)
5870 return;
5871
5872 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
5873 return;
5874
5875 netif_carrier_off(ndev);
5876 netif_tx_disable(ndev);
5877
5878 for (i = 0; i < priv->vector_num; i++)
5879 hns3_vector_disable(&priv->tqp_vector[i]);
5880
5881 for (i = 0; i < h->kinfo.num_tqps; i++)
5882 hns3_tqp_disable(h->kinfo.tqp[i]);
5883
5884 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
5885 * during reset process, because driver may not be able
5886 * to disable the ring through firmware when downing the netdev.
5887 */
5888 if (!hns3_nic_resetting(ndev))
5889 hns3_nic_reset_all_ring(priv->ae_handle);
5890
5891 hns3_reset_tx_queue(priv->ae_handle);
5892 }
5893
hns3_external_lb_restore(struct net_device * ndev,bool if_running)5894 void hns3_external_lb_restore(struct net_device *ndev, bool if_running)
5895 {
5896 struct hns3_nic_priv *priv = netdev_priv(ndev);
5897 struct hnae3_handle *h = priv->ae_handle;
5898 int i;
5899
5900 if (!if_running)
5901 return;
5902
5903 if (hns3_nic_resetting(ndev))
5904 return;
5905
5906 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
5907 return;
5908
5909 if (hns3_nic_reset_all_ring(priv->ae_handle))
5910 return;
5911
5912 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
5913
5914 for (i = 0; i < priv->vector_num; i++)
5915 hns3_vector_enable(&priv->tqp_vector[i]);
5916
5917 for (i = 0; i < h->kinfo.num_tqps; i++)
5918 hns3_tqp_enable(h->kinfo.tqp[i]);
5919
5920 netif_tx_wake_all_queues(ndev);
5921
5922 if (h->ae_algo->ops->get_status(h))
5923 netif_carrier_on(ndev);
5924 }
5925
5926 static const struct hns3_hw_error_info hns3_hw_err[] = {
5927 { .type = HNAE3_PPU_POISON_ERROR,
5928 .msg = "PPU poison" },
5929 { .type = HNAE3_CMDQ_ECC_ERROR,
5930 .msg = "IMP CMDQ error" },
5931 { .type = HNAE3_IMP_RD_POISON_ERROR,
5932 .msg = "IMP RD poison" },
5933 { .type = HNAE3_ROCEE_AXI_RESP_ERROR,
5934 .msg = "ROCEE AXI RESP error" },
5935 };
5936
hns3_process_hw_error(struct hnae3_handle * handle,enum hnae3_hw_error_type type)5937 static void hns3_process_hw_error(struct hnae3_handle *handle,
5938 enum hnae3_hw_error_type type)
5939 {
5940 int i;
5941
5942 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
5943 if (hns3_hw_err[i].type == type) {
5944 dev_err(&handle->pdev->dev, "Detected %s!\n",
5945 hns3_hw_err[i].msg);
5946 break;
5947 }
5948 }
5949 }
5950
5951 static const struct hnae3_client_ops client_ops = {
5952 .init_instance = hns3_client_init,
5953 .uninit_instance = hns3_client_uninit,
5954 .link_status_change = hns3_link_status_change,
5955 .reset_notify = hns3_reset_notify,
5956 .process_hw_error = hns3_process_hw_error,
5957 };
5958
5959 /* hns3_init_module - Driver registration routine
5960 * hns3_init_module is the first routine called when the driver is
5961 * loaded. All it does is register with the PCI subsystem.
5962 */
hns3_init_module(void)5963 static int __init hns3_init_module(void)
5964 {
5965 int ret;
5966
5967 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
5968 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
5969
5970 client.type = HNAE3_CLIENT_KNIC;
5971 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s",
5972 hns3_driver_name);
5973
5974 client.ops = &client_ops;
5975
5976 INIT_LIST_HEAD(&client.node);
5977
5978 hns3_dbg_register_debugfs(hns3_driver_name);
5979
5980 ret = hnae3_register_client(&client);
5981 if (ret)
5982 goto err_reg_client;
5983
5984 ret = pci_register_driver(&hns3_driver);
5985 if (ret)
5986 goto err_reg_driver;
5987
5988 return ret;
5989
5990 err_reg_driver:
5991 hnae3_unregister_client(&client);
5992 err_reg_client:
5993 hns3_dbg_unregister_debugfs();
5994 return ret;
5995 }
5996 module_init(hns3_init_module);
5997
5998 /* hns3_exit_module - Driver exit cleanup routine
5999 * hns3_exit_module is called just before the driver is removed
6000 * from memory.
6001 */
hns3_exit_module(void)6002 static void __exit hns3_exit_module(void)
6003 {
6004 pci_unregister_driver(&hns3_driver);
6005 hnae3_unregister_client(&client);
6006 hns3_dbg_unregister_debugfs();
6007 }
6008 module_exit(hns3_exit_module);
6009
6010 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
6011 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6012 MODULE_LICENSE("GPL");
6013 MODULE_ALIAS("pci:hns-nic");
6014
