1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *
4  *   Copyright (C) 2011 John Crispin <john@phrozen.org>
5  */
6 
7 #include <linux/init.h>
8 #include <linux/platform_device.h>
9 #include <linux/io.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/export.h>
12 #include <linux/spinlock.h>
13 #include <linux/clk.h>
14 #include <linux/err.h>
15 #include <linux/of.h>
16 
17 #include <lantiq_soc.h>
18 #include <xway_dma.h>
19 
20 #define LTQ_DMA_ID		0x08
21 #define LTQ_DMA_CTRL		0x10
22 #define LTQ_DMA_CPOLL		0x14
23 #define LTQ_DMA_CS		0x18
24 #define LTQ_DMA_CCTRL		0x1C
25 #define LTQ_DMA_CDBA		0x20
26 #define LTQ_DMA_CDLEN		0x24
27 #define LTQ_DMA_CIS		0x28
28 #define LTQ_DMA_CIE		0x2C
29 #define LTQ_DMA_PS		0x40
30 #define LTQ_DMA_PCTRL		0x44
31 #define LTQ_DMA_IRNEN		0xf4
32 
33 #define DMA_DESCPT		BIT(3)		/* descriptor complete irq */
34 #define DMA_TX			BIT(8)		/* TX channel direction */
35 #define DMA_CHAN_ON		BIT(0)		/* channel on / off bit */
36 #define DMA_PDEN		BIT(6)		/* enable packet drop */
37 #define DMA_CHAN_RST		BIT(1)		/* channel on / off bit */
38 #define DMA_RESET		BIT(0)		/* channel on / off bit */
39 #define DMA_IRQ_ACK		0x7e		/* IRQ status register */
40 #define DMA_POLL		BIT(31)		/* turn on channel polling */
41 #define DMA_CLK_DIV4		BIT(6)		/* polling clock divider */
42 #define DMA_2W_BURST		BIT(1)		/* 2 word burst length */
43 #define DMA_MAX_CHANNEL		20		/* the soc has 20 channels */
44 #define DMA_ETOP_ENDIANNESS	(0xf << 8) /* endianness swap etop channels */
45 #define DMA_WEIGHT	(BIT(17) | BIT(16))	/* default channel wheight */
46 
47 #define ltq_dma_r32(x)			ltq_r32(ltq_dma_membase + (x))
48 #define ltq_dma_w32(x, y)		ltq_w32(x, ltq_dma_membase + (y))
49 #define ltq_dma_w32_mask(x, y, z)	ltq_w32_mask(x, y, \
50 						ltq_dma_membase + (z))
51 
52 static void __iomem *ltq_dma_membase;
53 static DEFINE_SPINLOCK(ltq_dma_lock);
54 
55 void
ltq_dma_enable_irq(struct ltq_dma_channel * ch)56 ltq_dma_enable_irq(struct ltq_dma_channel *ch)
57 {
58 	unsigned long flags;
59 
60 	spin_lock_irqsave(&ltq_dma_lock, flags);
61 	ltq_dma_w32(ch->nr, LTQ_DMA_CS);
62 	ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
63 	spin_unlock_irqrestore(&ltq_dma_lock, flags);
64 }
65 EXPORT_SYMBOL_GPL(ltq_dma_enable_irq);
66 
67 void
ltq_dma_disable_irq(struct ltq_dma_channel * ch)68 ltq_dma_disable_irq(struct ltq_dma_channel *ch)
69 {
70 	unsigned long flags;
71 
72 	spin_lock_irqsave(&ltq_dma_lock, flags);
73 	ltq_dma_w32(ch->nr, LTQ_DMA_CS);
74 	ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);
75 	spin_unlock_irqrestore(&ltq_dma_lock, flags);
76 }
77 EXPORT_SYMBOL_GPL(ltq_dma_disable_irq);
78 
79 void
ltq_dma_ack_irq(struct ltq_dma_channel * ch)80 ltq_dma_ack_irq(struct ltq_dma_channel *ch)
81 {
82 	unsigned long flags;
83 
84 	spin_lock_irqsave(&ltq_dma_lock, flags);
85 	ltq_dma_w32(ch->nr, LTQ_DMA_CS);
86 	ltq_dma_w32(DMA_IRQ_ACK, LTQ_DMA_CIS);
87 	spin_unlock_irqrestore(&ltq_dma_lock, flags);
88 }
89 EXPORT_SYMBOL_GPL(ltq_dma_ack_irq);
90 
91 void
ltq_dma_open(struct ltq_dma_channel * ch)92 ltq_dma_open(struct ltq_dma_channel *ch)
93 {
94 	unsigned long flag;
95 
96 	spin_lock_irqsave(&ltq_dma_lock, flag);
97 	ltq_dma_w32(ch->nr, LTQ_DMA_CS);
98 	ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL);
99 	spin_unlock_irqrestore(&ltq_dma_lock, flag);
100 }
101 EXPORT_SYMBOL_GPL(ltq_dma_open);
102 
103 void
ltq_dma_close(struct ltq_dma_channel * ch)104 ltq_dma_close(struct ltq_dma_channel *ch)
105 {
106 	unsigned long flag;
107 
108 	spin_lock_irqsave(&ltq_dma_lock, flag);
109 	ltq_dma_w32(ch->nr, LTQ_DMA_CS);
110 	ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
111 	ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);
112 	spin_unlock_irqrestore(&ltq_dma_lock, flag);
113 }
114 EXPORT_SYMBOL_GPL(ltq_dma_close);
115 
116 static void
ltq_dma_alloc(struct ltq_dma_channel * ch)117 ltq_dma_alloc(struct ltq_dma_channel *ch)
118 {
119 	unsigned long flags;
120 
121 	ch->desc = 0;
122 	ch->desc_base = dma_alloc_coherent(ch->dev,
123 					   LTQ_DESC_NUM * LTQ_DESC_SIZE,
124 					   &ch->phys, GFP_ATOMIC);
125 
126 	spin_lock_irqsave(&ltq_dma_lock, flags);
127 	ltq_dma_w32(ch->nr, LTQ_DMA_CS);
128 	ltq_dma_w32(ch->phys, LTQ_DMA_CDBA);
129 	ltq_dma_w32(LTQ_DESC_NUM, LTQ_DMA_CDLEN);
130 	ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
131 	wmb();
132 	ltq_dma_w32_mask(0, DMA_CHAN_RST, LTQ_DMA_CCTRL);
133 	while (ltq_dma_r32(LTQ_DMA_CCTRL) & DMA_CHAN_RST)
134 		;
135 	spin_unlock_irqrestore(&ltq_dma_lock, flags);
136 }
137 
138 void
ltq_dma_alloc_tx(struct ltq_dma_channel * ch)139 ltq_dma_alloc_tx(struct ltq_dma_channel *ch)
140 {
141 	unsigned long flags;
142 
143 	ltq_dma_alloc(ch);
144 
145 	spin_lock_irqsave(&ltq_dma_lock, flags);
146 	ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
147 	ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
148 	ltq_dma_w32(DMA_WEIGHT | DMA_TX, LTQ_DMA_CCTRL);
149 	spin_unlock_irqrestore(&ltq_dma_lock, flags);
150 }
151 EXPORT_SYMBOL_GPL(ltq_dma_alloc_tx);
152 
153 void
ltq_dma_alloc_rx(struct ltq_dma_channel * ch)154 ltq_dma_alloc_rx(struct ltq_dma_channel *ch)
155 {
156 	unsigned long flags;
157 
158 	ltq_dma_alloc(ch);
159 
160 	spin_lock_irqsave(&ltq_dma_lock, flags);
161 	ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
162 	ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
163 	ltq_dma_w32(DMA_WEIGHT, LTQ_DMA_CCTRL);
164 	spin_unlock_irqrestore(&ltq_dma_lock, flags);
165 }
166 EXPORT_SYMBOL_GPL(ltq_dma_alloc_rx);
167 
168 void
ltq_dma_free(struct ltq_dma_channel * ch)169 ltq_dma_free(struct ltq_dma_channel *ch)
170 {
171 	if (!ch->desc_base)
172 		return;
173 	ltq_dma_close(ch);
174 	dma_free_coherent(ch->dev, LTQ_DESC_NUM * LTQ_DESC_SIZE,
175 		ch->desc_base, ch->phys);
176 }
177 EXPORT_SYMBOL_GPL(ltq_dma_free);
178 
179 void
ltq_dma_init_port(int p)180 ltq_dma_init_port(int p)
181 {
182 	ltq_dma_w32(p, LTQ_DMA_PS);
183 	switch (p) {
184 	case DMA_PORT_ETOP:
185 		/*
186 		 * Tell the DMA engine to swap the endianness of data frames and
187 		 * drop packets if the channel arbitration fails.
188 		 */
189 		ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN,
190 			LTQ_DMA_PCTRL);
191 		break;
192 
193 	case DMA_PORT_DEU:
194 		ltq_dma_w32((DMA_2W_BURST << 4) | (DMA_2W_BURST << 2),
195 			LTQ_DMA_PCTRL);
196 		break;
197 
198 	default:
199 		break;
200 	}
201 }
202 EXPORT_SYMBOL_GPL(ltq_dma_init_port);
203 
204 static int
ltq_dma_init(struct platform_device * pdev)205 ltq_dma_init(struct platform_device *pdev)
206 {
207 	struct clk *clk;
208 	struct resource *res;
209 	unsigned id;
210 	int i;
211 
212 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
213 	ltq_dma_membase = devm_ioremap_resource(&pdev->dev, res);
214 	if (IS_ERR(ltq_dma_membase))
215 		panic("Failed to remap dma resource");
216 
217 	/* power up and reset the dma engine */
218 	clk = clk_get(&pdev->dev, NULL);
219 	if (IS_ERR(clk))
220 		panic("Failed to get dma clock");
221 
222 	clk_enable(clk);
223 	ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL);
224 
225 	/* disable all interrupts */
226 	ltq_dma_w32(0, LTQ_DMA_IRNEN);
227 
228 	/* reset/configure each channel */
229 	for (i = 0; i < DMA_MAX_CHANNEL; i++) {
230 		ltq_dma_w32(i, LTQ_DMA_CS);
231 		ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL);
232 		ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL);
233 		ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
234 	}
235 
236 	id = ltq_dma_r32(LTQ_DMA_ID);
237 	dev_info(&pdev->dev,
238 		"Init done - hw rev: %X, ports: %d, channels: %d\n",
239 		id & 0x1f, (id >> 16) & 0xf, id >> 20);
240 
241 	return 0;
242 }
243 
244 static const struct of_device_id dma_match[] = {
245 	{ .compatible = "lantiq,dma-xway" },
246 	{},
247 };
248 
249 static struct platform_driver dma_driver = {
250 	.probe = ltq_dma_init,
251 	.driver = {
252 		.name = "dma-xway",
253 		.of_match_table = dma_match,
254 	},
255 };
256 
257 int __init
dma_init(void)258 dma_init(void)
259 {
260 	return platform_driver_register(&dma_driver);
261 }
262 
263 postcore_initcall(dma_init);
264