1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Generation of main entry point for the guest, exception handling.
7 *
8 * Copyright (C) 2012 MIPS Technologies, Inc.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
10 *
11 * Copyright (C) 2016 Imagination Technologies Ltd.
12 */
13
14 #include <linux/kvm_host.h>
15 #include <linux/log2.h>
16 #include <asm/mmu_context.h>
17 #include <asm/msa.h>
18 #include <asm/setup.h>
19 #include <asm/tlbex.h>
20 #include <asm/uasm.h>
21
22 /* Register names */
23 #define ZERO 0
24 #define AT 1
25 #define V0 2
26 #define V1 3
27 #define A0 4
28 #define A1 5
29
30 #if _MIPS_SIM == _MIPS_SIM_ABI32
31 #define T0 8
32 #define T1 9
33 #define T2 10
34 #define T3 11
35 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
36
37 #if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
38 #define T0 12
39 #define T1 13
40 #define T2 14
41 #define T3 15
42 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
43
44 #define S0 16
45 #define S1 17
46 #define T9 25
47 #define K0 26
48 #define K1 27
49 #define GP 28
50 #define SP 29
51 #define RA 31
52
53 /* Some CP0 registers */
54 #define C0_PWBASE 5, 5
55 #define C0_HWRENA 7, 0
56 #define C0_BADVADDR 8, 0
57 #define C0_BADINSTR 8, 1
58 #define C0_BADINSTRP 8, 2
59 #define C0_PGD 9, 7
60 #define C0_ENTRYHI 10, 0
61 #define C0_GUESTCTL1 10, 4
62 #define C0_STATUS 12, 0
63 #define C0_GUESTCTL0 12, 6
64 #define C0_CAUSE 13, 0
65 #define C0_EPC 14, 0
66 #define C0_EBASE 15, 1
67 #define C0_CONFIG5 16, 5
68 #define C0_DDATA_LO 28, 3
69 #define C0_ERROREPC 30, 0
70
71 #define CALLFRAME_SIZ 32
72
73 #ifdef CONFIG_64BIT
74 #define ST0_KX_IF_64 ST0_KX
75 #else
76 #define ST0_KX_IF_64 0
77 #endif
78
79 static unsigned int scratch_vcpu[2] = { C0_DDATA_LO };
80 static unsigned int scratch_tmp[2] = { C0_ERROREPC };
81
82 enum label_id {
83 label_fpu_1 = 1,
84 label_msa_1,
85 label_return_to_host,
86 label_kernel_asid,
87 label_exit_common,
88 };
89
90 UASM_L_LA(_fpu_1)
91 UASM_L_LA(_msa_1)
92 UASM_L_LA(_return_to_host)
93 UASM_L_LA(_kernel_asid)
94 UASM_L_LA(_exit_common)
95
96 static void *kvm_mips_build_enter_guest(void *addr);
97 static void *kvm_mips_build_ret_from_exit(void *addr);
98 static void *kvm_mips_build_ret_to_guest(void *addr);
99 static void *kvm_mips_build_ret_to_host(void *addr);
100
101 /*
102 * The version of this function in tlbex.c uses current_cpu_type(), but for KVM
103 * we assume symmetry.
104 */
c0_kscratch(void)105 static int c0_kscratch(void)
106 {
107 switch (boot_cpu_type()) {
108 case CPU_XLP:
109 case CPU_XLR:
110 return 22;
111 default:
112 return 31;
113 }
114 }
115
116 /**
117 * kvm_mips_entry_setup() - Perform global setup for entry code.
118 *
119 * Perform global setup for entry code, such as choosing a scratch register.
120 *
121 * Returns: 0 on success.
122 * -errno on failure.
123 */
kvm_mips_entry_setup(void)124 int kvm_mips_entry_setup(void)
125 {
126 /*
127 * We prefer to use KScratchN registers if they are available over the
128 * defaults above, which may not work on all cores.
129 */
130 unsigned int kscratch_mask = cpu_data[0].kscratch_mask;
131
132 if (pgd_reg != -1)
133 kscratch_mask &= ~BIT(pgd_reg);
134
135 /* Pick a scratch register for storing VCPU */
136 if (kscratch_mask) {
137 scratch_vcpu[0] = c0_kscratch();
138 scratch_vcpu[1] = ffs(kscratch_mask) - 1;
139 kscratch_mask &= ~BIT(scratch_vcpu[1]);
140 }
141
142 /* Pick a scratch register to use as a temp for saving state */
143 if (kscratch_mask) {
144 scratch_tmp[0] = c0_kscratch();
145 scratch_tmp[1] = ffs(kscratch_mask) - 1;
146 kscratch_mask &= ~BIT(scratch_tmp[1]);
147 }
148
149 return 0;
150 }
151
kvm_mips_build_save_scratch(u32 ** p,unsigned int tmp,unsigned int frame)152 static void kvm_mips_build_save_scratch(u32 **p, unsigned int tmp,
153 unsigned int frame)
154 {
155 /* Save the VCPU scratch register value in cp0_epc of the stack frame */
156 UASM_i_MFC0(p, tmp, scratch_vcpu[0], scratch_vcpu[1]);
157 UASM_i_SW(p, tmp, offsetof(struct pt_regs, cp0_epc), frame);
158
159 /* Save the temp scratch register value in cp0_cause of stack frame */
160 if (scratch_tmp[0] == c0_kscratch()) {
161 UASM_i_MFC0(p, tmp, scratch_tmp[0], scratch_tmp[1]);
162 UASM_i_SW(p, tmp, offsetof(struct pt_regs, cp0_cause), frame);
163 }
164 }
165
kvm_mips_build_restore_scratch(u32 ** p,unsigned int tmp,unsigned int frame)166 static void kvm_mips_build_restore_scratch(u32 **p, unsigned int tmp,
167 unsigned int frame)
168 {
169 /*
170 * Restore host scratch register values saved by
171 * kvm_mips_build_save_scratch().
172 */
173 UASM_i_LW(p, tmp, offsetof(struct pt_regs, cp0_epc), frame);
174 UASM_i_MTC0(p, tmp, scratch_vcpu[0], scratch_vcpu[1]);
175
176 if (scratch_tmp[0] == c0_kscratch()) {
177 UASM_i_LW(p, tmp, offsetof(struct pt_regs, cp0_cause), frame);
178 UASM_i_MTC0(p, tmp, scratch_tmp[0], scratch_tmp[1]);
179 }
180 }
181
182 /**
183 * build_set_exc_base() - Assemble code to write exception base address.
184 * @p: Code buffer pointer.
185 * @reg: Source register (generated code may set WG bit in @reg).
186 *
187 * Assemble code to modify the exception base address in the EBase register,
188 * using the appropriately sized access and setting the WG bit if necessary.
189 */
build_set_exc_base(u32 ** p,unsigned int reg)190 static inline void build_set_exc_base(u32 **p, unsigned int reg)
191 {
192 if (cpu_has_ebase_wg) {
193 /* Set WG so that all the bits get written */
194 uasm_i_ori(p, reg, reg, MIPS_EBASE_WG);
195 UASM_i_MTC0(p, reg, C0_EBASE);
196 } else {
197 uasm_i_mtc0(p, reg, C0_EBASE);
198 }
199 }
200
201 /**
202 * kvm_mips_build_vcpu_run() - Assemble function to start running a guest VCPU.
203 * @addr: Address to start writing code.
204 *
205 * Assemble the start of the vcpu_run function to run a guest VCPU. The function
206 * conforms to the following prototype:
207 *
208 * int vcpu_run(struct kvm_vcpu *vcpu);
209 *
210 * The exit from the guest and return to the caller is handled by the code
211 * generated by kvm_mips_build_ret_to_host().
212 *
213 * Returns: Next address after end of written function.
214 */
kvm_mips_build_vcpu_run(void * addr)215 void *kvm_mips_build_vcpu_run(void *addr)
216 {
217 u32 *p = addr;
218 unsigned int i;
219
220 /*
221 * A0: vcpu
222 */
223
224 /* k0/k1 not being used in host kernel context */
225 UASM_i_ADDIU(&p, K1, SP, -(int)sizeof(struct pt_regs));
226 for (i = 16; i < 32; ++i) {
227 if (i == 24)
228 i = 28;
229 UASM_i_SW(&p, i, offsetof(struct pt_regs, regs[i]), K1);
230 }
231
232 /* Save host status */
233 uasm_i_mfc0(&p, V0, C0_STATUS);
234 UASM_i_SW(&p, V0, offsetof(struct pt_regs, cp0_status), K1);
235
236 /* Save scratch registers, will be used to store pointer to vcpu etc */
237 kvm_mips_build_save_scratch(&p, V1, K1);
238
239 /* VCPU scratch register has pointer to vcpu */
240 UASM_i_MTC0(&p, A0, scratch_vcpu[0], scratch_vcpu[1]);
241
242 /* Offset into vcpu->arch */
243 UASM_i_ADDIU(&p, K1, A0, offsetof(struct kvm_vcpu, arch));
244
245 /*
246 * Save the host stack to VCPU, used for exception processing
247 * when we exit from the Guest
248 */
249 UASM_i_SW(&p, SP, offsetof(struct kvm_vcpu_arch, host_stack), K1);
250
251 /* Save the kernel gp as well */
252 UASM_i_SW(&p, GP, offsetof(struct kvm_vcpu_arch, host_gp), K1);
253
254 /*
255 * Setup status register for running the guest in UM, interrupts
256 * are disabled
257 */
258 UASM_i_LA(&p, K0, ST0_EXL | KSU_USER | ST0_BEV | ST0_KX_IF_64);
259 uasm_i_mtc0(&p, K0, C0_STATUS);
260 uasm_i_ehb(&p);
261
262 /* load up the new EBASE */
263 UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, guest_ebase), K1);
264 build_set_exc_base(&p, K0);
265
266 /*
267 * Now that the new EBASE has been loaded, unset BEV, set
268 * interrupt mask as it was but make sure that timer interrupts
269 * are enabled
270 */
271 uasm_i_addiu(&p, K0, ZERO, ST0_EXL | KSU_USER | ST0_IE | ST0_KX_IF_64);
272 uasm_i_andi(&p, V0, V0, ST0_IM);
273 uasm_i_or(&p, K0, K0, V0);
274 uasm_i_mtc0(&p, K0, C0_STATUS);
275 uasm_i_ehb(&p);
276
277 p = kvm_mips_build_enter_guest(p);
278
279 return p;
280 }
281
282 /**
283 * kvm_mips_build_enter_guest() - Assemble code to resume guest execution.
284 * @addr: Address to start writing code.
285 *
286 * Assemble the code to resume guest execution. This code is common between the
287 * initial entry into the guest from the host, and returning from the exit
288 * handler back to the guest.
289 *
290 * Returns: Next address after end of written function.
291 */
kvm_mips_build_enter_guest(void * addr)292 static void *kvm_mips_build_enter_guest(void *addr)
293 {
294 u32 *p = addr;
295 unsigned int i;
296 struct uasm_label labels[2];
297 struct uasm_reloc relocs[2];
298 struct uasm_label __maybe_unused *l = labels;
299 struct uasm_reloc __maybe_unused *r = relocs;
300
301 memset(labels, 0, sizeof(labels));
302 memset(relocs, 0, sizeof(relocs));
303
304 /* Set Guest EPC */
305 UASM_i_LW(&p, T0, offsetof(struct kvm_vcpu_arch, pc), K1);
306 UASM_i_MTC0(&p, T0, C0_EPC);
307
308 #ifdef CONFIG_KVM_MIPS_VZ
309 /* Save normal linux process pgd (VZ guarantees pgd_reg is set) */
310 if (cpu_has_ldpte)
311 UASM_i_MFC0(&p, K0, C0_PWBASE);
312 else
313 UASM_i_MFC0(&p, K0, c0_kscratch(), pgd_reg);
314 UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu_arch, host_pgd), K1);
315
316 /*
317 * Set up KVM GPA pgd.
318 * This does roughly the same as TLBMISS_HANDLER_SETUP_PGD():
319 * - call tlbmiss_handler_setup_pgd(mm->pgd)
320 * - write mm->pgd into CP0_PWBase
321 *
322 * We keep S0 pointing at struct kvm so we can load the ASID below.
323 */
324 UASM_i_LW(&p, S0, (int)offsetof(struct kvm_vcpu, kvm) -
325 (int)offsetof(struct kvm_vcpu, arch), K1);
326 UASM_i_LW(&p, A0, offsetof(struct kvm, arch.gpa_mm.pgd), S0);
327 UASM_i_LA(&p, T9, (unsigned long)tlbmiss_handler_setup_pgd);
328 uasm_i_jalr(&p, RA, T9);
329 /* delay slot */
330 if (cpu_has_htw)
331 UASM_i_MTC0(&p, A0, C0_PWBASE);
332 else
333 uasm_i_nop(&p);
334
335 /* Set GM bit to setup eret to VZ guest context */
336 uasm_i_addiu(&p, V1, ZERO, 1);
337 uasm_i_mfc0(&p, K0, C0_GUESTCTL0);
338 uasm_i_ins(&p, K0, V1, MIPS_GCTL0_GM_SHIFT, 1);
339 uasm_i_mtc0(&p, K0, C0_GUESTCTL0);
340
341 if (cpu_has_guestid) {
342 /*
343 * Set root mode GuestID, so that root TLB refill handler can
344 * use the correct GuestID in the root TLB.
345 */
346
347 /* Get current GuestID */
348 uasm_i_mfc0(&p, T0, C0_GUESTCTL1);
349 /* Set GuestCtl1.RID = GuestCtl1.ID */
350 uasm_i_ext(&p, T1, T0, MIPS_GCTL1_ID_SHIFT,
351 MIPS_GCTL1_ID_WIDTH);
352 uasm_i_ins(&p, T0, T1, MIPS_GCTL1_RID_SHIFT,
353 MIPS_GCTL1_RID_WIDTH);
354 uasm_i_mtc0(&p, T0, C0_GUESTCTL1);
355
356 /* GuestID handles dealiasing so we don't need to touch ASID */
357 goto skip_asid_restore;
358 }
359
360 /* Root ASID Dealias (RAD) */
361
362 /* Save host ASID */
363 UASM_i_MFC0(&p, K0, C0_ENTRYHI);
364 UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu_arch, host_entryhi),
365 K1);
366
367 /* Set the root ASID for the Guest */
368 UASM_i_ADDIU(&p, T1, S0,
369 offsetof(struct kvm, arch.gpa_mm.context.asid));
370 #else
371 /* Set the ASID for the Guest Kernel or User */
372 UASM_i_LW(&p, T0, offsetof(struct kvm_vcpu_arch, cop0), K1);
373 UASM_i_LW(&p, T0, offsetof(struct mips_coproc, reg[MIPS_CP0_STATUS][0]),
374 T0);
375 uasm_i_andi(&p, T0, T0, KSU_USER | ST0_ERL | ST0_EXL);
376 uasm_i_xori(&p, T0, T0, KSU_USER);
377 uasm_il_bnez(&p, &r, T0, label_kernel_asid);
378 UASM_i_ADDIU(&p, T1, K1, offsetof(struct kvm_vcpu_arch,
379 guest_kernel_mm.context.asid));
380 /* else user */
381 UASM_i_ADDIU(&p, T1, K1, offsetof(struct kvm_vcpu_arch,
382 guest_user_mm.context.asid));
383 uasm_l_kernel_asid(&l, p);
384 #endif
385
386 /* t1: contains the base of the ASID array, need to get the cpu id */
387 /* smp_processor_id */
388 uasm_i_lw(&p, T2, offsetof(struct thread_info, cpu), GP);
389 /* index the ASID array */
390 uasm_i_sll(&p, T2, T2, ilog2(sizeof(long)));
391 UASM_i_ADDU(&p, T3, T1, T2);
392 UASM_i_LW(&p, K0, 0, T3);
393 #ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
394 /*
395 * reuse ASID array offset
396 * cpuinfo_mips is a multiple of sizeof(long)
397 */
398 uasm_i_addiu(&p, T3, ZERO, sizeof(struct cpuinfo_mips)/sizeof(long));
399 uasm_i_mul(&p, T2, T2, T3);
400
401 UASM_i_LA_mostly(&p, AT, (long)&cpu_data[0].asid_mask);
402 UASM_i_ADDU(&p, AT, AT, T2);
403 UASM_i_LW(&p, T2, uasm_rel_lo((long)&cpu_data[0].asid_mask), AT);
404 uasm_i_and(&p, K0, K0, T2);
405 #else
406 uasm_i_andi(&p, K0, K0, MIPS_ENTRYHI_ASID);
407 #endif
408
409 #ifndef CONFIG_KVM_MIPS_VZ
410 /*
411 * Set up KVM T&E GVA pgd.
412 * This does roughly the same as TLBMISS_HANDLER_SETUP_PGD():
413 * - call tlbmiss_handler_setup_pgd(mm->pgd)
414 * - but skips write into CP0_PWBase for now
415 */
416 UASM_i_LW(&p, A0, (int)offsetof(struct mm_struct, pgd) -
417 (int)offsetof(struct mm_struct, context.asid), T1);
418
419 UASM_i_LA(&p, T9, (unsigned long)tlbmiss_handler_setup_pgd);
420 uasm_i_jalr(&p, RA, T9);
421 uasm_i_mtc0(&p, K0, C0_ENTRYHI);
422 #else
423 /* Set up KVM VZ root ASID (!guestid) */
424 uasm_i_mtc0(&p, K0, C0_ENTRYHI);
425 skip_asid_restore:
426 #endif
427 uasm_i_ehb(&p);
428
429 /* Disable RDHWR access */
430 uasm_i_mtc0(&p, ZERO, C0_HWRENA);
431
432 /* load the guest context from VCPU and return */
433 for (i = 1; i < 32; ++i) {
434 /* Guest k0/k1 loaded later */
435 if (i == K0 || i == K1)
436 continue;
437 UASM_i_LW(&p, i, offsetof(struct kvm_vcpu_arch, gprs[i]), K1);
438 }
439
440 #ifndef CONFIG_CPU_MIPSR6
441 /* Restore hi/lo */
442 UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, hi), K1);
443 uasm_i_mthi(&p, K0);
444
445 UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, lo), K1);
446 uasm_i_mtlo(&p, K0);
447 #endif
448
449 /* Restore the guest's k0/k1 registers */
450 UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, gprs[K0]), K1);
451 UASM_i_LW(&p, K1, offsetof(struct kvm_vcpu_arch, gprs[K1]), K1);
452
453 /* Jump to guest */
454 uasm_i_eret(&p);
455
456 uasm_resolve_relocs(relocs, labels);
457
458 return p;
459 }
460
461 /**
462 * kvm_mips_build_tlb_refill_exception() - Assemble TLB refill handler.
463 * @addr: Address to start writing code.
464 * @handler: Address of common handler (within range of @addr).
465 *
466 * Assemble TLB refill exception fast path handler for guest execution.
467 *
468 * Returns: Next address after end of written function.
469 */
kvm_mips_build_tlb_refill_exception(void * addr,void * handler)470 void *kvm_mips_build_tlb_refill_exception(void *addr, void *handler)
471 {
472 u32 *p = addr;
473 struct uasm_label labels[2];
474 struct uasm_reloc relocs[2];
475 #ifndef CONFIG_CPU_LOONGSON64
476 struct uasm_label *l = labels;
477 struct uasm_reloc *r = relocs;
478 #endif
479
480 memset(labels, 0, sizeof(labels));
481 memset(relocs, 0, sizeof(relocs));
482
483 /* Save guest k1 into scratch register */
484 UASM_i_MTC0(&p, K1, scratch_tmp[0], scratch_tmp[1]);
485
486 /* Get the VCPU pointer from the VCPU scratch register */
487 UASM_i_MFC0(&p, K1, scratch_vcpu[0], scratch_vcpu[1]);
488
489 /* Save guest k0 into VCPU structure */
490 UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu, arch.gprs[K0]), K1);
491
492 /*
493 * Some of the common tlbex code uses current_cpu_type(). For KVM we
494 * assume symmetry and just disable preemption to silence the warning.
495 */
496 preempt_disable();
497
498 #ifdef CONFIG_CPU_LOONGSON64
499 UASM_i_MFC0(&p, K1, C0_PGD);
500 uasm_i_lddir(&p, K0, K1, 3); /* global page dir */
501 #ifndef __PAGETABLE_PMD_FOLDED
502 uasm_i_lddir(&p, K1, K0, 1); /* middle page dir */
503 #endif
504 uasm_i_ldpte(&p, K1, 0); /* even */
505 uasm_i_ldpte(&p, K1, 1); /* odd */
506 uasm_i_tlbwr(&p);
507 #else
508 /*
509 * Now for the actual refill bit. A lot of this can be common with the
510 * Linux TLB refill handler, however we don't need to handle so many
511 * cases. We only need to handle user mode refills, and user mode runs
512 * with 32-bit addressing.
513 *
514 * Therefore the branch to label_vmalloc generated by build_get_pmde64()
515 * that isn't resolved should never actually get taken and is harmless
516 * to leave in place for now.
517 */
518
519 #ifdef CONFIG_64BIT
520 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
521 #else
522 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
523 #endif
524
525 /* we don't support huge pages yet */
526
527 build_get_ptep(&p, K0, K1);
528 build_update_entries(&p, K0, K1);
529 build_tlb_write_entry(&p, &l, &r, tlb_random);
530 #endif
531
532 preempt_enable();
533
534 /* Get the VCPU pointer from the VCPU scratch register again */
535 UASM_i_MFC0(&p, K1, scratch_vcpu[0], scratch_vcpu[1]);
536
537 /* Restore the guest's k0/k1 registers */
538 UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu, arch.gprs[K0]), K1);
539 uasm_i_ehb(&p);
540 UASM_i_MFC0(&p, K1, scratch_tmp[0], scratch_tmp[1]);
541
542 /* Jump to guest */
543 uasm_i_eret(&p);
544
545 return p;
546 }
547
548 /**
549 * kvm_mips_build_exception() - Assemble first level guest exception handler.
550 * @addr: Address to start writing code.
551 * @handler: Address of common handler (within range of @addr).
552 *
553 * Assemble exception vector code for guest execution. The generated vector will
554 * branch to the common exception handler generated by kvm_mips_build_exit().
555 *
556 * Returns: Next address after end of written function.
557 */
kvm_mips_build_exception(void * addr,void * handler)558 void *kvm_mips_build_exception(void *addr, void *handler)
559 {
560 u32 *p = addr;
561 struct uasm_label labels[2];
562 struct uasm_reloc relocs[2];
563 struct uasm_label *l = labels;
564 struct uasm_reloc *r = relocs;
565
566 memset(labels, 0, sizeof(labels));
567 memset(relocs, 0, sizeof(relocs));
568
569 /* Save guest k1 into scratch register */
570 UASM_i_MTC0(&p, K1, scratch_tmp[0], scratch_tmp[1]);
571
572 /* Get the VCPU pointer from the VCPU scratch register */
573 UASM_i_MFC0(&p, K1, scratch_vcpu[0], scratch_vcpu[1]);
574 UASM_i_ADDIU(&p, K1, K1, offsetof(struct kvm_vcpu, arch));
575
576 /* Save guest k0 into VCPU structure */
577 UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu_arch, gprs[K0]), K1);
578
579 /* Branch to the common handler */
580 uasm_il_b(&p, &r, label_exit_common);
581 uasm_i_nop(&p);
582
583 uasm_l_exit_common(&l, handler);
584 uasm_resolve_relocs(relocs, labels);
585
586 return p;
587 }
588
589 /**
590 * kvm_mips_build_exit() - Assemble common guest exit handler.
591 * @addr: Address to start writing code.
592 *
593 * Assemble the generic guest exit handling code. This is called by the
594 * exception vectors (generated by kvm_mips_build_exception()), and calls
595 * kvm_mips_handle_exit(), then either resumes the guest or returns to the host
596 * depending on the return value.
597 *
598 * Returns: Next address after end of written function.
599 */
kvm_mips_build_exit(void * addr)600 void *kvm_mips_build_exit(void *addr)
601 {
602 u32 *p = addr;
603 unsigned int i;
604 struct uasm_label labels[3];
605 struct uasm_reloc relocs[3];
606 struct uasm_label *l = labels;
607 struct uasm_reloc *r = relocs;
608
609 memset(labels, 0, sizeof(labels));
610 memset(relocs, 0, sizeof(relocs));
611
612 /*
613 * Generic Guest exception handler. We end up here when the guest
614 * does something that causes a trap to kernel mode.
615 *
616 * Both k0/k1 registers will have already been saved (k0 into the vcpu
617 * structure, and k1 into the scratch_tmp register).
618 *
619 * The k1 register will already contain the kvm_vcpu_arch pointer.
620 */
621
622 /* Start saving Guest context to VCPU */
623 for (i = 0; i < 32; ++i) {
624 /* Guest k0/k1 saved later */
625 if (i == K0 || i == K1)
626 continue;
627 UASM_i_SW(&p, i, offsetof(struct kvm_vcpu_arch, gprs[i]), K1);
628 }
629
630 #ifndef CONFIG_CPU_MIPSR6
631 /* We need to save hi/lo and restore them on the way out */
632 uasm_i_mfhi(&p, T0);
633 UASM_i_SW(&p, T0, offsetof(struct kvm_vcpu_arch, hi), K1);
634
635 uasm_i_mflo(&p, T0);
636 UASM_i_SW(&p, T0, offsetof(struct kvm_vcpu_arch, lo), K1);
637 #endif
638
639 /* Finally save guest k1 to VCPU */
640 uasm_i_ehb(&p);
641 UASM_i_MFC0(&p, T0, scratch_tmp[0], scratch_tmp[1]);
642 UASM_i_SW(&p, T0, offsetof(struct kvm_vcpu_arch, gprs[K1]), K1);
643
644 /* Now that context has been saved, we can use other registers */
645
646 /* Restore vcpu */
647 UASM_i_MFC0(&p, S0, scratch_vcpu[0], scratch_vcpu[1]);
648
649 /*
650 * Save Host level EPC, BadVaddr and Cause to VCPU, useful to process
651 * the exception
652 */
653 UASM_i_MFC0(&p, K0, C0_EPC);
654 UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu_arch, pc), K1);
655
656 UASM_i_MFC0(&p, K0, C0_BADVADDR);
657 UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu_arch, host_cp0_badvaddr),
658 K1);
659
660 uasm_i_mfc0(&p, K0, C0_CAUSE);
661 uasm_i_sw(&p, K0, offsetof(struct kvm_vcpu_arch, host_cp0_cause), K1);
662
663 if (cpu_has_badinstr) {
664 uasm_i_mfc0(&p, K0, C0_BADINSTR);
665 uasm_i_sw(&p, K0, offsetof(struct kvm_vcpu_arch,
666 host_cp0_badinstr), K1);
667 }
668
669 if (cpu_has_badinstrp) {
670 uasm_i_mfc0(&p, K0, C0_BADINSTRP);
671 uasm_i_sw(&p, K0, offsetof(struct kvm_vcpu_arch,
672 host_cp0_badinstrp), K1);
673 }
674
675 /* Now restore the host state just enough to run the handlers */
676
677 /* Switch EBASE to the one used by Linux */
678 /* load up the host EBASE */
679 uasm_i_mfc0(&p, V0, C0_STATUS);
680
681 uasm_i_lui(&p, AT, ST0_BEV >> 16);
682 uasm_i_or(&p, K0, V0, AT);
683
684 uasm_i_mtc0(&p, K0, C0_STATUS);
685 uasm_i_ehb(&p);
686
687 UASM_i_LA_mostly(&p, K0, (long)&ebase);
688 UASM_i_LW(&p, K0, uasm_rel_lo((long)&ebase), K0);
689 build_set_exc_base(&p, K0);
690
691 if (raw_cpu_has_fpu) {
692 /*
693 * If FPU is enabled, save FCR31 and clear it so that later
694 * ctc1's don't trigger FPE for pending exceptions.
695 */
696 uasm_i_lui(&p, AT, ST0_CU1 >> 16);
697 uasm_i_and(&p, V1, V0, AT);
698 uasm_il_beqz(&p, &r, V1, label_fpu_1);
699 uasm_i_nop(&p);
700 uasm_i_cfc1(&p, T0, 31);
701 uasm_i_sw(&p, T0, offsetof(struct kvm_vcpu_arch, fpu.fcr31),
702 K1);
703 uasm_i_ctc1(&p, ZERO, 31);
704 uasm_l_fpu_1(&l, p);
705 }
706
707 if (cpu_has_msa) {
708 /*
709 * If MSA is enabled, save MSACSR and clear it so that later
710 * instructions don't trigger MSAFPE for pending exceptions.
711 */
712 uasm_i_mfc0(&p, T0, C0_CONFIG5);
713 uasm_i_ext(&p, T0, T0, 27, 1); /* MIPS_CONF5_MSAEN */
714 uasm_il_beqz(&p, &r, T0, label_msa_1);
715 uasm_i_nop(&p);
716 uasm_i_cfcmsa(&p, T0, MSA_CSR);
717 uasm_i_sw(&p, T0, offsetof(struct kvm_vcpu_arch, fpu.msacsr),
718 K1);
719 uasm_i_ctcmsa(&p, MSA_CSR, ZERO);
720 uasm_l_msa_1(&l, p);
721 }
722
723 #ifdef CONFIG_KVM_MIPS_VZ
724 /* Restore host ASID */
725 if (!cpu_has_guestid) {
726 UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, host_entryhi),
727 K1);
728 UASM_i_MTC0(&p, K0, C0_ENTRYHI);
729 }
730
731 /*
732 * Set up normal Linux process pgd.
733 * This does roughly the same as TLBMISS_HANDLER_SETUP_PGD():
734 * - call tlbmiss_handler_setup_pgd(mm->pgd)
735 * - write mm->pgd into CP0_PWBase
736 */
737 UASM_i_LW(&p, A0,
738 offsetof(struct kvm_vcpu_arch, host_pgd), K1);
739 UASM_i_LA(&p, T9, (unsigned long)tlbmiss_handler_setup_pgd);
740 uasm_i_jalr(&p, RA, T9);
741 /* delay slot */
742 if (cpu_has_htw)
743 UASM_i_MTC0(&p, A0, C0_PWBASE);
744 else
745 uasm_i_nop(&p);
746
747 /* Clear GM bit so we don't enter guest mode when EXL is cleared */
748 uasm_i_mfc0(&p, K0, C0_GUESTCTL0);
749 uasm_i_ins(&p, K0, ZERO, MIPS_GCTL0_GM_SHIFT, 1);
750 uasm_i_mtc0(&p, K0, C0_GUESTCTL0);
751
752 /* Save GuestCtl0 so we can access GExcCode after CPU migration */
753 uasm_i_sw(&p, K0,
754 offsetof(struct kvm_vcpu_arch, host_cp0_guestctl0), K1);
755
756 if (cpu_has_guestid) {
757 /*
758 * Clear root mode GuestID, so that root TLB operations use the
759 * root GuestID in the root TLB.
760 */
761 uasm_i_mfc0(&p, T0, C0_GUESTCTL1);
762 /* Set GuestCtl1.RID = MIPS_GCTL1_ROOT_GUESTID (i.e. 0) */
763 uasm_i_ins(&p, T0, ZERO, MIPS_GCTL1_RID_SHIFT,
764 MIPS_GCTL1_RID_WIDTH);
765 uasm_i_mtc0(&p, T0, C0_GUESTCTL1);
766 }
767 #endif
768
769 /* Now that the new EBASE has been loaded, unset BEV and KSU_USER */
770 uasm_i_addiu(&p, AT, ZERO, ~(ST0_EXL | KSU_USER | ST0_IE));
771 uasm_i_and(&p, V0, V0, AT);
772 uasm_i_lui(&p, AT, ST0_CU0 >> 16);
773 uasm_i_or(&p, V0, V0, AT);
774 #ifdef CONFIG_64BIT
775 uasm_i_ori(&p, V0, V0, ST0_SX | ST0_UX);
776 #endif
777 uasm_i_mtc0(&p, V0, C0_STATUS);
778 uasm_i_ehb(&p);
779
780 /* Load up host GP */
781 UASM_i_LW(&p, GP, offsetof(struct kvm_vcpu_arch, host_gp), K1);
782
783 /* Need a stack before we can jump to "C" */
784 UASM_i_LW(&p, SP, offsetof(struct kvm_vcpu_arch, host_stack), K1);
785
786 /* Saved host state */
787 UASM_i_ADDIU(&p, SP, SP, -(int)sizeof(struct pt_regs));
788
789 /*
790 * XXXKYMA do we need to load the host ASID, maybe not because the
791 * kernel entries are marked GLOBAL, need to verify
792 */
793
794 /* Restore host scratch registers, as we'll have clobbered them */
795 kvm_mips_build_restore_scratch(&p, K0, SP);
796
797 /* Restore RDHWR access */
798 UASM_i_LA_mostly(&p, K0, (long)&hwrena);
799 uasm_i_lw(&p, K0, uasm_rel_lo((long)&hwrena), K0);
800 uasm_i_mtc0(&p, K0, C0_HWRENA);
801
802 /* Jump to handler */
803 /*
804 * XXXKYMA: not sure if this is safe, how large is the stack??
805 * Now jump to the kvm_mips_handle_exit() to see if we can deal
806 * with this in the kernel
807 */
808 uasm_i_move(&p, A0, S0);
809 UASM_i_LA(&p, T9, (unsigned long)kvm_mips_handle_exit);
810 uasm_i_jalr(&p, RA, T9);
811 UASM_i_ADDIU(&p, SP, SP, -CALLFRAME_SIZ);
812
813 uasm_resolve_relocs(relocs, labels);
814
815 p = kvm_mips_build_ret_from_exit(p);
816
817 return p;
818 }
819
820 /**
821 * kvm_mips_build_ret_from_exit() - Assemble guest exit return handler.
822 * @addr: Address to start writing code.
823 *
824 * Assemble the code to handle the return from kvm_mips_handle_exit(), either
825 * resuming the guest or returning to the host depending on the return value.
826 *
827 * Returns: Next address after end of written function.
828 */
kvm_mips_build_ret_from_exit(void * addr)829 static void *kvm_mips_build_ret_from_exit(void *addr)
830 {
831 u32 *p = addr;
832 struct uasm_label labels[2];
833 struct uasm_reloc relocs[2];
834 struct uasm_label *l = labels;
835 struct uasm_reloc *r = relocs;
836
837 memset(labels, 0, sizeof(labels));
838 memset(relocs, 0, sizeof(relocs));
839
840 /* Return from handler Make sure interrupts are disabled */
841 uasm_i_di(&p, ZERO);
842 uasm_i_ehb(&p);
843
844 /*
845 * XXXKYMA: k0/k1 could have been blown away if we processed
846 * an exception while we were handling the exception from the
847 * guest, reload k1
848 */
849
850 uasm_i_move(&p, K1, S0);
851 UASM_i_ADDIU(&p, K1, K1, offsetof(struct kvm_vcpu, arch));
852
853 /*
854 * Check return value, should tell us if we are returning to the
855 * host (handle I/O etc)or resuming the guest
856 */
857 uasm_i_andi(&p, T0, V0, RESUME_HOST);
858 uasm_il_bnez(&p, &r, T0, label_return_to_host);
859 uasm_i_nop(&p);
860
861 p = kvm_mips_build_ret_to_guest(p);
862
863 uasm_l_return_to_host(&l, p);
864 p = kvm_mips_build_ret_to_host(p);
865
866 uasm_resolve_relocs(relocs, labels);
867
868 return p;
869 }
870
871 /**
872 * kvm_mips_build_ret_to_guest() - Assemble code to return to the guest.
873 * @addr: Address to start writing code.
874 *
875 * Assemble the code to handle return from the guest exit handler
876 * (kvm_mips_handle_exit()) back to the guest.
877 *
878 * Returns: Next address after end of written function.
879 */
kvm_mips_build_ret_to_guest(void * addr)880 static void *kvm_mips_build_ret_to_guest(void *addr)
881 {
882 u32 *p = addr;
883
884 /* Put the saved pointer to vcpu (s0) back into the scratch register */
885 UASM_i_MTC0(&p, S0, scratch_vcpu[0], scratch_vcpu[1]);
886
887 /* Load up the Guest EBASE to minimize the window where BEV is set */
888 UASM_i_LW(&p, T0, offsetof(struct kvm_vcpu_arch, guest_ebase), K1);
889
890 /* Switch EBASE back to the one used by KVM */
891 uasm_i_mfc0(&p, V1, C0_STATUS);
892 uasm_i_lui(&p, AT, ST0_BEV >> 16);
893 uasm_i_or(&p, K0, V1, AT);
894 uasm_i_mtc0(&p, K0, C0_STATUS);
895 uasm_i_ehb(&p);
896 build_set_exc_base(&p, T0);
897
898 /* Setup status register for running guest in UM */
899 uasm_i_ori(&p, V1, V1, ST0_EXL | KSU_USER | ST0_IE);
900 UASM_i_LA(&p, AT, ~(ST0_CU0 | ST0_MX | ST0_SX | ST0_UX));
901 uasm_i_and(&p, V1, V1, AT);
902 uasm_i_mtc0(&p, V1, C0_STATUS);
903 uasm_i_ehb(&p);
904
905 p = kvm_mips_build_enter_guest(p);
906
907 return p;
908 }
909
910 /**
911 * kvm_mips_build_ret_to_host() - Assemble code to return to the host.
912 * @addr: Address to start writing code.
913 *
914 * Assemble the code to handle return from the guest exit handler
915 * (kvm_mips_handle_exit()) back to the host, i.e. to the caller of the vcpu_run
916 * function generated by kvm_mips_build_vcpu_run().
917 *
918 * Returns: Next address after end of written function.
919 */
kvm_mips_build_ret_to_host(void * addr)920 static void *kvm_mips_build_ret_to_host(void *addr)
921 {
922 u32 *p = addr;
923 unsigned int i;
924
925 /* EBASE is already pointing to Linux */
926 UASM_i_LW(&p, K1, offsetof(struct kvm_vcpu_arch, host_stack), K1);
927 UASM_i_ADDIU(&p, K1, K1, -(int)sizeof(struct pt_regs));
928
929 /*
930 * r2/v0 is the return code, shift it down by 2 (arithmetic)
931 * to recover the err code
932 */
933 uasm_i_sra(&p, K0, V0, 2);
934 uasm_i_move(&p, V0, K0);
935
936 /* Load context saved on the host stack */
937 for (i = 16; i < 31; ++i) {
938 if (i == 24)
939 i = 28;
940 UASM_i_LW(&p, i, offsetof(struct pt_regs, regs[i]), K1);
941 }
942
943 /* Restore RDHWR access */
944 UASM_i_LA_mostly(&p, K0, (long)&hwrena);
945 uasm_i_lw(&p, K0, uasm_rel_lo((long)&hwrena), K0);
946 uasm_i_mtc0(&p, K0, C0_HWRENA);
947
948 /* Restore RA, which is the address we will return to */
949 UASM_i_LW(&p, RA, offsetof(struct pt_regs, regs[RA]), K1);
950 uasm_i_jr(&p, RA);
951 uasm_i_nop(&p);
952
953 return p;
954 }
955
956
