1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * KVM/MIPS: Instruction/Exception emulation
7 *
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
10 */
11
12 #include <linux/errno.h>
13 #include <linux/err.h>
14 #include <linux/ktime.h>
15 #include <linux/kvm_host.h>
16 #include <linux/vmalloc.h>
17 #include <linux/fs.h>
18 #include <linux/memblock.h>
19 #include <linux/random.h>
20 #include <asm/page.h>
21 #include <asm/cacheflush.h>
22 #include <asm/cacheops.h>
23 #include <asm/cpu-info.h>
24 #include <asm/mmu_context.h>
25 #include <asm/tlbflush.h>
26 #include <asm/inst.h>
27
28 #undef CONFIG_MIPS_MT
29 #include <asm/r4kcache.h>
30 #define CONFIG_MIPS_MT
31
32 #include "interrupt.h"
33 #include "commpage.h"
34
35 #include "trace.h"
36
37 /*
38 * Compute the return address and do emulate branch simulation, if required.
39 * This function should be called only in branch delay slot active.
40 */
kvm_compute_return_epc(struct kvm_vcpu * vcpu,unsigned long instpc,unsigned long * out)41 static int kvm_compute_return_epc(struct kvm_vcpu *vcpu, unsigned long instpc,
42 unsigned long *out)
43 {
44 unsigned int dspcontrol;
45 union mips_instruction insn;
46 struct kvm_vcpu_arch *arch = &vcpu->arch;
47 long epc = instpc;
48 long nextpc;
49 int err;
50
51 if (epc & 3) {
52 kvm_err("%s: unaligned epc\n", __func__);
53 return -EINVAL;
54 }
55
56 /* Read the instruction */
57 err = kvm_get_badinstrp((u32 *)epc, vcpu, &insn.word);
58 if (err)
59 return err;
60
61 switch (insn.i_format.opcode) {
62 /* jr and jalr are in r_format format. */
63 case spec_op:
64 switch (insn.r_format.func) {
65 case jalr_op:
66 arch->gprs[insn.r_format.rd] = epc + 8;
67 fallthrough;
68 case jr_op:
69 nextpc = arch->gprs[insn.r_format.rs];
70 break;
71 default:
72 return -EINVAL;
73 }
74 break;
75
76 /*
77 * This group contains:
78 * bltz_op, bgez_op, bltzl_op, bgezl_op,
79 * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
80 */
81 case bcond_op:
82 switch (insn.i_format.rt) {
83 case bltz_op:
84 case bltzl_op:
85 if ((long)arch->gprs[insn.i_format.rs] < 0)
86 epc = epc + 4 + (insn.i_format.simmediate << 2);
87 else
88 epc += 8;
89 nextpc = epc;
90 break;
91
92 case bgez_op:
93 case bgezl_op:
94 if ((long)arch->gprs[insn.i_format.rs] >= 0)
95 epc = epc + 4 + (insn.i_format.simmediate << 2);
96 else
97 epc += 8;
98 nextpc = epc;
99 break;
100
101 case bltzal_op:
102 case bltzall_op:
103 arch->gprs[31] = epc + 8;
104 if ((long)arch->gprs[insn.i_format.rs] < 0)
105 epc = epc + 4 + (insn.i_format.simmediate << 2);
106 else
107 epc += 8;
108 nextpc = epc;
109 break;
110
111 case bgezal_op:
112 case bgezall_op:
113 arch->gprs[31] = epc + 8;
114 if ((long)arch->gprs[insn.i_format.rs] >= 0)
115 epc = epc + 4 + (insn.i_format.simmediate << 2);
116 else
117 epc += 8;
118 nextpc = epc;
119 break;
120 case bposge32_op:
121 if (!cpu_has_dsp) {
122 kvm_err("%s: DSP branch but not DSP ASE\n",
123 __func__);
124 return -EINVAL;
125 }
126
127 dspcontrol = rddsp(0x01);
128
129 if (dspcontrol >= 32)
130 epc = epc + 4 + (insn.i_format.simmediate << 2);
131 else
132 epc += 8;
133 nextpc = epc;
134 break;
135 default:
136 return -EINVAL;
137 }
138 break;
139
140 /* These are unconditional and in j_format. */
141 case jal_op:
142 arch->gprs[31] = instpc + 8;
143 fallthrough;
144 case j_op:
145 epc += 4;
146 epc >>= 28;
147 epc <<= 28;
148 epc |= (insn.j_format.target << 2);
149 nextpc = epc;
150 break;
151
152 /* These are conditional and in i_format. */
153 case beq_op:
154 case beql_op:
155 if (arch->gprs[insn.i_format.rs] ==
156 arch->gprs[insn.i_format.rt])
157 epc = epc + 4 + (insn.i_format.simmediate << 2);
158 else
159 epc += 8;
160 nextpc = epc;
161 break;
162
163 case bne_op:
164 case bnel_op:
165 if (arch->gprs[insn.i_format.rs] !=
166 arch->gprs[insn.i_format.rt])
167 epc = epc + 4 + (insn.i_format.simmediate << 2);
168 else
169 epc += 8;
170 nextpc = epc;
171 break;
172
173 case blez_op: /* POP06 */
174 #ifndef CONFIG_CPU_MIPSR6
175 case blezl_op: /* removed in R6 */
176 #endif
177 if (insn.i_format.rt != 0)
178 goto compact_branch;
179 if ((long)arch->gprs[insn.i_format.rs] <= 0)
180 epc = epc + 4 + (insn.i_format.simmediate << 2);
181 else
182 epc += 8;
183 nextpc = epc;
184 break;
185
186 case bgtz_op: /* POP07 */
187 #ifndef CONFIG_CPU_MIPSR6
188 case bgtzl_op: /* removed in R6 */
189 #endif
190 if (insn.i_format.rt != 0)
191 goto compact_branch;
192 if ((long)arch->gprs[insn.i_format.rs] > 0)
193 epc = epc + 4 + (insn.i_format.simmediate << 2);
194 else
195 epc += 8;
196 nextpc = epc;
197 break;
198
199 /* And now the FPA/cp1 branch instructions. */
200 case cop1_op:
201 kvm_err("%s: unsupported cop1_op\n", __func__);
202 return -EINVAL;
203
204 #ifdef CONFIG_CPU_MIPSR6
205 /* R6 added the following compact branches with forbidden slots */
206 case blezl_op: /* POP26 */
207 case bgtzl_op: /* POP27 */
208 /* only rt == 0 isn't compact branch */
209 if (insn.i_format.rt != 0)
210 goto compact_branch;
211 return -EINVAL;
212 case pop10_op:
213 case pop30_op:
214 /* only rs == rt == 0 is reserved, rest are compact branches */
215 if (insn.i_format.rs != 0 || insn.i_format.rt != 0)
216 goto compact_branch;
217 return -EINVAL;
218 case pop66_op:
219 case pop76_op:
220 /* only rs == 0 isn't compact branch */
221 if (insn.i_format.rs != 0)
222 goto compact_branch;
223 return -EINVAL;
224 compact_branch:
225 /*
226 * If we've hit an exception on the forbidden slot, then
227 * the branch must not have been taken.
228 */
229 epc += 8;
230 nextpc = epc;
231 break;
232 #else
233 compact_branch:
234 /* Fall through - Compact branches not supported before R6 */
235 #endif
236 default:
237 return -EINVAL;
238 }
239
240 *out = nextpc;
241 return 0;
242 }
243
update_pc(struct kvm_vcpu * vcpu,u32 cause)244 enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause)
245 {
246 int err;
247
248 if (cause & CAUSEF_BD) {
249 err = kvm_compute_return_epc(vcpu, vcpu->arch.pc,
250 &vcpu->arch.pc);
251 if (err)
252 return EMULATE_FAIL;
253 } else {
254 vcpu->arch.pc += 4;
255 }
256
257 kvm_debug("update_pc(): New PC: %#lx\n", vcpu->arch.pc);
258
259 return EMULATE_DONE;
260 }
261
262 /**
263 * kvm_get_badinstr() - Get bad instruction encoding.
264 * @opc: Guest pointer to faulting instruction.
265 * @vcpu: KVM VCPU information.
266 *
267 * Gets the instruction encoding of the faulting instruction, using the saved
268 * BadInstr register value if it exists, otherwise falling back to reading guest
269 * memory at @opc.
270 *
271 * Returns: The instruction encoding of the faulting instruction.
272 */
kvm_get_badinstr(u32 * opc,struct kvm_vcpu * vcpu,u32 * out)273 int kvm_get_badinstr(u32 *opc, struct kvm_vcpu *vcpu, u32 *out)
274 {
275 if (cpu_has_badinstr) {
276 *out = vcpu->arch.host_cp0_badinstr;
277 return 0;
278 } else {
279 return kvm_get_inst(opc, vcpu, out);
280 }
281 }
282
283 /**
284 * kvm_get_badinstrp() - Get bad prior instruction encoding.
285 * @opc: Guest pointer to prior faulting instruction.
286 * @vcpu: KVM VCPU information.
287 *
288 * Gets the instruction encoding of the prior faulting instruction (the branch
289 * containing the delay slot which faulted), using the saved BadInstrP register
290 * value if it exists, otherwise falling back to reading guest memory at @opc.
291 *
292 * Returns: The instruction encoding of the prior faulting instruction.
293 */
kvm_get_badinstrp(u32 * opc,struct kvm_vcpu * vcpu,u32 * out)294 int kvm_get_badinstrp(u32 *opc, struct kvm_vcpu *vcpu, u32 *out)
295 {
296 if (cpu_has_badinstrp) {
297 *out = vcpu->arch.host_cp0_badinstrp;
298 return 0;
299 } else {
300 return kvm_get_inst(opc, vcpu, out);
301 }
302 }
303
304 /**
305 * kvm_mips_count_disabled() - Find whether the CP0_Count timer is disabled.
306 * @vcpu: Virtual CPU.
307 *
308 * Returns: 1 if the CP0_Count timer is disabled by either the guest
309 * CP0_Cause.DC bit or the count_ctl.DC bit.
310 * 0 otherwise (in which case CP0_Count timer is running).
311 */
kvm_mips_count_disabled(struct kvm_vcpu * vcpu)312 int kvm_mips_count_disabled(struct kvm_vcpu *vcpu)
313 {
314 struct mips_coproc *cop0 = vcpu->arch.cop0;
315
316 return (vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) ||
317 (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC);
318 }
319
320 /**
321 * kvm_mips_ktime_to_count() - Scale ktime_t to a 32-bit count.
322 *
323 * Caches the dynamic nanosecond bias in vcpu->arch.count_dyn_bias.
324 *
325 * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
326 */
kvm_mips_ktime_to_count(struct kvm_vcpu * vcpu,ktime_t now)327 static u32 kvm_mips_ktime_to_count(struct kvm_vcpu *vcpu, ktime_t now)
328 {
329 s64 now_ns, periods;
330 u64 delta;
331
332 now_ns = ktime_to_ns(now);
333 delta = now_ns + vcpu->arch.count_dyn_bias;
334
335 if (delta >= vcpu->arch.count_period) {
336 /* If delta is out of safe range the bias needs adjusting */
337 periods = div64_s64(now_ns, vcpu->arch.count_period);
338 vcpu->arch.count_dyn_bias = -periods * vcpu->arch.count_period;
339 /* Recalculate delta with new bias */
340 delta = now_ns + vcpu->arch.count_dyn_bias;
341 }
342
343 /*
344 * We've ensured that:
345 * delta < count_period
346 *
347 * Therefore the intermediate delta*count_hz will never overflow since
348 * at the boundary condition:
349 * delta = count_period
350 * delta = NSEC_PER_SEC * 2^32 / count_hz
351 * delta * count_hz = NSEC_PER_SEC * 2^32
352 */
353 return div_u64(delta * vcpu->arch.count_hz, NSEC_PER_SEC);
354 }
355
356 /**
357 * kvm_mips_count_time() - Get effective current time.
358 * @vcpu: Virtual CPU.
359 *
360 * Get effective monotonic ktime. This is usually a straightforward ktime_get(),
361 * except when the master disable bit is set in count_ctl, in which case it is
362 * count_resume, i.e. the time that the count was disabled.
363 *
364 * Returns: Effective monotonic ktime for CP0_Count.
365 */
kvm_mips_count_time(struct kvm_vcpu * vcpu)366 static inline ktime_t kvm_mips_count_time(struct kvm_vcpu *vcpu)
367 {
368 if (unlikely(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC))
369 return vcpu->arch.count_resume;
370
371 return ktime_get();
372 }
373
374 /**
375 * kvm_mips_read_count_running() - Read the current count value as if running.
376 * @vcpu: Virtual CPU.
377 * @now: Kernel time to read CP0_Count at.
378 *
379 * Returns the current guest CP0_Count register at time @now and handles if the
380 * timer interrupt is pending and hasn't been handled yet.
381 *
382 * Returns: The current value of the guest CP0_Count register.
383 */
kvm_mips_read_count_running(struct kvm_vcpu * vcpu,ktime_t now)384 static u32 kvm_mips_read_count_running(struct kvm_vcpu *vcpu, ktime_t now)
385 {
386 struct mips_coproc *cop0 = vcpu->arch.cop0;
387 ktime_t expires, threshold;
388 u32 count, compare;
389 int running;
390
391 /* Calculate the biased and scaled guest CP0_Count */
392 count = vcpu->arch.count_bias + kvm_mips_ktime_to_count(vcpu, now);
393 compare = kvm_read_c0_guest_compare(cop0);
394
395 /*
396 * Find whether CP0_Count has reached the closest timer interrupt. If
397 * not, we shouldn't inject it.
398 */
399 if ((s32)(count - compare) < 0)
400 return count;
401
402 /*
403 * The CP0_Count we're going to return has already reached the closest
404 * timer interrupt. Quickly check if it really is a new interrupt by
405 * looking at whether the interval until the hrtimer expiry time is
406 * less than 1/4 of the timer period.
407 */
408 expires = hrtimer_get_expires(&vcpu->arch.comparecount_timer);
409 threshold = ktime_add_ns(now, vcpu->arch.count_period / 4);
410 if (ktime_before(expires, threshold)) {
411 /*
412 * Cancel it while we handle it so there's no chance of
413 * interference with the timeout handler.
414 */
415 running = hrtimer_cancel(&vcpu->arch.comparecount_timer);
416
417 /* Nothing should be waiting on the timeout */
418 kvm_mips_callbacks->queue_timer_int(vcpu);
419
420 /*
421 * Restart the timer if it was running based on the expiry time
422 * we read, so that we don't push it back 2 periods.
423 */
424 if (running) {
425 expires = ktime_add_ns(expires,
426 vcpu->arch.count_period);
427 hrtimer_start(&vcpu->arch.comparecount_timer, expires,
428 HRTIMER_MODE_ABS);
429 }
430 }
431
432 return count;
433 }
434
435 /**
436 * kvm_mips_read_count() - Read the current count value.
437 * @vcpu: Virtual CPU.
438 *
439 * Read the current guest CP0_Count value, taking into account whether the timer
440 * is stopped.
441 *
442 * Returns: The current guest CP0_Count value.
443 */
kvm_mips_read_count(struct kvm_vcpu * vcpu)444 u32 kvm_mips_read_count(struct kvm_vcpu *vcpu)
445 {
446 struct mips_coproc *cop0 = vcpu->arch.cop0;
447
448 /* If count disabled just read static copy of count */
449 if (kvm_mips_count_disabled(vcpu))
450 return kvm_read_c0_guest_count(cop0);
451
452 return kvm_mips_read_count_running(vcpu, ktime_get());
453 }
454
455 /**
456 * kvm_mips_freeze_hrtimer() - Safely stop the hrtimer.
457 * @vcpu: Virtual CPU.
458 * @count: Output pointer for CP0_Count value at point of freeze.
459 *
460 * Freeze the hrtimer safely and return both the ktime and the CP0_Count value
461 * at the point it was frozen. It is guaranteed that any pending interrupts at
462 * the point it was frozen are handled, and none after that point.
463 *
464 * This is useful where the time/CP0_Count is needed in the calculation of the
465 * new parameters.
466 *
467 * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
468 *
469 * Returns: The ktime at the point of freeze.
470 */
kvm_mips_freeze_hrtimer(struct kvm_vcpu * vcpu,u32 * count)471 ktime_t kvm_mips_freeze_hrtimer(struct kvm_vcpu *vcpu, u32 *count)
472 {
473 ktime_t now;
474
475 /* stop hrtimer before finding time */
476 hrtimer_cancel(&vcpu->arch.comparecount_timer);
477 now = ktime_get();
478
479 /* find count at this point and handle pending hrtimer */
480 *count = kvm_mips_read_count_running(vcpu, now);
481
482 return now;
483 }
484
485 /**
486 * kvm_mips_resume_hrtimer() - Resume hrtimer, updating expiry.
487 * @vcpu: Virtual CPU.
488 * @now: ktime at point of resume.
489 * @count: CP0_Count at point of resume.
490 *
491 * Resumes the timer and updates the timer expiry based on @now and @count.
492 * This can be used in conjunction with kvm_mips_freeze_timer() when timer
493 * parameters need to be changed.
494 *
495 * It is guaranteed that a timer interrupt immediately after resume will be
496 * handled, but not if CP_Compare is exactly at @count. That case is already
497 * handled by kvm_mips_freeze_timer().
498 *
499 * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
500 */
kvm_mips_resume_hrtimer(struct kvm_vcpu * vcpu,ktime_t now,u32 count)501 static void kvm_mips_resume_hrtimer(struct kvm_vcpu *vcpu,
502 ktime_t now, u32 count)
503 {
504 struct mips_coproc *cop0 = vcpu->arch.cop0;
505 u32 compare;
506 u64 delta;
507 ktime_t expire;
508
509 /* Calculate timeout (wrap 0 to 2^32) */
510 compare = kvm_read_c0_guest_compare(cop0);
511 delta = (u64)(u32)(compare - count - 1) + 1;
512 delta = div_u64(delta * NSEC_PER_SEC, vcpu->arch.count_hz);
513 expire = ktime_add_ns(now, delta);
514
515 /* Update hrtimer to use new timeout */
516 hrtimer_cancel(&vcpu->arch.comparecount_timer);
517 hrtimer_start(&vcpu->arch.comparecount_timer, expire, HRTIMER_MODE_ABS);
518 }
519
520 /**
521 * kvm_mips_restore_hrtimer() - Restore hrtimer after a gap, updating expiry.
522 * @vcpu: Virtual CPU.
523 * @before: Time before Count was saved, lower bound of drift calculation.
524 * @count: CP0_Count at point of restore.
525 * @min_drift: Minimum amount of drift permitted before correction.
526 * Must be <= 0.
527 *
528 * Restores the timer from a particular @count, accounting for drift. This can
529 * be used in conjunction with kvm_mips_freeze_timer() when a hardware timer is
530 * to be used for a period of time, but the exact ktime corresponding to the
531 * final Count that must be restored is not known.
532 *
533 * It is gauranteed that a timer interrupt immediately after restore will be
534 * handled, but not if CP0_Compare is exactly at @count. That case should
535 * already be handled when the hardware timer state is saved.
536 *
537 * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is not
538 * stopped).
539 *
540 * Returns: Amount of correction to count_bias due to drift.
541 */
kvm_mips_restore_hrtimer(struct kvm_vcpu * vcpu,ktime_t before,u32 count,int min_drift)542 int kvm_mips_restore_hrtimer(struct kvm_vcpu *vcpu, ktime_t before,
543 u32 count, int min_drift)
544 {
545 ktime_t now, count_time;
546 u32 now_count, before_count;
547 u64 delta;
548 int drift, ret = 0;
549
550 /* Calculate expected count at before */
551 before_count = vcpu->arch.count_bias +
552 kvm_mips_ktime_to_count(vcpu, before);
553
554 /*
555 * Detect significantly negative drift, where count is lower than
556 * expected. Some negative drift is expected when hardware counter is
557 * set after kvm_mips_freeze_timer(), and it is harmless to allow the
558 * time to jump forwards a little, within reason. If the drift is too
559 * significant, adjust the bias to avoid a big Guest.CP0_Count jump.
560 */
561 drift = count - before_count;
562 if (drift < min_drift) {
563 count_time = before;
564 vcpu->arch.count_bias += drift;
565 ret = drift;
566 goto resume;
567 }
568
569 /* Calculate expected count right now */
570 now = ktime_get();
571 now_count = vcpu->arch.count_bias + kvm_mips_ktime_to_count(vcpu, now);
572
573 /*
574 * Detect positive drift, where count is higher than expected, and
575 * adjust the bias to avoid guest time going backwards.
576 */
577 drift = count - now_count;
578 if (drift > 0) {
579 count_time = now;
580 vcpu->arch.count_bias += drift;
581 ret = drift;
582 goto resume;
583 }
584
585 /* Subtract nanosecond delta to find ktime when count was read */
586 delta = (u64)(u32)(now_count - count);
587 delta = div_u64(delta * NSEC_PER_SEC, vcpu->arch.count_hz);
588 count_time = ktime_sub_ns(now, delta);
589
590 resume:
591 /* Resume using the calculated ktime */
592 kvm_mips_resume_hrtimer(vcpu, count_time, count);
593 return ret;
594 }
595
596 /**
597 * kvm_mips_write_count() - Modify the count and update timer.
598 * @vcpu: Virtual CPU.
599 * @count: Guest CP0_Count value to set.
600 *
601 * Sets the CP0_Count value and updates the timer accordingly.
602 */
kvm_mips_write_count(struct kvm_vcpu * vcpu,u32 count)603 void kvm_mips_write_count(struct kvm_vcpu *vcpu, u32 count)
604 {
605 struct mips_coproc *cop0 = vcpu->arch.cop0;
606 ktime_t now;
607
608 /* Calculate bias */
609 now = kvm_mips_count_time(vcpu);
610 vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now);
611
612 if (kvm_mips_count_disabled(vcpu))
613 /* The timer's disabled, adjust the static count */
614 kvm_write_c0_guest_count(cop0, count);
615 else
616 /* Update timeout */
617 kvm_mips_resume_hrtimer(vcpu, now, count);
618 }
619
620 /**
621 * kvm_mips_init_count() - Initialise timer.
622 * @vcpu: Virtual CPU.
623 * @count_hz: Frequency of timer.
624 *
625 * Initialise the timer to the specified frequency, zero it, and set it going if
626 * it's enabled.
627 */
kvm_mips_init_count(struct kvm_vcpu * vcpu,unsigned long count_hz)628 void kvm_mips_init_count(struct kvm_vcpu *vcpu, unsigned long count_hz)
629 {
630 vcpu->arch.count_hz = count_hz;
631 vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32, count_hz);
632 vcpu->arch.count_dyn_bias = 0;
633
634 /* Starting at 0 */
635 kvm_mips_write_count(vcpu, 0);
636 }
637
638 /**
639 * kvm_mips_set_count_hz() - Update the frequency of the timer.
640 * @vcpu: Virtual CPU.
641 * @count_hz: Frequency of CP0_Count timer in Hz.
642 *
643 * Change the frequency of the CP0_Count timer. This is done atomically so that
644 * CP0_Count is continuous and no timer interrupt is lost.
645 *
646 * Returns: -EINVAL if @count_hz is out of range.
647 * 0 on success.
648 */
kvm_mips_set_count_hz(struct kvm_vcpu * vcpu,s64 count_hz)649 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz)
650 {
651 struct mips_coproc *cop0 = vcpu->arch.cop0;
652 int dc;
653 ktime_t now;
654 u32 count;
655
656 /* ensure the frequency is in a sensible range... */
657 if (count_hz <= 0 || count_hz > NSEC_PER_SEC)
658 return -EINVAL;
659 /* ... and has actually changed */
660 if (vcpu->arch.count_hz == count_hz)
661 return 0;
662
663 /* Safely freeze timer so we can keep it continuous */
664 dc = kvm_mips_count_disabled(vcpu);
665 if (dc) {
666 now = kvm_mips_count_time(vcpu);
667 count = kvm_read_c0_guest_count(cop0);
668 } else {
669 now = kvm_mips_freeze_hrtimer(vcpu, &count);
670 }
671
672 /* Update the frequency */
673 vcpu->arch.count_hz = count_hz;
674 vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32, count_hz);
675 vcpu->arch.count_dyn_bias = 0;
676
677 /* Calculate adjusted bias so dynamic count is unchanged */
678 vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now);
679
680 /* Update and resume hrtimer */
681 if (!dc)
682 kvm_mips_resume_hrtimer(vcpu, now, count);
683 return 0;
684 }
685
686 /**
687 * kvm_mips_write_compare() - Modify compare and update timer.
688 * @vcpu: Virtual CPU.
689 * @compare: New CP0_Compare value.
690 * @ack: Whether to acknowledge timer interrupt.
691 *
692 * Update CP0_Compare to a new value and update the timeout.
693 * If @ack, atomically acknowledge any pending timer interrupt, otherwise ensure
694 * any pending timer interrupt is preserved.
695 */
kvm_mips_write_compare(struct kvm_vcpu * vcpu,u32 compare,bool ack)696 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack)
697 {
698 struct mips_coproc *cop0 = vcpu->arch.cop0;
699 int dc;
700 u32 old_compare = kvm_read_c0_guest_compare(cop0);
701 s32 delta = compare - old_compare;
702 u32 cause;
703 ktime_t now = ktime_set(0, 0); /* silence bogus GCC warning */
704 u32 count;
705
706 /* if unchanged, must just be an ack */
707 if (old_compare == compare) {
708 if (!ack)
709 return;
710 kvm_mips_callbacks->dequeue_timer_int(vcpu);
711 kvm_write_c0_guest_compare(cop0, compare);
712 return;
713 }
714
715 /*
716 * If guest CP0_Compare moves forward, CP0_GTOffset should be adjusted
717 * too to prevent guest CP0_Count hitting guest CP0_Compare.
718 *
719 * The new GTOffset corresponds to the new value of CP0_Compare, and is
720 * set prior to it being written into the guest context. We disable
721 * preemption until the new value is written to prevent restore of a
722 * GTOffset corresponding to the old CP0_Compare value.
723 */
724 if (IS_ENABLED(CONFIG_KVM_MIPS_VZ) && delta > 0) {
725 preempt_disable();
726 write_c0_gtoffset(compare - read_c0_count());
727 back_to_back_c0_hazard();
728 }
729
730 /* freeze_hrtimer() takes care of timer interrupts <= count */
731 dc = kvm_mips_count_disabled(vcpu);
732 if (!dc)
733 now = kvm_mips_freeze_hrtimer(vcpu, &count);
734
735 if (ack)
736 kvm_mips_callbacks->dequeue_timer_int(vcpu);
737 else if (IS_ENABLED(CONFIG_KVM_MIPS_VZ))
738 /*
739 * With VZ, writing CP0_Compare acks (clears) CP0_Cause.TI, so
740 * preserve guest CP0_Cause.TI if we don't want to ack it.
741 */
742 cause = kvm_read_c0_guest_cause(cop0);
743
744 kvm_write_c0_guest_compare(cop0, compare);
745
746 if (IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
747 if (delta > 0)
748 preempt_enable();
749
750 back_to_back_c0_hazard();
751
752 if (!ack && cause & CAUSEF_TI)
753 kvm_write_c0_guest_cause(cop0, cause);
754 }
755
756 /* resume_hrtimer() takes care of timer interrupts > count */
757 if (!dc)
758 kvm_mips_resume_hrtimer(vcpu, now, count);
759
760 /*
761 * If guest CP0_Compare is moving backward, we delay CP0_GTOffset change
762 * until after the new CP0_Compare is written, otherwise new guest
763 * CP0_Count could hit new guest CP0_Compare.
764 */
765 if (IS_ENABLED(CONFIG_KVM_MIPS_VZ) && delta <= 0)
766 write_c0_gtoffset(compare - read_c0_count());
767 }
768
769 /**
770 * kvm_mips_count_disable() - Disable count.
771 * @vcpu: Virtual CPU.
772 *
773 * Disable the CP0_Count timer. A timer interrupt on or before the final stop
774 * time will be handled but not after.
775 *
776 * Assumes CP0_Count was previously enabled but now Guest.CP0_Cause.DC or
777 * count_ctl.DC has been set (count disabled).
778 *
779 * Returns: The time that the timer was stopped.
780 */
kvm_mips_count_disable(struct kvm_vcpu * vcpu)781 static ktime_t kvm_mips_count_disable(struct kvm_vcpu *vcpu)
782 {
783 struct mips_coproc *cop0 = vcpu->arch.cop0;
784 u32 count;
785 ktime_t now;
786
787 /* Stop hrtimer */
788 hrtimer_cancel(&vcpu->arch.comparecount_timer);
789
790 /* Set the static count from the dynamic count, handling pending TI */
791 now = ktime_get();
792 count = kvm_mips_read_count_running(vcpu, now);
793 kvm_write_c0_guest_count(cop0, count);
794
795 return now;
796 }
797
798 /**
799 * kvm_mips_count_disable_cause() - Disable count using CP0_Cause.DC.
800 * @vcpu: Virtual CPU.
801 *
802 * Disable the CP0_Count timer and set CP0_Cause.DC. A timer interrupt on or
803 * before the final stop time will be handled if the timer isn't disabled by
804 * count_ctl.DC, but not after.
805 *
806 * Assumes CP0_Cause.DC is clear (count enabled).
807 */
kvm_mips_count_disable_cause(struct kvm_vcpu * vcpu)808 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu)
809 {
810 struct mips_coproc *cop0 = vcpu->arch.cop0;
811
812 kvm_set_c0_guest_cause(cop0, CAUSEF_DC);
813 if (!(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC))
814 kvm_mips_count_disable(vcpu);
815 }
816
817 /**
818 * kvm_mips_count_enable_cause() - Enable count using CP0_Cause.DC.
819 * @vcpu: Virtual CPU.
820 *
821 * Enable the CP0_Count timer and clear CP0_Cause.DC. A timer interrupt after
822 * the start time will be handled if the timer isn't disabled by count_ctl.DC,
823 * potentially before even returning, so the caller should be careful with
824 * ordering of CP0_Cause modifications so as not to lose it.
825 *
826 * Assumes CP0_Cause.DC is set (count disabled).
827 */
kvm_mips_count_enable_cause(struct kvm_vcpu * vcpu)828 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu)
829 {
830 struct mips_coproc *cop0 = vcpu->arch.cop0;
831 u32 count;
832
833 kvm_clear_c0_guest_cause(cop0, CAUSEF_DC);
834
835 /*
836 * Set the dynamic count to match the static count.
837 * This starts the hrtimer if count_ctl.DC allows it.
838 * Otherwise it conveniently updates the biases.
839 */
840 count = kvm_read_c0_guest_count(cop0);
841 kvm_mips_write_count(vcpu, count);
842 }
843
844 /**
845 * kvm_mips_set_count_ctl() - Update the count control KVM register.
846 * @vcpu: Virtual CPU.
847 * @count_ctl: Count control register new value.
848 *
849 * Set the count control KVM register. The timer is updated accordingly.
850 *
851 * Returns: -EINVAL if reserved bits are set.
852 * 0 on success.
853 */
kvm_mips_set_count_ctl(struct kvm_vcpu * vcpu,s64 count_ctl)854 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl)
855 {
856 struct mips_coproc *cop0 = vcpu->arch.cop0;
857 s64 changed = count_ctl ^ vcpu->arch.count_ctl;
858 s64 delta;
859 ktime_t expire, now;
860 u32 count, compare;
861
862 /* Only allow defined bits to be changed */
863 if (changed & ~(s64)(KVM_REG_MIPS_COUNT_CTL_DC))
864 return -EINVAL;
865
866 /* Apply new value */
867 vcpu->arch.count_ctl = count_ctl;
868
869 /* Master CP0_Count disable */
870 if (changed & KVM_REG_MIPS_COUNT_CTL_DC) {
871 /* Is CP0_Cause.DC already disabling CP0_Count? */
872 if (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC) {
873 if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)
874 /* Just record the current time */
875 vcpu->arch.count_resume = ktime_get();
876 } else if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) {
877 /* disable timer and record current time */
878 vcpu->arch.count_resume = kvm_mips_count_disable(vcpu);
879 } else {
880 /*
881 * Calculate timeout relative to static count at resume
882 * time (wrap 0 to 2^32).
883 */
884 count = kvm_read_c0_guest_count(cop0);
885 compare = kvm_read_c0_guest_compare(cop0);
886 delta = (u64)(u32)(compare - count - 1) + 1;
887 delta = div_u64(delta * NSEC_PER_SEC,
888 vcpu->arch.count_hz);
889 expire = ktime_add_ns(vcpu->arch.count_resume, delta);
890
891 /* Handle pending interrupt */
892 now = ktime_get();
893 if (ktime_compare(now, expire) >= 0)
894 /* Nothing should be waiting on the timeout */
895 kvm_mips_callbacks->queue_timer_int(vcpu);
896
897 /* Resume hrtimer without changing bias */
898 count = kvm_mips_read_count_running(vcpu, now);
899 kvm_mips_resume_hrtimer(vcpu, now, count);
900 }
901 }
902
903 return 0;
904 }
905
906 /**
907 * kvm_mips_set_count_resume() - Update the count resume KVM register.
908 * @vcpu: Virtual CPU.
909 * @count_resume: Count resume register new value.
910 *
911 * Set the count resume KVM register.
912 *
913 * Returns: -EINVAL if out of valid range (0..now).
914 * 0 on success.
915 */
kvm_mips_set_count_resume(struct kvm_vcpu * vcpu,s64 count_resume)916 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume)
917 {
918 /*
919 * It doesn't make sense for the resume time to be in the future, as it
920 * would be possible for the next interrupt to be more than a full
921 * period in the future.
922 */
923 if (count_resume < 0 || count_resume > ktime_to_ns(ktime_get()))
924 return -EINVAL;
925
926 vcpu->arch.count_resume = ns_to_ktime(count_resume);
927 return 0;
928 }
929
930 /**
931 * kvm_mips_count_timeout() - Push timer forward on timeout.
932 * @vcpu: Virtual CPU.
933 *
934 * Handle an hrtimer event by push the hrtimer forward a period.
935 *
936 * Returns: The hrtimer_restart value to return to the hrtimer subsystem.
937 */
kvm_mips_count_timeout(struct kvm_vcpu * vcpu)938 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu)
939 {
940 /* Add the Count period to the current expiry time */
941 hrtimer_add_expires_ns(&vcpu->arch.comparecount_timer,
942 vcpu->arch.count_period);
943 return HRTIMER_RESTART;
944 }
945
kvm_mips_emul_eret(struct kvm_vcpu * vcpu)946 enum emulation_result kvm_mips_emul_eret(struct kvm_vcpu *vcpu)
947 {
948 struct mips_coproc *cop0 = vcpu->arch.cop0;
949 enum emulation_result er = EMULATE_DONE;
950
951 if (kvm_read_c0_guest_status(cop0) & ST0_ERL) {
952 kvm_clear_c0_guest_status(cop0, ST0_ERL);
953 vcpu->arch.pc = kvm_read_c0_guest_errorepc(cop0);
954 } else if (kvm_read_c0_guest_status(cop0) & ST0_EXL) {
955 kvm_debug("[%#lx] ERET to %#lx\n", vcpu->arch.pc,
956 kvm_read_c0_guest_epc(cop0));
957 kvm_clear_c0_guest_status(cop0, ST0_EXL);
958 vcpu->arch.pc = kvm_read_c0_guest_epc(cop0);
959
960 } else {
961 kvm_err("[%#lx] ERET when MIPS_SR_EXL|MIPS_SR_ERL == 0\n",
962 vcpu->arch.pc);
963 er = EMULATE_FAIL;
964 }
965
966 return er;
967 }
968
kvm_mips_emul_wait(struct kvm_vcpu * vcpu)969 enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu)
970 {
971 kvm_debug("[%#lx] !!!WAIT!!! (%#lx)\n", vcpu->arch.pc,
972 vcpu->arch.pending_exceptions);
973
974 ++vcpu->stat.wait_exits;
975 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_WAIT);
976 if (!vcpu->arch.pending_exceptions) {
977 kvm_vz_lose_htimer(vcpu);
978 vcpu->arch.wait = 1;
979 kvm_vcpu_block(vcpu);
980
981 /*
982 * We we are runnable, then definitely go off to user space to
983 * check if any I/O interrupts are pending.
984 */
985 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
986 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
987 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
988 }
989 }
990
991 return EMULATE_DONE;
992 }
993
kvm_mips_change_entryhi(struct kvm_vcpu * vcpu,unsigned long entryhi)994 static void kvm_mips_change_entryhi(struct kvm_vcpu *vcpu,
995 unsigned long entryhi)
996 {
997 struct mips_coproc *cop0 = vcpu->arch.cop0;
998 struct mm_struct *kern_mm = &vcpu->arch.guest_kernel_mm;
999 int cpu, i;
1000 u32 nasid = entryhi & KVM_ENTRYHI_ASID;
1001
1002 if (((kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID) != nasid)) {
1003 trace_kvm_asid_change(vcpu, kvm_read_c0_guest_entryhi(cop0) &
1004 KVM_ENTRYHI_ASID, nasid);
1005
1006 /*
1007 * Flush entries from the GVA page tables.
1008 * Guest user page table will get flushed lazily on re-entry to
1009 * guest user if the guest ASID actually changes.
1010 */
1011 kvm_mips_flush_gva_pt(kern_mm->pgd, KMF_KERN);
1012
1013 /*
1014 * Regenerate/invalidate kernel MMU context.
1015 * The user MMU context will be regenerated lazily on re-entry
1016 * to guest user if the guest ASID actually changes.
1017 */
1018 preempt_disable();
1019 cpu = smp_processor_id();
1020 get_new_mmu_context(kern_mm);
1021 for_each_possible_cpu(i)
1022 if (i != cpu)
1023 set_cpu_context(i, kern_mm, 0);
1024 preempt_enable();
1025 }
1026 kvm_write_c0_guest_entryhi(cop0, entryhi);
1027 }
1028
kvm_mips_emul_tlbr(struct kvm_vcpu * vcpu)1029 enum emulation_result kvm_mips_emul_tlbr(struct kvm_vcpu *vcpu)
1030 {
1031 struct mips_coproc *cop0 = vcpu->arch.cop0;
1032 struct kvm_mips_tlb *tlb;
1033 unsigned long pc = vcpu->arch.pc;
1034 int index;
1035
1036 index = kvm_read_c0_guest_index(cop0);
1037 if (index < 0 || index >= KVM_MIPS_GUEST_TLB_SIZE) {
1038 /* UNDEFINED */
1039 kvm_debug("[%#lx] TLBR Index %#x out of range\n", pc, index);
1040 index &= KVM_MIPS_GUEST_TLB_SIZE - 1;
1041 }
1042
1043 tlb = &vcpu->arch.guest_tlb[index];
1044 kvm_write_c0_guest_pagemask(cop0, tlb->tlb_mask);
1045 kvm_write_c0_guest_entrylo0(cop0, tlb->tlb_lo[0]);
1046 kvm_write_c0_guest_entrylo1(cop0, tlb->tlb_lo[1]);
1047 kvm_mips_change_entryhi(vcpu, tlb->tlb_hi);
1048
1049 return EMULATE_DONE;
1050 }
1051
1052 /**
1053 * kvm_mips_invalidate_guest_tlb() - Indicates a change in guest MMU map.
1054 * @vcpu: VCPU with changed mappings.
1055 * @tlb: TLB entry being removed.
1056 *
1057 * This is called to indicate a single change in guest MMU mappings, so that we
1058 * can arrange TLB flushes on this and other CPUs.
1059 */
kvm_mips_invalidate_guest_tlb(struct kvm_vcpu * vcpu,struct kvm_mips_tlb * tlb)1060 static void kvm_mips_invalidate_guest_tlb(struct kvm_vcpu *vcpu,
1061 struct kvm_mips_tlb *tlb)
1062 {
1063 struct mm_struct *kern_mm = &vcpu->arch.guest_kernel_mm;
1064 struct mm_struct *user_mm = &vcpu->arch.guest_user_mm;
1065 int cpu, i;
1066 bool user;
1067
1068 /* No need to flush for entries which are already invalid */
1069 if (!((tlb->tlb_lo[0] | tlb->tlb_lo[1]) & ENTRYLO_V))
1070 return;
1071 /* Don't touch host kernel page tables or TLB mappings */
1072 if ((unsigned long)tlb->tlb_hi > 0x7fffffff)
1073 return;
1074 /* User address space doesn't need flushing for KSeg2/3 changes */
1075 user = tlb->tlb_hi < KVM_GUEST_KSEG0;
1076
1077 preempt_disable();
1078
1079 /* Invalidate page table entries */
1080 kvm_trap_emul_invalidate_gva(vcpu, tlb->tlb_hi & VPN2_MASK, user);
1081
1082 /*
1083 * Probe the shadow host TLB for the entry being overwritten, if one
1084 * matches, invalidate it
1085 */
1086 kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi, user, true);
1087
1088 /* Invalidate the whole ASID on other CPUs */
1089 cpu = smp_processor_id();
1090 for_each_possible_cpu(i) {
1091 if (i == cpu)
1092 continue;
1093 if (user)
1094 set_cpu_context(i, user_mm, 0);
1095 set_cpu_context(i, kern_mm, 0);
1096 }
1097
1098 preempt_enable();
1099 }
1100
1101 /* Write Guest TLB Entry @ Index */
kvm_mips_emul_tlbwi(struct kvm_vcpu * vcpu)1102 enum emulation_result kvm_mips_emul_tlbwi(struct kvm_vcpu *vcpu)
1103 {
1104 struct mips_coproc *cop0 = vcpu->arch.cop0;
1105 int index = kvm_read_c0_guest_index(cop0);
1106 struct kvm_mips_tlb *tlb = NULL;
1107 unsigned long pc = vcpu->arch.pc;
1108
1109 if (index < 0 || index >= KVM_MIPS_GUEST_TLB_SIZE) {
1110 kvm_debug("%s: illegal index: %d\n", __func__, index);
1111 kvm_debug("[%#lx] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n",
1112 pc, index, kvm_read_c0_guest_entryhi(cop0),
1113 kvm_read_c0_guest_entrylo0(cop0),
1114 kvm_read_c0_guest_entrylo1(cop0),
1115 kvm_read_c0_guest_pagemask(cop0));
1116 index = (index & ~0x80000000) % KVM_MIPS_GUEST_TLB_SIZE;
1117 }
1118
1119 tlb = &vcpu->arch.guest_tlb[index];
1120
1121 kvm_mips_invalidate_guest_tlb(vcpu, tlb);
1122
1123 tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);
1124 tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
1125 tlb->tlb_lo[0] = kvm_read_c0_guest_entrylo0(cop0);
1126 tlb->tlb_lo[1] = kvm_read_c0_guest_entrylo1(cop0);
1127
1128 kvm_debug("[%#lx] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n",
1129 pc, index, kvm_read_c0_guest_entryhi(cop0),
1130 kvm_read_c0_guest_entrylo0(cop0),
1131 kvm_read_c0_guest_entrylo1(cop0),
1132 kvm_read_c0_guest_pagemask(cop0));
1133
1134 return EMULATE_DONE;
1135 }
1136
1137 /* Write Guest TLB Entry @ Random Index */
kvm_mips_emul_tlbwr(struct kvm_vcpu * vcpu)1138 enum emulation_result kvm_mips_emul_tlbwr(struct kvm_vcpu *vcpu)
1139 {
1140 struct mips_coproc *cop0 = vcpu->arch.cop0;
1141 struct kvm_mips_tlb *tlb = NULL;
1142 unsigned long pc = vcpu->arch.pc;
1143 int index;
1144
1145 index = prandom_u32_max(KVM_MIPS_GUEST_TLB_SIZE);
1146 tlb = &vcpu->arch.guest_tlb[index];
1147
1148 kvm_mips_invalidate_guest_tlb(vcpu, tlb);
1149
1150 tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);
1151 tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
1152 tlb->tlb_lo[0] = kvm_read_c0_guest_entrylo0(cop0);
1153 tlb->tlb_lo[1] = kvm_read_c0_guest_entrylo1(cop0);
1154
1155 kvm_debug("[%#lx] COP0_TLBWR[%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx)\n",
1156 pc, index, kvm_read_c0_guest_entryhi(cop0),
1157 kvm_read_c0_guest_entrylo0(cop0),
1158 kvm_read_c0_guest_entrylo1(cop0));
1159
1160 return EMULATE_DONE;
1161 }
1162
kvm_mips_emul_tlbp(struct kvm_vcpu * vcpu)1163 enum emulation_result kvm_mips_emul_tlbp(struct kvm_vcpu *vcpu)
1164 {
1165 struct mips_coproc *cop0 = vcpu->arch.cop0;
1166 long entryhi = kvm_read_c0_guest_entryhi(cop0);
1167 unsigned long pc = vcpu->arch.pc;
1168 int index = -1;
1169
1170 index = kvm_mips_guest_tlb_lookup(vcpu, entryhi);
1171
1172 kvm_write_c0_guest_index(cop0, index);
1173
1174 kvm_debug("[%#lx] COP0_TLBP (entryhi: %#lx), index: %d\n", pc, entryhi,
1175 index);
1176
1177 return EMULATE_DONE;
1178 }
1179
1180 /**
1181 * kvm_mips_config1_wrmask() - Find mask of writable bits in guest Config1
1182 * @vcpu: Virtual CPU.
1183 *
1184 * Finds the mask of bits which are writable in the guest's Config1 CP0
1185 * register, by userland (currently read-only to the guest).
1186 */
kvm_mips_config1_wrmask(struct kvm_vcpu * vcpu)1187 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu)
1188 {
1189 unsigned int mask = 0;
1190
1191 /* Permit FPU to be present if FPU is supported */
1192 if (kvm_mips_guest_can_have_fpu(&vcpu->arch))
1193 mask |= MIPS_CONF1_FP;
1194
1195 return mask;
1196 }
1197
1198 /**
1199 * kvm_mips_config3_wrmask() - Find mask of writable bits in guest Config3
1200 * @vcpu: Virtual CPU.
1201 *
1202 * Finds the mask of bits which are writable in the guest's Config3 CP0
1203 * register, by userland (currently read-only to the guest).
1204 */
kvm_mips_config3_wrmask(struct kvm_vcpu * vcpu)1205 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu)
1206 {
1207 /* Config4 and ULRI are optional */
1208 unsigned int mask = MIPS_CONF_M | MIPS_CONF3_ULRI;
1209
1210 /* Permit MSA to be present if MSA is supported */
1211 if (kvm_mips_guest_can_have_msa(&vcpu->arch))
1212 mask |= MIPS_CONF3_MSA;
1213
1214 return mask;
1215 }
1216
1217 /**
1218 * kvm_mips_config4_wrmask() - Find mask of writable bits in guest Config4
1219 * @vcpu: Virtual CPU.
1220 *
1221 * Finds the mask of bits which are writable in the guest's Config4 CP0
1222 * register, by userland (currently read-only to the guest).
1223 */
kvm_mips_config4_wrmask(struct kvm_vcpu * vcpu)1224 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu)
1225 {
1226 /* Config5 is optional */
1227 unsigned int mask = MIPS_CONF_M;
1228
1229 /* KScrExist */
1230 mask |= 0xfc << MIPS_CONF4_KSCREXIST_SHIFT;
1231
1232 return mask;
1233 }
1234
1235 /**
1236 * kvm_mips_config5_wrmask() - Find mask of writable bits in guest Config5
1237 * @vcpu: Virtual CPU.
1238 *
1239 * Finds the mask of bits which are writable in the guest's Config5 CP0
1240 * register, by the guest itself.
1241 */
kvm_mips_config5_wrmask(struct kvm_vcpu * vcpu)1242 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu)
1243 {
1244 unsigned int mask = 0;
1245
1246 /* Permit MSAEn changes if MSA supported and enabled */
1247 if (kvm_mips_guest_has_msa(&vcpu->arch))
1248 mask |= MIPS_CONF5_MSAEN;
1249
1250 /*
1251 * Permit guest FPU mode changes if FPU is enabled and the relevant
1252 * feature exists according to FIR register.
1253 */
1254 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1255 if (cpu_has_fre)
1256 mask |= MIPS_CONF5_FRE;
1257 /* We don't support UFR or UFE */
1258 }
1259
1260 return mask;
1261 }
1262
kvm_mips_emulate_CP0(union mips_instruction inst,u32 * opc,u32 cause,struct kvm_vcpu * vcpu)1263 enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst,
1264 u32 *opc, u32 cause,
1265 struct kvm_vcpu *vcpu)
1266 {
1267 struct mips_coproc *cop0 = vcpu->arch.cop0;
1268 enum emulation_result er = EMULATE_DONE;
1269 u32 rt, rd, sel;
1270 unsigned long curr_pc;
1271
1272 /*
1273 * Update PC and hold onto current PC in case there is
1274 * an error and we want to rollback the PC
1275 */
1276 curr_pc = vcpu->arch.pc;
1277 er = update_pc(vcpu, cause);
1278 if (er == EMULATE_FAIL)
1279 return er;
1280
1281 if (inst.co_format.co) {
1282 switch (inst.co_format.func) {
1283 case tlbr_op: /* Read indexed TLB entry */
1284 er = kvm_mips_emul_tlbr(vcpu);
1285 break;
1286 case tlbwi_op: /* Write indexed */
1287 er = kvm_mips_emul_tlbwi(vcpu);
1288 break;
1289 case tlbwr_op: /* Write random */
1290 er = kvm_mips_emul_tlbwr(vcpu);
1291 break;
1292 case tlbp_op: /* TLB Probe */
1293 er = kvm_mips_emul_tlbp(vcpu);
1294 break;
1295 case rfe_op:
1296 kvm_err("!!!COP0_RFE!!!\n");
1297 break;
1298 case eret_op:
1299 er = kvm_mips_emul_eret(vcpu);
1300 goto dont_update_pc;
1301 case wait_op:
1302 er = kvm_mips_emul_wait(vcpu);
1303 break;
1304 case hypcall_op:
1305 er = kvm_mips_emul_hypcall(vcpu, inst);
1306 break;
1307 }
1308 } else {
1309 rt = inst.c0r_format.rt;
1310 rd = inst.c0r_format.rd;
1311 sel = inst.c0r_format.sel;
1312
1313 switch (inst.c0r_format.rs) {
1314 case mfc_op:
1315 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
1316 cop0->stat[rd][sel]++;
1317 #endif
1318 /* Get reg */
1319 if ((rd == MIPS_CP0_COUNT) && (sel == 0)) {
1320 vcpu->arch.gprs[rt] =
1321 (s32)kvm_mips_read_count(vcpu);
1322 } else if ((rd == MIPS_CP0_ERRCTL) && (sel == 0)) {
1323 vcpu->arch.gprs[rt] = 0x0;
1324 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1325 kvm_mips_trans_mfc0(inst, opc, vcpu);
1326 #endif
1327 } else {
1328 vcpu->arch.gprs[rt] = (s32)cop0->reg[rd][sel];
1329
1330 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1331 kvm_mips_trans_mfc0(inst, opc, vcpu);
1332 #endif
1333 }
1334
1335 trace_kvm_hwr(vcpu, KVM_TRACE_MFC0,
1336 KVM_TRACE_COP0(rd, sel),
1337 vcpu->arch.gprs[rt]);
1338 break;
1339
1340 case dmfc_op:
1341 vcpu->arch.gprs[rt] = cop0->reg[rd][sel];
1342
1343 trace_kvm_hwr(vcpu, KVM_TRACE_DMFC0,
1344 KVM_TRACE_COP0(rd, sel),
1345 vcpu->arch.gprs[rt]);
1346 break;
1347
1348 case mtc_op:
1349 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
1350 cop0->stat[rd][sel]++;
1351 #endif
1352 trace_kvm_hwr(vcpu, KVM_TRACE_MTC0,
1353 KVM_TRACE_COP0(rd, sel),
1354 vcpu->arch.gprs[rt]);
1355
1356 if ((rd == MIPS_CP0_TLB_INDEX)
1357 && (vcpu->arch.gprs[rt] >=
1358 KVM_MIPS_GUEST_TLB_SIZE)) {
1359 kvm_err("Invalid TLB Index: %ld",
1360 vcpu->arch.gprs[rt]);
1361 er = EMULATE_FAIL;
1362 break;
1363 }
1364 if ((rd == MIPS_CP0_PRID) && (sel == 1)) {
1365 /*
1366 * Preserve core number, and keep the exception
1367 * base in guest KSeg0.
1368 */
1369 kvm_change_c0_guest_ebase(cop0, 0x1ffff000,
1370 vcpu->arch.gprs[rt]);
1371 } else if (rd == MIPS_CP0_TLB_HI && sel == 0) {
1372 kvm_mips_change_entryhi(vcpu,
1373 vcpu->arch.gprs[rt]);
1374 }
1375 /* Are we writing to COUNT */
1376 else if ((rd == MIPS_CP0_COUNT) && (sel == 0)) {
1377 kvm_mips_write_count(vcpu, vcpu->arch.gprs[rt]);
1378 goto done;
1379 } else if ((rd == MIPS_CP0_COMPARE) && (sel == 0)) {
1380 /* If we are writing to COMPARE */
1381 /* Clear pending timer interrupt, if any */
1382 kvm_mips_write_compare(vcpu,
1383 vcpu->arch.gprs[rt],
1384 true);
1385 } else if ((rd == MIPS_CP0_STATUS) && (sel == 0)) {
1386 unsigned int old_val, val, change;
1387
1388 old_val = kvm_read_c0_guest_status(cop0);
1389 val = vcpu->arch.gprs[rt];
1390 change = val ^ old_val;
1391
1392 /* Make sure that the NMI bit is never set */
1393 val &= ~ST0_NMI;
1394
1395 /*
1396 * Don't allow CU1 or FR to be set unless FPU
1397 * capability enabled and exists in guest
1398 * configuration.
1399 */
1400 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
1401 val &= ~(ST0_CU1 | ST0_FR);
1402
1403 /*
1404 * Also don't allow FR to be set if host doesn't
1405 * support it.
1406 */
1407 if (!(current_cpu_data.fpu_id & MIPS_FPIR_F64))
1408 val &= ~ST0_FR;
1409
1410
1411 /* Handle changes in FPU mode */
1412 preempt_disable();
1413
1414 /*
1415 * FPU and Vector register state is made
1416 * UNPREDICTABLE by a change of FR, so don't
1417 * even bother saving it.
1418 */
1419 if (change & ST0_FR)
1420 kvm_drop_fpu(vcpu);
1421
1422 /*
1423 * If MSA state is already live, it is undefined
1424 * how it interacts with FR=0 FPU state, and we
1425 * don't want to hit reserved instruction
1426 * exceptions trying to save the MSA state later
1427 * when CU=1 && FR=1, so play it safe and save
1428 * it first.
1429 */
1430 if (change & ST0_CU1 && !(val & ST0_FR) &&
1431 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1432 kvm_lose_fpu(vcpu);
1433
1434 /*
1435 * Propagate CU1 (FPU enable) changes
1436 * immediately if the FPU context is already
1437 * loaded. When disabling we leave the context
1438 * loaded so it can be quickly enabled again in
1439 * the near future.
1440 */
1441 if (change & ST0_CU1 &&
1442 vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)
1443 change_c0_status(ST0_CU1, val);
1444
1445 preempt_enable();
1446
1447 kvm_write_c0_guest_status(cop0, val);
1448
1449 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1450 /*
1451 * If FPU present, we need CU1/FR bits to take
1452 * effect fairly soon.
1453 */
1454 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
1455 kvm_mips_trans_mtc0(inst, opc, vcpu);
1456 #endif
1457 } else if ((rd == MIPS_CP0_CONFIG) && (sel == 5)) {
1458 unsigned int old_val, val, change, wrmask;
1459
1460 old_val = kvm_read_c0_guest_config5(cop0);
1461 val = vcpu->arch.gprs[rt];
1462
1463 /* Only a few bits are writable in Config5 */
1464 wrmask = kvm_mips_config5_wrmask(vcpu);
1465 change = (val ^ old_val) & wrmask;
1466 val = old_val ^ change;
1467
1468
1469 /* Handle changes in FPU/MSA modes */
1470 preempt_disable();
1471
1472 /*
1473 * Propagate FRE changes immediately if the FPU
1474 * context is already loaded.
1475 */
1476 if (change & MIPS_CONF5_FRE &&
1477 vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)
1478 change_c0_config5(MIPS_CONF5_FRE, val);
1479
1480 /*
1481 * Propagate MSAEn changes immediately if the
1482 * MSA context is already loaded. When disabling
1483 * we leave the context loaded so it can be
1484 * quickly enabled again in the near future.
1485 */
1486 if (change & MIPS_CONF5_MSAEN &&
1487 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1488 change_c0_config5(MIPS_CONF5_MSAEN,
1489 val);
1490
1491 preempt_enable();
1492
1493 kvm_write_c0_guest_config5(cop0, val);
1494 } else if ((rd == MIPS_CP0_CAUSE) && (sel == 0)) {
1495 u32 old_cause, new_cause;
1496
1497 old_cause = kvm_read_c0_guest_cause(cop0);
1498 new_cause = vcpu->arch.gprs[rt];
1499 /* Update R/W bits */
1500 kvm_change_c0_guest_cause(cop0, 0x08800300,
1501 new_cause);
1502 /* DC bit enabling/disabling timer? */
1503 if ((old_cause ^ new_cause) & CAUSEF_DC) {
1504 if (new_cause & CAUSEF_DC)
1505 kvm_mips_count_disable_cause(vcpu);
1506 else
1507 kvm_mips_count_enable_cause(vcpu);
1508 }
1509 } else if ((rd == MIPS_CP0_HWRENA) && (sel == 0)) {
1510 u32 mask = MIPS_HWRENA_CPUNUM |
1511 MIPS_HWRENA_SYNCISTEP |
1512 MIPS_HWRENA_CC |
1513 MIPS_HWRENA_CCRES;
1514
1515 if (kvm_read_c0_guest_config3(cop0) &
1516 MIPS_CONF3_ULRI)
1517 mask |= MIPS_HWRENA_ULR;
1518 cop0->reg[rd][sel] = vcpu->arch.gprs[rt] & mask;
1519 } else {
1520 cop0->reg[rd][sel] = vcpu->arch.gprs[rt];
1521 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1522 kvm_mips_trans_mtc0(inst, opc, vcpu);
1523 #endif
1524 }
1525 break;
1526
1527 case dmtc_op:
1528 kvm_err("!!!!!!![%#lx]dmtc_op: rt: %d, rd: %d, sel: %d!!!!!!\n",
1529 vcpu->arch.pc, rt, rd, sel);
1530 trace_kvm_hwr(vcpu, KVM_TRACE_DMTC0,
1531 KVM_TRACE_COP0(rd, sel),
1532 vcpu->arch.gprs[rt]);
1533 er = EMULATE_FAIL;
1534 break;
1535
1536 case mfmc0_op:
1537 #ifdef KVM_MIPS_DEBUG_COP0_COUNTERS
1538 cop0->stat[MIPS_CP0_STATUS][0]++;
1539 #endif
1540 if (rt != 0)
1541 vcpu->arch.gprs[rt] =
1542 kvm_read_c0_guest_status(cop0);
1543 /* EI */
1544 if (inst.mfmc0_format.sc) {
1545 kvm_debug("[%#lx] mfmc0_op: EI\n",
1546 vcpu->arch.pc);
1547 kvm_set_c0_guest_status(cop0, ST0_IE);
1548 } else {
1549 kvm_debug("[%#lx] mfmc0_op: DI\n",
1550 vcpu->arch.pc);
1551 kvm_clear_c0_guest_status(cop0, ST0_IE);
1552 }
1553
1554 break;
1555
1556 case wrpgpr_op:
1557 {
1558 u32 css = cop0->reg[MIPS_CP0_STATUS][2] & 0xf;
1559 u32 pss =
1560 (cop0->reg[MIPS_CP0_STATUS][2] >> 6) & 0xf;
1561 /*
1562 * We don't support any shadow register sets, so
1563 * SRSCtl[PSS] == SRSCtl[CSS] = 0
1564 */
1565 if (css || pss) {
1566 er = EMULATE_FAIL;
1567 break;
1568 }
1569 kvm_debug("WRPGPR[%d][%d] = %#lx\n", pss, rd,
1570 vcpu->arch.gprs[rt]);
1571 vcpu->arch.gprs[rd] = vcpu->arch.gprs[rt];
1572 }
1573 break;
1574 default:
1575 kvm_err("[%#lx]MachEmulateCP0: unsupported COP0, copz: 0x%x\n",
1576 vcpu->arch.pc, inst.c0r_format.rs);
1577 er = EMULATE_FAIL;
1578 break;
1579 }
1580 }
1581
1582 done:
1583 /* Rollback PC only if emulation was unsuccessful */
1584 if (er == EMULATE_FAIL)
1585 vcpu->arch.pc = curr_pc;
1586
1587 dont_update_pc:
1588 /*
1589 * This is for special instructions whose emulation
1590 * updates the PC, so do not overwrite the PC under
1591 * any circumstances
1592 */
1593
1594 return er;
1595 }
1596
kvm_mips_emulate_store(union mips_instruction inst,u32 cause,struct kvm_vcpu * vcpu)1597 enum emulation_result kvm_mips_emulate_store(union mips_instruction inst,
1598 u32 cause,
1599 struct kvm_vcpu *vcpu)
1600 {
1601 int r;
1602 enum emulation_result er;
1603 u32 rt;
1604 struct kvm_run *run = vcpu->run;
1605 void *data = run->mmio.data;
1606 unsigned int imme;
1607 unsigned long curr_pc;
1608
1609 /*
1610 * Update PC and hold onto current PC in case there is
1611 * an error and we want to rollback the PC
1612 */
1613 curr_pc = vcpu->arch.pc;
1614 er = update_pc(vcpu, cause);
1615 if (er == EMULATE_FAIL)
1616 return er;
1617
1618 rt = inst.i_format.rt;
1619
1620 run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa(
1621 vcpu->arch.host_cp0_badvaddr);
1622 if (run->mmio.phys_addr == KVM_INVALID_ADDR)
1623 goto out_fail;
1624
1625 switch (inst.i_format.opcode) {
1626 #if defined(CONFIG_64BIT) && defined(CONFIG_KVM_MIPS_VZ)
1627 case sd_op:
1628 run->mmio.len = 8;
1629 *(u64 *)data = vcpu->arch.gprs[rt];
1630
1631 kvm_debug("[%#lx] OP_SD: eaddr: %#lx, gpr: %#lx, data: %#llx\n",
1632 vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1633 vcpu->arch.gprs[rt], *(u64 *)data);
1634 break;
1635 #endif
1636
1637 case sw_op:
1638 run->mmio.len = 4;
1639 *(u32 *)data = vcpu->arch.gprs[rt];
1640
1641 kvm_debug("[%#lx] OP_SW: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1642 vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1643 vcpu->arch.gprs[rt], *(u32 *)data);
1644 break;
1645
1646 case sh_op:
1647 run->mmio.len = 2;
1648 *(u16 *)data = vcpu->arch.gprs[rt];
1649
1650 kvm_debug("[%#lx] OP_SH: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1651 vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1652 vcpu->arch.gprs[rt], *(u16 *)data);
1653 break;
1654
1655 case sb_op:
1656 run->mmio.len = 1;
1657 *(u8 *)data = vcpu->arch.gprs[rt];
1658
1659 kvm_debug("[%#lx] OP_SB: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1660 vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1661 vcpu->arch.gprs[rt], *(u8 *)data);
1662 break;
1663
1664 case swl_op:
1665 run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa(
1666 vcpu->arch.host_cp0_badvaddr) & (~0x3);
1667 run->mmio.len = 4;
1668 imme = vcpu->arch.host_cp0_badvaddr & 0x3;
1669 switch (imme) {
1670 case 0:
1671 *(u32 *)data = ((*(u32 *)data) & 0xffffff00) |
1672 (vcpu->arch.gprs[rt] >> 24);
1673 break;
1674 case 1:
1675 *(u32 *)data = ((*(u32 *)data) & 0xffff0000) |
1676 (vcpu->arch.gprs[rt] >> 16);
1677 break;
1678 case 2:
1679 *(u32 *)data = ((*(u32 *)data) & 0xff000000) |
1680 (vcpu->arch.gprs[rt] >> 8);
1681 break;
1682 case 3:
1683 *(u32 *)data = vcpu->arch.gprs[rt];
1684 break;
1685 default:
1686 break;
1687 }
1688
1689 kvm_debug("[%#lx] OP_SWL: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1690 vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1691 vcpu->arch.gprs[rt], *(u32 *)data);
1692 break;
1693
1694 case swr_op:
1695 run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa(
1696 vcpu->arch.host_cp0_badvaddr) & (~0x3);
1697 run->mmio.len = 4;
1698 imme = vcpu->arch.host_cp0_badvaddr & 0x3;
1699 switch (imme) {
1700 case 0:
1701 *(u32 *)data = vcpu->arch.gprs[rt];
1702 break;
1703 case 1:
1704 *(u32 *)data = ((*(u32 *)data) & 0xff) |
1705 (vcpu->arch.gprs[rt] << 8);
1706 break;
1707 case 2:
1708 *(u32 *)data = ((*(u32 *)data) & 0xffff) |
1709 (vcpu->arch.gprs[rt] << 16);
1710 break;
1711 case 3:
1712 *(u32 *)data = ((*(u32 *)data) & 0xffffff) |
1713 (vcpu->arch.gprs[rt] << 24);
1714 break;
1715 default:
1716 break;
1717 }
1718
1719 kvm_debug("[%#lx] OP_SWR: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1720 vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1721 vcpu->arch.gprs[rt], *(u32 *)data);
1722 break;
1723
1724 #if defined(CONFIG_64BIT) && defined(CONFIG_KVM_MIPS_VZ)
1725 case sdl_op:
1726 run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa(
1727 vcpu->arch.host_cp0_badvaddr) & (~0x7);
1728
1729 run->mmio.len = 8;
1730 imme = vcpu->arch.host_cp0_badvaddr & 0x7;
1731 switch (imme) {
1732 case 0:
1733 *(u64 *)data = ((*(u64 *)data) & 0xffffffffffffff00) |
1734 ((vcpu->arch.gprs[rt] >> 56) & 0xff);
1735 break;
1736 case 1:
1737 *(u64 *)data = ((*(u64 *)data) & 0xffffffffffff0000) |
1738 ((vcpu->arch.gprs[rt] >> 48) & 0xffff);
1739 break;
1740 case 2:
1741 *(u64 *)data = ((*(u64 *)data) & 0xffffffffff000000) |
1742 ((vcpu->arch.gprs[rt] >> 40) & 0xffffff);
1743 break;
1744 case 3:
1745 *(u64 *)data = ((*(u64 *)data) & 0xffffffff00000000) |
1746 ((vcpu->arch.gprs[rt] >> 32) & 0xffffffff);
1747 break;
1748 case 4:
1749 *(u64 *)data = ((*(u64 *)data) & 0xffffff0000000000) |
1750 ((vcpu->arch.gprs[rt] >> 24) & 0xffffffffff);
1751 break;
1752 case 5:
1753 *(u64 *)data = ((*(u64 *)data) & 0xffff000000000000) |
1754 ((vcpu->arch.gprs[rt] >> 16) & 0xffffffffffff);
1755 break;
1756 case 6:
1757 *(u64 *)data = ((*(u64 *)data) & 0xff00000000000000) |
1758 ((vcpu->arch.gprs[rt] >> 8) & 0xffffffffffffff);
1759 break;
1760 case 7:
1761 *(u64 *)data = vcpu->arch.gprs[rt];
1762 break;
1763 default:
1764 break;
1765 }
1766
1767 kvm_debug("[%#lx] OP_SDL: eaddr: %#lx, gpr: %#lx, data: %llx\n",
1768 vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1769 vcpu->arch.gprs[rt], *(u64 *)data);
1770 break;
1771
1772 case sdr_op:
1773 run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa(
1774 vcpu->arch.host_cp0_badvaddr) & (~0x7);
1775
1776 run->mmio.len = 8;
1777 imme = vcpu->arch.host_cp0_badvaddr & 0x7;
1778 switch (imme) {
1779 case 0:
1780 *(u64 *)data = vcpu->arch.gprs[rt];
1781 break;
1782 case 1:
1783 *(u64 *)data = ((*(u64 *)data) & 0xff) |
1784 (vcpu->arch.gprs[rt] << 8);
1785 break;
1786 case 2:
1787 *(u64 *)data = ((*(u64 *)data) & 0xffff) |
1788 (vcpu->arch.gprs[rt] << 16);
1789 break;
1790 case 3:
1791 *(u64 *)data = ((*(u64 *)data) & 0xffffff) |
1792 (vcpu->arch.gprs[rt] << 24);
1793 break;
1794 case 4:
1795 *(u64 *)data = ((*(u64 *)data) & 0xffffffff) |
1796 (vcpu->arch.gprs[rt] << 32);
1797 break;
1798 case 5:
1799 *(u64 *)data = ((*(u64 *)data) & 0xffffffffff) |
1800 (vcpu->arch.gprs[rt] << 40);
1801 break;
1802 case 6:
1803 *(u64 *)data = ((*(u64 *)data) & 0xffffffffffff) |
1804 (vcpu->arch.gprs[rt] << 48);
1805 break;
1806 case 7:
1807 *(u64 *)data = ((*(u64 *)data) & 0xffffffffffffff) |
1808 (vcpu->arch.gprs[rt] << 56);
1809 break;
1810 default:
1811 break;
1812 }
1813
1814 kvm_debug("[%#lx] OP_SDR: eaddr: %#lx, gpr: %#lx, data: %llx\n",
1815 vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1816 vcpu->arch.gprs[rt], *(u64 *)data);
1817 break;
1818 #endif
1819
1820 #ifdef CONFIG_CPU_LOONGSON64
1821 case sdc2_op:
1822 rt = inst.loongson3_lsdc2_format.rt;
1823 switch (inst.loongson3_lsdc2_format.opcode1) {
1824 /*
1825 * Loongson-3 overridden sdc2 instructions.
1826 * opcode1 instruction
1827 * 0x0 gssbx: store 1 bytes from GPR
1828 * 0x1 gsshx: store 2 bytes from GPR
1829 * 0x2 gsswx: store 4 bytes from GPR
1830 * 0x3 gssdx: store 8 bytes from GPR
1831 */
1832 case 0x0:
1833 run->mmio.len = 1;
1834 *(u8 *)data = vcpu->arch.gprs[rt];
1835
1836 kvm_debug("[%#lx] OP_GSSBX: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1837 vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1838 vcpu->arch.gprs[rt], *(u8 *)data);
1839 break;
1840 case 0x1:
1841 run->mmio.len = 2;
1842 *(u16 *)data = vcpu->arch.gprs[rt];
1843
1844 kvm_debug("[%#lx] OP_GSSSHX: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1845 vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1846 vcpu->arch.gprs[rt], *(u16 *)data);
1847 break;
1848 case 0x2:
1849 run->mmio.len = 4;
1850 *(u32 *)data = vcpu->arch.gprs[rt];
1851
1852 kvm_debug("[%#lx] OP_GSSWX: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1853 vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1854 vcpu->arch.gprs[rt], *(u32 *)data);
1855 break;
1856 case 0x3:
1857 run->mmio.len = 8;
1858 *(u64 *)data = vcpu->arch.gprs[rt];
1859
1860 kvm_debug("[%#lx] OP_GSSDX: eaddr: %#lx, gpr: %#lx, data: %#llx\n",
1861 vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1862 vcpu->arch.gprs[rt], *(u64 *)data);
1863 break;
1864 default:
1865 kvm_err("Godson Extended GS-Store not yet supported (inst=0x%08x)\n",
1866 inst.word);
1867 break;
1868 }
1869 break;
1870 #endif
1871 default:
1872 kvm_err("Store not yet supported (inst=0x%08x)\n",
1873 inst.word);
1874 goto out_fail;
1875 }
1876
1877 vcpu->mmio_needed = 1;
1878 run->mmio.is_write = 1;
1879 vcpu->mmio_is_write = 1;
1880
1881 r = kvm_io_bus_write(vcpu, KVM_MMIO_BUS,
1882 run->mmio.phys_addr, run->mmio.len, data);
1883
1884 if (!r) {
1885 vcpu->mmio_needed = 0;
1886 return EMULATE_DONE;
1887 }
1888
1889 return EMULATE_DO_MMIO;
1890
1891 out_fail:
1892 /* Rollback PC if emulation was unsuccessful */
1893 vcpu->arch.pc = curr_pc;
1894 return EMULATE_FAIL;
1895 }
1896
kvm_mips_emulate_load(union mips_instruction inst,u32 cause,struct kvm_vcpu * vcpu)1897 enum emulation_result kvm_mips_emulate_load(union mips_instruction inst,
1898 u32 cause, struct kvm_vcpu *vcpu)
1899 {
1900 struct kvm_run *run = vcpu->run;
1901 int r;
1902 enum emulation_result er;
1903 unsigned long curr_pc;
1904 u32 op, rt;
1905 unsigned int imme;
1906
1907 rt = inst.i_format.rt;
1908 op = inst.i_format.opcode;
1909
1910 /*
1911 * Find the resume PC now while we have safe and easy access to the
1912 * prior branch instruction, and save it for
1913 * kvm_mips_complete_mmio_load() to restore later.
1914 */
1915 curr_pc = vcpu->arch.pc;
1916 er = update_pc(vcpu, cause);
1917 if (er == EMULATE_FAIL)
1918 return er;
1919 vcpu->arch.io_pc = vcpu->arch.pc;
1920 vcpu->arch.pc = curr_pc;
1921
1922 vcpu->arch.io_gpr = rt;
1923
1924 run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa(
1925 vcpu->arch.host_cp0_badvaddr);
1926 if (run->mmio.phys_addr == KVM_INVALID_ADDR)
1927 return EMULATE_FAIL;
1928
1929 vcpu->mmio_needed = 2; /* signed */
1930 switch (op) {
1931 #if defined(CONFIG_64BIT) && defined(CONFIG_KVM_MIPS_VZ)
1932 case ld_op:
1933 run->mmio.len = 8;
1934 break;
1935
1936 case lwu_op:
1937 vcpu->mmio_needed = 1; /* unsigned */
1938 fallthrough;
1939 #endif
1940 case lw_op:
1941 run->mmio.len = 4;
1942 break;
1943
1944 case lhu_op:
1945 vcpu->mmio_needed = 1; /* unsigned */
1946 fallthrough;
1947 case lh_op:
1948 run->mmio.len = 2;
1949 break;
1950
1951 case lbu_op:
1952 vcpu->mmio_needed = 1; /* unsigned */
1953 fallthrough;
1954 case lb_op:
1955 run->mmio.len = 1;
1956 break;
1957
1958 case lwl_op:
1959 run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa(
1960 vcpu->arch.host_cp0_badvaddr) & (~0x3);
1961
1962 run->mmio.len = 4;
1963 imme = vcpu->arch.host_cp0_badvaddr & 0x3;
1964 switch (imme) {
1965 case 0:
1966 vcpu->mmio_needed = 3; /* 1 byte */
1967 break;
1968 case 1:
1969 vcpu->mmio_needed = 4; /* 2 bytes */
1970 break;
1971 case 2:
1972 vcpu->mmio_needed = 5; /* 3 bytes */
1973 break;
1974 case 3:
1975 vcpu->mmio_needed = 6; /* 4 bytes */
1976 break;
1977 default:
1978 break;
1979 }
1980 break;
1981
1982 case lwr_op:
1983 run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa(
1984 vcpu->arch.host_cp0_badvaddr) & (~0x3);
1985
1986 run->mmio.len = 4;
1987 imme = vcpu->arch.host_cp0_badvaddr & 0x3;
1988 switch (imme) {
1989 case 0:
1990 vcpu->mmio_needed = 7; /* 4 bytes */
1991 break;
1992 case 1:
1993 vcpu->mmio_needed = 8; /* 3 bytes */
1994 break;
1995 case 2:
1996 vcpu->mmio_needed = 9; /* 2 bytes */
1997 break;
1998 case 3:
1999 vcpu->mmio_needed = 10; /* 1 byte */
2000 break;
2001 default:
2002 break;
2003 }
2004 break;
2005
2006 #if defined(CONFIG_64BIT) && defined(CONFIG_KVM_MIPS_VZ)
2007 case ldl_op:
2008 run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa(
2009 vcpu->arch.host_cp0_badvaddr) & (~0x7);
2010
2011 run->mmio.len = 8;
2012 imme = vcpu->arch.host_cp0_badvaddr & 0x7;
2013 switch (imme) {
2014 case 0:
2015 vcpu->mmio_needed = 11; /* 1 byte */
2016 break;
2017 case 1:
2018 vcpu->mmio_needed = 12; /* 2 bytes */
2019 break;
2020 case 2:
2021 vcpu->mmio_needed = 13; /* 3 bytes */
2022 break;
2023 case 3:
2024 vcpu->mmio_needed = 14; /* 4 bytes */
2025 break;
2026 case 4:
2027 vcpu->mmio_needed = 15; /* 5 bytes */
2028 break;
2029 case 5:
2030 vcpu->mmio_needed = 16; /* 6 bytes */
2031 break;
2032 case 6:
2033 vcpu->mmio_needed = 17; /* 7 bytes */
2034 break;
2035 case 7:
2036 vcpu->mmio_needed = 18; /* 8 bytes */
2037 break;
2038 default:
2039 break;
2040 }
2041 break;
2042
2043 case ldr_op:
2044 run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa(
2045 vcpu->arch.host_cp0_badvaddr) & (~0x7);
2046
2047 run->mmio.len = 8;
2048 imme = vcpu->arch.host_cp0_badvaddr & 0x7;
2049 switch (imme) {
2050 case 0:
2051 vcpu->mmio_needed = 19; /* 8 bytes */
2052 break;
2053 case 1:
2054 vcpu->mmio_needed = 20; /* 7 bytes */
2055 break;
2056 case 2:
2057 vcpu->mmio_needed = 21; /* 6 bytes */
2058 break;
2059 case 3:
2060 vcpu->mmio_needed = 22; /* 5 bytes */
2061 break;
2062 case 4:
2063 vcpu->mmio_needed = 23; /* 4 bytes */
2064 break;
2065 case 5:
2066 vcpu->mmio_needed = 24; /* 3 bytes */
2067 break;
2068 case 6:
2069 vcpu->mmio_needed = 25; /* 2 bytes */
2070 break;
2071 case 7:
2072 vcpu->mmio_needed = 26; /* 1 byte */
2073 break;
2074 default:
2075 break;
2076 }
2077 break;
2078 #endif
2079
2080 #ifdef CONFIG_CPU_LOONGSON64
2081 case ldc2_op:
2082 rt = inst.loongson3_lsdc2_format.rt;
2083 switch (inst.loongson3_lsdc2_format.opcode1) {
2084 /*
2085 * Loongson-3 overridden ldc2 instructions.
2086 * opcode1 instruction
2087 * 0x0 gslbx: store 1 bytes from GPR
2088 * 0x1 gslhx: store 2 bytes from GPR
2089 * 0x2 gslwx: store 4 bytes from GPR
2090 * 0x3 gsldx: store 8 bytes from GPR
2091 */
2092 case 0x0:
2093 run->mmio.len = 1;
2094 vcpu->mmio_needed = 27; /* signed */
2095 break;
2096 case 0x1:
2097 run->mmio.len = 2;
2098 vcpu->mmio_needed = 28; /* signed */
2099 break;
2100 case 0x2:
2101 run->mmio.len = 4;
2102 vcpu->mmio_needed = 29; /* signed */
2103 break;
2104 case 0x3:
2105 run->mmio.len = 8;
2106 vcpu->mmio_needed = 30; /* signed */
2107 break;
2108 default:
2109 kvm_err("Godson Extended GS-Load for float not yet supported (inst=0x%08x)\n",
2110 inst.word);
2111 break;
2112 }
2113 break;
2114 #endif
2115
2116 default:
2117 kvm_err("Load not yet supported (inst=0x%08x)\n",
2118 inst.word);
2119 vcpu->mmio_needed = 0;
2120 return EMULATE_FAIL;
2121 }
2122
2123 run->mmio.is_write = 0;
2124 vcpu->mmio_is_write = 0;
2125
2126 r = kvm_io_bus_read(vcpu, KVM_MMIO_BUS,
2127 run->mmio.phys_addr, run->mmio.len, run->mmio.data);
2128
2129 if (!r) {
2130 kvm_mips_complete_mmio_load(vcpu);
2131 vcpu->mmio_needed = 0;
2132 return EMULATE_DONE;
2133 }
2134
2135 return EMULATE_DO_MMIO;
2136 }
2137
2138 #ifndef CONFIG_KVM_MIPS_VZ
kvm_mips_guest_cache_op(int (* fn)(unsigned long),unsigned long curr_pc,unsigned long addr,struct kvm_vcpu * vcpu,u32 cause)2139 static enum emulation_result kvm_mips_guest_cache_op(int (*fn)(unsigned long),
2140 unsigned long curr_pc,
2141 unsigned long addr,
2142 struct kvm_vcpu *vcpu,
2143 u32 cause)
2144 {
2145 int err;
2146
2147 for (;;) {
2148 /* Carefully attempt the cache operation */
2149 kvm_trap_emul_gva_lockless_begin(vcpu);
2150 err = fn(addr);
2151 kvm_trap_emul_gva_lockless_end(vcpu);
2152
2153 if (likely(!err))
2154 return EMULATE_DONE;
2155
2156 /*
2157 * Try to handle the fault and retry, maybe we just raced with a
2158 * GVA invalidation.
2159 */
2160 switch (kvm_trap_emul_gva_fault(vcpu, addr, false)) {
2161 case KVM_MIPS_GVA:
2162 case KVM_MIPS_GPA:
2163 /* bad virtual or physical address */
2164 return EMULATE_FAIL;
2165 case KVM_MIPS_TLB:
2166 /* no matching guest TLB */
2167 vcpu->arch.host_cp0_badvaddr = addr;
2168 vcpu->arch.pc = curr_pc;
2169 kvm_mips_emulate_tlbmiss_ld(cause, NULL, vcpu);
2170 return EMULATE_EXCEPT;
2171 case KVM_MIPS_TLBINV:
2172 /* invalid matching guest TLB */
2173 vcpu->arch.host_cp0_badvaddr = addr;
2174 vcpu->arch.pc = curr_pc;
2175 kvm_mips_emulate_tlbinv_ld(cause, NULL, vcpu);
2176 return EMULATE_EXCEPT;
2177 default:
2178 break;
2179 }
2180 }
2181 }
2182
kvm_mips_emulate_cache(union mips_instruction inst,u32 * opc,u32 cause,struct kvm_vcpu * vcpu)2183 enum emulation_result kvm_mips_emulate_cache(union mips_instruction inst,
2184 u32 *opc, u32 cause,
2185 struct kvm_vcpu *vcpu)
2186 {
2187 enum emulation_result er = EMULATE_DONE;
2188 u32 cache, op_inst, op, base;
2189 s16 offset;
2190 struct kvm_vcpu_arch *arch = &vcpu->arch;
2191 unsigned long va;
2192 unsigned long curr_pc;
2193
2194 /*
2195 * Update PC and hold onto current PC in case there is
2196 * an error and we want to rollback the PC
2197 */
2198 curr_pc = vcpu->arch.pc;
2199 er = update_pc(vcpu, cause);
2200 if (er == EMULATE_FAIL)
2201 return er;
2202
2203 base = inst.i_format.rs;
2204 op_inst = inst.i_format.rt;
2205 if (cpu_has_mips_r6)
2206 offset = inst.spec3_format.simmediate;
2207 else
2208 offset = inst.i_format.simmediate;
2209 cache = op_inst & CacheOp_Cache;
2210 op = op_inst & CacheOp_Op;
2211
2212 va = arch->gprs[base] + offset;
2213
2214 kvm_debug("CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
2215 cache, op, base, arch->gprs[base], offset);
2216
2217 /*
2218 * Treat INDEX_INV as a nop, basically issued by Linux on startup to
2219 * invalidate the caches entirely by stepping through all the
2220 * ways/indexes
2221 */
2222 if (op == Index_Writeback_Inv) {
2223 kvm_debug("@ %#lx/%#lx CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
2224 vcpu->arch.pc, vcpu->arch.gprs[31], cache, op, base,
2225 arch->gprs[base], offset);
2226
2227 if (cache == Cache_D) {
2228 #ifdef CONFIG_CPU_R4K_CACHE_TLB
2229 r4k_blast_dcache();
2230 #else
2231 switch (boot_cpu_type()) {
2232 case CPU_CAVIUM_OCTEON3:
2233 /* locally flush icache */
2234 local_flush_icache_range(0, 0);
2235 break;
2236 default:
2237 __flush_cache_all();
2238 break;
2239 }
2240 #endif
2241 } else if (cache == Cache_I) {
2242 #ifdef CONFIG_CPU_R4K_CACHE_TLB
2243 r4k_blast_icache();
2244 #else
2245 switch (boot_cpu_type()) {
2246 case CPU_CAVIUM_OCTEON3:
2247 /* locally flush icache */
2248 local_flush_icache_range(0, 0);
2249 break;
2250 default:
2251 flush_icache_all();
2252 break;
2253 }
2254 #endif
2255 } else {
2256 kvm_err("%s: unsupported CACHE INDEX operation\n",
2257 __func__);
2258 return EMULATE_FAIL;
2259 }
2260
2261 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
2262 kvm_mips_trans_cache_index(inst, opc, vcpu);
2263 #endif
2264 goto done;
2265 }
2266
2267 /* XXXKYMA: Only a subset of cache ops are supported, used by Linux */
2268 if (op_inst == Hit_Writeback_Inv_D || op_inst == Hit_Invalidate_D) {
2269 /*
2270 * Perform the dcache part of icache synchronisation on the
2271 * guest's behalf.
2272 */
2273 er = kvm_mips_guest_cache_op(protected_writeback_dcache_line,
2274 curr_pc, va, vcpu, cause);
2275 if (er != EMULATE_DONE)
2276 goto done;
2277 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
2278 /*
2279 * Replace the CACHE instruction, with a SYNCI, not the same,
2280 * but avoids a trap
2281 */
2282 kvm_mips_trans_cache_va(inst, opc, vcpu);
2283 #endif
2284 } else if (op_inst == Hit_Invalidate_I) {
2285 /* Perform the icache synchronisation on the guest's behalf */
2286 er = kvm_mips_guest_cache_op(protected_writeback_dcache_line,
2287 curr_pc, va, vcpu, cause);
2288 if (er != EMULATE_DONE)
2289 goto done;
2290 er = kvm_mips_guest_cache_op(protected_flush_icache_line,
2291 curr_pc, va, vcpu, cause);
2292 if (er != EMULATE_DONE)
2293 goto done;
2294
2295 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
2296 /* Replace the CACHE instruction, with a SYNCI */
2297 kvm_mips_trans_cache_va(inst, opc, vcpu);
2298 #endif
2299 } else {
2300 kvm_err("NO-OP CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
2301 cache, op, base, arch->gprs[base], offset);
2302 er = EMULATE_FAIL;
2303 }
2304
2305 done:
2306 /* Rollback PC only if emulation was unsuccessful */
2307 if (er == EMULATE_FAIL)
2308 vcpu->arch.pc = curr_pc;
2309 /* Guest exception needs guest to resume */
2310 if (er == EMULATE_EXCEPT)
2311 er = EMULATE_DONE;
2312
2313 return er;
2314 }
2315
kvm_mips_emulate_inst(u32 cause,u32 * opc,struct kvm_vcpu * vcpu)2316 enum emulation_result kvm_mips_emulate_inst(u32 cause, u32 *opc,
2317 struct kvm_vcpu *vcpu)
2318 {
2319 union mips_instruction inst;
2320 enum emulation_result er = EMULATE_DONE;
2321 int err;
2322
2323 /* Fetch the instruction. */
2324 if (cause & CAUSEF_BD)
2325 opc += 1;
2326 err = kvm_get_badinstr(opc, vcpu, &inst.word);
2327 if (err)
2328 return EMULATE_FAIL;
2329
2330 switch (inst.r_format.opcode) {
2331 case cop0_op:
2332 er = kvm_mips_emulate_CP0(inst, opc, cause, vcpu);
2333 break;
2334
2335 #ifndef CONFIG_CPU_MIPSR6
2336 case cache_op:
2337 ++vcpu->stat.cache_exits;
2338 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_CACHE);
2339 er = kvm_mips_emulate_cache(inst, opc, cause, vcpu);
2340 break;
2341 #else
2342 case spec3_op:
2343 switch (inst.spec3_format.func) {
2344 case cache6_op:
2345 ++vcpu->stat.cache_exits;
2346 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_CACHE);
2347 er = kvm_mips_emulate_cache(inst, opc, cause,
2348 vcpu);
2349 break;
2350 default:
2351 goto unknown;
2352 }
2353 break;
2354 unknown:
2355 #endif
2356
2357 default:
2358 kvm_err("Instruction emulation not supported (%p/%#x)\n", opc,
2359 inst.word);
2360 kvm_arch_vcpu_dump_regs(vcpu);
2361 er = EMULATE_FAIL;
2362 break;
2363 }
2364
2365 return er;
2366 }
2367 #endif /* CONFIG_KVM_MIPS_VZ */
2368
2369 /**
2370 * kvm_mips_guest_exception_base() - Find guest exception vector base address.
2371 *
2372 * Returns: The base address of the current guest exception vector, taking
2373 * both Guest.CP0_Status.BEV and Guest.CP0_EBase into account.
2374 */
kvm_mips_guest_exception_base(struct kvm_vcpu * vcpu)2375 long kvm_mips_guest_exception_base(struct kvm_vcpu *vcpu)
2376 {
2377 struct mips_coproc *cop0 = vcpu->arch.cop0;
2378
2379 if (kvm_read_c0_guest_status(cop0) & ST0_BEV)
2380 return KVM_GUEST_CKSEG1ADDR(0x1fc00200);
2381 else
2382 return kvm_read_c0_guest_ebase(cop0) & MIPS_EBASE_BASE;
2383 }
2384
kvm_mips_emulate_syscall(u32 cause,u32 * opc,struct kvm_vcpu * vcpu)2385 enum emulation_result kvm_mips_emulate_syscall(u32 cause,
2386 u32 *opc,
2387 struct kvm_vcpu *vcpu)
2388 {
2389 struct mips_coproc *cop0 = vcpu->arch.cop0;
2390 struct kvm_vcpu_arch *arch = &vcpu->arch;
2391 enum emulation_result er = EMULATE_DONE;
2392
2393 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2394 /* save old pc */
2395 kvm_write_c0_guest_epc(cop0, arch->pc);
2396 kvm_set_c0_guest_status(cop0, ST0_EXL);
2397
2398 if (cause & CAUSEF_BD)
2399 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2400 else
2401 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2402
2403 kvm_debug("Delivering SYSCALL @ pc %#lx\n", arch->pc);
2404
2405 kvm_change_c0_guest_cause(cop0, (0xff),
2406 (EXCCODE_SYS << CAUSEB_EXCCODE));
2407
2408 /* Set PC to the exception entry point */
2409 arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
2410
2411 } else {
2412 kvm_err("Trying to deliver SYSCALL when EXL is already set\n");
2413 er = EMULATE_FAIL;
2414 }
2415
2416 return er;
2417 }
2418
kvm_mips_emulate_tlbmiss_ld(u32 cause,u32 * opc,struct kvm_vcpu * vcpu)2419 enum emulation_result kvm_mips_emulate_tlbmiss_ld(u32 cause,
2420 u32 *opc,
2421 struct kvm_vcpu *vcpu)
2422 {
2423 struct mips_coproc *cop0 = vcpu->arch.cop0;
2424 struct kvm_vcpu_arch *arch = &vcpu->arch;
2425 unsigned long entryhi = (vcpu->arch. host_cp0_badvaddr & VPN2_MASK) |
2426 (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
2427
2428 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2429 /* save old pc */
2430 kvm_write_c0_guest_epc(cop0, arch->pc);
2431 kvm_set_c0_guest_status(cop0, ST0_EXL);
2432
2433 if (cause & CAUSEF_BD)
2434 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2435 else
2436 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2437
2438 kvm_debug("[EXL == 0] delivering TLB MISS @ pc %#lx\n",
2439 arch->pc);
2440
2441 /* set pc to the exception entry point */
2442 arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x0;
2443
2444 } else {
2445 kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n",
2446 arch->pc);
2447
2448 arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
2449 }
2450
2451 kvm_change_c0_guest_cause(cop0, (0xff),
2452 (EXCCODE_TLBL << CAUSEB_EXCCODE));
2453
2454 /* setup badvaddr, context and entryhi registers for the guest */
2455 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
2456 /* XXXKYMA: is the context register used by linux??? */
2457 kvm_write_c0_guest_entryhi(cop0, entryhi);
2458
2459 return EMULATE_DONE;
2460 }
2461
kvm_mips_emulate_tlbinv_ld(u32 cause,u32 * opc,struct kvm_vcpu * vcpu)2462 enum emulation_result kvm_mips_emulate_tlbinv_ld(u32 cause,
2463 u32 *opc,
2464 struct kvm_vcpu *vcpu)
2465 {
2466 struct mips_coproc *cop0 = vcpu->arch.cop0;
2467 struct kvm_vcpu_arch *arch = &vcpu->arch;
2468 unsigned long entryhi =
2469 (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
2470 (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
2471
2472 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2473 /* save old pc */
2474 kvm_write_c0_guest_epc(cop0, arch->pc);
2475 kvm_set_c0_guest_status(cop0, ST0_EXL);
2476
2477 if (cause & CAUSEF_BD)
2478 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2479 else
2480 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2481
2482 kvm_debug("[EXL == 0] delivering TLB INV @ pc %#lx\n",
2483 arch->pc);
2484 } else {
2485 kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n",
2486 arch->pc);
2487 }
2488
2489 /* set pc to the exception entry point */
2490 arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
2491
2492 kvm_change_c0_guest_cause(cop0, (0xff),
2493 (EXCCODE_TLBL << CAUSEB_EXCCODE));
2494
2495 /* setup badvaddr, context and entryhi registers for the guest */
2496 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
2497 /* XXXKYMA: is the context register used by linux??? */
2498 kvm_write_c0_guest_entryhi(cop0, entryhi);
2499
2500 return EMULATE_DONE;
2501 }
2502
kvm_mips_emulate_tlbmiss_st(u32 cause,u32 * opc,struct kvm_vcpu * vcpu)2503 enum emulation_result kvm_mips_emulate_tlbmiss_st(u32 cause,
2504 u32 *opc,
2505 struct kvm_vcpu *vcpu)
2506 {
2507 struct mips_coproc *cop0 = vcpu->arch.cop0;
2508 struct kvm_vcpu_arch *arch = &vcpu->arch;
2509 unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
2510 (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
2511
2512 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2513 /* save old pc */
2514 kvm_write_c0_guest_epc(cop0, arch->pc);
2515 kvm_set_c0_guest_status(cop0, ST0_EXL);
2516
2517 if (cause & CAUSEF_BD)
2518 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2519 else
2520 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2521
2522 kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n",
2523 arch->pc);
2524
2525 /* Set PC to the exception entry point */
2526 arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x0;
2527 } else {
2528 kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n",
2529 arch->pc);
2530 arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
2531 }
2532
2533 kvm_change_c0_guest_cause(cop0, (0xff),
2534 (EXCCODE_TLBS << CAUSEB_EXCCODE));
2535
2536 /* setup badvaddr, context and entryhi registers for the guest */
2537 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
2538 /* XXXKYMA: is the context register used by linux??? */
2539 kvm_write_c0_guest_entryhi(cop0, entryhi);
2540
2541 return EMULATE_DONE;
2542 }
2543
kvm_mips_emulate_tlbinv_st(u32 cause,u32 * opc,struct kvm_vcpu * vcpu)2544 enum emulation_result kvm_mips_emulate_tlbinv_st(u32 cause,
2545 u32 *opc,
2546 struct kvm_vcpu *vcpu)
2547 {
2548 struct mips_coproc *cop0 = vcpu->arch.cop0;
2549 struct kvm_vcpu_arch *arch = &vcpu->arch;
2550 unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
2551 (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
2552
2553 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2554 /* save old pc */
2555 kvm_write_c0_guest_epc(cop0, arch->pc);
2556 kvm_set_c0_guest_status(cop0, ST0_EXL);
2557
2558 if (cause & CAUSEF_BD)
2559 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2560 else
2561 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2562
2563 kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n",
2564 arch->pc);
2565 } else {
2566 kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n",
2567 arch->pc);
2568 }
2569
2570 /* Set PC to the exception entry point */
2571 arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
2572
2573 kvm_change_c0_guest_cause(cop0, (0xff),
2574 (EXCCODE_TLBS << CAUSEB_EXCCODE));
2575
2576 /* setup badvaddr, context and entryhi registers for the guest */
2577 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
2578 /* XXXKYMA: is the context register used by linux??? */
2579 kvm_write_c0_guest_entryhi(cop0, entryhi);
2580
2581 return EMULATE_DONE;
2582 }
2583
kvm_mips_emulate_tlbmod(u32 cause,u32 * opc,struct kvm_vcpu * vcpu)2584 enum emulation_result kvm_mips_emulate_tlbmod(u32 cause,
2585 u32 *opc,
2586 struct kvm_vcpu *vcpu)
2587 {
2588 struct mips_coproc *cop0 = vcpu->arch.cop0;
2589 unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
2590 (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
2591 struct kvm_vcpu_arch *arch = &vcpu->arch;
2592
2593 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2594 /* save old pc */
2595 kvm_write_c0_guest_epc(cop0, arch->pc);
2596 kvm_set_c0_guest_status(cop0, ST0_EXL);
2597
2598 if (cause & CAUSEF_BD)
2599 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2600 else
2601 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2602
2603 kvm_debug("[EXL == 0] Delivering TLB MOD @ pc %#lx\n",
2604 arch->pc);
2605 } else {
2606 kvm_debug("[EXL == 1] Delivering TLB MOD @ pc %#lx\n",
2607 arch->pc);
2608 }
2609
2610 arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
2611
2612 kvm_change_c0_guest_cause(cop0, (0xff),
2613 (EXCCODE_MOD << CAUSEB_EXCCODE));
2614
2615 /* setup badvaddr, context and entryhi registers for the guest */
2616 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
2617 /* XXXKYMA: is the context register used by linux??? */
2618 kvm_write_c0_guest_entryhi(cop0, entryhi);
2619
2620 return EMULATE_DONE;
2621 }
2622
kvm_mips_emulate_fpu_exc(u32 cause,u32 * opc,struct kvm_vcpu * vcpu)2623 enum emulation_result kvm_mips_emulate_fpu_exc(u32 cause,
2624 u32 *opc,
2625 struct kvm_vcpu *vcpu)
2626 {
2627 struct mips_coproc *cop0 = vcpu->arch.cop0;
2628 struct kvm_vcpu_arch *arch = &vcpu->arch;
2629
2630 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2631 /* save old pc */
2632 kvm_write_c0_guest_epc(cop0, arch->pc);
2633 kvm_set_c0_guest_status(cop0, ST0_EXL);
2634
2635 if (cause & CAUSEF_BD)
2636 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2637 else
2638 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2639
2640 }
2641
2642 arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
2643
2644 kvm_change_c0_guest_cause(cop0, (0xff),
2645 (EXCCODE_CPU << CAUSEB_EXCCODE));
2646 kvm_change_c0_guest_cause(cop0, (CAUSEF_CE), (0x1 << CAUSEB_CE));
2647
2648 return EMULATE_DONE;
2649 }
2650
kvm_mips_emulate_ri_exc(u32 cause,u32 * opc,struct kvm_vcpu * vcpu)2651 enum emulation_result kvm_mips_emulate_ri_exc(u32 cause,
2652 u32 *opc,
2653 struct kvm_vcpu *vcpu)
2654 {
2655 struct mips_coproc *cop0 = vcpu->arch.cop0;
2656 struct kvm_vcpu_arch *arch = &vcpu->arch;
2657 enum emulation_result er = EMULATE_DONE;
2658
2659 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2660 /* save old pc */
2661 kvm_write_c0_guest_epc(cop0, arch->pc);
2662 kvm_set_c0_guest_status(cop0, ST0_EXL);
2663
2664 if (cause & CAUSEF_BD)
2665 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2666 else
2667 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2668
2669 kvm_debug("Delivering RI @ pc %#lx\n", arch->pc);
2670
2671 kvm_change_c0_guest_cause(cop0, (0xff),
2672 (EXCCODE_RI << CAUSEB_EXCCODE));
2673
2674 /* Set PC to the exception entry point */
2675 arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
2676
2677 } else {
2678 kvm_err("Trying to deliver RI when EXL is already set\n");
2679 er = EMULATE_FAIL;
2680 }
2681
2682 return er;
2683 }
2684
kvm_mips_emulate_bp_exc(u32 cause,u32 * opc,struct kvm_vcpu * vcpu)2685 enum emulation_result kvm_mips_emulate_bp_exc(u32 cause,
2686 u32 *opc,
2687 struct kvm_vcpu *vcpu)
2688 {
2689 struct mips_coproc *cop0 = vcpu->arch.cop0;
2690 struct kvm_vcpu_arch *arch = &vcpu->arch;
2691 enum emulation_result er = EMULATE_DONE;
2692
2693 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2694 /* save old pc */
2695 kvm_write_c0_guest_epc(cop0, arch->pc);
2696 kvm_set_c0_guest_status(cop0, ST0_EXL);
2697
2698 if (cause & CAUSEF_BD)
2699 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2700 else
2701 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2702
2703 kvm_debug("Delivering BP @ pc %#lx\n", arch->pc);
2704
2705 kvm_change_c0_guest_cause(cop0, (0xff),
2706 (EXCCODE_BP << CAUSEB_EXCCODE));
2707
2708 /* Set PC to the exception entry point */
2709 arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
2710
2711 } else {
2712 kvm_err("Trying to deliver BP when EXL is already set\n");
2713 er = EMULATE_FAIL;
2714 }
2715
2716 return er;
2717 }
2718
kvm_mips_emulate_trap_exc(u32 cause,u32 * opc,struct kvm_vcpu * vcpu)2719 enum emulation_result kvm_mips_emulate_trap_exc(u32 cause,
2720 u32 *opc,
2721 struct kvm_vcpu *vcpu)
2722 {
2723 struct mips_coproc *cop0 = vcpu->arch.cop0;
2724 struct kvm_vcpu_arch *arch = &vcpu->arch;
2725 enum emulation_result er = EMULATE_DONE;
2726
2727 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2728 /* save old pc */
2729 kvm_write_c0_guest_epc(cop0, arch->pc);
2730 kvm_set_c0_guest_status(cop0, ST0_EXL);
2731
2732 if (cause & CAUSEF_BD)
2733 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2734 else
2735 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2736
2737 kvm_debug("Delivering TRAP @ pc %#lx\n", arch->pc);
2738
2739 kvm_change_c0_guest_cause(cop0, (0xff),
2740 (EXCCODE_TR << CAUSEB_EXCCODE));
2741
2742 /* Set PC to the exception entry point */
2743 arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
2744
2745 } else {
2746 kvm_err("Trying to deliver TRAP when EXL is already set\n");
2747 er = EMULATE_FAIL;
2748 }
2749
2750 return er;
2751 }
2752
kvm_mips_emulate_msafpe_exc(u32 cause,u32 * opc,struct kvm_vcpu * vcpu)2753 enum emulation_result kvm_mips_emulate_msafpe_exc(u32 cause,
2754 u32 *opc,
2755 struct kvm_vcpu *vcpu)
2756 {
2757 struct mips_coproc *cop0 = vcpu->arch.cop0;
2758 struct kvm_vcpu_arch *arch = &vcpu->arch;
2759 enum emulation_result er = EMULATE_DONE;
2760
2761 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2762 /* save old pc */
2763 kvm_write_c0_guest_epc(cop0, arch->pc);
2764 kvm_set_c0_guest_status(cop0, ST0_EXL);
2765
2766 if (cause & CAUSEF_BD)
2767 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2768 else
2769 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2770
2771 kvm_debug("Delivering MSAFPE @ pc %#lx\n", arch->pc);
2772
2773 kvm_change_c0_guest_cause(cop0, (0xff),
2774 (EXCCODE_MSAFPE << CAUSEB_EXCCODE));
2775
2776 /* Set PC to the exception entry point */
2777 arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
2778
2779 } else {
2780 kvm_err("Trying to deliver MSAFPE when EXL is already set\n");
2781 er = EMULATE_FAIL;
2782 }
2783
2784 return er;
2785 }
2786
kvm_mips_emulate_fpe_exc(u32 cause,u32 * opc,struct kvm_vcpu * vcpu)2787 enum emulation_result kvm_mips_emulate_fpe_exc(u32 cause,
2788 u32 *opc,
2789 struct kvm_vcpu *vcpu)
2790 {
2791 struct mips_coproc *cop0 = vcpu->arch.cop0;
2792 struct kvm_vcpu_arch *arch = &vcpu->arch;
2793 enum emulation_result er = EMULATE_DONE;
2794
2795 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2796 /* save old pc */
2797 kvm_write_c0_guest_epc(cop0, arch->pc);
2798 kvm_set_c0_guest_status(cop0, ST0_EXL);
2799
2800 if (cause & CAUSEF_BD)
2801 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2802 else
2803 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2804
2805 kvm_debug("Delivering FPE @ pc %#lx\n", arch->pc);
2806
2807 kvm_change_c0_guest_cause(cop0, (0xff),
2808 (EXCCODE_FPE << CAUSEB_EXCCODE));
2809
2810 /* Set PC to the exception entry point */
2811 arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
2812
2813 } else {
2814 kvm_err("Trying to deliver FPE when EXL is already set\n");
2815 er = EMULATE_FAIL;
2816 }
2817
2818 return er;
2819 }
2820
kvm_mips_emulate_msadis_exc(u32 cause,u32 * opc,struct kvm_vcpu * vcpu)2821 enum emulation_result kvm_mips_emulate_msadis_exc(u32 cause,
2822 u32 *opc,
2823 struct kvm_vcpu *vcpu)
2824 {
2825 struct mips_coproc *cop0 = vcpu->arch.cop0;
2826 struct kvm_vcpu_arch *arch = &vcpu->arch;
2827 enum emulation_result er = EMULATE_DONE;
2828
2829 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2830 /* save old pc */
2831 kvm_write_c0_guest_epc(cop0, arch->pc);
2832 kvm_set_c0_guest_status(cop0, ST0_EXL);
2833
2834 if (cause & CAUSEF_BD)
2835 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2836 else
2837 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2838
2839 kvm_debug("Delivering MSADIS @ pc %#lx\n", arch->pc);
2840
2841 kvm_change_c0_guest_cause(cop0, (0xff),
2842 (EXCCODE_MSADIS << CAUSEB_EXCCODE));
2843
2844 /* Set PC to the exception entry point */
2845 arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
2846
2847 } else {
2848 kvm_err("Trying to deliver MSADIS when EXL is already set\n");
2849 er = EMULATE_FAIL;
2850 }
2851
2852 return er;
2853 }
2854
kvm_mips_handle_ri(u32 cause,u32 * opc,struct kvm_vcpu * vcpu)2855 enum emulation_result kvm_mips_handle_ri(u32 cause, u32 *opc,
2856 struct kvm_vcpu *vcpu)
2857 {
2858 struct mips_coproc *cop0 = vcpu->arch.cop0;
2859 struct kvm_vcpu_arch *arch = &vcpu->arch;
2860 enum emulation_result er = EMULATE_DONE;
2861 unsigned long curr_pc;
2862 union mips_instruction inst;
2863 int err;
2864
2865 /*
2866 * Update PC and hold onto current PC in case there is
2867 * an error and we want to rollback the PC
2868 */
2869 curr_pc = vcpu->arch.pc;
2870 er = update_pc(vcpu, cause);
2871 if (er == EMULATE_FAIL)
2872 return er;
2873
2874 /* Fetch the instruction. */
2875 if (cause & CAUSEF_BD)
2876 opc += 1;
2877 err = kvm_get_badinstr(opc, vcpu, &inst.word);
2878 if (err) {
2879 kvm_err("%s: Cannot get inst @ %p (%d)\n", __func__, opc, err);
2880 return EMULATE_FAIL;
2881 }
2882
2883 if (inst.r_format.opcode == spec3_op &&
2884 inst.r_format.func == rdhwr_op &&
2885 inst.r_format.rs == 0 &&
2886 (inst.r_format.re >> 3) == 0) {
2887 int usermode = !KVM_GUEST_KERNEL_MODE(vcpu);
2888 int rd = inst.r_format.rd;
2889 int rt = inst.r_format.rt;
2890 int sel = inst.r_format.re & 0x7;
2891
2892 /* If usermode, check RDHWR rd is allowed by guest HWREna */
2893 if (usermode && !(kvm_read_c0_guest_hwrena(cop0) & BIT(rd))) {
2894 kvm_debug("RDHWR %#x disallowed by HWREna @ %p\n",
2895 rd, opc);
2896 goto emulate_ri;
2897 }
2898 switch (rd) {
2899 case MIPS_HWR_CPUNUM: /* CPU number */
2900 arch->gprs[rt] = vcpu->vcpu_id;
2901 break;
2902 case MIPS_HWR_SYNCISTEP: /* SYNCI length */
2903 arch->gprs[rt] = min(current_cpu_data.dcache.linesz,
2904 current_cpu_data.icache.linesz);
2905 break;
2906 case MIPS_HWR_CC: /* Read count register */
2907 arch->gprs[rt] = (s32)kvm_mips_read_count(vcpu);
2908 break;
2909 case MIPS_HWR_CCRES: /* Count register resolution */
2910 switch (current_cpu_data.cputype) {
2911 case CPU_20KC:
2912 case CPU_25KF:
2913 arch->gprs[rt] = 1;
2914 break;
2915 default:
2916 arch->gprs[rt] = 2;
2917 }
2918 break;
2919 case MIPS_HWR_ULR: /* Read UserLocal register */
2920 arch->gprs[rt] = kvm_read_c0_guest_userlocal(cop0);
2921 break;
2922
2923 default:
2924 kvm_debug("RDHWR %#x not supported @ %p\n", rd, opc);
2925 goto emulate_ri;
2926 }
2927
2928 trace_kvm_hwr(vcpu, KVM_TRACE_RDHWR, KVM_TRACE_HWR(rd, sel),
2929 vcpu->arch.gprs[rt]);
2930 } else {
2931 kvm_debug("Emulate RI not supported @ %p: %#x\n",
2932 opc, inst.word);
2933 goto emulate_ri;
2934 }
2935
2936 return EMULATE_DONE;
2937
2938 emulate_ri:
2939 /*
2940 * Rollback PC (if in branch delay slot then the PC already points to
2941 * branch target), and pass the RI exception to the guest OS.
2942 */
2943 vcpu->arch.pc = curr_pc;
2944 return kvm_mips_emulate_ri_exc(cause, opc, vcpu);
2945 }
2946
kvm_mips_complete_mmio_load(struct kvm_vcpu * vcpu)2947 enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu)
2948 {
2949 struct kvm_run *run = vcpu->run;
2950 unsigned long *gpr = &vcpu->arch.gprs[vcpu->arch.io_gpr];
2951 enum emulation_result er = EMULATE_DONE;
2952
2953 if (run->mmio.len > sizeof(*gpr)) {
2954 kvm_err("Bad MMIO length: %d", run->mmio.len);
2955 er = EMULATE_FAIL;
2956 goto done;
2957 }
2958
2959 /* Restore saved resume PC */
2960 vcpu->arch.pc = vcpu->arch.io_pc;
2961
2962 switch (run->mmio.len) {
2963 case 8:
2964 switch (vcpu->mmio_needed) {
2965 case 11:
2966 *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffffffffffff) |
2967 (((*(s64 *)run->mmio.data) & 0xff) << 56);
2968 break;
2969 case 12:
2970 *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffffffffff) |
2971 (((*(s64 *)run->mmio.data) & 0xffff) << 48);
2972 break;
2973 case 13:
2974 *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffffffff) |
2975 (((*(s64 *)run->mmio.data) & 0xffffff) << 40);
2976 break;
2977 case 14:
2978 *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffffff) |
2979 (((*(s64 *)run->mmio.data) & 0xffffffff) << 32);
2980 break;
2981 case 15:
2982 *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffff) |
2983 (((*(s64 *)run->mmio.data) & 0xffffffffff) << 24);
2984 break;
2985 case 16:
2986 *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffff) |
2987 (((*(s64 *)run->mmio.data) & 0xffffffffffff) << 16);
2988 break;
2989 case 17:
2990 *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xff) |
2991 (((*(s64 *)run->mmio.data) & 0xffffffffffffff) << 8);
2992 break;
2993 case 18:
2994 case 19:
2995 *gpr = *(s64 *)run->mmio.data;
2996 break;
2997 case 20:
2998 *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xff00000000000000) |
2999 ((((*(s64 *)run->mmio.data)) >> 8) & 0xffffffffffffff);
3000 break;
3001 case 21:
3002 *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffff000000000000) |
3003 ((((*(s64 *)run->mmio.data)) >> 16) & 0xffffffffffff);
3004 break;
3005 case 22:
3006 *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffff0000000000) |
3007 ((((*(s64 *)run->mmio.data)) >> 24) & 0xffffffffff);
3008 break;
3009 case 23:
3010 *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffffff00000000) |
3011 ((((*(s64 *)run->mmio.data)) >> 32) & 0xffffffff);
3012 break;
3013 case 24:
3014 *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffffffff000000) |
3015 ((((*(s64 *)run->mmio.data)) >> 40) & 0xffffff);
3016 break;
3017 case 25:
3018 *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffffffffff0000) |
3019 ((((*(s64 *)run->mmio.data)) >> 48) & 0xffff);
3020 break;
3021 case 26:
3022 *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffffffffffff00) |
3023 ((((*(s64 *)run->mmio.data)) >> 56) & 0xff);
3024 break;
3025 default:
3026 *gpr = *(s64 *)run->mmio.data;
3027 }
3028 break;
3029
3030 case 4:
3031 switch (vcpu->mmio_needed) {
3032 case 1:
3033 *gpr = *(u32 *)run->mmio.data;
3034 break;
3035 case 2:
3036 *gpr = *(s32 *)run->mmio.data;
3037 break;
3038 case 3:
3039 *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffff) |
3040 (((*(s32 *)run->mmio.data) & 0xff) << 24);
3041 break;
3042 case 4:
3043 *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffff) |
3044 (((*(s32 *)run->mmio.data) & 0xffff) << 16);
3045 break;
3046 case 5:
3047 *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xff) |
3048 (((*(s32 *)run->mmio.data) & 0xffffff) << 8);
3049 break;
3050 case 6:
3051 case 7:
3052 *gpr = *(s32 *)run->mmio.data;
3053 break;
3054 case 8:
3055 *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xff000000) |
3056 ((((*(s32 *)run->mmio.data)) >> 8) & 0xffffff);
3057 break;
3058 case 9:
3059 *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffff0000) |
3060 ((((*(s32 *)run->mmio.data)) >> 16) & 0xffff);
3061 break;
3062 case 10:
3063 *gpr = (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffff00) |
3064 ((((*(s32 *)run->mmio.data)) >> 24) & 0xff);
3065 break;
3066 default:
3067 *gpr = *(s32 *)run->mmio.data;
3068 }
3069 break;
3070
3071 case 2:
3072 if (vcpu->mmio_needed == 1)
3073 *gpr = *(u16 *)run->mmio.data;
3074 else
3075 *gpr = *(s16 *)run->mmio.data;
3076
3077 break;
3078 case 1:
3079 if (vcpu->mmio_needed == 1)
3080 *gpr = *(u8 *)run->mmio.data;
3081 else
3082 *gpr = *(s8 *)run->mmio.data;
3083 break;
3084 }
3085
3086 done:
3087 return er;
3088 }
3089
kvm_mips_emulate_exc(u32 cause,u32 * opc,struct kvm_vcpu * vcpu)3090 static enum emulation_result kvm_mips_emulate_exc(u32 cause,
3091 u32 *opc,
3092 struct kvm_vcpu *vcpu)
3093 {
3094 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
3095 struct mips_coproc *cop0 = vcpu->arch.cop0;
3096 struct kvm_vcpu_arch *arch = &vcpu->arch;
3097 enum emulation_result er = EMULATE_DONE;
3098
3099 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
3100 /* save old pc */
3101 kvm_write_c0_guest_epc(cop0, arch->pc);
3102 kvm_set_c0_guest_status(cop0, ST0_EXL);
3103
3104 if (cause & CAUSEF_BD)
3105 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
3106 else
3107 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
3108
3109 kvm_change_c0_guest_cause(cop0, (0xff),
3110 (exccode << CAUSEB_EXCCODE));
3111
3112 /* Set PC to the exception entry point */
3113 arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
3114 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
3115
3116 kvm_debug("Delivering EXC %d @ pc %#lx, badVaddr: %#lx\n",
3117 exccode, kvm_read_c0_guest_epc(cop0),
3118 kvm_read_c0_guest_badvaddr(cop0));
3119 } else {
3120 kvm_err("Trying to deliver EXC when EXL is already set\n");
3121 er = EMULATE_FAIL;
3122 }
3123
3124 return er;
3125 }
3126
kvm_mips_check_privilege(u32 cause,u32 * opc,struct kvm_vcpu * vcpu)3127 enum emulation_result kvm_mips_check_privilege(u32 cause,
3128 u32 *opc,
3129 struct kvm_vcpu *vcpu)
3130 {
3131 enum emulation_result er = EMULATE_DONE;
3132 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
3133 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
3134
3135 int usermode = !KVM_GUEST_KERNEL_MODE(vcpu);
3136
3137 if (usermode) {
3138 switch (exccode) {
3139 case EXCCODE_INT:
3140 case EXCCODE_SYS:
3141 case EXCCODE_BP:
3142 case EXCCODE_RI:
3143 case EXCCODE_TR:
3144 case EXCCODE_MSAFPE:
3145 case EXCCODE_FPE:
3146 case EXCCODE_MSADIS:
3147 break;
3148
3149 case EXCCODE_CPU:
3150 if (((cause & CAUSEF_CE) >> CAUSEB_CE) == 0)
3151 er = EMULATE_PRIV_FAIL;
3152 break;
3153
3154 case EXCCODE_MOD:
3155 break;
3156
3157 case EXCCODE_TLBL:
3158 /*
3159 * We we are accessing Guest kernel space, then send an
3160 * address error exception to the guest
3161 */
3162 if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) {
3163 kvm_debug("%s: LD MISS @ %#lx\n", __func__,
3164 badvaddr);
3165 cause &= ~0xff;
3166 cause |= (EXCCODE_ADEL << CAUSEB_EXCCODE);
3167 er = EMULATE_PRIV_FAIL;
3168 }
3169 break;
3170
3171 case EXCCODE_TLBS:
3172 /*
3173 * We we are accessing Guest kernel space, then send an
3174 * address error exception to the guest
3175 */
3176 if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) {
3177 kvm_debug("%s: ST MISS @ %#lx\n", __func__,
3178 badvaddr);
3179 cause &= ~0xff;
3180 cause |= (EXCCODE_ADES << CAUSEB_EXCCODE);
3181 er = EMULATE_PRIV_FAIL;
3182 }
3183 break;
3184
3185 case EXCCODE_ADES:
3186 kvm_debug("%s: address error ST @ %#lx\n", __func__,
3187 badvaddr);
3188 if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) {
3189 cause &= ~0xff;
3190 cause |= (EXCCODE_TLBS << CAUSEB_EXCCODE);
3191 }
3192 er = EMULATE_PRIV_FAIL;
3193 break;
3194 case EXCCODE_ADEL:
3195 kvm_debug("%s: address error LD @ %#lx\n", __func__,
3196 badvaddr);
3197 if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) {
3198 cause &= ~0xff;
3199 cause |= (EXCCODE_TLBL << CAUSEB_EXCCODE);
3200 }
3201 er = EMULATE_PRIV_FAIL;
3202 break;
3203 default:
3204 er = EMULATE_PRIV_FAIL;
3205 break;
3206 }
3207 }
3208
3209 if (er == EMULATE_PRIV_FAIL)
3210 kvm_mips_emulate_exc(cause, opc, vcpu);
3211
3212 return er;
3213 }
3214
3215 /*
3216 * User Address (UA) fault, this could happen if
3217 * (1) TLB entry not present/valid in both Guest and shadow host TLBs, in this
3218 * case we pass on the fault to the guest kernel and let it handle it.
3219 * (2) TLB entry is present in the Guest TLB but not in the shadow, in this
3220 * case we inject the TLB from the Guest TLB into the shadow host TLB
3221 */
kvm_mips_handle_tlbmiss(u32 cause,u32 * opc,struct kvm_vcpu * vcpu,bool write_fault)3222 enum emulation_result kvm_mips_handle_tlbmiss(u32 cause,
3223 u32 *opc,
3224 struct kvm_vcpu *vcpu,
3225 bool write_fault)
3226 {
3227 enum emulation_result er = EMULATE_DONE;
3228 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
3229 unsigned long va = vcpu->arch.host_cp0_badvaddr;
3230 int index;
3231
3232 kvm_debug("kvm_mips_handle_tlbmiss: badvaddr: %#lx\n",
3233 vcpu->arch.host_cp0_badvaddr);
3234
3235 /*
3236 * KVM would not have got the exception if this entry was valid in the
3237 * shadow host TLB. Check the Guest TLB, if the entry is not there then
3238 * send the guest an exception. The guest exc handler should then inject
3239 * an entry into the guest TLB.
3240 */
3241 index = kvm_mips_guest_tlb_lookup(vcpu,
3242 (va & VPN2_MASK) |
3243 (kvm_read_c0_guest_entryhi(vcpu->arch.cop0) &
3244 KVM_ENTRYHI_ASID));
3245 if (index < 0) {
3246 if (exccode == EXCCODE_TLBL) {
3247 er = kvm_mips_emulate_tlbmiss_ld(cause, opc, vcpu);
3248 } else if (exccode == EXCCODE_TLBS) {
3249 er = kvm_mips_emulate_tlbmiss_st(cause, opc, vcpu);
3250 } else {
3251 kvm_err("%s: invalid exc code: %d\n", __func__,
3252 exccode);
3253 er = EMULATE_FAIL;
3254 }
3255 } else {
3256 struct kvm_mips_tlb *tlb = &vcpu->arch.guest_tlb[index];
3257
3258 /*
3259 * Check if the entry is valid, if not then setup a TLB invalid
3260 * exception to the guest
3261 */
3262 if (!TLB_IS_VALID(*tlb, va)) {
3263 if (exccode == EXCCODE_TLBL) {
3264 er = kvm_mips_emulate_tlbinv_ld(cause, opc,
3265 vcpu);
3266 } else if (exccode == EXCCODE_TLBS) {
3267 er = kvm_mips_emulate_tlbinv_st(cause, opc,
3268 vcpu);
3269 } else {
3270 kvm_err("%s: invalid exc code: %d\n", __func__,
3271 exccode);
3272 er = EMULATE_FAIL;
3273 }
3274 } else {
3275 kvm_debug("Injecting hi: %#lx, lo0: %#lx, lo1: %#lx into shadow host TLB\n",
3276 tlb->tlb_hi, tlb->tlb_lo[0], tlb->tlb_lo[1]);
3277 /*
3278 * OK we have a Guest TLB entry, now inject it into the
3279 * shadow host TLB
3280 */
3281 if (kvm_mips_handle_mapped_seg_tlb_fault(vcpu, tlb, va,
3282 write_fault)) {
3283 kvm_err("%s: handling mapped seg tlb fault for %lx, index: %u, vcpu: %p, ASID: %#lx\n",
3284 __func__, va, index, vcpu,
3285 read_c0_entryhi());
3286 er = EMULATE_FAIL;
3287 }
3288 }
3289 }
3290
3291 return er;
3292 }
3293
