1 /*
2 * Copyright 2016-2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "kfd_kernel_queue.h"
25 #include "kfd_device_queue_manager.h"
26 #include "kfd_pm4_headers_ai.h"
27 #include "kfd_pm4_opcodes.h"
28
29 static bool initialize_v9(struct kernel_queue *kq, struct kfd_dev *dev,
30 enum kfd_queue_type type, unsigned int queue_size);
31 static void uninitialize_v9(struct kernel_queue *kq);
32 static void submit_packet_v9(struct kernel_queue *kq);
33
kernel_queue_init_v9(struct kernel_queue_ops * ops)34 void kernel_queue_init_v9(struct kernel_queue_ops *ops)
35 {
36 ops->initialize = initialize_v9;
37 ops->uninitialize = uninitialize_v9;
38 ops->submit_packet = submit_packet_v9;
39 }
40
initialize_v9(struct kernel_queue * kq,struct kfd_dev * dev,enum kfd_queue_type type,unsigned int queue_size)41 static bool initialize_v9(struct kernel_queue *kq, struct kfd_dev *dev,
42 enum kfd_queue_type type, unsigned int queue_size)
43 {
44 int retval;
45
46 retval = kfd_gtt_sa_allocate(dev, PAGE_SIZE, &kq->eop_mem);
47 if (retval)
48 return false;
49
50 kq->eop_gpu_addr = kq->eop_mem->gpu_addr;
51 kq->eop_kernel_addr = kq->eop_mem->cpu_ptr;
52
53 memset(kq->eop_kernel_addr, 0, PAGE_SIZE);
54
55 return true;
56 }
57
uninitialize_v9(struct kernel_queue * kq)58 static void uninitialize_v9(struct kernel_queue *kq)
59 {
60 kfd_gtt_sa_free(kq->dev, kq->eop_mem);
61 }
62
submit_packet_v9(struct kernel_queue * kq)63 static void submit_packet_v9(struct kernel_queue *kq)
64 {
65 *kq->wptr64_kernel = kq->pending_wptr64;
66 write_kernel_doorbell64(kq->queue->properties.doorbell_ptr,
67 kq->pending_wptr64);
68 }
69
pm_map_process_v9(struct packet_manager * pm,uint32_t * buffer,struct qcm_process_device * qpd)70 static int pm_map_process_v9(struct packet_manager *pm,
71 uint32_t *buffer, struct qcm_process_device *qpd)
72 {
73 struct pm4_mes_map_process *packet;
74 uint64_t vm_page_table_base_addr =
75 (uint64_t)(qpd->page_table_base) << 12;
76
77 packet = (struct pm4_mes_map_process *)buffer;
78 memset(buffer, 0, sizeof(struct pm4_mes_map_process));
79
80 packet->header.u32All = pm_build_pm4_header(IT_MAP_PROCESS,
81 sizeof(struct pm4_mes_map_process));
82 packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0;
83 packet->bitfields2.process_quantum = 1;
84 packet->bitfields2.pasid = qpd->pqm->process->pasid;
85 packet->bitfields14.gds_size = qpd->gds_size;
86 packet->bitfields14.num_gws = qpd->num_gws;
87 packet->bitfields14.num_oac = qpd->num_oac;
88 packet->bitfields14.sdma_enable = 1;
89 packet->bitfields14.num_queues = (qpd->is_debug) ? 0 : qpd->queue_count;
90
91 packet->sh_mem_config = qpd->sh_mem_config;
92 packet->sh_mem_bases = qpd->sh_mem_bases;
93 packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8);
94 packet->sq_shader_tba_hi = upper_32_bits(qpd->tba_addr >> 8);
95 packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8);
96 packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8);
97
98 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area);
99 packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area);
100
101 packet->vm_context_page_table_base_addr_lo32 =
102 lower_32_bits(vm_page_table_base_addr);
103 packet->vm_context_page_table_base_addr_hi32 =
104 upper_32_bits(vm_page_table_base_addr);
105
106 return 0;
107 }
108
pm_runlist_v9(struct packet_manager * pm,uint32_t * buffer,uint64_t ib,size_t ib_size_in_dwords,bool chain)109 static int pm_runlist_v9(struct packet_manager *pm, uint32_t *buffer,
110 uint64_t ib, size_t ib_size_in_dwords, bool chain)
111 {
112 struct pm4_mes_runlist *packet;
113
114 int concurrent_proc_cnt = 0;
115 struct kfd_dev *kfd = pm->dqm->dev;
116
117 /* Determine the number of processes to map together to HW:
118 * it can not exceed the number of VMIDs available to the
119 * scheduler, and it is determined by the smaller of the number
120 * of processes in the runlist and kfd module parameter
121 * hws_max_conc_proc.
122 * Note: the arbitration between the number of VMIDs and
123 * hws_max_conc_proc has been done in
124 * kgd2kfd_device_init().
125 */
126 concurrent_proc_cnt = min(pm->dqm->processes_count,
127 kfd->max_proc_per_quantum);
128
129 packet = (struct pm4_mes_runlist *)buffer;
130
131 memset(buffer, 0, sizeof(struct pm4_mes_runlist));
132 packet->header.u32All = pm_build_pm4_header(IT_RUN_LIST,
133 sizeof(struct pm4_mes_runlist));
134
135 packet->bitfields4.ib_size = ib_size_in_dwords;
136 packet->bitfields4.chain = chain ? 1 : 0;
137 packet->bitfields4.offload_polling = 0;
138 packet->bitfields4.valid = 1;
139 packet->bitfields4.process_cnt = concurrent_proc_cnt;
140 packet->ordinal2 = lower_32_bits(ib);
141 packet->ib_base_hi = upper_32_bits(ib);
142
143 return 0;
144 }
145
pm_map_queues_v9(struct packet_manager * pm,uint32_t * buffer,struct queue * q,bool is_static)146 static int pm_map_queues_v9(struct packet_manager *pm, uint32_t *buffer,
147 struct queue *q, bool is_static)
148 {
149 struct pm4_mes_map_queues *packet;
150 bool use_static = is_static;
151
152 packet = (struct pm4_mes_map_queues *)buffer;
153 memset(buffer, 0, sizeof(struct pm4_mes_map_queues));
154
155 packet->header.u32All = pm_build_pm4_header(IT_MAP_QUEUES,
156 sizeof(struct pm4_mes_map_queues));
157 packet->bitfields2.alloc_format =
158 alloc_format__mes_map_queues__one_per_pipe_vi;
159 packet->bitfields2.num_queues = 1;
160 packet->bitfields2.queue_sel =
161 queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi;
162
163 packet->bitfields2.engine_sel =
164 engine_sel__mes_map_queues__compute_vi;
165 packet->bitfields2.queue_type =
166 queue_type__mes_map_queues__normal_compute_vi;
167
168 switch (q->properties.type) {
169 case KFD_QUEUE_TYPE_COMPUTE:
170 if (use_static)
171 packet->bitfields2.queue_type =
172 queue_type__mes_map_queues__normal_latency_static_queue_vi;
173 break;
174 case KFD_QUEUE_TYPE_DIQ:
175 packet->bitfields2.queue_type =
176 queue_type__mes_map_queues__debug_interface_queue_vi;
177 break;
178 case KFD_QUEUE_TYPE_SDMA:
179 packet->bitfields2.engine_sel = q->properties.sdma_engine_id +
180 engine_sel__mes_map_queues__sdma0_vi;
181 use_static = false; /* no static queues under SDMA */
182 break;
183 default:
184 WARN(1, "queue type %d", q->properties.type);
185 return -EINVAL;
186 }
187 packet->bitfields3.doorbell_offset =
188 q->properties.doorbell_off;
189
190 packet->mqd_addr_lo =
191 lower_32_bits(q->gart_mqd_addr);
192
193 packet->mqd_addr_hi =
194 upper_32_bits(q->gart_mqd_addr);
195
196 packet->wptr_addr_lo =
197 lower_32_bits((uint64_t)q->properties.write_ptr);
198
199 packet->wptr_addr_hi =
200 upper_32_bits((uint64_t)q->properties.write_ptr);
201
202 return 0;
203 }
204
pm_unmap_queues_v9(struct packet_manager * pm,uint32_t * buffer,enum kfd_queue_type type,enum kfd_unmap_queues_filter filter,uint32_t filter_param,bool reset,unsigned int sdma_engine)205 static int pm_unmap_queues_v9(struct packet_manager *pm, uint32_t *buffer,
206 enum kfd_queue_type type,
207 enum kfd_unmap_queues_filter filter,
208 uint32_t filter_param, bool reset,
209 unsigned int sdma_engine)
210 {
211 struct pm4_mes_unmap_queues *packet;
212
213 packet = (struct pm4_mes_unmap_queues *)buffer;
214 memset(buffer, 0, sizeof(struct pm4_mes_unmap_queues));
215
216 packet->header.u32All = pm_build_pm4_header(IT_UNMAP_QUEUES,
217 sizeof(struct pm4_mes_unmap_queues));
218 switch (type) {
219 case KFD_QUEUE_TYPE_COMPUTE:
220 case KFD_QUEUE_TYPE_DIQ:
221 packet->bitfields2.engine_sel =
222 engine_sel__mes_unmap_queues__compute;
223 break;
224 case KFD_QUEUE_TYPE_SDMA:
225 packet->bitfields2.engine_sel =
226 engine_sel__mes_unmap_queues__sdma0 + sdma_engine;
227 break;
228 default:
229 WARN(1, "queue type %d", type);
230 return -EINVAL;
231 }
232
233 if (reset)
234 packet->bitfields2.action =
235 action__mes_unmap_queues__reset_queues;
236 else
237 packet->bitfields2.action =
238 action__mes_unmap_queues__preempt_queues;
239
240 switch (filter) {
241 case KFD_UNMAP_QUEUES_FILTER_SINGLE_QUEUE:
242 packet->bitfields2.queue_sel =
243 queue_sel__mes_unmap_queues__perform_request_on_specified_queues;
244 packet->bitfields2.num_queues = 1;
245 packet->bitfields3b.doorbell_offset0 = filter_param;
246 break;
247 case KFD_UNMAP_QUEUES_FILTER_BY_PASID:
248 packet->bitfields2.queue_sel =
249 queue_sel__mes_unmap_queues__perform_request_on_pasid_queues;
250 packet->bitfields3a.pasid = filter_param;
251 break;
252 case KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES:
253 packet->bitfields2.queue_sel =
254 queue_sel__mes_unmap_queues__unmap_all_queues;
255 break;
256 case KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES:
257 /* in this case, we do not preempt static queues */
258 packet->bitfields2.queue_sel =
259 queue_sel__mes_unmap_queues__unmap_all_non_static_queues;
260 break;
261 default:
262 WARN(1, "filter %d", filter);
263 return -EINVAL;
264 }
265
266 return 0;
267
268 }
269
pm_query_status_v9(struct packet_manager * pm,uint32_t * buffer,uint64_t fence_address,uint32_t fence_value)270 static int pm_query_status_v9(struct packet_manager *pm, uint32_t *buffer,
271 uint64_t fence_address, uint32_t fence_value)
272 {
273 struct pm4_mes_query_status *packet;
274
275 packet = (struct pm4_mes_query_status *)buffer;
276 memset(buffer, 0, sizeof(struct pm4_mes_query_status));
277
278
279 packet->header.u32All = pm_build_pm4_header(IT_QUERY_STATUS,
280 sizeof(struct pm4_mes_query_status));
281
282 packet->bitfields2.context_id = 0;
283 packet->bitfields2.interrupt_sel =
284 interrupt_sel__mes_query_status__completion_status;
285 packet->bitfields2.command =
286 command__mes_query_status__fence_only_after_write_ack;
287
288 packet->addr_hi = upper_32_bits((uint64_t)fence_address);
289 packet->addr_lo = lower_32_bits((uint64_t)fence_address);
290 packet->data_hi = upper_32_bits((uint64_t)fence_value);
291 packet->data_lo = lower_32_bits((uint64_t)fence_value);
292
293 return 0;
294 }
295
296
pm_release_mem_v9(uint64_t gpu_addr,uint32_t * buffer)297 static int pm_release_mem_v9(uint64_t gpu_addr, uint32_t *buffer)
298 {
299 struct pm4_mec_release_mem *packet;
300
301 packet = (struct pm4_mec_release_mem *)buffer;
302 memset(buffer, 0, sizeof(struct pm4_mec_release_mem));
303
304 packet->header.u32All = pm_build_pm4_header(IT_RELEASE_MEM,
305 sizeof(struct pm4_mec_release_mem));
306
307 packet->bitfields2.event_type = CACHE_FLUSH_AND_INV_TS_EVENT;
308 packet->bitfields2.event_index = event_index__mec_release_mem__end_of_pipe;
309 packet->bitfields2.tcl1_action_ena = 1;
310 packet->bitfields2.tc_action_ena = 1;
311 packet->bitfields2.cache_policy = cache_policy__mec_release_mem__lru;
312
313 packet->bitfields3.data_sel = data_sel__mec_release_mem__send_32_bit_low;
314 packet->bitfields3.int_sel =
315 int_sel__mec_release_mem__send_interrupt_after_write_confirm;
316
317 packet->bitfields4.address_lo_32b = (gpu_addr & 0xffffffff) >> 2;
318 packet->address_hi = upper_32_bits(gpu_addr);
319
320 packet->data_lo = 0;
321
322 return 0;
323 }
324
325 const struct packet_manager_funcs kfd_v9_pm_funcs = {
326 .map_process = pm_map_process_v9,
327 .runlist = pm_runlist_v9,
328 .set_resources = pm_set_resources_vi,
329 .map_queues = pm_map_queues_v9,
330 .unmap_queues = pm_unmap_queues_v9,
331 .query_status = pm_query_status_v9,
332 .release_mem = pm_release_mem_v9,
333 .map_process_size = sizeof(struct pm4_mes_map_process),
334 .runlist_size = sizeof(struct pm4_mes_runlist),
335 .set_resources_size = sizeof(struct pm4_mes_set_resources),
336 .map_queues_size = sizeof(struct pm4_mes_map_queues),
337 .unmap_queues_size = sizeof(struct pm4_mes_unmap_queues),
338 .query_status_size = sizeof(struct pm4_mes_query_status),
339 .release_mem_size = sizeof(struct pm4_mec_release_mem)
340 };
341
