1 /* 2 * drxk_hard: DRX-K DVB-C/T demodulator driver 3 * 4 * Copyright (C) 2010-2011 Digital Devices GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 only, as published by the Free Software Foundation. 9 * 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * To obtain the license, point your browser to 17 * http://www.gnu.org/copyleft/gpl.html 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/moduleparam.h> 25 #include <linux/init.h> 26 #include <linux/delay.h> 27 #include <linux/firmware.h> 28 #include <linux/i2c.h> 29 #include <linux/hardirq.h> 30 #include <asm/div64.h> 31 32 #include <media/dvb_frontend.h> 33 #include "drxk.h" 34 #include "drxk_hard.h" 35 #include <media/dvb_math.h> 36 37 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode); 38 static int power_down_qam(struct drxk_state *state); 39 static int set_dvbt_standard(struct drxk_state *state, 40 enum operation_mode o_mode); 41 static int set_qam_standard(struct drxk_state *state, 42 enum operation_mode o_mode); 43 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, 44 s32 tuner_freq_offset); 45 static int set_dvbt_standard(struct drxk_state *state, 46 enum operation_mode o_mode); 47 static int dvbt_start(struct drxk_state *state); 48 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, 49 s32 tuner_freq_offset); 50 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status); 51 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status); 52 static int switch_antenna_to_qam(struct drxk_state *state); 53 static int switch_antenna_to_dvbt(struct drxk_state *state); 54 is_dvbt(struct drxk_state * state)55 static bool is_dvbt(struct drxk_state *state) 56 { 57 return state->m_operation_mode == OM_DVBT; 58 } 59 is_qam(struct drxk_state * state)60 static bool is_qam(struct drxk_state *state) 61 { 62 return state->m_operation_mode == OM_QAM_ITU_A || 63 state->m_operation_mode == OM_QAM_ITU_B || 64 state->m_operation_mode == OM_QAM_ITU_C; 65 } 66 67 #define NOA1ROM 0 68 69 #define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0) 70 #define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0) 71 72 #define DEFAULT_MER_83 165 73 #define DEFAULT_MER_93 250 74 75 #ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH 76 #define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02) 77 #endif 78 79 #ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH 80 #define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03) 81 #endif 82 83 #define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700 84 #define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500 85 86 #ifndef DRXK_KI_RAGC_ATV 87 #define DRXK_KI_RAGC_ATV 4 88 #endif 89 #ifndef DRXK_KI_IAGC_ATV 90 #define DRXK_KI_IAGC_ATV 6 91 #endif 92 #ifndef DRXK_KI_DAGC_ATV 93 #define DRXK_KI_DAGC_ATV 7 94 #endif 95 96 #ifndef DRXK_KI_RAGC_QAM 97 #define DRXK_KI_RAGC_QAM 3 98 #endif 99 #ifndef DRXK_KI_IAGC_QAM 100 #define DRXK_KI_IAGC_QAM 4 101 #endif 102 #ifndef DRXK_KI_DAGC_QAM 103 #define DRXK_KI_DAGC_QAM 7 104 #endif 105 #ifndef DRXK_KI_RAGC_DVBT 106 #define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2) 107 #endif 108 #ifndef DRXK_KI_IAGC_DVBT 109 #define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2) 110 #endif 111 #ifndef DRXK_KI_DAGC_DVBT 112 #define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7) 113 #endif 114 115 #ifndef DRXK_AGC_DAC_OFFSET 116 #define DRXK_AGC_DAC_OFFSET (0x800) 117 #endif 118 119 #ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ 120 #define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L) 121 #endif 122 123 #ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ 124 #define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L) 125 #endif 126 127 #ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ 128 #define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L) 129 #endif 130 131 #ifndef DRXK_QAM_SYMBOLRATE_MAX 132 #define DRXK_QAM_SYMBOLRATE_MAX (7233000) 133 #endif 134 135 #define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56 136 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64 137 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0 138 #define DRXK_BL_ROM_OFFSET_TAPS_BG 24 139 #define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32 140 #define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40 141 #define DRXK_BL_ROM_OFFSET_TAPS_FM 48 142 #define DRXK_BL_ROM_OFFSET_UCODE 0 143 144 #define DRXK_BLC_TIMEOUT 100 145 146 #define DRXK_BLCC_NR_ELEMENTS_TAPS 2 147 #define DRXK_BLCC_NR_ELEMENTS_UCODE 6 148 149 #define DRXK_BLDC_NR_ELEMENTS_TAPS 28 150 151 #ifndef DRXK_OFDM_NE_NOTCH_WIDTH 152 #define DRXK_OFDM_NE_NOTCH_WIDTH (4) 153 #endif 154 155 #define DRXK_QAM_SL_SIG_POWER_QAM16 (40960) 156 #define DRXK_QAM_SL_SIG_POWER_QAM32 (20480) 157 #define DRXK_QAM_SL_SIG_POWER_QAM64 (43008) 158 #define DRXK_QAM_SL_SIG_POWER_QAM128 (20992) 159 #define DRXK_QAM_SL_SIG_POWER_QAM256 (43520) 160 161 static unsigned int debug; 162 module_param(debug, int, 0644); 163 MODULE_PARM_DESC(debug, "enable debug messages"); 164 165 #define dprintk(level, fmt, arg...) do { \ 166 if (debug >= level) \ 167 printk(KERN_DEBUG KBUILD_MODNAME ": %s " fmt, __func__, ##arg); \ 168 } while (0) 169 170 MulDiv32(u32 a,u32 b,u32 c)171 static inline u32 MulDiv32(u32 a, u32 b, u32 c) 172 { 173 u64 tmp64; 174 175 tmp64 = (u64) a * (u64) b; 176 do_div(tmp64, c); 177 178 return (u32) tmp64; 179 } 180 Frac28a(u32 a,u32 c)181 static inline u32 Frac28a(u32 a, u32 c) 182 { 183 int i = 0; 184 u32 Q1 = 0; 185 u32 R0 = 0; 186 187 R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */ 188 Q1 = a / c; /* 189 * integer part, only the 4 least significant 190 * bits will be visible in the result 191 */ 192 193 /* division using radix 16, 7 nibbles in the result */ 194 for (i = 0; i < 7; i++) { 195 Q1 = (Q1 << 4) | (R0 / c); 196 R0 = (R0 % c) << 4; 197 } 198 /* rounding */ 199 if ((R0 >> 3) >= c) 200 Q1++; 201 202 return Q1; 203 } 204 log10times100(u32 value)205 static inline u32 log10times100(u32 value) 206 { 207 return (100L * intlog10(value)) >> 24; 208 } 209 210 /***************************************************************************/ 211 /* I2C **********************************************************************/ 212 /***************************************************************************/ 213 drxk_i2c_lock(struct drxk_state * state)214 static int drxk_i2c_lock(struct drxk_state *state) 215 { 216 i2c_lock_bus(state->i2c, I2C_LOCK_SEGMENT); 217 state->drxk_i2c_exclusive_lock = true; 218 219 return 0; 220 } 221 drxk_i2c_unlock(struct drxk_state * state)222 static void drxk_i2c_unlock(struct drxk_state *state) 223 { 224 if (!state->drxk_i2c_exclusive_lock) 225 return; 226 227 i2c_unlock_bus(state->i2c, I2C_LOCK_SEGMENT); 228 state->drxk_i2c_exclusive_lock = false; 229 } 230 drxk_i2c_transfer(struct drxk_state * state,struct i2c_msg * msgs,unsigned len)231 static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs, 232 unsigned len) 233 { 234 if (state->drxk_i2c_exclusive_lock) 235 return __i2c_transfer(state->i2c, msgs, len); 236 else 237 return i2c_transfer(state->i2c, msgs, len); 238 } 239 i2c_read1(struct drxk_state * state,u8 adr,u8 * val)240 static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val) 241 { 242 struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD, 243 .buf = val, .len = 1} 244 }; 245 246 return drxk_i2c_transfer(state, msgs, 1); 247 } 248 i2c_write(struct drxk_state * state,u8 adr,u8 * data,int len)249 static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len) 250 { 251 int status; 252 struct i2c_msg msg = { 253 .addr = adr, .flags = 0, .buf = data, .len = len }; 254 255 dprintk(3, ":"); 256 if (debug > 2) { 257 int i; 258 for (i = 0; i < len; i++) 259 pr_cont(" %02x", data[i]); 260 pr_cont("\n"); 261 } 262 status = drxk_i2c_transfer(state, &msg, 1); 263 if (status >= 0 && status != 1) 264 status = -EIO; 265 266 if (status < 0) 267 pr_err("i2c write error at addr 0x%02x\n", adr); 268 269 return status; 270 } 271 i2c_read(struct drxk_state * state,u8 adr,u8 * msg,int len,u8 * answ,int alen)272 static int i2c_read(struct drxk_state *state, 273 u8 adr, u8 *msg, int len, u8 *answ, int alen) 274 { 275 int status; 276 struct i2c_msg msgs[2] = { 277 {.addr = adr, .flags = 0, 278 .buf = msg, .len = len}, 279 {.addr = adr, .flags = I2C_M_RD, 280 .buf = answ, .len = alen} 281 }; 282 283 status = drxk_i2c_transfer(state, msgs, 2); 284 if (status != 2) { 285 if (debug > 2) 286 pr_cont(": ERROR!\n"); 287 if (status >= 0) 288 status = -EIO; 289 290 pr_err("i2c read error at addr 0x%02x\n", adr); 291 return status; 292 } 293 if (debug > 2) { 294 int i; 295 dprintk(2, ": read from"); 296 for (i = 0; i < len; i++) 297 pr_cont(" %02x", msg[i]); 298 pr_cont(", value = "); 299 for (i = 0; i < alen; i++) 300 pr_cont(" %02x", answ[i]); 301 pr_cont("\n"); 302 } 303 return 0; 304 } 305 read16_flags(struct drxk_state * state,u32 reg,u16 * data,u8 flags)306 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags) 307 { 308 int status; 309 u8 adr = state->demod_address, mm1[4], mm2[2], len; 310 311 if (state->single_master) 312 flags |= 0xC0; 313 314 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { 315 mm1[0] = (((reg << 1) & 0xFF) | 0x01); 316 mm1[1] = ((reg >> 16) & 0xFF); 317 mm1[2] = ((reg >> 24) & 0xFF) | flags; 318 mm1[3] = ((reg >> 7) & 0xFF); 319 len = 4; 320 } else { 321 mm1[0] = ((reg << 1) & 0xFF); 322 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); 323 len = 2; 324 } 325 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags); 326 status = i2c_read(state, adr, mm1, len, mm2, 2); 327 if (status < 0) 328 return status; 329 if (data) 330 *data = mm2[0] | (mm2[1] << 8); 331 332 return 0; 333 } 334 read16(struct drxk_state * state,u32 reg,u16 * data)335 static int read16(struct drxk_state *state, u32 reg, u16 *data) 336 { 337 return read16_flags(state, reg, data, 0); 338 } 339 read32_flags(struct drxk_state * state,u32 reg,u32 * data,u8 flags)340 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags) 341 { 342 int status; 343 u8 adr = state->demod_address, mm1[4], mm2[4], len; 344 345 if (state->single_master) 346 flags |= 0xC0; 347 348 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { 349 mm1[0] = (((reg << 1) & 0xFF) | 0x01); 350 mm1[1] = ((reg >> 16) & 0xFF); 351 mm1[2] = ((reg >> 24) & 0xFF) | flags; 352 mm1[3] = ((reg >> 7) & 0xFF); 353 len = 4; 354 } else { 355 mm1[0] = ((reg << 1) & 0xFF); 356 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); 357 len = 2; 358 } 359 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags); 360 status = i2c_read(state, adr, mm1, len, mm2, 4); 361 if (status < 0) 362 return status; 363 if (data) 364 *data = mm2[0] | (mm2[1] << 8) | 365 (mm2[2] << 16) | (mm2[3] << 24); 366 367 return 0; 368 } 369 read32(struct drxk_state * state,u32 reg,u32 * data)370 static int read32(struct drxk_state *state, u32 reg, u32 *data) 371 { 372 return read32_flags(state, reg, data, 0); 373 } 374 write16_flags(struct drxk_state * state,u32 reg,u16 data,u8 flags)375 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags) 376 { 377 u8 adr = state->demod_address, mm[6], len; 378 379 if (state->single_master) 380 flags |= 0xC0; 381 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { 382 mm[0] = (((reg << 1) & 0xFF) | 0x01); 383 mm[1] = ((reg >> 16) & 0xFF); 384 mm[2] = ((reg >> 24) & 0xFF) | flags; 385 mm[3] = ((reg >> 7) & 0xFF); 386 len = 4; 387 } else { 388 mm[0] = ((reg << 1) & 0xFF); 389 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); 390 len = 2; 391 } 392 mm[len] = data & 0xff; 393 mm[len + 1] = (data >> 8) & 0xff; 394 395 dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags); 396 return i2c_write(state, adr, mm, len + 2); 397 } 398 write16(struct drxk_state * state,u32 reg,u16 data)399 static int write16(struct drxk_state *state, u32 reg, u16 data) 400 { 401 return write16_flags(state, reg, data, 0); 402 } 403 write32_flags(struct drxk_state * state,u32 reg,u32 data,u8 flags)404 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags) 405 { 406 u8 adr = state->demod_address, mm[8], len; 407 408 if (state->single_master) 409 flags |= 0xC0; 410 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { 411 mm[0] = (((reg << 1) & 0xFF) | 0x01); 412 mm[1] = ((reg >> 16) & 0xFF); 413 mm[2] = ((reg >> 24) & 0xFF) | flags; 414 mm[3] = ((reg >> 7) & 0xFF); 415 len = 4; 416 } else { 417 mm[0] = ((reg << 1) & 0xFF); 418 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); 419 len = 2; 420 } 421 mm[len] = data & 0xff; 422 mm[len + 1] = (data >> 8) & 0xff; 423 mm[len + 2] = (data >> 16) & 0xff; 424 mm[len + 3] = (data >> 24) & 0xff; 425 dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags); 426 427 return i2c_write(state, adr, mm, len + 4); 428 } 429 write32(struct drxk_state * state,u32 reg,u32 data)430 static int write32(struct drxk_state *state, u32 reg, u32 data) 431 { 432 return write32_flags(state, reg, data, 0); 433 } 434 write_block(struct drxk_state * state,u32 address,const int block_size,const u8 p_block[])435 static int write_block(struct drxk_state *state, u32 address, 436 const int block_size, const u8 p_block[]) 437 { 438 int status = 0, blk_size = block_size; 439 u8 flags = 0; 440 441 if (state->single_master) 442 flags |= 0xC0; 443 444 while (blk_size > 0) { 445 int chunk = blk_size > state->m_chunk_size ? 446 state->m_chunk_size : blk_size; 447 u8 *adr_buf = &state->chunk[0]; 448 u32 adr_length = 0; 449 450 if (DRXDAP_FASI_LONG_FORMAT(address) || (flags != 0)) { 451 adr_buf[0] = (((address << 1) & 0xFF) | 0x01); 452 adr_buf[1] = ((address >> 16) & 0xFF); 453 adr_buf[2] = ((address >> 24) & 0xFF); 454 adr_buf[3] = ((address >> 7) & 0xFF); 455 adr_buf[2] |= flags; 456 adr_length = 4; 457 if (chunk == state->m_chunk_size) 458 chunk -= 2; 459 } else { 460 adr_buf[0] = ((address << 1) & 0xFF); 461 adr_buf[1] = (((address >> 16) & 0x0F) | 462 ((address >> 18) & 0xF0)); 463 adr_length = 2; 464 } 465 memcpy(&state->chunk[adr_length], p_block, chunk); 466 dprintk(2, "(0x%08x, 0x%02x)\n", address, flags); 467 if (debug > 1) { 468 int i; 469 if (p_block) 470 for (i = 0; i < chunk; i++) 471 pr_cont(" %02x", p_block[i]); 472 pr_cont("\n"); 473 } 474 status = i2c_write(state, state->demod_address, 475 &state->chunk[0], chunk + adr_length); 476 if (status < 0) { 477 pr_err("%s: i2c write error at addr 0x%02x\n", 478 __func__, address); 479 break; 480 } 481 p_block += chunk; 482 address += (chunk >> 1); 483 blk_size -= chunk; 484 } 485 return status; 486 } 487 488 #ifndef DRXK_MAX_RETRIES_POWERUP 489 #define DRXK_MAX_RETRIES_POWERUP 20 490 #endif 491 power_up_device(struct drxk_state * state)492 static int power_up_device(struct drxk_state *state) 493 { 494 int status; 495 u8 data = 0; 496 u16 retry_count = 0; 497 498 dprintk(1, "\n"); 499 500 status = i2c_read1(state, state->demod_address, &data); 501 if (status < 0) { 502 do { 503 data = 0; 504 status = i2c_write(state, state->demod_address, 505 &data, 1); 506 usleep_range(10000, 11000); 507 retry_count++; 508 if (status < 0) 509 continue; 510 status = i2c_read1(state, state->demod_address, 511 &data); 512 } while (status < 0 && 513 (retry_count < DRXK_MAX_RETRIES_POWERUP)); 514 if (status < 0 && retry_count >= DRXK_MAX_RETRIES_POWERUP) 515 goto error; 516 } 517 518 /* Make sure all clk domains are active */ 519 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE); 520 if (status < 0) 521 goto error; 522 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); 523 if (status < 0) 524 goto error; 525 /* Enable pll lock tests */ 526 status = write16(state, SIO_CC_PLL_LOCK__A, 1); 527 if (status < 0) 528 goto error; 529 530 state->m_current_power_mode = DRX_POWER_UP; 531 532 error: 533 if (status < 0) 534 pr_err("Error %d on %s\n", status, __func__); 535 536 return status; 537 } 538 539 init_state(struct drxk_state * state)540 static int init_state(struct drxk_state *state) 541 { 542 /* 543 * FIXME: most (all?) of the values below should be moved into 544 * struct drxk_config, as they are probably board-specific 545 */ 546 u32 ul_vsb_if_agc_mode = DRXK_AGC_CTRL_AUTO; 547 u32 ul_vsb_if_agc_output_level = 0; 548 u32 ul_vsb_if_agc_min_level = 0; 549 u32 ul_vsb_if_agc_max_level = 0x7FFF; 550 u32 ul_vsb_if_agc_speed = 3; 551 552 u32 ul_vsb_rf_agc_mode = DRXK_AGC_CTRL_AUTO; 553 u32 ul_vsb_rf_agc_output_level = 0; 554 u32 ul_vsb_rf_agc_min_level = 0; 555 u32 ul_vsb_rf_agc_max_level = 0x7FFF; 556 u32 ul_vsb_rf_agc_speed = 3; 557 u32 ul_vsb_rf_agc_top = 9500; 558 u32 ul_vsb_rf_agc_cut_off_current = 4000; 559 560 u32 ul_atv_if_agc_mode = DRXK_AGC_CTRL_AUTO; 561 u32 ul_atv_if_agc_output_level = 0; 562 u32 ul_atv_if_agc_min_level = 0; 563 u32 ul_atv_if_agc_max_level = 0; 564 u32 ul_atv_if_agc_speed = 3; 565 566 u32 ul_atv_rf_agc_mode = DRXK_AGC_CTRL_OFF; 567 u32 ul_atv_rf_agc_output_level = 0; 568 u32 ul_atv_rf_agc_min_level = 0; 569 u32 ul_atv_rf_agc_max_level = 0; 570 u32 ul_atv_rf_agc_top = 9500; 571 u32 ul_atv_rf_agc_cut_off_current = 4000; 572 u32 ul_atv_rf_agc_speed = 3; 573 574 u32 ulQual83 = DEFAULT_MER_83; 575 u32 ulQual93 = DEFAULT_MER_93; 576 577 u32 ul_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; 578 u32 ul_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; 579 580 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ 581 /* io_pad_cfg_mode output mode is drive always */ 582 /* io_pad_cfg_drive is set to power 2 (23 mA) */ 583 u32 ul_gpio_cfg = 0x0113; 584 u32 ul_invert_ts_clock = 0; 585 u32 ul_ts_data_strength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH; 586 u32 ul_dvbt_bitrate = 50000000; 587 u32 ul_dvbc_bitrate = DRXK_QAM_SYMBOLRATE_MAX * 8; 588 589 u32 ul_insert_rs_byte = 0; 590 591 u32 ul_rf_mirror = 1; 592 u32 ul_power_down = 0; 593 594 dprintk(1, "\n"); 595 596 state->m_has_lna = false; 597 state->m_has_dvbt = false; 598 state->m_has_dvbc = false; 599 state->m_has_atv = false; 600 state->m_has_oob = false; 601 state->m_has_audio = false; 602 603 if (!state->m_chunk_size) 604 state->m_chunk_size = 124; 605 606 state->m_osc_clock_freq = 0; 607 state->m_smart_ant_inverted = false; 608 state->m_b_p_down_open_bridge = false; 609 610 /* real system clock frequency in kHz */ 611 state->m_sys_clock_freq = 151875; 612 /* Timing div, 250ns/Psys */ 613 /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */ 614 state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) * 615 HI_I2C_DELAY) / 1000; 616 /* Clipping */ 617 if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) 618 state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; 619 state->m_hi_cfg_wake_up_key = (state->demod_address << 1); 620 /* port/bridge/power down ctrl */ 621 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; 622 623 state->m_b_power_down = (ul_power_down != 0); 624 625 state->m_drxk_a3_patch_code = false; 626 627 /* Init AGC and PGA parameters */ 628 /* VSB IF */ 629 state->m_vsb_if_agc_cfg.ctrl_mode = ul_vsb_if_agc_mode; 630 state->m_vsb_if_agc_cfg.output_level = ul_vsb_if_agc_output_level; 631 state->m_vsb_if_agc_cfg.min_output_level = ul_vsb_if_agc_min_level; 632 state->m_vsb_if_agc_cfg.max_output_level = ul_vsb_if_agc_max_level; 633 state->m_vsb_if_agc_cfg.speed = ul_vsb_if_agc_speed; 634 state->m_vsb_pga_cfg = 140; 635 636 /* VSB RF */ 637 state->m_vsb_rf_agc_cfg.ctrl_mode = ul_vsb_rf_agc_mode; 638 state->m_vsb_rf_agc_cfg.output_level = ul_vsb_rf_agc_output_level; 639 state->m_vsb_rf_agc_cfg.min_output_level = ul_vsb_rf_agc_min_level; 640 state->m_vsb_rf_agc_cfg.max_output_level = ul_vsb_rf_agc_max_level; 641 state->m_vsb_rf_agc_cfg.speed = ul_vsb_rf_agc_speed; 642 state->m_vsb_rf_agc_cfg.top = ul_vsb_rf_agc_top; 643 state->m_vsb_rf_agc_cfg.cut_off_current = ul_vsb_rf_agc_cut_off_current; 644 state->m_vsb_pre_saw_cfg.reference = 0x07; 645 state->m_vsb_pre_saw_cfg.use_pre_saw = true; 646 647 state->m_Quality83percent = DEFAULT_MER_83; 648 state->m_Quality93percent = DEFAULT_MER_93; 649 if (ulQual93 <= 500 && ulQual83 < ulQual93) { 650 state->m_Quality83percent = ulQual83; 651 state->m_Quality93percent = ulQual93; 652 } 653 654 /* ATV IF */ 655 state->m_atv_if_agc_cfg.ctrl_mode = ul_atv_if_agc_mode; 656 state->m_atv_if_agc_cfg.output_level = ul_atv_if_agc_output_level; 657 state->m_atv_if_agc_cfg.min_output_level = ul_atv_if_agc_min_level; 658 state->m_atv_if_agc_cfg.max_output_level = ul_atv_if_agc_max_level; 659 state->m_atv_if_agc_cfg.speed = ul_atv_if_agc_speed; 660 661 /* ATV RF */ 662 state->m_atv_rf_agc_cfg.ctrl_mode = ul_atv_rf_agc_mode; 663 state->m_atv_rf_agc_cfg.output_level = ul_atv_rf_agc_output_level; 664 state->m_atv_rf_agc_cfg.min_output_level = ul_atv_rf_agc_min_level; 665 state->m_atv_rf_agc_cfg.max_output_level = ul_atv_rf_agc_max_level; 666 state->m_atv_rf_agc_cfg.speed = ul_atv_rf_agc_speed; 667 state->m_atv_rf_agc_cfg.top = ul_atv_rf_agc_top; 668 state->m_atv_rf_agc_cfg.cut_off_current = ul_atv_rf_agc_cut_off_current; 669 state->m_atv_pre_saw_cfg.reference = 0x04; 670 state->m_atv_pre_saw_cfg.use_pre_saw = true; 671 672 673 /* DVBT RF */ 674 state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF; 675 state->m_dvbt_rf_agc_cfg.output_level = 0; 676 state->m_dvbt_rf_agc_cfg.min_output_level = 0; 677 state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF; 678 state->m_dvbt_rf_agc_cfg.top = 0x2100; 679 state->m_dvbt_rf_agc_cfg.cut_off_current = 4000; 680 state->m_dvbt_rf_agc_cfg.speed = 1; 681 682 683 /* DVBT IF */ 684 state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO; 685 state->m_dvbt_if_agc_cfg.output_level = 0; 686 state->m_dvbt_if_agc_cfg.min_output_level = 0; 687 state->m_dvbt_if_agc_cfg.max_output_level = 9000; 688 state->m_dvbt_if_agc_cfg.top = 13424; 689 state->m_dvbt_if_agc_cfg.cut_off_current = 0; 690 state->m_dvbt_if_agc_cfg.speed = 3; 691 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30; 692 state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000; 693 /* state->m_dvbtPgaCfg = 140; */ 694 695 state->m_dvbt_pre_saw_cfg.reference = 4; 696 state->m_dvbt_pre_saw_cfg.use_pre_saw = false; 697 698 /* QAM RF */ 699 state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF; 700 state->m_qam_rf_agc_cfg.output_level = 0; 701 state->m_qam_rf_agc_cfg.min_output_level = 6023; 702 state->m_qam_rf_agc_cfg.max_output_level = 27000; 703 state->m_qam_rf_agc_cfg.top = 0x2380; 704 state->m_qam_rf_agc_cfg.cut_off_current = 4000; 705 state->m_qam_rf_agc_cfg.speed = 3; 706 707 /* QAM IF */ 708 state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO; 709 state->m_qam_if_agc_cfg.output_level = 0; 710 state->m_qam_if_agc_cfg.min_output_level = 0; 711 state->m_qam_if_agc_cfg.max_output_level = 9000; 712 state->m_qam_if_agc_cfg.top = 0x0511; 713 state->m_qam_if_agc_cfg.cut_off_current = 0; 714 state->m_qam_if_agc_cfg.speed = 3; 715 state->m_qam_if_agc_cfg.ingain_tgt_max = 5119; 716 state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50; 717 718 state->m_qam_pga_cfg = 140; 719 state->m_qam_pre_saw_cfg.reference = 4; 720 state->m_qam_pre_saw_cfg.use_pre_saw = false; 721 722 state->m_operation_mode = OM_NONE; 723 state->m_drxk_state = DRXK_UNINITIALIZED; 724 725 /* MPEG output configuration */ 726 state->m_enable_mpeg_output = true; /* If TRUE; enable MPEG ouput */ 727 state->m_insert_rs_byte = false; /* If TRUE; insert RS byte */ 728 state->m_invert_data = false; /* If TRUE; invert DATA signals */ 729 state->m_invert_err = false; /* If TRUE; invert ERR signal */ 730 state->m_invert_str = false; /* If TRUE; invert STR signals */ 731 state->m_invert_val = false; /* If TRUE; invert VAL signals */ 732 state->m_invert_clk = (ul_invert_ts_clock != 0); /* If TRUE; invert CLK signals */ 733 734 /* If TRUE; static MPEG clockrate will be used; 735 otherwise clockrate will adapt to the bitrate of the TS */ 736 737 state->m_dvbt_bitrate = ul_dvbt_bitrate; 738 state->m_dvbc_bitrate = ul_dvbc_bitrate; 739 740 state->m_ts_data_strength = (ul_ts_data_strength & 0x07); 741 742 /* Maximum bitrate in b/s in case static clockrate is selected */ 743 state->m_mpeg_ts_static_bitrate = 19392658; 744 state->m_disable_te_ihandling = false; 745 746 if (ul_insert_rs_byte) 747 state->m_insert_rs_byte = true; 748 749 state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; 750 if (ul_mpeg_lock_time_out < 10000) 751 state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out; 752 state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; 753 if (ul_demod_lock_time_out < 10000) 754 state->m_demod_lock_time_out = ul_demod_lock_time_out; 755 756 /* QAM defaults */ 757 state->m_constellation = DRX_CONSTELLATION_AUTO; 758 state->m_qam_interleave_mode = DRXK_QAM_I12_J17; 759 state->m_fec_rs_plen = 204 * 8; /* fecRsPlen annex A */ 760 state->m_fec_rs_prescale = 1; 761 762 state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM; 763 state->m_agcfast_clip_ctrl_delay = 0; 764 765 state->m_gpio_cfg = ul_gpio_cfg; 766 767 state->m_b_power_down = false; 768 state->m_current_power_mode = DRX_POWER_DOWN; 769 770 state->m_rfmirror = (ul_rf_mirror == 0); 771 state->m_if_agc_pol = false; 772 return 0; 773 } 774 drxx_open(struct drxk_state * state)775 static int drxx_open(struct drxk_state *state) 776 { 777 int status = 0; 778 u32 jtag = 0; 779 u16 bid = 0; 780 u16 key = 0; 781 782 dprintk(1, "\n"); 783 /* stop lock indicator process */ 784 status = write16(state, SCU_RAM_GPIO__A, 785 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 786 if (status < 0) 787 goto error; 788 /* Check device id */ 789 status = read16(state, SIO_TOP_COMM_KEY__A, &key); 790 if (status < 0) 791 goto error; 792 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); 793 if (status < 0) 794 goto error; 795 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag); 796 if (status < 0) 797 goto error; 798 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid); 799 if (status < 0) 800 goto error; 801 status = write16(state, SIO_TOP_COMM_KEY__A, key); 802 error: 803 if (status < 0) 804 pr_err("Error %d on %s\n", status, __func__); 805 return status; 806 } 807 get_device_capabilities(struct drxk_state * state)808 static int get_device_capabilities(struct drxk_state *state) 809 { 810 u16 sio_pdr_ohw_cfg = 0; 811 u32 sio_top_jtagid_lo = 0; 812 int status; 813 const char *spin = ""; 814 815 dprintk(1, "\n"); 816 817 /* driver 0.9.0 */ 818 /* stop lock indicator process */ 819 status = write16(state, SCU_RAM_GPIO__A, 820 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 821 if (status < 0) 822 goto error; 823 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); 824 if (status < 0) 825 goto error; 826 status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg); 827 if (status < 0) 828 goto error; 829 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); 830 if (status < 0) 831 goto error; 832 833 switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) { 834 case 0: 835 /* ignore (bypass ?) */ 836 break; 837 case 1: 838 /* 27 MHz */ 839 state->m_osc_clock_freq = 27000; 840 break; 841 case 2: 842 /* 20.25 MHz */ 843 state->m_osc_clock_freq = 20250; 844 break; 845 case 3: 846 /* 4 MHz */ 847 state->m_osc_clock_freq = 20250; 848 break; 849 default: 850 pr_err("Clock Frequency is unknown\n"); 851 return -EINVAL; 852 } 853 /* 854 Determine device capabilities 855 Based on pinning v14 856 */ 857 status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo); 858 if (status < 0) 859 goto error; 860 861 pr_info("status = 0x%08x\n", sio_top_jtagid_lo); 862 863 /* driver 0.9.0 */ 864 switch ((sio_top_jtagid_lo >> 29) & 0xF) { 865 case 0: 866 state->m_device_spin = DRXK_SPIN_A1; 867 spin = "A1"; 868 break; 869 case 2: 870 state->m_device_spin = DRXK_SPIN_A2; 871 spin = "A2"; 872 break; 873 case 3: 874 state->m_device_spin = DRXK_SPIN_A3; 875 spin = "A3"; 876 break; 877 default: 878 state->m_device_spin = DRXK_SPIN_UNKNOWN; 879 status = -EINVAL; 880 pr_err("Spin %d unknown\n", (sio_top_jtagid_lo >> 29) & 0xF); 881 goto error2; 882 } 883 switch ((sio_top_jtagid_lo >> 12) & 0xFF) { 884 case 0x13: 885 /* typeId = DRX3913K_TYPE_ID */ 886 state->m_has_lna = false; 887 state->m_has_oob = false; 888 state->m_has_atv = false; 889 state->m_has_audio = false; 890 state->m_has_dvbt = true; 891 state->m_has_dvbc = true; 892 state->m_has_sawsw = true; 893 state->m_has_gpio2 = false; 894 state->m_has_gpio1 = false; 895 state->m_has_irqn = false; 896 break; 897 case 0x15: 898 /* typeId = DRX3915K_TYPE_ID */ 899 state->m_has_lna = false; 900 state->m_has_oob = false; 901 state->m_has_atv = true; 902 state->m_has_audio = false; 903 state->m_has_dvbt = true; 904 state->m_has_dvbc = false; 905 state->m_has_sawsw = true; 906 state->m_has_gpio2 = true; 907 state->m_has_gpio1 = true; 908 state->m_has_irqn = false; 909 break; 910 case 0x16: 911 /* typeId = DRX3916K_TYPE_ID */ 912 state->m_has_lna = false; 913 state->m_has_oob = false; 914 state->m_has_atv = true; 915 state->m_has_audio = false; 916 state->m_has_dvbt = true; 917 state->m_has_dvbc = false; 918 state->m_has_sawsw = true; 919 state->m_has_gpio2 = true; 920 state->m_has_gpio1 = true; 921 state->m_has_irqn = false; 922 break; 923 case 0x18: 924 /* typeId = DRX3918K_TYPE_ID */ 925 state->m_has_lna = false; 926 state->m_has_oob = false; 927 state->m_has_atv = true; 928 state->m_has_audio = true; 929 state->m_has_dvbt = true; 930 state->m_has_dvbc = false; 931 state->m_has_sawsw = true; 932 state->m_has_gpio2 = true; 933 state->m_has_gpio1 = true; 934 state->m_has_irqn = false; 935 break; 936 case 0x21: 937 /* typeId = DRX3921K_TYPE_ID */ 938 state->m_has_lna = false; 939 state->m_has_oob = false; 940 state->m_has_atv = true; 941 state->m_has_audio = true; 942 state->m_has_dvbt = true; 943 state->m_has_dvbc = true; 944 state->m_has_sawsw = true; 945 state->m_has_gpio2 = true; 946 state->m_has_gpio1 = true; 947 state->m_has_irqn = false; 948 break; 949 case 0x23: 950 /* typeId = DRX3923K_TYPE_ID */ 951 state->m_has_lna = false; 952 state->m_has_oob = false; 953 state->m_has_atv = true; 954 state->m_has_audio = true; 955 state->m_has_dvbt = true; 956 state->m_has_dvbc = true; 957 state->m_has_sawsw = true; 958 state->m_has_gpio2 = true; 959 state->m_has_gpio1 = true; 960 state->m_has_irqn = false; 961 break; 962 case 0x25: 963 /* typeId = DRX3925K_TYPE_ID */ 964 state->m_has_lna = false; 965 state->m_has_oob = false; 966 state->m_has_atv = true; 967 state->m_has_audio = true; 968 state->m_has_dvbt = true; 969 state->m_has_dvbc = true; 970 state->m_has_sawsw = true; 971 state->m_has_gpio2 = true; 972 state->m_has_gpio1 = true; 973 state->m_has_irqn = false; 974 break; 975 case 0x26: 976 /* typeId = DRX3926K_TYPE_ID */ 977 state->m_has_lna = false; 978 state->m_has_oob = false; 979 state->m_has_atv = true; 980 state->m_has_audio = false; 981 state->m_has_dvbt = true; 982 state->m_has_dvbc = true; 983 state->m_has_sawsw = true; 984 state->m_has_gpio2 = true; 985 state->m_has_gpio1 = true; 986 state->m_has_irqn = false; 987 break; 988 default: 989 pr_err("DeviceID 0x%02x not supported\n", 990 ((sio_top_jtagid_lo >> 12) & 0xFF)); 991 status = -EINVAL; 992 goto error2; 993 } 994 995 pr_info("detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n", 996 ((sio_top_jtagid_lo >> 12) & 0xFF), spin, 997 state->m_osc_clock_freq / 1000, 998 state->m_osc_clock_freq % 1000); 999 1000 error: 1001 if (status < 0) 1002 pr_err("Error %d on %s\n", status, __func__); 1003 1004 error2: 1005 return status; 1006 } 1007 hi_command(struct drxk_state * state,u16 cmd,u16 * p_result)1008 static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result) 1009 { 1010 int status; 1011 bool powerdown_cmd; 1012 1013 dprintk(1, "\n"); 1014 1015 /* Write command */ 1016 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd); 1017 if (status < 0) 1018 goto error; 1019 if (cmd == SIO_HI_RA_RAM_CMD_RESET) 1020 usleep_range(1000, 2000); 1021 1022 powerdown_cmd = 1023 (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) && 1024 ((state->m_hi_cfg_ctrl) & 1025 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) == 1026 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ); 1027 if (!powerdown_cmd) { 1028 /* Wait until command rdy */ 1029 u32 retry_count = 0; 1030 u16 wait_cmd; 1031 1032 do { 1033 usleep_range(1000, 2000); 1034 retry_count += 1; 1035 status = read16(state, SIO_HI_RA_RAM_CMD__A, 1036 &wait_cmd); 1037 } while ((status < 0) && (retry_count < DRXK_MAX_RETRIES) 1038 && (wait_cmd != 0)); 1039 if (status < 0) 1040 goto error; 1041 status = read16(state, SIO_HI_RA_RAM_RES__A, p_result); 1042 } 1043 error: 1044 if (status < 0) 1045 pr_err("Error %d on %s\n", status, __func__); 1046 1047 return status; 1048 } 1049 hi_cfg_command(struct drxk_state * state)1050 static int hi_cfg_command(struct drxk_state *state) 1051 { 1052 int status; 1053 1054 dprintk(1, "\n"); 1055 1056 mutex_lock(&state->mutex); 1057 1058 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, 1059 state->m_hi_cfg_timeout); 1060 if (status < 0) 1061 goto error; 1062 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, 1063 state->m_hi_cfg_ctrl); 1064 if (status < 0) 1065 goto error; 1066 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, 1067 state->m_hi_cfg_wake_up_key); 1068 if (status < 0) 1069 goto error; 1070 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, 1071 state->m_hi_cfg_bridge_delay); 1072 if (status < 0) 1073 goto error; 1074 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, 1075 state->m_hi_cfg_timing_div); 1076 if (status < 0) 1077 goto error; 1078 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, 1079 SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); 1080 if (status < 0) 1081 goto error; 1082 status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL); 1083 if (status < 0) 1084 goto error; 1085 1086 state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; 1087 error: 1088 mutex_unlock(&state->mutex); 1089 if (status < 0) 1090 pr_err("Error %d on %s\n", status, __func__); 1091 return status; 1092 } 1093 init_hi(struct drxk_state * state)1094 static int init_hi(struct drxk_state *state) 1095 { 1096 dprintk(1, "\n"); 1097 1098 state->m_hi_cfg_wake_up_key = (state->demod_address << 1); 1099 state->m_hi_cfg_timeout = 0x96FF; 1100 /* port/bridge/power down ctrl */ 1101 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; 1102 1103 return hi_cfg_command(state); 1104 } 1105 mpegts_configure_pins(struct drxk_state * state,bool mpeg_enable)1106 static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable) 1107 { 1108 int status = -1; 1109 u16 sio_pdr_mclk_cfg = 0; 1110 u16 sio_pdr_mdx_cfg = 0; 1111 u16 err_cfg = 0; 1112 1113 dprintk(1, ": mpeg %s, %s mode\n", 1114 mpeg_enable ? "enable" : "disable", 1115 state->m_enable_parallel ? "parallel" : "serial"); 1116 1117 /* stop lock indicator process */ 1118 status = write16(state, SCU_RAM_GPIO__A, 1119 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 1120 if (status < 0) 1121 goto error; 1122 1123 /* MPEG TS pad configuration */ 1124 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); 1125 if (status < 0) 1126 goto error; 1127 1128 if (!mpeg_enable) { 1129 /* Set MPEG TS pads to inputmode */ 1130 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000); 1131 if (status < 0) 1132 goto error; 1133 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000); 1134 if (status < 0) 1135 goto error; 1136 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000); 1137 if (status < 0) 1138 goto error; 1139 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000); 1140 if (status < 0) 1141 goto error; 1142 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000); 1143 if (status < 0) 1144 goto error; 1145 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000); 1146 if (status < 0) 1147 goto error; 1148 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000); 1149 if (status < 0) 1150 goto error; 1151 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000); 1152 if (status < 0) 1153 goto error; 1154 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000); 1155 if (status < 0) 1156 goto error; 1157 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000); 1158 if (status < 0) 1159 goto error; 1160 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000); 1161 if (status < 0) 1162 goto error; 1163 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000); 1164 if (status < 0) 1165 goto error; 1166 } else { 1167 /* Enable MPEG output */ 1168 sio_pdr_mdx_cfg = 1169 ((state->m_ts_data_strength << 1170 SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003); 1171 sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength << 1172 SIO_PDR_MCLK_CFG_DRIVE__B) | 1173 0x0003); 1174 1175 status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg); 1176 if (status < 0) 1177 goto error; 1178 1179 if (state->enable_merr_cfg) 1180 err_cfg = sio_pdr_mdx_cfg; 1181 1182 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg); 1183 if (status < 0) 1184 goto error; 1185 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg); 1186 if (status < 0) 1187 goto error; 1188 1189 if (state->m_enable_parallel) { 1190 /* parallel -> enable MD1 to MD7 */ 1191 status = write16(state, SIO_PDR_MD1_CFG__A, 1192 sio_pdr_mdx_cfg); 1193 if (status < 0) 1194 goto error; 1195 status = write16(state, SIO_PDR_MD2_CFG__A, 1196 sio_pdr_mdx_cfg); 1197 if (status < 0) 1198 goto error; 1199 status = write16(state, SIO_PDR_MD3_CFG__A, 1200 sio_pdr_mdx_cfg); 1201 if (status < 0) 1202 goto error; 1203 status = write16(state, SIO_PDR_MD4_CFG__A, 1204 sio_pdr_mdx_cfg); 1205 if (status < 0) 1206 goto error; 1207 status = write16(state, SIO_PDR_MD5_CFG__A, 1208 sio_pdr_mdx_cfg); 1209 if (status < 0) 1210 goto error; 1211 status = write16(state, SIO_PDR_MD6_CFG__A, 1212 sio_pdr_mdx_cfg); 1213 if (status < 0) 1214 goto error; 1215 status = write16(state, SIO_PDR_MD7_CFG__A, 1216 sio_pdr_mdx_cfg); 1217 if (status < 0) 1218 goto error; 1219 } else { 1220 sio_pdr_mdx_cfg = ((state->m_ts_data_strength << 1221 SIO_PDR_MD0_CFG_DRIVE__B) 1222 | 0x0003); 1223 /* serial -> disable MD1 to MD7 */ 1224 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000); 1225 if (status < 0) 1226 goto error; 1227 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000); 1228 if (status < 0) 1229 goto error; 1230 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000); 1231 if (status < 0) 1232 goto error; 1233 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000); 1234 if (status < 0) 1235 goto error; 1236 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000); 1237 if (status < 0) 1238 goto error; 1239 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000); 1240 if (status < 0) 1241 goto error; 1242 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000); 1243 if (status < 0) 1244 goto error; 1245 } 1246 status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg); 1247 if (status < 0) 1248 goto error; 1249 status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg); 1250 if (status < 0) 1251 goto error; 1252 } 1253 /* Enable MB output over MPEG pads and ctl input */ 1254 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000); 1255 if (status < 0) 1256 goto error; 1257 /* Write nomagic word to enable pdr reg write */ 1258 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); 1259 error: 1260 if (status < 0) 1261 pr_err("Error %d on %s\n", status, __func__); 1262 return status; 1263 } 1264 mpegts_disable(struct drxk_state * state)1265 static int mpegts_disable(struct drxk_state *state) 1266 { 1267 dprintk(1, "\n"); 1268 1269 return mpegts_configure_pins(state, false); 1270 } 1271 bl_chain_cmd(struct drxk_state * state,u16 rom_offset,u16 nr_of_elements,u32 time_out)1272 static int bl_chain_cmd(struct drxk_state *state, 1273 u16 rom_offset, u16 nr_of_elements, u32 time_out) 1274 { 1275 u16 bl_status = 0; 1276 int status; 1277 unsigned long end; 1278 1279 dprintk(1, "\n"); 1280 mutex_lock(&state->mutex); 1281 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN); 1282 if (status < 0) 1283 goto error; 1284 status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset); 1285 if (status < 0) 1286 goto error; 1287 status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements); 1288 if (status < 0) 1289 goto error; 1290 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); 1291 if (status < 0) 1292 goto error; 1293 1294 end = jiffies + msecs_to_jiffies(time_out); 1295 do { 1296 usleep_range(1000, 2000); 1297 status = read16(state, SIO_BL_STATUS__A, &bl_status); 1298 if (status < 0) 1299 goto error; 1300 } while ((bl_status == 0x1) && 1301 ((time_is_after_jiffies(end)))); 1302 1303 if (bl_status == 0x1) { 1304 pr_err("SIO not ready\n"); 1305 status = -EINVAL; 1306 goto error2; 1307 } 1308 error: 1309 if (status < 0) 1310 pr_err("Error %d on %s\n", status, __func__); 1311 error2: 1312 mutex_unlock(&state->mutex); 1313 return status; 1314 } 1315 1316 download_microcode(struct drxk_state * state,const u8 p_mc_image[],u32 length)1317 static int download_microcode(struct drxk_state *state, 1318 const u8 p_mc_image[], u32 length) 1319 { 1320 const u8 *p_src = p_mc_image; 1321 u32 address; 1322 u16 n_blocks; 1323 u16 block_size; 1324 u32 offset = 0; 1325 u32 i; 1326 int status = 0; 1327 1328 dprintk(1, "\n"); 1329 1330 /* down the drain (we don't care about MAGIC_WORD) */ 1331 #if 0 1332 /* For future reference */ 1333 drain = (p_src[0] << 8) | p_src[1]; 1334 #endif 1335 p_src += sizeof(u16); 1336 offset += sizeof(u16); 1337 n_blocks = (p_src[0] << 8) | p_src[1]; 1338 p_src += sizeof(u16); 1339 offset += sizeof(u16); 1340 1341 for (i = 0; i < n_blocks; i += 1) { 1342 address = (p_src[0] << 24) | (p_src[1] << 16) | 1343 (p_src[2] << 8) | p_src[3]; 1344 p_src += sizeof(u32); 1345 offset += sizeof(u32); 1346 1347 block_size = ((p_src[0] << 8) | p_src[1]) * sizeof(u16); 1348 p_src += sizeof(u16); 1349 offset += sizeof(u16); 1350 1351 #if 0 1352 /* For future reference */ 1353 flags = (p_src[0] << 8) | p_src[1]; 1354 #endif 1355 p_src += sizeof(u16); 1356 offset += sizeof(u16); 1357 1358 #if 0 1359 /* For future reference */ 1360 block_crc = (p_src[0] << 8) | p_src[1]; 1361 #endif 1362 p_src += sizeof(u16); 1363 offset += sizeof(u16); 1364 1365 if (offset + block_size > length) { 1366 pr_err("Firmware is corrupted.\n"); 1367 return -EINVAL; 1368 } 1369 1370 status = write_block(state, address, block_size, p_src); 1371 if (status < 0) { 1372 pr_err("Error %d while loading firmware\n", status); 1373 break; 1374 } 1375 p_src += block_size; 1376 offset += block_size; 1377 } 1378 return status; 1379 } 1380 dvbt_enable_ofdm_token_ring(struct drxk_state * state,bool enable)1381 static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable) 1382 { 1383 int status; 1384 u16 data = 0; 1385 u16 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON; 1386 u16 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED; 1387 unsigned long end; 1388 1389 dprintk(1, "\n"); 1390 1391 if (!enable) { 1392 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF; 1393 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN; 1394 } 1395 1396 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); 1397 if (status >= 0 && data == desired_status) { 1398 /* tokenring already has correct status */ 1399 return status; 1400 } 1401 /* Disable/enable dvbt tokenring bridge */ 1402 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl); 1403 1404 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT); 1405 do { 1406 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); 1407 if ((status >= 0 && data == desired_status) 1408 || time_is_after_jiffies(end)) 1409 break; 1410 usleep_range(1000, 2000); 1411 } while (1); 1412 if (data != desired_status) { 1413 pr_err("SIO not ready\n"); 1414 return -EINVAL; 1415 } 1416 return status; 1417 } 1418 mpegts_stop(struct drxk_state * state)1419 static int mpegts_stop(struct drxk_state *state) 1420 { 1421 int status = 0; 1422 u16 fec_oc_snc_mode = 0; 1423 u16 fec_oc_ipr_mode = 0; 1424 1425 dprintk(1, "\n"); 1426 1427 /* Graceful shutdown (byte boundaries) */ 1428 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode); 1429 if (status < 0) 1430 goto error; 1431 fec_oc_snc_mode |= FEC_OC_SNC_MODE_SHUTDOWN__M; 1432 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode); 1433 if (status < 0) 1434 goto error; 1435 1436 /* Suppress MCLK during absence of data */ 1437 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode); 1438 if (status < 0) 1439 goto error; 1440 fec_oc_ipr_mode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M; 1441 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode); 1442 1443 error: 1444 if (status < 0) 1445 pr_err("Error %d on %s\n", status, __func__); 1446 1447 return status; 1448 } 1449 scu_command(struct drxk_state * state,u16 cmd,u8 parameter_len,u16 * parameter,u8 result_len,u16 * result)1450 static int scu_command(struct drxk_state *state, 1451 u16 cmd, u8 parameter_len, 1452 u16 *parameter, u8 result_len, u16 *result) 1453 { 1454 #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15 1455 #error DRXK register mapping no longer compatible with this routine! 1456 #endif 1457 u16 cur_cmd = 0; 1458 int status = -EINVAL; 1459 unsigned long end; 1460 u8 buffer[34]; 1461 int cnt = 0, ii; 1462 const char *p; 1463 char errname[30]; 1464 1465 dprintk(1, "\n"); 1466 1467 if ((cmd == 0) || ((parameter_len > 0) && (parameter == NULL)) || 1468 ((result_len > 0) && (result == NULL))) { 1469 pr_err("Error %d on %s\n", status, __func__); 1470 return status; 1471 } 1472 1473 mutex_lock(&state->mutex); 1474 1475 /* assume that the command register is ready 1476 since it is checked afterwards */ 1477 for (ii = parameter_len - 1; ii >= 0; ii -= 1) { 1478 buffer[cnt++] = (parameter[ii] & 0xFF); 1479 buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF); 1480 } 1481 buffer[cnt++] = (cmd & 0xFF); 1482 buffer[cnt++] = ((cmd >> 8) & 0xFF); 1483 1484 write_block(state, SCU_RAM_PARAM_0__A - 1485 (parameter_len - 1), cnt, buffer); 1486 /* Wait until SCU has processed command */ 1487 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME); 1488 do { 1489 usleep_range(1000, 2000); 1490 status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd); 1491 if (status < 0) 1492 goto error; 1493 } while (!(cur_cmd == DRX_SCU_READY) && (time_is_after_jiffies(end))); 1494 if (cur_cmd != DRX_SCU_READY) { 1495 pr_err("SCU not ready\n"); 1496 status = -EIO; 1497 goto error2; 1498 } 1499 /* read results */ 1500 if ((result_len > 0) && (result != NULL)) { 1501 s16 err; 1502 int ii; 1503 1504 for (ii = result_len - 1; ii >= 0; ii -= 1) { 1505 status = read16(state, SCU_RAM_PARAM_0__A - ii, 1506 &result[ii]); 1507 if (status < 0) 1508 goto error; 1509 } 1510 1511 /* Check if an error was reported by SCU */ 1512 err = (s16)result[0]; 1513 if (err >= 0) 1514 goto error; 1515 1516 /* check for the known error codes */ 1517 switch (err) { 1518 case SCU_RESULT_UNKCMD: 1519 p = "SCU_RESULT_UNKCMD"; 1520 break; 1521 case SCU_RESULT_UNKSTD: 1522 p = "SCU_RESULT_UNKSTD"; 1523 break; 1524 case SCU_RESULT_SIZE: 1525 p = "SCU_RESULT_SIZE"; 1526 break; 1527 case SCU_RESULT_INVPAR: 1528 p = "SCU_RESULT_INVPAR"; 1529 break; 1530 default: /* Other negative values are errors */ 1531 sprintf(errname, "ERROR: %d\n", err); 1532 p = errname; 1533 } 1534 pr_err("%s while sending cmd 0x%04x with params:", p, cmd); 1535 print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt); 1536 status = -EINVAL; 1537 goto error2; 1538 } 1539 1540 error: 1541 if (status < 0) 1542 pr_err("Error %d on %s\n", status, __func__); 1543 error2: 1544 mutex_unlock(&state->mutex); 1545 return status; 1546 } 1547 set_iqm_af(struct drxk_state * state,bool active)1548 static int set_iqm_af(struct drxk_state *state, bool active) 1549 { 1550 u16 data = 0; 1551 int status; 1552 1553 dprintk(1, "\n"); 1554 1555 /* Configure IQM */ 1556 status = read16(state, IQM_AF_STDBY__A, &data); 1557 if (status < 0) 1558 goto error; 1559 1560 if (!active) { 1561 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY 1562 | IQM_AF_STDBY_STDBY_AMP_STANDBY 1563 | IQM_AF_STDBY_STDBY_PD_STANDBY 1564 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 1565 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY); 1566 } else { 1567 data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY) 1568 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY) 1569 & (~IQM_AF_STDBY_STDBY_PD_STANDBY) 1570 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY) 1571 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY) 1572 ); 1573 } 1574 status = write16(state, IQM_AF_STDBY__A, data); 1575 1576 error: 1577 if (status < 0) 1578 pr_err("Error %d on %s\n", status, __func__); 1579 return status; 1580 } 1581 ctrl_power_mode(struct drxk_state * state,enum drx_power_mode * mode)1582 static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode) 1583 { 1584 int status = 0; 1585 u16 sio_cc_pwd_mode = 0; 1586 1587 dprintk(1, "\n"); 1588 1589 /* Check arguments */ 1590 if (mode == NULL) 1591 return -EINVAL; 1592 1593 switch (*mode) { 1594 case DRX_POWER_UP: 1595 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE; 1596 break; 1597 case DRXK_POWER_DOWN_OFDM: 1598 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OFDM; 1599 break; 1600 case DRXK_POWER_DOWN_CORE: 1601 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK; 1602 break; 1603 case DRXK_POWER_DOWN_PLL: 1604 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL; 1605 break; 1606 case DRX_POWER_DOWN: 1607 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC; 1608 break; 1609 default: 1610 /* Unknow sleep mode */ 1611 return -EINVAL; 1612 } 1613 1614 /* If already in requested power mode, do nothing */ 1615 if (state->m_current_power_mode == *mode) 1616 return 0; 1617 1618 /* For next steps make sure to start from DRX_POWER_UP mode */ 1619 if (state->m_current_power_mode != DRX_POWER_UP) { 1620 status = power_up_device(state); 1621 if (status < 0) 1622 goto error; 1623 status = dvbt_enable_ofdm_token_ring(state, true); 1624 if (status < 0) 1625 goto error; 1626 } 1627 1628 if (*mode == DRX_POWER_UP) { 1629 /* Restore analog & pin configuration */ 1630 } else { 1631 /* Power down to requested mode */ 1632 /* Backup some register settings */ 1633 /* Set pins with possible pull-ups connected 1634 to them in input mode */ 1635 /* Analog power down */ 1636 /* ADC power down */ 1637 /* Power down device */ 1638 /* stop all comm_exec */ 1639 /* Stop and power down previous standard */ 1640 switch (state->m_operation_mode) { 1641 case OM_DVBT: 1642 status = mpegts_stop(state); 1643 if (status < 0) 1644 goto error; 1645 status = power_down_dvbt(state, false); 1646 if (status < 0) 1647 goto error; 1648 break; 1649 case OM_QAM_ITU_A: 1650 case OM_QAM_ITU_C: 1651 status = mpegts_stop(state); 1652 if (status < 0) 1653 goto error; 1654 status = power_down_qam(state); 1655 if (status < 0) 1656 goto error; 1657 break; 1658 default: 1659 break; 1660 } 1661 status = dvbt_enable_ofdm_token_ring(state, false); 1662 if (status < 0) 1663 goto error; 1664 status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode); 1665 if (status < 0) 1666 goto error; 1667 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); 1668 if (status < 0) 1669 goto error; 1670 1671 if (*mode != DRXK_POWER_DOWN_OFDM) { 1672 state->m_hi_cfg_ctrl |= 1673 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; 1674 status = hi_cfg_command(state); 1675 if (status < 0) 1676 goto error; 1677 } 1678 } 1679 state->m_current_power_mode = *mode; 1680 1681 error: 1682 if (status < 0) 1683 pr_err("Error %d on %s\n", status, __func__); 1684 1685 return status; 1686 } 1687 power_down_dvbt(struct drxk_state * state,bool set_power_mode)1688 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode) 1689 { 1690 enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM; 1691 u16 cmd_result = 0; 1692 u16 data = 0; 1693 int status; 1694 1695 dprintk(1, "\n"); 1696 1697 status = read16(state, SCU_COMM_EXEC__A, &data); 1698 if (status < 0) 1699 goto error; 1700 if (data == SCU_COMM_EXEC_ACTIVE) { 1701 /* Send OFDM stop command */ 1702 status = scu_command(state, 1703 SCU_RAM_COMMAND_STANDARD_OFDM 1704 | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 1705 0, NULL, 1, &cmd_result); 1706 if (status < 0) 1707 goto error; 1708 /* Send OFDM reset command */ 1709 status = scu_command(state, 1710 SCU_RAM_COMMAND_STANDARD_OFDM 1711 | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 1712 0, NULL, 1, &cmd_result); 1713 if (status < 0) 1714 goto error; 1715 } 1716 1717 /* Reset datapath for OFDM, processors first */ 1718 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); 1719 if (status < 0) 1720 goto error; 1721 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); 1722 if (status < 0) 1723 goto error; 1724 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); 1725 if (status < 0) 1726 goto error; 1727 1728 /* powerdown AFE */ 1729 status = set_iqm_af(state, false); 1730 if (status < 0) 1731 goto error; 1732 1733 /* powerdown to OFDM mode */ 1734 if (set_power_mode) { 1735 status = ctrl_power_mode(state, &power_mode); 1736 if (status < 0) 1737 goto error; 1738 } 1739 error: 1740 if (status < 0) 1741 pr_err("Error %d on %s\n", status, __func__); 1742 return status; 1743 } 1744 setoperation_mode(struct drxk_state * state,enum operation_mode o_mode)1745 static int setoperation_mode(struct drxk_state *state, 1746 enum operation_mode o_mode) 1747 { 1748 int status = 0; 1749 1750 dprintk(1, "\n"); 1751 /* 1752 Stop and power down previous standard 1753 TODO investigate total power down instead of partial 1754 power down depending on "previous" standard. 1755 */ 1756 1757 /* disable HW lock indicator */ 1758 status = write16(state, SCU_RAM_GPIO__A, 1759 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 1760 if (status < 0) 1761 goto error; 1762 1763 /* Device is already at the required mode */ 1764 if (state->m_operation_mode == o_mode) 1765 return 0; 1766 1767 switch (state->m_operation_mode) { 1768 /* OM_NONE was added for start up */ 1769 case OM_NONE: 1770 break; 1771 case OM_DVBT: 1772 status = mpegts_stop(state); 1773 if (status < 0) 1774 goto error; 1775 status = power_down_dvbt(state, true); 1776 if (status < 0) 1777 goto error; 1778 state->m_operation_mode = OM_NONE; 1779 break; 1780 case OM_QAM_ITU_A: /* fallthrough */ 1781 case OM_QAM_ITU_C: 1782 status = mpegts_stop(state); 1783 if (status < 0) 1784 goto error; 1785 status = power_down_qam(state); 1786 if (status < 0) 1787 goto error; 1788 state->m_operation_mode = OM_NONE; 1789 break; 1790 case OM_QAM_ITU_B: 1791 default: 1792 status = -EINVAL; 1793 goto error; 1794 } 1795 1796 /* 1797 Power up new standard 1798 */ 1799 switch (o_mode) { 1800 case OM_DVBT: 1801 dprintk(1, ": DVB-T\n"); 1802 state->m_operation_mode = o_mode; 1803 status = set_dvbt_standard(state, o_mode); 1804 if (status < 0) 1805 goto error; 1806 break; 1807 case OM_QAM_ITU_A: /* fallthrough */ 1808 case OM_QAM_ITU_C: 1809 dprintk(1, ": DVB-C Annex %c\n", 1810 (state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C'); 1811 state->m_operation_mode = o_mode; 1812 status = set_qam_standard(state, o_mode); 1813 if (status < 0) 1814 goto error; 1815 break; 1816 case OM_QAM_ITU_B: 1817 default: 1818 status = -EINVAL; 1819 } 1820 error: 1821 if (status < 0) 1822 pr_err("Error %d on %s\n", status, __func__); 1823 return status; 1824 } 1825 start(struct drxk_state * state,s32 offset_freq,s32 intermediate_frequency)1826 static int start(struct drxk_state *state, s32 offset_freq, 1827 s32 intermediate_frequency) 1828 { 1829 int status = -EINVAL; 1830 1831 u16 i_freqk_hz; 1832 s32 offsetk_hz = offset_freq / 1000; 1833 1834 dprintk(1, "\n"); 1835 if (state->m_drxk_state != DRXK_STOPPED && 1836 state->m_drxk_state != DRXK_DTV_STARTED) 1837 goto error; 1838 1839 state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON); 1840 1841 if (intermediate_frequency < 0) { 1842 state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect; 1843 intermediate_frequency = -intermediate_frequency; 1844 } 1845 1846 switch (state->m_operation_mode) { 1847 case OM_QAM_ITU_A: 1848 case OM_QAM_ITU_C: 1849 i_freqk_hz = (intermediate_frequency / 1000); 1850 status = set_qam(state, i_freqk_hz, offsetk_hz); 1851 if (status < 0) 1852 goto error; 1853 state->m_drxk_state = DRXK_DTV_STARTED; 1854 break; 1855 case OM_DVBT: 1856 i_freqk_hz = (intermediate_frequency / 1000); 1857 status = mpegts_stop(state); 1858 if (status < 0) 1859 goto error; 1860 status = set_dvbt(state, i_freqk_hz, offsetk_hz); 1861 if (status < 0) 1862 goto error; 1863 status = dvbt_start(state); 1864 if (status < 0) 1865 goto error; 1866 state->m_drxk_state = DRXK_DTV_STARTED; 1867 break; 1868 default: 1869 break; 1870 } 1871 error: 1872 if (status < 0) 1873 pr_err("Error %d on %s\n", status, __func__); 1874 return status; 1875 } 1876 shut_down(struct drxk_state * state)1877 static int shut_down(struct drxk_state *state) 1878 { 1879 dprintk(1, "\n"); 1880 1881 mpegts_stop(state); 1882 return 0; 1883 } 1884 get_lock_status(struct drxk_state * state,u32 * p_lock_status)1885 static int get_lock_status(struct drxk_state *state, u32 *p_lock_status) 1886 { 1887 int status = -EINVAL; 1888 1889 dprintk(1, "\n"); 1890 1891 if (p_lock_status == NULL) 1892 goto error; 1893 1894 *p_lock_status = NOT_LOCKED; 1895 1896 /* define the SCU command code */ 1897 switch (state->m_operation_mode) { 1898 case OM_QAM_ITU_A: 1899 case OM_QAM_ITU_B: 1900 case OM_QAM_ITU_C: 1901 status = get_qam_lock_status(state, p_lock_status); 1902 break; 1903 case OM_DVBT: 1904 status = get_dvbt_lock_status(state, p_lock_status); 1905 break; 1906 default: 1907 pr_debug("Unsupported operation mode %d in %s\n", 1908 state->m_operation_mode, __func__); 1909 return 0; 1910 } 1911 error: 1912 if (status < 0) 1913 pr_err("Error %d on %s\n", status, __func__); 1914 return status; 1915 } 1916 mpegts_start(struct drxk_state * state)1917 static int mpegts_start(struct drxk_state *state) 1918 { 1919 int status; 1920 1921 u16 fec_oc_snc_mode = 0; 1922 1923 /* Allow OC to sync again */ 1924 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode); 1925 if (status < 0) 1926 goto error; 1927 fec_oc_snc_mode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M; 1928 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode); 1929 if (status < 0) 1930 goto error; 1931 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1); 1932 error: 1933 if (status < 0) 1934 pr_err("Error %d on %s\n", status, __func__); 1935 return status; 1936 } 1937 mpegts_dto_init(struct drxk_state * state)1938 static int mpegts_dto_init(struct drxk_state *state) 1939 { 1940 int status; 1941 1942 dprintk(1, "\n"); 1943 1944 /* Rate integration settings */ 1945 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000); 1946 if (status < 0) 1947 goto error; 1948 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C); 1949 if (status < 0) 1950 goto error; 1951 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A); 1952 if (status < 0) 1953 goto error; 1954 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008); 1955 if (status < 0) 1956 goto error; 1957 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006); 1958 if (status < 0) 1959 goto error; 1960 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680); 1961 if (status < 0) 1962 goto error; 1963 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080); 1964 if (status < 0) 1965 goto error; 1966 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4); 1967 if (status < 0) 1968 goto error; 1969 1970 /* Additional configuration */ 1971 status = write16(state, FEC_OC_OCR_INVERT__A, 0); 1972 if (status < 0) 1973 goto error; 1974 status = write16(state, FEC_OC_SNC_LWM__A, 2); 1975 if (status < 0) 1976 goto error; 1977 status = write16(state, FEC_OC_SNC_HWM__A, 12); 1978 error: 1979 if (status < 0) 1980 pr_err("Error %d on %s\n", status, __func__); 1981 1982 return status; 1983 } 1984 mpegts_dto_setup(struct drxk_state * state,enum operation_mode o_mode)1985 static int mpegts_dto_setup(struct drxk_state *state, 1986 enum operation_mode o_mode) 1987 { 1988 int status; 1989 1990 u16 fec_oc_reg_mode = 0; /* FEC_OC_MODE register value */ 1991 u16 fec_oc_reg_ipr_mode = 0; /* FEC_OC_IPR_MODE register value */ 1992 u16 fec_oc_dto_mode = 0; /* FEC_OC_IPR_INVERT register value */ 1993 u16 fec_oc_fct_mode = 0; /* FEC_OC_IPR_INVERT register value */ 1994 u16 fec_oc_dto_period = 2; /* FEC_OC_IPR_INVERT register value */ 1995 u16 fec_oc_dto_burst_len = 188; /* FEC_OC_IPR_INVERT register value */ 1996 u32 fec_oc_rcn_ctl_rate = 0; /* FEC_OC_IPR_INVERT register value */ 1997 u16 fec_oc_tmd_mode = 0; 1998 u16 fec_oc_tmd_int_upd_rate = 0; 1999 u32 max_bit_rate = 0; 2000 bool static_clk = false; 2001 2002 dprintk(1, "\n"); 2003 2004 /* Check insertion of the Reed-Solomon parity bytes */ 2005 status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode); 2006 if (status < 0) 2007 goto error; 2008 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode); 2009 if (status < 0) 2010 goto error; 2011 fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M); 2012 fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); 2013 if (state->m_insert_rs_byte) { 2014 /* enable parity symbol forward */ 2015 fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M; 2016 /* MVAL disable during parity bytes */ 2017 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; 2018 /* TS burst length to 204 */ 2019 fec_oc_dto_burst_len = 204; 2020 } 2021 2022 /* Check serial or parallel output */ 2023 fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); 2024 if (!state->m_enable_parallel) { 2025 /* MPEG data output is serial -> set ipr_mode[0] */ 2026 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M; 2027 } 2028 2029 switch (o_mode) { 2030 case OM_DVBT: 2031 max_bit_rate = state->m_dvbt_bitrate; 2032 fec_oc_tmd_mode = 3; 2033 fec_oc_rcn_ctl_rate = 0xC00000; 2034 static_clk = state->m_dvbt_static_clk; 2035 break; 2036 case OM_QAM_ITU_A: /* fallthrough */ 2037 case OM_QAM_ITU_C: 2038 fec_oc_tmd_mode = 0x0004; 2039 fec_oc_rcn_ctl_rate = 0xD2B4EE; /* good for >63 Mb/s */ 2040 max_bit_rate = state->m_dvbc_bitrate; 2041 static_clk = state->m_dvbc_static_clk; 2042 break; 2043 default: 2044 status = -EINVAL; 2045 } /* switch (standard) */ 2046 if (status < 0) 2047 goto error; 2048 2049 /* Configure DTO's */ 2050 if (static_clk) { 2051 u32 bit_rate = 0; 2052 2053 /* Rational DTO for MCLK source (static MCLK rate), 2054 Dynamic DTO for optimal grouping 2055 (avoid intra-packet gaps), 2056 DTO offset enable to sync TS burst with MSTRT */ 2057 fec_oc_dto_mode = (FEC_OC_DTO_MODE_DYNAMIC__M | 2058 FEC_OC_DTO_MODE_OFFSET_ENABLE__M); 2059 fec_oc_fct_mode = (FEC_OC_FCT_MODE_RAT_ENA__M | 2060 FEC_OC_FCT_MODE_VIRT_ENA__M); 2061 2062 /* Check user defined bitrate */ 2063 bit_rate = max_bit_rate; 2064 if (bit_rate > 75900000UL) { /* max is 75.9 Mb/s */ 2065 bit_rate = 75900000UL; 2066 } 2067 /* Rational DTO period: 2068 dto_period = (Fsys / bitrate) - 2 2069 2070 result should be floored, 2071 to make sure >= requested bitrate 2072 */ 2073 fec_oc_dto_period = (u16) (((state->m_sys_clock_freq) 2074 * 1000) / bit_rate); 2075 if (fec_oc_dto_period <= 2) 2076 fec_oc_dto_period = 0; 2077 else 2078 fec_oc_dto_period -= 2; 2079 fec_oc_tmd_int_upd_rate = 8; 2080 } else { 2081 /* (commonAttr->static_clk == false) => dynamic mode */ 2082 fec_oc_dto_mode = FEC_OC_DTO_MODE_DYNAMIC__M; 2083 fec_oc_fct_mode = FEC_OC_FCT_MODE__PRE; 2084 fec_oc_tmd_int_upd_rate = 5; 2085 } 2086 2087 /* Write appropriate registers with requested configuration */ 2088 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len); 2089 if (status < 0) 2090 goto error; 2091 status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period); 2092 if (status < 0) 2093 goto error; 2094 status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode); 2095 if (status < 0) 2096 goto error; 2097 status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode); 2098 if (status < 0) 2099 goto error; 2100 status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode); 2101 if (status < 0) 2102 goto error; 2103 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode); 2104 if (status < 0) 2105 goto error; 2106 2107 /* Rate integration settings */ 2108 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate); 2109 if (status < 0) 2110 goto error; 2111 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, 2112 fec_oc_tmd_int_upd_rate); 2113 if (status < 0) 2114 goto error; 2115 status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode); 2116 error: 2117 if (status < 0) 2118 pr_err("Error %d on %s\n", status, __func__); 2119 return status; 2120 } 2121 mpegts_configure_polarity(struct drxk_state * state)2122 static int mpegts_configure_polarity(struct drxk_state *state) 2123 { 2124 u16 fec_oc_reg_ipr_invert = 0; 2125 2126 /* Data mask for the output data byte */ 2127 u16 invert_data_mask = 2128 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | 2129 FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | 2130 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | 2131 FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M; 2132 2133 dprintk(1, "\n"); 2134 2135 /* Control selective inversion of output bits */ 2136 fec_oc_reg_ipr_invert &= (~(invert_data_mask)); 2137 if (state->m_invert_data) 2138 fec_oc_reg_ipr_invert |= invert_data_mask; 2139 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M)); 2140 if (state->m_invert_err) 2141 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M; 2142 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); 2143 if (state->m_invert_str) 2144 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M; 2145 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); 2146 if (state->m_invert_val) 2147 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M; 2148 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); 2149 if (state->m_invert_clk) 2150 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M; 2151 2152 return write16(state, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert); 2153 } 2154 2155 #define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000 2156 set_agc_rf(struct drxk_state * state,struct s_cfg_agc * p_agc_cfg,bool is_dtv)2157 static int set_agc_rf(struct drxk_state *state, 2158 struct s_cfg_agc *p_agc_cfg, bool is_dtv) 2159 { 2160 int status = -EINVAL; 2161 u16 data = 0; 2162 struct s_cfg_agc *p_if_agc_settings; 2163 2164 dprintk(1, "\n"); 2165 2166 if (p_agc_cfg == NULL) 2167 goto error; 2168 2169 switch (p_agc_cfg->ctrl_mode) { 2170 case DRXK_AGC_CTRL_AUTO: 2171 /* Enable RF AGC DAC */ 2172 status = read16(state, IQM_AF_STDBY__A, &data); 2173 if (status < 0) 2174 goto error; 2175 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; 2176 status = write16(state, IQM_AF_STDBY__A, data); 2177 if (status < 0) 2178 goto error; 2179 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); 2180 if (status < 0) 2181 goto error; 2182 2183 /* Enable SCU RF AGC loop */ 2184 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; 2185 2186 /* Polarity */ 2187 if (state->m_rf_agc_pol) 2188 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2189 else 2190 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2191 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); 2192 if (status < 0) 2193 goto error; 2194 2195 /* Set speed (using complementary reduction value) */ 2196 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data); 2197 if (status < 0) 2198 goto error; 2199 2200 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; 2201 data |= (~(p_agc_cfg->speed << 2202 SCU_RAM_AGC_KI_RED_RAGC_RED__B) 2203 & SCU_RAM_AGC_KI_RED_RAGC_RED__M); 2204 2205 status = write16(state, SCU_RAM_AGC_KI_RED__A, data); 2206 if (status < 0) 2207 goto error; 2208 2209 if (is_dvbt(state)) 2210 p_if_agc_settings = &state->m_dvbt_if_agc_cfg; 2211 else if (is_qam(state)) 2212 p_if_agc_settings = &state->m_qam_if_agc_cfg; 2213 else 2214 p_if_agc_settings = &state->m_atv_if_agc_cfg; 2215 if (p_if_agc_settings == NULL) { 2216 status = -EINVAL; 2217 goto error; 2218 } 2219 2220 /* Set TOP, only if IF-AGC is in AUTO mode */ 2221 if (p_if_agc_settings->ctrl_mode == DRXK_AGC_CTRL_AUTO) { 2222 status = write16(state, 2223 SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 2224 p_agc_cfg->top); 2225 if (status < 0) 2226 goto error; 2227 } 2228 2229 /* Cut-Off current */ 2230 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 2231 p_agc_cfg->cut_off_current); 2232 if (status < 0) 2233 goto error; 2234 2235 /* Max. output level */ 2236 status = write16(state, SCU_RAM_AGC_RF_MAX__A, 2237 p_agc_cfg->max_output_level); 2238 if (status < 0) 2239 goto error; 2240 2241 break; 2242 2243 case DRXK_AGC_CTRL_USER: 2244 /* Enable RF AGC DAC */ 2245 status = read16(state, IQM_AF_STDBY__A, &data); 2246 if (status < 0) 2247 goto error; 2248 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; 2249 status = write16(state, IQM_AF_STDBY__A, data); 2250 if (status < 0) 2251 goto error; 2252 2253 /* Disable SCU RF AGC loop */ 2254 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); 2255 if (status < 0) 2256 goto error; 2257 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; 2258 if (state->m_rf_agc_pol) 2259 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2260 else 2261 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2262 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); 2263 if (status < 0) 2264 goto error; 2265 2266 /* SCU c.o.c. to 0, enabling full control range */ 2267 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0); 2268 if (status < 0) 2269 goto error; 2270 2271 /* Write value to output pin */ 2272 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 2273 p_agc_cfg->output_level); 2274 if (status < 0) 2275 goto error; 2276 break; 2277 2278 case DRXK_AGC_CTRL_OFF: 2279 /* Disable RF AGC DAC */ 2280 status = read16(state, IQM_AF_STDBY__A, &data); 2281 if (status < 0) 2282 goto error; 2283 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; 2284 status = write16(state, IQM_AF_STDBY__A, data); 2285 if (status < 0) 2286 goto error; 2287 2288 /* Disable SCU RF AGC loop */ 2289 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); 2290 if (status < 0) 2291 goto error; 2292 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; 2293 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); 2294 if (status < 0) 2295 goto error; 2296 break; 2297 2298 default: 2299 status = -EINVAL; 2300 2301 } 2302 error: 2303 if (status < 0) 2304 pr_err("Error %d on %s\n", status, __func__); 2305 return status; 2306 } 2307 2308 #define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000 2309 set_agc_if(struct drxk_state * state,struct s_cfg_agc * p_agc_cfg,bool is_dtv)2310 static int set_agc_if(struct drxk_state *state, 2311 struct s_cfg_agc *p_agc_cfg, bool is_dtv) 2312 { 2313 u16 data = 0; 2314 int status = 0; 2315 struct s_cfg_agc *p_rf_agc_settings; 2316 2317 dprintk(1, "\n"); 2318 2319 switch (p_agc_cfg->ctrl_mode) { 2320 case DRXK_AGC_CTRL_AUTO: 2321 2322 /* Enable IF AGC DAC */ 2323 status = read16(state, IQM_AF_STDBY__A, &data); 2324 if (status < 0) 2325 goto error; 2326 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; 2327 status = write16(state, IQM_AF_STDBY__A, data); 2328 if (status < 0) 2329 goto error; 2330 2331 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); 2332 if (status < 0) 2333 goto error; 2334 2335 /* Enable SCU IF AGC loop */ 2336 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; 2337 2338 /* Polarity */ 2339 if (state->m_if_agc_pol) 2340 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2341 else 2342 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2343 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); 2344 if (status < 0) 2345 goto error; 2346 2347 /* Set speed (using complementary reduction value) */ 2348 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data); 2349 if (status < 0) 2350 goto error; 2351 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; 2352 data |= (~(p_agc_cfg->speed << 2353 SCU_RAM_AGC_KI_RED_IAGC_RED__B) 2354 & SCU_RAM_AGC_KI_RED_IAGC_RED__M); 2355 2356 status = write16(state, SCU_RAM_AGC_KI_RED__A, data); 2357 if (status < 0) 2358 goto error; 2359 2360 if (is_qam(state)) 2361 p_rf_agc_settings = &state->m_qam_rf_agc_cfg; 2362 else 2363 p_rf_agc_settings = &state->m_atv_rf_agc_cfg; 2364 if (p_rf_agc_settings == NULL) 2365 return -1; 2366 /* Restore TOP */ 2367 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 2368 p_rf_agc_settings->top); 2369 if (status < 0) 2370 goto error; 2371 break; 2372 2373 case DRXK_AGC_CTRL_USER: 2374 2375 /* Enable IF AGC DAC */ 2376 status = read16(state, IQM_AF_STDBY__A, &data); 2377 if (status < 0) 2378 goto error; 2379 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; 2380 status = write16(state, IQM_AF_STDBY__A, data); 2381 if (status < 0) 2382 goto error; 2383 2384 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); 2385 if (status < 0) 2386 goto error; 2387 2388 /* Disable SCU IF AGC loop */ 2389 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; 2390 2391 /* Polarity */ 2392 if (state->m_if_agc_pol) 2393 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2394 else 2395 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2396 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); 2397 if (status < 0) 2398 goto error; 2399 2400 /* Write value to output pin */ 2401 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 2402 p_agc_cfg->output_level); 2403 if (status < 0) 2404 goto error; 2405 break; 2406 2407 case DRXK_AGC_CTRL_OFF: 2408 2409 /* Disable If AGC DAC */ 2410 status = read16(state, IQM_AF_STDBY__A, &data); 2411 if (status < 0) 2412 goto error; 2413 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; 2414 status = write16(state, IQM_AF_STDBY__A, data); 2415 if (status < 0) 2416 goto error; 2417 2418 /* Disable SCU IF AGC loop */ 2419 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); 2420 if (status < 0) 2421 goto error; 2422 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; 2423 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); 2424 if (status < 0) 2425 goto error; 2426 break; 2427 } /* switch (agcSettingsIf->ctrl_mode) */ 2428 2429 /* always set the top to support 2430 configurations without if-loop */ 2431 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top); 2432 error: 2433 if (status < 0) 2434 pr_err("Error %d on %s\n", status, __func__); 2435 return status; 2436 } 2437 get_qam_signal_to_noise(struct drxk_state * state,s32 * p_signal_to_noise)2438 static int get_qam_signal_to_noise(struct drxk_state *state, 2439 s32 *p_signal_to_noise) 2440 { 2441 int status = 0; 2442 u16 qam_sl_err_power = 0; /* accum. error between 2443 raw and sliced symbols */ 2444 u32 qam_sl_sig_power = 0; /* used for MER, depends of 2445 QAM modulation */ 2446 u32 qam_sl_mer = 0; /* QAM MER */ 2447 2448 dprintk(1, "\n"); 2449 2450 /* MER calculation */ 2451 2452 /* get the register value needed for MER */ 2453 status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power); 2454 if (status < 0) { 2455 pr_err("Error %d on %s\n", status, __func__); 2456 return -EINVAL; 2457 } 2458 2459 switch (state->props.modulation) { 2460 case QAM_16: 2461 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM16 << 2; 2462 break; 2463 case QAM_32: 2464 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM32 << 2; 2465 break; 2466 case QAM_64: 2467 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM64 << 2; 2468 break; 2469 case QAM_128: 2470 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM128 << 2; 2471 break; 2472 default: 2473 case QAM_256: 2474 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM256 << 2; 2475 break; 2476 } 2477 2478 if (qam_sl_err_power > 0) { 2479 qam_sl_mer = log10times100(qam_sl_sig_power) - 2480 log10times100((u32) qam_sl_err_power); 2481 } 2482 *p_signal_to_noise = qam_sl_mer; 2483 2484 return status; 2485 } 2486 get_dvbt_signal_to_noise(struct drxk_state * state,s32 * p_signal_to_noise)2487 static int get_dvbt_signal_to_noise(struct drxk_state *state, 2488 s32 *p_signal_to_noise) 2489 { 2490 int status; 2491 u16 reg_data = 0; 2492 u32 eq_reg_td_sqr_err_i = 0; 2493 u32 eq_reg_td_sqr_err_q = 0; 2494 u16 eq_reg_td_sqr_err_exp = 0; 2495 u16 eq_reg_td_tps_pwr_ofs = 0; 2496 u16 eq_reg_td_req_smb_cnt = 0; 2497 u32 tps_cnt = 0; 2498 u32 sqr_err_iq = 0; 2499 u32 a = 0; 2500 u32 b = 0; 2501 u32 c = 0; 2502 u32 i_mer = 0; 2503 u16 transmission_params = 0; 2504 2505 dprintk(1, "\n"); 2506 2507 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, 2508 &eq_reg_td_tps_pwr_ofs); 2509 if (status < 0) 2510 goto error; 2511 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, 2512 &eq_reg_td_req_smb_cnt); 2513 if (status < 0) 2514 goto error; 2515 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, 2516 &eq_reg_td_sqr_err_exp); 2517 if (status < 0) 2518 goto error; 2519 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, 2520 ®_data); 2521 if (status < 0) 2522 goto error; 2523 /* Extend SQR_ERR_I operational range */ 2524 eq_reg_td_sqr_err_i = (u32) reg_data; 2525 if ((eq_reg_td_sqr_err_exp > 11) && 2526 (eq_reg_td_sqr_err_i < 0x00000FFFUL)) { 2527 eq_reg_td_sqr_err_i += 0x00010000UL; 2528 } 2529 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®_data); 2530 if (status < 0) 2531 goto error; 2532 /* Extend SQR_ERR_Q operational range */ 2533 eq_reg_td_sqr_err_q = (u32) reg_data; 2534 if ((eq_reg_td_sqr_err_exp > 11) && 2535 (eq_reg_td_sqr_err_q < 0x00000FFFUL)) 2536 eq_reg_td_sqr_err_q += 0x00010000UL; 2537 2538 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, 2539 &transmission_params); 2540 if (status < 0) 2541 goto error; 2542 2543 /* Check input data for MER */ 2544 2545 /* MER calculation (in 0.1 dB) without math.h */ 2546 if ((eq_reg_td_tps_pwr_ofs == 0) || (eq_reg_td_req_smb_cnt == 0)) 2547 i_mer = 0; 2548 else if ((eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) == 0) { 2549 /* No error at all, this must be the HW reset value 2550 * Apparently no first measurement yet 2551 * Set MER to 0.0 */ 2552 i_mer = 0; 2553 } else { 2554 sqr_err_iq = (eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) << 2555 eq_reg_td_sqr_err_exp; 2556 if ((transmission_params & 2557 OFDM_SC_RA_RAM_OP_PARAM_MODE__M) 2558 == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K) 2559 tps_cnt = 17; 2560 else 2561 tps_cnt = 68; 2562 2563 /* IMER = 100 * log10 (x) 2564 where x = (eq_reg_td_tps_pwr_ofs^2 * 2565 eq_reg_td_req_smb_cnt * tps_cnt)/sqr_err_iq 2566 2567 => IMER = a + b -c 2568 where a = 100 * log10 (eq_reg_td_tps_pwr_ofs^2) 2569 b = 100 * log10 (eq_reg_td_req_smb_cnt * tps_cnt) 2570 c = 100 * log10 (sqr_err_iq) 2571 */ 2572 2573 /* log(x) x = 9bits * 9bits->18 bits */ 2574 a = log10times100(eq_reg_td_tps_pwr_ofs * 2575 eq_reg_td_tps_pwr_ofs); 2576 /* log(x) x = 16bits * 7bits->23 bits */ 2577 b = log10times100(eq_reg_td_req_smb_cnt * tps_cnt); 2578 /* log(x) x = (16bits + 16bits) << 15 ->32 bits */ 2579 c = log10times100(sqr_err_iq); 2580 2581 i_mer = a + b - c; 2582 } 2583 *p_signal_to_noise = i_mer; 2584 2585 error: 2586 if (status < 0) 2587 pr_err("Error %d on %s\n", status, __func__); 2588 return status; 2589 } 2590 get_signal_to_noise(struct drxk_state * state,s32 * p_signal_to_noise)2591 static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise) 2592 { 2593 dprintk(1, "\n"); 2594 2595 *p_signal_to_noise = 0; 2596 switch (state->m_operation_mode) { 2597 case OM_DVBT: 2598 return get_dvbt_signal_to_noise(state, p_signal_to_noise); 2599 case OM_QAM_ITU_A: 2600 case OM_QAM_ITU_C: 2601 return get_qam_signal_to_noise(state, p_signal_to_noise); 2602 default: 2603 break; 2604 } 2605 return 0; 2606 } 2607 2608 #if 0 2609 static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality) 2610 { 2611 /* SNR Values for quasi errorfree reception rom Nordig 2.2 */ 2612 int status = 0; 2613 2614 dprintk(1, "\n"); 2615 2616 static s32 QE_SN[] = { 2617 51, /* QPSK 1/2 */ 2618 69, /* QPSK 2/3 */ 2619 79, /* QPSK 3/4 */ 2620 89, /* QPSK 5/6 */ 2621 97, /* QPSK 7/8 */ 2622 108, /* 16-QAM 1/2 */ 2623 131, /* 16-QAM 2/3 */ 2624 146, /* 16-QAM 3/4 */ 2625 156, /* 16-QAM 5/6 */ 2626 160, /* 16-QAM 7/8 */ 2627 165, /* 64-QAM 1/2 */ 2628 187, /* 64-QAM 2/3 */ 2629 202, /* 64-QAM 3/4 */ 2630 216, /* 64-QAM 5/6 */ 2631 225, /* 64-QAM 7/8 */ 2632 }; 2633 2634 *p_quality = 0; 2635 2636 do { 2637 s32 signal_to_noise = 0; 2638 u16 constellation = 0; 2639 u16 code_rate = 0; 2640 u32 signal_to_noise_rel; 2641 u32 ber_quality; 2642 2643 status = get_dvbt_signal_to_noise(state, &signal_to_noise); 2644 if (status < 0) 2645 break; 2646 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, 2647 &constellation); 2648 if (status < 0) 2649 break; 2650 constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M; 2651 2652 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, 2653 &code_rate); 2654 if (status < 0) 2655 break; 2656 code_rate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M; 2657 2658 if (constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM || 2659 code_rate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8) 2660 break; 2661 signal_to_noise_rel = signal_to_noise - 2662 QE_SN[constellation * 5 + code_rate]; 2663 ber_quality = 100; 2664 2665 if (signal_to_noise_rel < -70) 2666 *p_quality = 0; 2667 else if (signal_to_noise_rel < 30) 2668 *p_quality = ((signal_to_noise_rel + 70) * 2669 ber_quality) / 100; 2670 else 2671 *p_quality = ber_quality; 2672 } while (0); 2673 return 0; 2674 }; 2675 2676 static int get_dvbc_quality(struct drxk_state *state, s32 *p_quality) 2677 { 2678 int status = 0; 2679 *p_quality = 0; 2680 2681 dprintk(1, "\n"); 2682 2683 do { 2684 u32 signal_to_noise = 0; 2685 u32 ber_quality = 100; 2686 u32 signal_to_noise_rel = 0; 2687 2688 status = get_qam_signal_to_noise(state, &signal_to_noise); 2689 if (status < 0) 2690 break; 2691 2692 switch (state->props.modulation) { 2693 case QAM_16: 2694 signal_to_noise_rel = signal_to_noise - 200; 2695 break; 2696 case QAM_32: 2697 signal_to_noise_rel = signal_to_noise - 230; 2698 break; /* Not in NorDig */ 2699 case QAM_64: 2700 signal_to_noise_rel = signal_to_noise - 260; 2701 break; 2702 case QAM_128: 2703 signal_to_noise_rel = signal_to_noise - 290; 2704 break; 2705 default: 2706 case QAM_256: 2707 signal_to_noise_rel = signal_to_noise - 320; 2708 break; 2709 } 2710 2711 if (signal_to_noise_rel < -70) 2712 *p_quality = 0; 2713 else if (signal_to_noise_rel < 30) 2714 *p_quality = ((signal_to_noise_rel + 70) * 2715 ber_quality) / 100; 2716 else 2717 *p_quality = ber_quality; 2718 } while (0); 2719 2720 return status; 2721 } 2722 2723 static int get_quality(struct drxk_state *state, s32 *p_quality) 2724 { 2725 dprintk(1, "\n"); 2726 2727 switch (state->m_operation_mode) { 2728 case OM_DVBT: 2729 return get_dvbt_quality(state, p_quality); 2730 case OM_QAM_ITU_A: 2731 return get_dvbc_quality(state, p_quality); 2732 default: 2733 break; 2734 } 2735 2736 return 0; 2737 } 2738 #endif 2739 2740 /* Free data ram in SIO HI */ 2741 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040 2742 #define SIO_HI_RA_RAM_USR_END__A 0x420060 2743 2744 #define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A) 2745 #define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7) 2746 #define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 2747 #define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 2748 2749 #define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F) 2750 #define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F) 2751 #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF) 2752 ConfigureI2CBridge(struct drxk_state * state,bool b_enable_bridge)2753 static int ConfigureI2CBridge(struct drxk_state *state, bool b_enable_bridge) 2754 { 2755 int status = -EINVAL; 2756 2757 dprintk(1, "\n"); 2758 2759 if (state->m_drxk_state == DRXK_UNINITIALIZED) 2760 return 0; 2761 if (state->m_drxk_state == DRXK_POWERED_DOWN) 2762 goto error; 2763 2764 if (state->no_i2c_bridge) 2765 return 0; 2766 2767 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, 2768 SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); 2769 if (status < 0) 2770 goto error; 2771 if (b_enable_bridge) { 2772 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, 2773 SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED); 2774 if (status < 0) 2775 goto error; 2776 } else { 2777 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, 2778 SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN); 2779 if (status < 0) 2780 goto error; 2781 } 2782 2783 status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL); 2784 2785 error: 2786 if (status < 0) 2787 pr_err("Error %d on %s\n", status, __func__); 2788 return status; 2789 } 2790 set_pre_saw(struct drxk_state * state,struct s_cfg_pre_saw * p_pre_saw_cfg)2791 static int set_pre_saw(struct drxk_state *state, 2792 struct s_cfg_pre_saw *p_pre_saw_cfg) 2793 { 2794 int status = -EINVAL; 2795 2796 dprintk(1, "\n"); 2797 2798 if ((p_pre_saw_cfg == NULL) 2799 || (p_pre_saw_cfg->reference > IQM_AF_PDREF__M)) 2800 goto error; 2801 2802 status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference); 2803 error: 2804 if (status < 0) 2805 pr_err("Error %d on %s\n", status, __func__); 2806 return status; 2807 } 2808 bl_direct_cmd(struct drxk_state * state,u32 target_addr,u16 rom_offset,u16 nr_of_elements,u32 time_out)2809 static int bl_direct_cmd(struct drxk_state *state, u32 target_addr, 2810 u16 rom_offset, u16 nr_of_elements, u32 time_out) 2811 { 2812 u16 bl_status = 0; 2813 u16 offset = (u16) ((target_addr >> 0) & 0x00FFFF); 2814 u16 blockbank = (u16) ((target_addr >> 16) & 0x000FFF); 2815 int status; 2816 unsigned long end; 2817 2818 dprintk(1, "\n"); 2819 2820 mutex_lock(&state->mutex); 2821 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT); 2822 if (status < 0) 2823 goto error; 2824 status = write16(state, SIO_BL_TGT_HDR__A, blockbank); 2825 if (status < 0) 2826 goto error; 2827 status = write16(state, SIO_BL_TGT_ADDR__A, offset); 2828 if (status < 0) 2829 goto error; 2830 status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset); 2831 if (status < 0) 2832 goto error; 2833 status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements); 2834 if (status < 0) 2835 goto error; 2836 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); 2837 if (status < 0) 2838 goto error; 2839 2840 end = jiffies + msecs_to_jiffies(time_out); 2841 do { 2842 status = read16(state, SIO_BL_STATUS__A, &bl_status); 2843 if (status < 0) 2844 goto error; 2845 } while ((bl_status == 0x1) && time_is_after_jiffies(end)); 2846 if (bl_status == 0x1) { 2847 pr_err("SIO not ready\n"); 2848 status = -EINVAL; 2849 goto error2; 2850 } 2851 error: 2852 if (status < 0) 2853 pr_err("Error %d on %s\n", status, __func__); 2854 error2: 2855 mutex_unlock(&state->mutex); 2856 return status; 2857 2858 } 2859 adc_sync_measurement(struct drxk_state * state,u16 * count)2860 static int adc_sync_measurement(struct drxk_state *state, u16 *count) 2861 { 2862 u16 data = 0; 2863 int status; 2864 2865 dprintk(1, "\n"); 2866 2867 /* start measurement */ 2868 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE); 2869 if (status < 0) 2870 goto error; 2871 status = write16(state, IQM_AF_START_LOCK__A, 1); 2872 if (status < 0) 2873 goto error; 2874 2875 *count = 0; 2876 status = read16(state, IQM_AF_PHASE0__A, &data); 2877 if (status < 0) 2878 goto error; 2879 if (data == 127) 2880 *count = *count + 1; 2881 status = read16(state, IQM_AF_PHASE1__A, &data); 2882 if (status < 0) 2883 goto error; 2884 if (data == 127) 2885 *count = *count + 1; 2886 status = read16(state, IQM_AF_PHASE2__A, &data); 2887 if (status < 0) 2888 goto error; 2889 if (data == 127) 2890 *count = *count + 1; 2891 2892 error: 2893 if (status < 0) 2894 pr_err("Error %d on %s\n", status, __func__); 2895 return status; 2896 } 2897 adc_synchronization(struct drxk_state * state)2898 static int adc_synchronization(struct drxk_state *state) 2899 { 2900 u16 count = 0; 2901 int status; 2902 2903 dprintk(1, "\n"); 2904 2905 status = adc_sync_measurement(state, &count); 2906 if (status < 0) 2907 goto error; 2908 2909 if (count == 1) { 2910 /* Try sampling on a different edge */ 2911 u16 clk_neg = 0; 2912 2913 status = read16(state, IQM_AF_CLKNEG__A, &clk_neg); 2914 if (status < 0) 2915 goto error; 2916 if ((clk_neg & IQM_AF_CLKNEG_CLKNEGDATA__M) == 2917 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) { 2918 clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); 2919 clk_neg |= 2920 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG; 2921 } else { 2922 clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); 2923 clk_neg |= 2924 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS; 2925 } 2926 status = write16(state, IQM_AF_CLKNEG__A, clk_neg); 2927 if (status < 0) 2928 goto error; 2929 status = adc_sync_measurement(state, &count); 2930 if (status < 0) 2931 goto error; 2932 } 2933 2934 if (count < 2) 2935 status = -EINVAL; 2936 error: 2937 if (status < 0) 2938 pr_err("Error %d on %s\n", status, __func__); 2939 return status; 2940 } 2941 set_frequency_shifter(struct drxk_state * state,u16 intermediate_freqk_hz,s32 tuner_freq_offset,bool is_dtv)2942 static int set_frequency_shifter(struct drxk_state *state, 2943 u16 intermediate_freqk_hz, 2944 s32 tuner_freq_offset, bool is_dtv) 2945 { 2946 bool select_pos_image = false; 2947 u32 rf_freq_residual = tuner_freq_offset; 2948 u32 fm_frequency_shift = 0; 2949 bool tuner_mirror = !state->m_b_mirror_freq_spect; 2950 u32 adc_freq; 2951 bool adc_flip; 2952 int status; 2953 u32 if_freq_actual; 2954 u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3); 2955 u32 frequency_shift; 2956 bool image_to_select; 2957 2958 dprintk(1, "\n"); 2959 2960 /* 2961 Program frequency shifter 2962 No need to account for mirroring on RF 2963 */ 2964 if (is_dtv) { 2965 if ((state->m_operation_mode == OM_QAM_ITU_A) || 2966 (state->m_operation_mode == OM_QAM_ITU_C) || 2967 (state->m_operation_mode == OM_DVBT)) 2968 select_pos_image = true; 2969 else 2970 select_pos_image = false; 2971 } 2972 if (tuner_mirror) 2973 /* tuner doesn't mirror */ 2974 if_freq_actual = intermediate_freqk_hz + 2975 rf_freq_residual + fm_frequency_shift; 2976 else 2977 /* tuner mirrors */ 2978 if_freq_actual = intermediate_freqk_hz - 2979 rf_freq_residual - fm_frequency_shift; 2980 if (if_freq_actual > sampling_frequency / 2) { 2981 /* adc mirrors */ 2982 adc_freq = sampling_frequency - if_freq_actual; 2983 adc_flip = true; 2984 } else { 2985 /* adc doesn't mirror */ 2986 adc_freq = if_freq_actual; 2987 adc_flip = false; 2988 } 2989 2990 frequency_shift = adc_freq; 2991 image_to_select = state->m_rfmirror ^ tuner_mirror ^ 2992 adc_flip ^ select_pos_image; 2993 state->m_iqm_fs_rate_ofs = 2994 Frac28a((frequency_shift), sampling_frequency); 2995 2996 if (image_to_select) 2997 state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1; 2998 2999 /* Program frequency shifter with tuner offset compensation */ 3000 /* frequency_shift += tuner_freq_offset; TODO */ 3001 status = write32(state, IQM_FS_RATE_OFS_LO__A, 3002 state->m_iqm_fs_rate_ofs); 3003 if (status < 0) 3004 pr_err("Error %d on %s\n", status, __func__); 3005 return status; 3006 } 3007 init_agc(struct drxk_state * state,bool is_dtv)3008 static int init_agc(struct drxk_state *state, bool is_dtv) 3009 { 3010 u16 ingain_tgt = 0; 3011 u16 ingain_tgt_min = 0; 3012 u16 ingain_tgt_max = 0; 3013 u16 clp_cyclen = 0; 3014 u16 clp_sum_min = 0; 3015 u16 clp_dir_to = 0; 3016 u16 sns_sum_min = 0; 3017 u16 sns_sum_max = 0; 3018 u16 clp_sum_max = 0; 3019 u16 sns_dir_to = 0; 3020 u16 ki_innergain_min = 0; 3021 u16 if_iaccu_hi_tgt = 0; 3022 u16 if_iaccu_hi_tgt_min = 0; 3023 u16 if_iaccu_hi_tgt_max = 0; 3024 u16 data = 0; 3025 u16 fast_clp_ctrl_delay = 0; 3026 u16 clp_ctrl_mode = 0; 3027 int status = 0; 3028 3029 dprintk(1, "\n"); 3030 3031 /* Common settings */ 3032 sns_sum_max = 1023; 3033 if_iaccu_hi_tgt_min = 2047; 3034 clp_cyclen = 500; 3035 clp_sum_max = 1023; 3036 3037 /* AGCInit() not available for DVBT; init done in microcode */ 3038 if (!is_qam(state)) { 3039 pr_err("%s: mode %d is not DVB-C\n", 3040 __func__, state->m_operation_mode); 3041 return -EINVAL; 3042 } 3043 3044 /* FIXME: Analog TV AGC require different settings */ 3045 3046 /* Standard specific settings */ 3047 clp_sum_min = 8; 3048 clp_dir_to = (u16) -9; 3049 clp_ctrl_mode = 0; 3050 sns_sum_min = 8; 3051 sns_dir_to = (u16) -9; 3052 ki_innergain_min = (u16) -1030; 3053 if_iaccu_hi_tgt_max = 0x2380; 3054 if_iaccu_hi_tgt = 0x2380; 3055 ingain_tgt_min = 0x0511; 3056 ingain_tgt = 0x0511; 3057 ingain_tgt_max = 5119; 3058 fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay; 3059 3060 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 3061 fast_clp_ctrl_delay); 3062 if (status < 0) 3063 goto error; 3064 3065 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode); 3066 if (status < 0) 3067 goto error; 3068 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt); 3069 if (status < 0) 3070 goto error; 3071 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min); 3072 if (status < 0) 3073 goto error; 3074 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max); 3075 if (status < 0) 3076 goto error; 3077 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, 3078 if_iaccu_hi_tgt_min); 3079 if (status < 0) 3080 goto error; 3081 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 3082 if_iaccu_hi_tgt_max); 3083 if (status < 0) 3084 goto error; 3085 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0); 3086 if (status < 0) 3087 goto error; 3088 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0); 3089 if (status < 0) 3090 goto error; 3091 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0); 3092 if (status < 0) 3093 goto error; 3094 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0); 3095 if (status < 0) 3096 goto error; 3097 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max); 3098 if (status < 0) 3099 goto error; 3100 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max); 3101 if (status < 0) 3102 goto error; 3103 3104 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, 3105 ki_innergain_min); 3106 if (status < 0) 3107 goto error; 3108 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 3109 if_iaccu_hi_tgt); 3110 if (status < 0) 3111 goto error; 3112 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen); 3113 if (status < 0) 3114 goto error; 3115 3116 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023); 3117 if (status < 0) 3118 goto error; 3119 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023); 3120 if (status < 0) 3121 goto error; 3122 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50); 3123 if (status < 0) 3124 goto error; 3125 3126 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20); 3127 if (status < 0) 3128 goto error; 3129 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min); 3130 if (status < 0) 3131 goto error; 3132 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min); 3133 if (status < 0) 3134 goto error; 3135 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to); 3136 if (status < 0) 3137 goto error; 3138 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to); 3139 if (status < 0) 3140 goto error; 3141 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff); 3142 if (status < 0) 3143 goto error; 3144 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0); 3145 if (status < 0) 3146 goto error; 3147 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117); 3148 if (status < 0) 3149 goto error; 3150 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657); 3151 if (status < 0) 3152 goto error; 3153 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0); 3154 if (status < 0) 3155 goto error; 3156 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0); 3157 if (status < 0) 3158 goto error; 3159 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0); 3160 if (status < 0) 3161 goto error; 3162 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1); 3163 if (status < 0) 3164 goto error; 3165 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0); 3166 if (status < 0) 3167 goto error; 3168 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0); 3169 if (status < 0) 3170 goto error; 3171 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0); 3172 if (status < 0) 3173 goto error; 3174 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1); 3175 if (status < 0) 3176 goto error; 3177 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500); 3178 if (status < 0) 3179 goto error; 3180 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500); 3181 if (status < 0) 3182 goto error; 3183 3184 /* Initialize inner-loop KI gain factors */ 3185 status = read16(state, SCU_RAM_AGC_KI__A, &data); 3186 if (status < 0) 3187 goto error; 3188 3189 data = 0x0657; 3190 data &= ~SCU_RAM_AGC_KI_RF__M; 3191 data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B); 3192 data &= ~SCU_RAM_AGC_KI_IF__M; 3193 data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B); 3194 3195 status = write16(state, SCU_RAM_AGC_KI__A, data); 3196 error: 3197 if (status < 0) 3198 pr_err("Error %d on %s\n", status, __func__); 3199 return status; 3200 } 3201 dvbtqam_get_acc_pkt_err(struct drxk_state * state,u16 * packet_err)3202 static int dvbtqam_get_acc_pkt_err(struct drxk_state *state, u16 *packet_err) 3203 { 3204 int status; 3205 3206 dprintk(1, "\n"); 3207 if (packet_err == NULL) 3208 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); 3209 else 3210 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 3211 packet_err); 3212 if (status < 0) 3213 pr_err("Error %d on %s\n", status, __func__); 3214 return status; 3215 } 3216 dvbt_sc_command(struct drxk_state * state,u16 cmd,u16 subcmd,u16 param0,u16 param1,u16 param2,u16 param3,u16 param4)3217 static int dvbt_sc_command(struct drxk_state *state, 3218 u16 cmd, u16 subcmd, 3219 u16 param0, u16 param1, u16 param2, 3220 u16 param3, u16 param4) 3221 { 3222 u16 cur_cmd = 0; 3223 u16 err_code = 0; 3224 u16 retry_cnt = 0; 3225 u16 sc_exec = 0; 3226 int status; 3227 3228 dprintk(1, "\n"); 3229 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec); 3230 if (sc_exec != 1) { 3231 /* SC is not running */ 3232 status = -EINVAL; 3233 } 3234 if (status < 0) 3235 goto error; 3236 3237 /* Wait until sc is ready to receive command */ 3238 retry_cnt = 0; 3239 do { 3240 usleep_range(1000, 2000); 3241 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd); 3242 retry_cnt++; 3243 } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES)); 3244 if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0)) 3245 goto error; 3246 3247 /* Write sub-command */ 3248 switch (cmd) { 3249 /* All commands using sub-cmd */ 3250 case OFDM_SC_RA_RAM_CMD_PROC_START: 3251 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: 3252 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: 3253 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd); 3254 if (status < 0) 3255 goto error; 3256 break; 3257 default: 3258 /* Do nothing */ 3259 break; 3260 } 3261 3262 /* Write needed parameters and the command */ 3263 status = 0; 3264 switch (cmd) { 3265 /* All commands using 5 parameters */ 3266 /* All commands using 4 parameters */ 3267 /* All commands using 3 parameters */ 3268 /* All commands using 2 parameters */ 3269 case OFDM_SC_RA_RAM_CMD_PROC_START: 3270 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: 3271 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: 3272 status |= write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1); 3273 /* fall through - All commands using 1 parameters */ 3274 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: 3275 case OFDM_SC_RA_RAM_CMD_USER_IO: 3276 status |= write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0); 3277 /* fall through - All commands using 0 parameters */ 3278 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: 3279 case OFDM_SC_RA_RAM_CMD_NULL: 3280 /* Write command */ 3281 status |= write16(state, OFDM_SC_RA_RAM_CMD__A, cmd); 3282 break; 3283 default: 3284 /* Unknown command */ 3285 status = -EINVAL; 3286 } 3287 if (status < 0) 3288 goto error; 3289 3290 /* Wait until sc is ready processing command */ 3291 retry_cnt = 0; 3292 do { 3293 usleep_range(1000, 2000); 3294 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd); 3295 retry_cnt++; 3296 } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES)); 3297 if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0)) 3298 goto error; 3299 3300 /* Check for illegal cmd */ 3301 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code); 3302 if (err_code == 0xFFFF) { 3303 /* illegal command */ 3304 status = -EINVAL; 3305 } 3306 if (status < 0) 3307 goto error; 3308 3309 /* Retrieve results parameters from SC */ 3310 switch (cmd) { 3311 /* All commands yielding 5 results */ 3312 /* All commands yielding 4 results */ 3313 /* All commands yielding 3 results */ 3314 /* All commands yielding 2 results */ 3315 /* All commands yielding 1 result */ 3316 case OFDM_SC_RA_RAM_CMD_USER_IO: 3317 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: 3318 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0)); 3319 /* All commands yielding 0 results */ 3320 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: 3321 case OFDM_SC_RA_RAM_CMD_SET_TIMER: 3322 case OFDM_SC_RA_RAM_CMD_PROC_START: 3323 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: 3324 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: 3325 case OFDM_SC_RA_RAM_CMD_NULL: 3326 break; 3327 default: 3328 /* Unknown command */ 3329 status = -EINVAL; 3330 break; 3331 } /* switch (cmd->cmd) */ 3332 error: 3333 if (status < 0) 3334 pr_err("Error %d on %s\n", status, __func__); 3335 return status; 3336 } 3337 power_up_dvbt(struct drxk_state * state)3338 static int power_up_dvbt(struct drxk_state *state) 3339 { 3340 enum drx_power_mode power_mode = DRX_POWER_UP; 3341 int status; 3342 3343 dprintk(1, "\n"); 3344 status = ctrl_power_mode(state, &power_mode); 3345 if (status < 0) 3346 pr_err("Error %d on %s\n", status, __func__); 3347 return status; 3348 } 3349 dvbt_ctrl_set_inc_enable(struct drxk_state * state,bool * enabled)3350 static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled) 3351 { 3352 int status; 3353 3354 dprintk(1, "\n"); 3355 if (*enabled) 3356 status = write16(state, IQM_CF_BYPASSDET__A, 0); 3357 else 3358 status = write16(state, IQM_CF_BYPASSDET__A, 1); 3359 if (status < 0) 3360 pr_err("Error %d on %s\n", status, __func__); 3361 return status; 3362 } 3363 3364 #define DEFAULT_FR_THRES_8K 4000 dvbt_ctrl_set_fr_enable(struct drxk_state * state,bool * enabled)3365 static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled) 3366 { 3367 3368 int status; 3369 3370 dprintk(1, "\n"); 3371 if (*enabled) { 3372 /* write mask to 1 */ 3373 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 3374 DEFAULT_FR_THRES_8K); 3375 } else { 3376 /* write mask to 0 */ 3377 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0); 3378 } 3379 if (status < 0) 3380 pr_err("Error %d on %s\n", status, __func__); 3381 3382 return status; 3383 } 3384 dvbt_ctrl_set_echo_threshold(struct drxk_state * state,struct drxk_cfg_dvbt_echo_thres_t * echo_thres)3385 static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state, 3386 struct drxk_cfg_dvbt_echo_thres_t *echo_thres) 3387 { 3388 u16 data = 0; 3389 int status; 3390 3391 dprintk(1, "\n"); 3392 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data); 3393 if (status < 0) 3394 goto error; 3395 3396 switch (echo_thres->fft_mode) { 3397 case DRX_FFTMODE_2K: 3398 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M; 3399 data |= ((echo_thres->threshold << 3400 OFDM_SC_RA_RAM_ECHO_THRES_2K__B) 3401 & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M)); 3402 break; 3403 case DRX_FFTMODE_8K: 3404 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M; 3405 data |= ((echo_thres->threshold << 3406 OFDM_SC_RA_RAM_ECHO_THRES_8K__B) 3407 & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M)); 3408 break; 3409 default: 3410 return -EINVAL; 3411 } 3412 3413 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data); 3414 error: 3415 if (status < 0) 3416 pr_err("Error %d on %s\n", status, __func__); 3417 return status; 3418 } 3419 dvbt_ctrl_set_sqi_speed(struct drxk_state * state,enum drxk_cfg_dvbt_sqi_speed * speed)3420 static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state, 3421 enum drxk_cfg_dvbt_sqi_speed *speed) 3422 { 3423 int status = -EINVAL; 3424 3425 dprintk(1, "\n"); 3426 3427 switch (*speed) { 3428 case DRXK_DVBT_SQI_SPEED_FAST: 3429 case DRXK_DVBT_SQI_SPEED_MEDIUM: 3430 case DRXK_DVBT_SQI_SPEED_SLOW: 3431 break; 3432 default: 3433 goto error; 3434 } 3435 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A, 3436 (u16) *speed); 3437 error: 3438 if (status < 0) 3439 pr_err("Error %d on %s\n", status, __func__); 3440 return status; 3441 } 3442 3443 /*============================================================================*/ 3444 3445 /* 3446 * \brief Activate DVBT specific presets 3447 * \param demod instance of demodulator. 3448 * \return DRXStatus_t. 3449 * 3450 * Called in DVBTSetStandard 3451 * 3452 */ dvbt_activate_presets(struct drxk_state * state)3453 static int dvbt_activate_presets(struct drxk_state *state) 3454 { 3455 int status; 3456 bool setincenable = false; 3457 bool setfrenable = true; 3458 3459 struct drxk_cfg_dvbt_echo_thres_t echo_thres2k = { 0, DRX_FFTMODE_2K }; 3460 struct drxk_cfg_dvbt_echo_thres_t echo_thres8k = { 0, DRX_FFTMODE_8K }; 3461 3462 dprintk(1, "\n"); 3463 status = dvbt_ctrl_set_inc_enable(state, &setincenable); 3464 if (status < 0) 3465 goto error; 3466 status = dvbt_ctrl_set_fr_enable(state, &setfrenable); 3467 if (status < 0) 3468 goto error; 3469 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k); 3470 if (status < 0) 3471 goto error; 3472 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k); 3473 if (status < 0) 3474 goto error; 3475 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, 3476 state->m_dvbt_if_agc_cfg.ingain_tgt_max); 3477 error: 3478 if (status < 0) 3479 pr_err("Error %d on %s\n", status, __func__); 3480 return status; 3481 } 3482 3483 /*============================================================================*/ 3484 3485 /* 3486 * \brief Initialize channelswitch-independent settings for DVBT. 3487 * \param demod instance of demodulator. 3488 * \return DRXStatus_t. 3489 * 3490 * For ROM code channel filter taps are loaded from the bootloader. For microcode 3491 * the DVB-T taps from the drxk_filters.h are used. 3492 */ set_dvbt_standard(struct drxk_state * state,enum operation_mode o_mode)3493 static int set_dvbt_standard(struct drxk_state *state, 3494 enum operation_mode o_mode) 3495 { 3496 u16 cmd_result = 0; 3497 u16 data = 0; 3498 int status; 3499 3500 dprintk(1, "\n"); 3501 3502 power_up_dvbt(state); 3503 /* added antenna switch */ 3504 switch_antenna_to_dvbt(state); 3505 /* send OFDM reset command */ 3506 status = scu_command(state, 3507 SCU_RAM_COMMAND_STANDARD_OFDM 3508 | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 3509 0, NULL, 1, &cmd_result); 3510 if (status < 0) 3511 goto error; 3512 3513 /* send OFDM setenv command */ 3514 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM 3515 | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 3516 0, NULL, 1, &cmd_result); 3517 if (status < 0) 3518 goto error; 3519 3520 /* reset datapath for OFDM, processors first */ 3521 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); 3522 if (status < 0) 3523 goto error; 3524 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); 3525 if (status < 0) 3526 goto error; 3527 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); 3528 if (status < 0) 3529 goto error; 3530 3531 /* IQM setup */ 3532 /* synchronize on ofdstate->m_festart */ 3533 status = write16(state, IQM_AF_UPD_SEL__A, 1); 3534 if (status < 0) 3535 goto error; 3536 /* window size for clipping ADC detection */ 3537 status = write16(state, IQM_AF_CLP_LEN__A, 0); 3538 if (status < 0) 3539 goto error; 3540 /* window size for for sense pre-SAW detection */ 3541 status = write16(state, IQM_AF_SNS_LEN__A, 0); 3542 if (status < 0) 3543 goto error; 3544 /* sense threshold for sense pre-SAW detection */ 3545 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); 3546 if (status < 0) 3547 goto error; 3548 status = set_iqm_af(state, true); 3549 if (status < 0) 3550 goto error; 3551 3552 status = write16(state, IQM_AF_AGC_RF__A, 0); 3553 if (status < 0) 3554 goto error; 3555 3556 /* Impulse noise cruncher setup */ 3557 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */ 3558 if (status < 0) 3559 goto error; 3560 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */ 3561 if (status < 0) 3562 goto error; 3563 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */ 3564 if (status < 0) 3565 goto error; 3566 3567 status = write16(state, IQM_RC_STRETCH__A, 16); 3568 if (status < 0) 3569 goto error; 3570 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */ 3571 if (status < 0) 3572 goto error; 3573 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */ 3574 if (status < 0) 3575 goto error; 3576 status = write16(state, IQM_CF_SCALE__A, 1600); 3577 if (status < 0) 3578 goto error; 3579 status = write16(state, IQM_CF_SCALE_SH__A, 0); 3580 if (status < 0) 3581 goto error; 3582 3583 /* virtual clipping threshold for clipping ADC detection */ 3584 status = write16(state, IQM_AF_CLP_TH__A, 448); 3585 if (status < 0) 3586 goto error; 3587 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */ 3588 if (status < 0) 3589 goto error; 3590 3591 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, 3592 DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); 3593 if (status < 0) 3594 goto error; 3595 3596 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */ 3597 if (status < 0) 3598 goto error; 3599 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2); 3600 if (status < 0) 3601 goto error; 3602 /* enable power measurement interrupt */ 3603 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1); 3604 if (status < 0) 3605 goto error; 3606 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE); 3607 if (status < 0) 3608 goto error; 3609 3610 /* IQM will not be reset from here, sync ADC and update/init AGC */ 3611 status = adc_synchronization(state); 3612 if (status < 0) 3613 goto error; 3614 status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg); 3615 if (status < 0) 3616 goto error; 3617 3618 /* Halt SCU to enable safe non-atomic accesses */ 3619 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); 3620 if (status < 0) 3621 goto error; 3622 3623 status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true); 3624 if (status < 0) 3625 goto error; 3626 status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true); 3627 if (status < 0) 3628 goto error; 3629 3630 /* Set Noise Estimation notch width and enable DC fix */ 3631 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data); 3632 if (status < 0) 3633 goto error; 3634 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M; 3635 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data); 3636 if (status < 0) 3637 goto error; 3638 3639 /* Activate SCU to enable SCU commands */ 3640 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 3641 if (status < 0) 3642 goto error; 3643 3644 if (!state->m_drxk_a3_rom_code) { 3645 /* AGCInit() is not done for DVBT, so set agcfast_clip_ctrl_delay */ 3646 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 3647 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay); 3648 if (status < 0) 3649 goto error; 3650 } 3651 3652 /* OFDM_SC setup */ 3653 #ifdef COMPILE_FOR_NONRT 3654 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1); 3655 if (status < 0) 3656 goto error; 3657 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2); 3658 if (status < 0) 3659 goto error; 3660 #endif 3661 3662 /* FEC setup */ 3663 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */ 3664 if (status < 0) 3665 goto error; 3666 3667 3668 #ifdef COMPILE_FOR_NONRT 3669 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400); 3670 if (status < 0) 3671 goto error; 3672 #else 3673 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000); 3674 if (status < 0) 3675 goto error; 3676 #endif 3677 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001); 3678 if (status < 0) 3679 goto error; 3680 3681 /* Setup MPEG bus */ 3682 status = mpegts_dto_setup(state, OM_DVBT); 3683 if (status < 0) 3684 goto error; 3685 /* Set DVBT Presets */ 3686 status = dvbt_activate_presets(state); 3687 if (status < 0) 3688 goto error; 3689 3690 error: 3691 if (status < 0) 3692 pr_err("Error %d on %s\n", status, __func__); 3693 return status; 3694 } 3695 3696 /*============================================================================*/ 3697 /* 3698 * \brief start dvbt demodulating for channel. 3699 * \param demod instance of demodulator. 3700 * \return DRXStatus_t. 3701 */ dvbt_start(struct drxk_state * state)3702 static int dvbt_start(struct drxk_state *state) 3703 { 3704 u16 param1; 3705 int status; 3706 /* drxk_ofdm_sc_cmd_t scCmd; */ 3707 3708 dprintk(1, "\n"); 3709 /* start correct processes to get in lock */ 3710 /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */ 3711 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN; 3712 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, 3713 OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 3714 0, 0, 0); 3715 if (status < 0) 3716 goto error; 3717 /* start FEC OC */ 3718 status = mpegts_start(state); 3719 if (status < 0) 3720 goto error; 3721 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); 3722 if (status < 0) 3723 goto error; 3724 error: 3725 if (status < 0) 3726 pr_err("Error %d on %s\n", status, __func__); 3727 return status; 3728 } 3729 3730 3731 /*============================================================================*/ 3732 3733 /* 3734 * \brief Set up dvbt demodulator for channel. 3735 * \param demod instance of demodulator. 3736 * \return DRXStatus_t. 3737 * // original DVBTSetChannel() 3738 */ set_dvbt(struct drxk_state * state,u16 intermediate_freqk_hz,s32 tuner_freq_offset)3739 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, 3740 s32 tuner_freq_offset) 3741 { 3742 u16 cmd_result = 0; 3743 u16 transmission_params = 0; 3744 u16 operation_mode = 0; 3745 u32 iqm_rc_rate_ofs = 0; 3746 u32 bandwidth = 0; 3747 u16 param1; 3748 int status; 3749 3750 dprintk(1, "IF =%d, TFO = %d\n", 3751 intermediate_freqk_hz, tuner_freq_offset); 3752 3753 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM 3754 | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 3755 0, NULL, 1, &cmd_result); 3756 if (status < 0) 3757 goto error; 3758 3759 /* Halt SCU to enable safe non-atomic accesses */ 3760 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); 3761 if (status < 0) 3762 goto error; 3763 3764 /* Stop processors */ 3765 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); 3766 if (status < 0) 3767 goto error; 3768 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); 3769 if (status < 0) 3770 goto error; 3771 3772 /* Mandatory fix, always stop CP, required to set spl offset back to 3773 hardware default (is set to 0 by ucode during pilot detection */ 3774 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP); 3775 if (status < 0) 3776 goto error; 3777 3778 /*== Write channel settings to device ================================*/ 3779 3780 /* mode */ 3781 switch (state->props.transmission_mode) { 3782 case TRANSMISSION_MODE_AUTO: 3783 default: 3784 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M; 3785 /* fall through - try first guess DRX_FFTMODE_8K */ 3786 case TRANSMISSION_MODE_8K: 3787 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K; 3788 break; 3789 case TRANSMISSION_MODE_2K: 3790 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K; 3791 break; 3792 } 3793 3794 /* guard */ 3795 switch (state->props.guard_interval) { 3796 default: 3797 case GUARD_INTERVAL_AUTO: 3798 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M; 3799 /* fall through - try first guess DRX_GUARD_1DIV4 */ 3800 case GUARD_INTERVAL_1_4: 3801 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4; 3802 break; 3803 case GUARD_INTERVAL_1_32: 3804 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32; 3805 break; 3806 case GUARD_INTERVAL_1_16: 3807 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16; 3808 break; 3809 case GUARD_INTERVAL_1_8: 3810 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8; 3811 break; 3812 } 3813 3814 /* hierarchy */ 3815 switch (state->props.hierarchy) { 3816 case HIERARCHY_AUTO: 3817 case HIERARCHY_NONE: 3818 default: 3819 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M; 3820 /* try first guess SC_RA_RAM_OP_PARAM_HIER_NO */ 3821 /* transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */ 3822 /* fall through */ 3823 case HIERARCHY_1: 3824 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1; 3825 break; 3826 case HIERARCHY_2: 3827 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2; 3828 break; 3829 case HIERARCHY_4: 3830 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4; 3831 break; 3832 } 3833 3834 3835 /* modulation */ 3836 switch (state->props.modulation) { 3837 case QAM_AUTO: 3838 default: 3839 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M; 3840 /* fall through - try first guess DRX_CONSTELLATION_QAM64 */ 3841 case QAM_64: 3842 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64; 3843 break; 3844 case QPSK: 3845 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK; 3846 break; 3847 case QAM_16: 3848 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16; 3849 break; 3850 } 3851 #if 0 3852 /* No hierarchical channels support in BDA */ 3853 /* Priority (only for hierarchical channels) */ 3854 switch (channel->priority) { 3855 case DRX_PRIORITY_LOW: 3856 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO; 3857 WR16(dev_addr, OFDM_EC_SB_PRIOR__A, 3858 OFDM_EC_SB_PRIOR_LO); 3859 break; 3860 case DRX_PRIORITY_HIGH: 3861 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; 3862 WR16(dev_addr, OFDM_EC_SB_PRIOR__A, 3863 OFDM_EC_SB_PRIOR_HI)); 3864 break; 3865 case DRX_PRIORITY_UNKNOWN: /* fall through */ 3866 default: 3867 status = -EINVAL; 3868 goto error; 3869 } 3870 #else 3871 /* Set Priorty high */ 3872 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; 3873 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI); 3874 if (status < 0) 3875 goto error; 3876 #endif 3877 3878 /* coderate */ 3879 switch (state->props.code_rate_HP) { 3880 case FEC_AUTO: 3881 default: 3882 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M; 3883 /* fall through - try first guess DRX_CODERATE_2DIV3 */ 3884 case FEC_2_3: 3885 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3; 3886 break; 3887 case FEC_1_2: 3888 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2; 3889 break; 3890 case FEC_3_4: 3891 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4; 3892 break; 3893 case FEC_5_6: 3894 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6; 3895 break; 3896 case FEC_7_8: 3897 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8; 3898 break; 3899 } 3900 3901 /* 3902 * SAW filter selection: normaly not necesarry, but if wanted 3903 * the application can select a SAW filter via the driver by 3904 * using UIOs 3905 */ 3906 3907 /* First determine real bandwidth (Hz) */ 3908 /* Also set delay for impulse noise cruncher */ 3909 /* 3910 * Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is 3911 * changed by SC for fix for some 8K,1/8 guard but is restored by 3912 * InitEC and ResetEC functions 3913 */ 3914 switch (state->props.bandwidth_hz) { 3915 case 0: 3916 state->props.bandwidth_hz = 8000000; 3917 /* fall through */ 3918 case 8000000: 3919 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ; 3920 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3921 3052); 3922 if (status < 0) 3923 goto error; 3924 /* cochannel protection for PAL 8 MHz */ 3925 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 3926 7); 3927 if (status < 0) 3928 goto error; 3929 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 3930 7); 3931 if (status < 0) 3932 goto error; 3933 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 3934 7); 3935 if (status < 0) 3936 goto error; 3937 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 3938 1); 3939 if (status < 0) 3940 goto error; 3941 break; 3942 case 7000000: 3943 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ; 3944 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3945 3491); 3946 if (status < 0) 3947 goto error; 3948 /* cochannel protection for PAL 7 MHz */ 3949 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 3950 8); 3951 if (status < 0) 3952 goto error; 3953 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 3954 8); 3955 if (status < 0) 3956 goto error; 3957 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 3958 4); 3959 if (status < 0) 3960 goto error; 3961 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 3962 1); 3963 if (status < 0) 3964 goto error; 3965 break; 3966 case 6000000: 3967 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ; 3968 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3969 4073); 3970 if (status < 0) 3971 goto error; 3972 /* cochannel protection for NTSC 6 MHz */ 3973 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 3974 19); 3975 if (status < 0) 3976 goto error; 3977 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 3978 19); 3979 if (status < 0) 3980 goto error; 3981 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 3982 14); 3983 if (status < 0) 3984 goto error; 3985 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 3986 1); 3987 if (status < 0) 3988 goto error; 3989 break; 3990 default: 3991 status = -EINVAL; 3992 goto error; 3993 } 3994 3995 if (iqm_rc_rate_ofs == 0) { 3996 /* Now compute IQM_RC_RATE_OFS 3997 (((SysFreq/BandWidth)/2)/2) -1) * 2^23) 3998 => 3999 ((SysFreq / BandWidth) * (2^21)) - (2^23) 4000 */ 4001 /* (SysFreq / BandWidth) * (2^28) */ 4002 /* 4003 * assert (MAX(sysClk)/MIN(bandwidth) < 16) 4004 * => assert(MAX(sysClk) < 16*MIN(bandwidth)) 4005 * => assert(109714272 > 48000000) = true 4006 * so Frac 28 can be used 4007 */ 4008 iqm_rc_rate_ofs = Frac28a((u32) 4009 ((state->m_sys_clock_freq * 4010 1000) / 3), bandwidth); 4011 /* (SysFreq / BandWidth) * (2^21), rounding before truncating */ 4012 if ((iqm_rc_rate_ofs & 0x7fL) >= 0x40) 4013 iqm_rc_rate_ofs += 0x80L; 4014 iqm_rc_rate_ofs = iqm_rc_rate_ofs >> 7; 4015 /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */ 4016 iqm_rc_rate_ofs = iqm_rc_rate_ofs - (1 << 23); 4017 } 4018 4019 iqm_rc_rate_ofs &= 4020 ((((u32) IQM_RC_RATE_OFS_HI__M) << 4021 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M); 4022 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs); 4023 if (status < 0) 4024 goto error; 4025 4026 /* Bandwidth setting done */ 4027 4028 #if 0 4029 status = dvbt_set_frequency_shift(demod, channel, tuner_offset); 4030 if (status < 0) 4031 goto error; 4032 #endif 4033 status = set_frequency_shifter(state, intermediate_freqk_hz, 4034 tuner_freq_offset, true); 4035 if (status < 0) 4036 goto error; 4037 4038 /*== start SC, write channel settings to SC ==========================*/ 4039 4040 /* Activate SCU to enable SCU commands */ 4041 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 4042 if (status < 0) 4043 goto error; 4044 4045 /* Enable SC after setting all other parameters */ 4046 status = write16(state, OFDM_SC_COMM_STATE__A, 0); 4047 if (status < 0) 4048 goto error; 4049 status = write16(state, OFDM_SC_COMM_EXEC__A, 1); 4050 if (status < 0) 4051 goto error; 4052 4053 4054 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM 4055 | SCU_RAM_COMMAND_CMD_DEMOD_START, 4056 0, NULL, 1, &cmd_result); 4057 if (status < 0) 4058 goto error; 4059 4060 /* Write SC parameter registers, set all AUTO flags in operation mode */ 4061 param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M | 4062 OFDM_SC_RA_RAM_OP_AUTO_GUARD__M | 4063 OFDM_SC_RA_RAM_OP_AUTO_CONST__M | 4064 OFDM_SC_RA_RAM_OP_AUTO_HIER__M | 4065 OFDM_SC_RA_RAM_OP_AUTO_RATE__M); 4066 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM, 4067 0, transmission_params, param1, 0, 0, 0); 4068 if (status < 0) 4069 goto error; 4070 4071 if (!state->m_drxk_a3_rom_code) 4072 status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed); 4073 error: 4074 if (status < 0) 4075 pr_err("Error %d on %s\n", status, __func__); 4076 4077 return status; 4078 } 4079 4080 4081 /*============================================================================*/ 4082 4083 /* 4084 * \brief Retrieve lock status . 4085 * \param demod Pointer to demodulator instance. 4086 * \param lockStat Pointer to lock status structure. 4087 * \return DRXStatus_t. 4088 * 4089 */ get_dvbt_lock_status(struct drxk_state * state,u32 * p_lock_status)4090 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status) 4091 { 4092 int status; 4093 const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M | 4094 OFDM_SC_RA_RAM_LOCK_FEC__M); 4095 const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M); 4096 const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M; 4097 4098 u16 sc_ra_ram_lock = 0; 4099 u16 sc_comm_exec = 0; 4100 4101 dprintk(1, "\n"); 4102 4103 *p_lock_status = NOT_LOCKED; 4104 /* driver 0.9.0 */ 4105 /* Check if SC is running */ 4106 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec); 4107 if (status < 0) 4108 goto end; 4109 if (sc_comm_exec == OFDM_SC_COMM_EXEC_STOP) 4110 goto end; 4111 4112 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock); 4113 if (status < 0) 4114 goto end; 4115 4116 if ((sc_ra_ram_lock & mpeg_lock_mask) == mpeg_lock_mask) 4117 *p_lock_status = MPEG_LOCK; 4118 else if ((sc_ra_ram_lock & fec_lock_mask) == fec_lock_mask) 4119 *p_lock_status = FEC_LOCK; 4120 else if ((sc_ra_ram_lock & demod_lock_mask) == demod_lock_mask) 4121 *p_lock_status = DEMOD_LOCK; 4122 else if (sc_ra_ram_lock & OFDM_SC_RA_RAM_LOCK_NODVBT__M) 4123 *p_lock_status = NEVER_LOCK; 4124 end: 4125 if (status < 0) 4126 pr_err("Error %d on %s\n", status, __func__); 4127 4128 return status; 4129 } 4130 power_up_qam(struct drxk_state * state)4131 static int power_up_qam(struct drxk_state *state) 4132 { 4133 enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM; 4134 int status; 4135 4136 dprintk(1, "\n"); 4137 status = ctrl_power_mode(state, &power_mode); 4138 if (status < 0) 4139 pr_err("Error %d on %s\n", status, __func__); 4140 4141 return status; 4142 } 4143 4144 4145 /* Power Down QAM */ power_down_qam(struct drxk_state * state)4146 static int power_down_qam(struct drxk_state *state) 4147 { 4148 u16 data = 0; 4149 u16 cmd_result; 4150 int status = 0; 4151 4152 dprintk(1, "\n"); 4153 status = read16(state, SCU_COMM_EXEC__A, &data); 4154 if (status < 0) 4155 goto error; 4156 if (data == SCU_COMM_EXEC_ACTIVE) { 4157 /* 4158 STOP demodulator 4159 QAM and HW blocks 4160 */ 4161 /* stop all comstate->m_exec */ 4162 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); 4163 if (status < 0) 4164 goto error; 4165 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM 4166 | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 4167 0, NULL, 1, &cmd_result); 4168 if (status < 0) 4169 goto error; 4170 } 4171 /* powerdown AFE */ 4172 status = set_iqm_af(state, false); 4173 4174 error: 4175 if (status < 0) 4176 pr_err("Error %d on %s\n", status, __func__); 4177 4178 return status; 4179 } 4180 4181 /*============================================================================*/ 4182 4183 /* 4184 * \brief Setup of the QAM Measurement intervals for signal quality 4185 * \param demod instance of demod. 4186 * \param modulation current modulation. 4187 * \return DRXStatus_t. 4188 * 4189 * NOTE: 4190 * Take into account that for certain settings the errorcounters can overflow. 4191 * The implementation does not check this. 4192 * 4193 */ set_qam_measurement(struct drxk_state * state,enum e_drxk_constellation modulation,u32 symbol_rate)4194 static int set_qam_measurement(struct drxk_state *state, 4195 enum e_drxk_constellation modulation, 4196 u32 symbol_rate) 4197 { 4198 u32 fec_bits_desired = 0; /* BER accounting period */ 4199 u32 fec_rs_period_total = 0; /* Total period */ 4200 u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */ 4201 u16 fec_rs_period = 0; /* Value for corresponding I2C register */ 4202 int status = 0; 4203 4204 dprintk(1, "\n"); 4205 4206 fec_rs_prescale = 1; 4207 /* fec_bits_desired = symbol_rate [kHz] * 4208 FrameLenght [ms] * 4209 (modulation + 1) * 4210 SyncLoss (== 1) * 4211 ViterbiLoss (==1) 4212 */ 4213 switch (modulation) { 4214 case DRX_CONSTELLATION_QAM16: 4215 fec_bits_desired = 4 * symbol_rate; 4216 break; 4217 case DRX_CONSTELLATION_QAM32: 4218 fec_bits_desired = 5 * symbol_rate; 4219 break; 4220 case DRX_CONSTELLATION_QAM64: 4221 fec_bits_desired = 6 * symbol_rate; 4222 break; 4223 case DRX_CONSTELLATION_QAM128: 4224 fec_bits_desired = 7 * symbol_rate; 4225 break; 4226 case DRX_CONSTELLATION_QAM256: 4227 fec_bits_desired = 8 * symbol_rate; 4228 break; 4229 default: 4230 status = -EINVAL; 4231 } 4232 if (status < 0) 4233 goto error; 4234 4235 fec_bits_desired /= 1000; /* symbol_rate [Hz] -> symbol_rate [kHz] */ 4236 fec_bits_desired *= 500; /* meas. period [ms] */ 4237 4238 /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */ 4239 /* fec_rs_period_total = fec_bits_desired / 1632 */ 4240 fec_rs_period_total = (fec_bits_desired / 1632UL) + 1; /* roughly ceil */ 4241 4242 /* fec_rs_period_total = fec_rs_prescale * fec_rs_period */ 4243 fec_rs_prescale = 1 + (u16) (fec_rs_period_total >> 16); 4244 if (fec_rs_prescale == 0) { 4245 /* Divide by zero (though impossible) */ 4246 status = -EINVAL; 4247 if (status < 0) 4248 goto error; 4249 } 4250 fec_rs_period = 4251 ((u16) fec_rs_period_total + 4252 (fec_rs_prescale >> 1)) / fec_rs_prescale; 4253 4254 /* write corresponding registers */ 4255 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period); 4256 if (status < 0) 4257 goto error; 4258 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 4259 fec_rs_prescale); 4260 if (status < 0) 4261 goto error; 4262 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period); 4263 error: 4264 if (status < 0) 4265 pr_err("Error %d on %s\n", status, __func__); 4266 return status; 4267 } 4268 set_qam16(struct drxk_state * state)4269 static int set_qam16(struct drxk_state *state) 4270 { 4271 int status = 0; 4272 4273 dprintk(1, "\n"); 4274 /* QAM Equalizer Setup */ 4275 /* Equalizer */ 4276 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517); 4277 if (status < 0) 4278 goto error; 4279 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517); 4280 if (status < 0) 4281 goto error; 4282 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517); 4283 if (status < 0) 4284 goto error; 4285 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517); 4286 if (status < 0) 4287 goto error; 4288 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517); 4289 if (status < 0) 4290 goto error; 4291 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517); 4292 if (status < 0) 4293 goto error; 4294 /* Decision Feedback Equalizer */ 4295 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2); 4296 if (status < 0) 4297 goto error; 4298 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2); 4299 if (status < 0) 4300 goto error; 4301 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2); 4302 if (status < 0) 4303 goto error; 4304 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2); 4305 if (status < 0) 4306 goto error; 4307 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2); 4308 if (status < 0) 4309 goto error; 4310 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); 4311 if (status < 0) 4312 goto error; 4313 4314 status = write16(state, QAM_SY_SYNC_HWM__A, 5); 4315 if (status < 0) 4316 goto error; 4317 status = write16(state, QAM_SY_SYNC_AWM__A, 4); 4318 if (status < 0) 4319 goto error; 4320 status = write16(state, QAM_SY_SYNC_LWM__A, 3); 4321 if (status < 0) 4322 goto error; 4323 4324 /* QAM Slicer Settings */ 4325 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, 4326 DRXK_QAM_SL_SIG_POWER_QAM16); 4327 if (status < 0) 4328 goto error; 4329 4330 /* QAM Loop Controller Coeficients */ 4331 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); 4332 if (status < 0) 4333 goto error; 4334 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); 4335 if (status < 0) 4336 goto error; 4337 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); 4338 if (status < 0) 4339 goto error; 4340 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); 4341 if (status < 0) 4342 goto error; 4343 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); 4344 if (status < 0) 4345 goto error; 4346 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); 4347 if (status < 0) 4348 goto error; 4349 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); 4350 if (status < 0) 4351 goto error; 4352 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); 4353 if (status < 0) 4354 goto error; 4355 4356 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); 4357 if (status < 0) 4358 goto error; 4359 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); 4360 if (status < 0) 4361 goto error; 4362 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); 4363 if (status < 0) 4364 goto error; 4365 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); 4366 if (status < 0) 4367 goto error; 4368 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); 4369 if (status < 0) 4370 goto error; 4371 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); 4372 if (status < 0) 4373 goto error; 4374 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); 4375 if (status < 0) 4376 goto error; 4377 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); 4378 if (status < 0) 4379 goto error; 4380 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32); 4381 if (status < 0) 4382 goto error; 4383 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); 4384 if (status < 0) 4385 goto error; 4386 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); 4387 if (status < 0) 4388 goto error; 4389 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); 4390 if (status < 0) 4391 goto error; 4392 4393 4394 /* QAM State Machine (FSM) Thresholds */ 4395 4396 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140); 4397 if (status < 0) 4398 goto error; 4399 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50); 4400 if (status < 0) 4401 goto error; 4402 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95); 4403 if (status < 0) 4404 goto error; 4405 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120); 4406 if (status < 0) 4407 goto error; 4408 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230); 4409 if (status < 0) 4410 goto error; 4411 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105); 4412 if (status < 0) 4413 goto error; 4414 4415 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); 4416 if (status < 0) 4417 goto error; 4418 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); 4419 if (status < 0) 4420 goto error; 4421 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24); 4422 if (status < 0) 4423 goto error; 4424 4425 4426 /* QAM FSM Tracking Parameters */ 4427 4428 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16); 4429 if (status < 0) 4430 goto error; 4431 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220); 4432 if (status < 0) 4433 goto error; 4434 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25); 4435 if (status < 0) 4436 goto error; 4437 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6); 4438 if (status < 0) 4439 goto error; 4440 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24); 4441 if (status < 0) 4442 goto error; 4443 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65); 4444 if (status < 0) 4445 goto error; 4446 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127); 4447 if (status < 0) 4448 goto error; 4449 4450 error: 4451 if (status < 0) 4452 pr_err("Error %d on %s\n", status, __func__); 4453 return status; 4454 } 4455 4456 /*============================================================================*/ 4457 4458 /* 4459 * \brief QAM32 specific setup 4460 * \param demod instance of demod. 4461 * \return DRXStatus_t. 4462 */ set_qam32(struct drxk_state * state)4463 static int set_qam32(struct drxk_state *state) 4464 { 4465 int status = 0; 4466 4467 dprintk(1, "\n"); 4468 4469 /* QAM Equalizer Setup */ 4470 /* Equalizer */ 4471 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707); 4472 if (status < 0) 4473 goto error; 4474 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707); 4475 if (status < 0) 4476 goto error; 4477 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707); 4478 if (status < 0) 4479 goto error; 4480 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707); 4481 if (status < 0) 4482 goto error; 4483 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707); 4484 if (status < 0) 4485 goto error; 4486 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707); 4487 if (status < 0) 4488 goto error; 4489 4490 /* Decision Feedback Equalizer */ 4491 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3); 4492 if (status < 0) 4493 goto error; 4494 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3); 4495 if (status < 0) 4496 goto error; 4497 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3); 4498 if (status < 0) 4499 goto error; 4500 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3); 4501 if (status < 0) 4502 goto error; 4503 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3); 4504 if (status < 0) 4505 goto error; 4506 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); 4507 if (status < 0) 4508 goto error; 4509 4510 status = write16(state, QAM_SY_SYNC_HWM__A, 6); 4511 if (status < 0) 4512 goto error; 4513 status = write16(state, QAM_SY_SYNC_AWM__A, 5); 4514 if (status < 0) 4515 goto error; 4516 status = write16(state, QAM_SY_SYNC_LWM__A, 3); 4517 if (status < 0) 4518 goto error; 4519 4520 /* QAM Slicer Settings */ 4521 4522 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, 4523 DRXK_QAM_SL_SIG_POWER_QAM32); 4524 if (status < 0) 4525 goto error; 4526 4527 4528 /* QAM Loop Controller Coeficients */ 4529 4530 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); 4531 if (status < 0) 4532 goto error; 4533 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); 4534 if (status < 0) 4535 goto error; 4536 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); 4537 if (status < 0) 4538 goto error; 4539 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); 4540 if (status < 0) 4541 goto error; 4542 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); 4543 if (status < 0) 4544 goto error; 4545 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); 4546 if (status < 0) 4547 goto error; 4548 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); 4549 if (status < 0) 4550 goto error; 4551 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); 4552 if (status < 0) 4553 goto error; 4554 4555 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); 4556 if (status < 0) 4557 goto error; 4558 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); 4559 if (status < 0) 4560 goto error; 4561 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); 4562 if (status < 0) 4563 goto error; 4564 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); 4565 if (status < 0) 4566 goto error; 4567 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); 4568 if (status < 0) 4569 goto error; 4570 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); 4571 if (status < 0) 4572 goto error; 4573 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); 4574 if (status < 0) 4575 goto error; 4576 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); 4577 if (status < 0) 4578 goto error; 4579 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16); 4580 if (status < 0) 4581 goto error; 4582 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); 4583 if (status < 0) 4584 goto error; 4585 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); 4586 if (status < 0) 4587 goto error; 4588 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0); 4589 if (status < 0) 4590 goto error; 4591 4592 4593 /* QAM State Machine (FSM) Thresholds */ 4594 4595 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90); 4596 if (status < 0) 4597 goto error; 4598 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50); 4599 if (status < 0) 4600 goto error; 4601 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); 4602 if (status < 0) 4603 goto error; 4604 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); 4605 if (status < 0) 4606 goto error; 4607 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170); 4608 if (status < 0) 4609 goto error; 4610 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100); 4611 if (status < 0) 4612 goto error; 4613 4614 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); 4615 if (status < 0) 4616 goto error; 4617 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); 4618 if (status < 0) 4619 goto error; 4620 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10); 4621 if (status < 0) 4622 goto error; 4623 4624 4625 /* QAM FSM Tracking Parameters */ 4626 4627 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); 4628 if (status < 0) 4629 goto error; 4630 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140); 4631 if (status < 0) 4632 goto error; 4633 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8); 4634 if (status < 0) 4635 goto error; 4636 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16); 4637 if (status < 0) 4638 goto error; 4639 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26); 4640 if (status < 0) 4641 goto error; 4642 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56); 4643 if (status < 0) 4644 goto error; 4645 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86); 4646 error: 4647 if (status < 0) 4648 pr_err("Error %d on %s\n", status, __func__); 4649 return status; 4650 } 4651 4652 /*============================================================================*/ 4653 4654 /* 4655 * \brief QAM64 specific setup 4656 * \param demod instance of demod. 4657 * \return DRXStatus_t. 4658 */ set_qam64(struct drxk_state * state)4659 static int set_qam64(struct drxk_state *state) 4660 { 4661 int status = 0; 4662 4663 dprintk(1, "\n"); 4664 /* QAM Equalizer Setup */ 4665 /* Equalizer */ 4666 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336); 4667 if (status < 0) 4668 goto error; 4669 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618); 4670 if (status < 0) 4671 goto error; 4672 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988); 4673 if (status < 0) 4674 goto error; 4675 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809); 4676 if (status < 0) 4677 goto error; 4678 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809); 4679 if (status < 0) 4680 goto error; 4681 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609); 4682 if (status < 0) 4683 goto error; 4684 4685 /* Decision Feedback Equalizer */ 4686 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4); 4687 if (status < 0) 4688 goto error; 4689 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4); 4690 if (status < 0) 4691 goto error; 4692 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4); 4693 if (status < 0) 4694 goto error; 4695 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4); 4696 if (status < 0) 4697 goto error; 4698 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3); 4699 if (status < 0) 4700 goto error; 4701 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); 4702 if (status < 0) 4703 goto error; 4704 4705 status = write16(state, QAM_SY_SYNC_HWM__A, 5); 4706 if (status < 0) 4707 goto error; 4708 status = write16(state, QAM_SY_SYNC_AWM__A, 4); 4709 if (status < 0) 4710 goto error; 4711 status = write16(state, QAM_SY_SYNC_LWM__A, 3); 4712 if (status < 0) 4713 goto error; 4714 4715 /* QAM Slicer Settings */ 4716 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, 4717 DRXK_QAM_SL_SIG_POWER_QAM64); 4718 if (status < 0) 4719 goto error; 4720 4721 4722 /* QAM Loop Controller Coeficients */ 4723 4724 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); 4725 if (status < 0) 4726 goto error; 4727 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); 4728 if (status < 0) 4729 goto error; 4730 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); 4731 if (status < 0) 4732 goto error; 4733 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); 4734 if (status < 0) 4735 goto error; 4736 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); 4737 if (status < 0) 4738 goto error; 4739 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); 4740 if (status < 0) 4741 goto error; 4742 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); 4743 if (status < 0) 4744 goto error; 4745 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); 4746 if (status < 0) 4747 goto error; 4748 4749 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); 4750 if (status < 0) 4751 goto error; 4752 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30); 4753 if (status < 0) 4754 goto error; 4755 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100); 4756 if (status < 0) 4757 goto error; 4758 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); 4759 if (status < 0) 4760 goto error; 4761 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30); 4762 if (status < 0) 4763 goto error; 4764 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); 4765 if (status < 0) 4766 goto error; 4767 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); 4768 if (status < 0) 4769 goto error; 4770 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); 4771 if (status < 0) 4772 goto error; 4773 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48); 4774 if (status < 0) 4775 goto error; 4776 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); 4777 if (status < 0) 4778 goto error; 4779 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); 4780 if (status < 0) 4781 goto error; 4782 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); 4783 if (status < 0) 4784 goto error; 4785 4786 4787 /* QAM State Machine (FSM) Thresholds */ 4788 4789 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100); 4790 if (status < 0) 4791 goto error; 4792 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); 4793 if (status < 0) 4794 goto error; 4795 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); 4796 if (status < 0) 4797 goto error; 4798 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110); 4799 if (status < 0) 4800 goto error; 4801 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200); 4802 if (status < 0) 4803 goto error; 4804 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95); 4805 if (status < 0) 4806 goto error; 4807 4808 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); 4809 if (status < 0) 4810 goto error; 4811 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); 4812 if (status < 0) 4813 goto error; 4814 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15); 4815 if (status < 0) 4816 goto error; 4817 4818 4819 /* QAM FSM Tracking Parameters */ 4820 4821 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); 4822 if (status < 0) 4823 goto error; 4824 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141); 4825 if (status < 0) 4826 goto error; 4827 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7); 4828 if (status < 0) 4829 goto error; 4830 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0); 4831 if (status < 0) 4832 goto error; 4833 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15); 4834 if (status < 0) 4835 goto error; 4836 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45); 4837 if (status < 0) 4838 goto error; 4839 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80); 4840 error: 4841 if (status < 0) 4842 pr_err("Error %d on %s\n", status, __func__); 4843 4844 return status; 4845 } 4846 4847 /*============================================================================*/ 4848 4849 /* 4850 * \brief QAM128 specific setup 4851 * \param demod: instance of demod. 4852 * \return DRXStatus_t. 4853 */ set_qam128(struct drxk_state * state)4854 static int set_qam128(struct drxk_state *state) 4855 { 4856 int status = 0; 4857 4858 dprintk(1, "\n"); 4859 /* QAM Equalizer Setup */ 4860 /* Equalizer */ 4861 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564); 4862 if (status < 0) 4863 goto error; 4864 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598); 4865 if (status < 0) 4866 goto error; 4867 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394); 4868 if (status < 0) 4869 goto error; 4870 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409); 4871 if (status < 0) 4872 goto error; 4873 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656); 4874 if (status < 0) 4875 goto error; 4876 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238); 4877 if (status < 0) 4878 goto error; 4879 4880 /* Decision Feedback Equalizer */ 4881 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6); 4882 if (status < 0) 4883 goto error; 4884 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6); 4885 if (status < 0) 4886 goto error; 4887 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6); 4888 if (status < 0) 4889 goto error; 4890 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6); 4891 if (status < 0) 4892 goto error; 4893 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5); 4894 if (status < 0) 4895 goto error; 4896 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); 4897 if (status < 0) 4898 goto error; 4899 4900 status = write16(state, QAM_SY_SYNC_HWM__A, 6); 4901 if (status < 0) 4902 goto error; 4903 status = write16(state, QAM_SY_SYNC_AWM__A, 5); 4904 if (status < 0) 4905 goto error; 4906 status = write16(state, QAM_SY_SYNC_LWM__A, 3); 4907 if (status < 0) 4908 goto error; 4909 4910 4911 /* QAM Slicer Settings */ 4912 4913 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, 4914 DRXK_QAM_SL_SIG_POWER_QAM128); 4915 if (status < 0) 4916 goto error; 4917 4918 4919 /* QAM Loop Controller Coeficients */ 4920 4921 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); 4922 if (status < 0) 4923 goto error; 4924 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); 4925 if (status < 0) 4926 goto error; 4927 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); 4928 if (status < 0) 4929 goto error; 4930 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); 4931 if (status < 0) 4932 goto error; 4933 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); 4934 if (status < 0) 4935 goto error; 4936 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); 4937 if (status < 0) 4938 goto error; 4939 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); 4940 if (status < 0) 4941 goto error; 4942 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); 4943 if (status < 0) 4944 goto error; 4945 4946 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); 4947 if (status < 0) 4948 goto error; 4949 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40); 4950 if (status < 0) 4951 goto error; 4952 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120); 4953 if (status < 0) 4954 goto error; 4955 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); 4956 if (status < 0) 4957 goto error; 4958 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40); 4959 if (status < 0) 4960 goto error; 4961 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60); 4962 if (status < 0) 4963 goto error; 4964 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); 4965 if (status < 0) 4966 goto error; 4967 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); 4968 if (status < 0) 4969 goto error; 4970 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64); 4971 if (status < 0) 4972 goto error; 4973 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); 4974 if (status < 0) 4975 goto error; 4976 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); 4977 if (status < 0) 4978 goto error; 4979 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0); 4980 if (status < 0) 4981 goto error; 4982 4983 4984 /* QAM State Machine (FSM) Thresholds */ 4985 4986 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50); 4987 if (status < 0) 4988 goto error; 4989 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); 4990 if (status < 0) 4991 goto error; 4992 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); 4993 if (status < 0) 4994 goto error; 4995 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); 4996 if (status < 0) 4997 goto error; 4998 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140); 4999 if (status < 0) 5000 goto error; 5001 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100); 5002 if (status < 0) 5003 goto error; 5004 5005 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); 5006 if (status < 0) 5007 goto error; 5008 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5); 5009 if (status < 0) 5010 goto error; 5011 5012 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); 5013 if (status < 0) 5014 goto error; 5015 5016 /* QAM FSM Tracking Parameters */ 5017 5018 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); 5019 if (status < 0) 5020 goto error; 5021 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65); 5022 if (status < 0) 5023 goto error; 5024 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5); 5025 if (status < 0) 5026 goto error; 5027 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3); 5028 if (status < 0) 5029 goto error; 5030 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1); 5031 if (status < 0) 5032 goto error; 5033 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12); 5034 if (status < 0) 5035 goto error; 5036 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23); 5037 error: 5038 if (status < 0) 5039 pr_err("Error %d on %s\n", status, __func__); 5040 5041 return status; 5042 } 5043 5044 /*============================================================================*/ 5045 5046 /* 5047 * \brief QAM256 specific setup 5048 * \param demod: instance of demod. 5049 * \return DRXStatus_t. 5050 */ set_qam256(struct drxk_state * state)5051 static int set_qam256(struct drxk_state *state) 5052 { 5053 int status = 0; 5054 5055 dprintk(1, "\n"); 5056 /* QAM Equalizer Setup */ 5057 /* Equalizer */ 5058 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502); 5059 if (status < 0) 5060 goto error; 5061 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084); 5062 if (status < 0) 5063 goto error; 5064 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543); 5065 if (status < 0) 5066 goto error; 5067 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931); 5068 if (status < 0) 5069 goto error; 5070 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629); 5071 if (status < 0) 5072 goto error; 5073 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385); 5074 if (status < 0) 5075 goto error; 5076 5077 /* Decision Feedback Equalizer */ 5078 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8); 5079 if (status < 0) 5080 goto error; 5081 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8); 5082 if (status < 0) 5083 goto error; 5084 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8); 5085 if (status < 0) 5086 goto error; 5087 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8); 5088 if (status < 0) 5089 goto error; 5090 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6); 5091 if (status < 0) 5092 goto error; 5093 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); 5094 if (status < 0) 5095 goto error; 5096 5097 status = write16(state, QAM_SY_SYNC_HWM__A, 5); 5098 if (status < 0) 5099 goto error; 5100 status = write16(state, QAM_SY_SYNC_AWM__A, 4); 5101 if (status < 0) 5102 goto error; 5103 status = write16(state, QAM_SY_SYNC_LWM__A, 3); 5104 if (status < 0) 5105 goto error; 5106 5107 /* QAM Slicer Settings */ 5108 5109 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, 5110 DRXK_QAM_SL_SIG_POWER_QAM256); 5111 if (status < 0) 5112 goto error; 5113 5114 5115 /* QAM Loop Controller Coeficients */ 5116 5117 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); 5118 if (status < 0) 5119 goto error; 5120 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); 5121 if (status < 0) 5122 goto error; 5123 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); 5124 if (status < 0) 5125 goto error; 5126 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); 5127 if (status < 0) 5128 goto error; 5129 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); 5130 if (status < 0) 5131 goto error; 5132 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); 5133 if (status < 0) 5134 goto error; 5135 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); 5136 if (status < 0) 5137 goto error; 5138 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); 5139 if (status < 0) 5140 goto error; 5141 5142 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); 5143 if (status < 0) 5144 goto error; 5145 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50); 5146 if (status < 0) 5147 goto error; 5148 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250); 5149 if (status < 0) 5150 goto error; 5151 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); 5152 if (status < 0) 5153 goto error; 5154 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50); 5155 if (status < 0) 5156 goto error; 5157 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125); 5158 if (status < 0) 5159 goto error; 5160 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); 5161 if (status < 0) 5162 goto error; 5163 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); 5164 if (status < 0) 5165 goto error; 5166 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48); 5167 if (status < 0) 5168 goto error; 5169 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); 5170 if (status < 0) 5171 goto error; 5172 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); 5173 if (status < 0) 5174 goto error; 5175 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); 5176 if (status < 0) 5177 goto error; 5178 5179 5180 /* QAM State Machine (FSM) Thresholds */ 5181 5182 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50); 5183 if (status < 0) 5184 goto error; 5185 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); 5186 if (status < 0) 5187 goto error; 5188 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); 5189 if (status < 0) 5190 goto error; 5191 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); 5192 if (status < 0) 5193 goto error; 5194 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150); 5195 if (status < 0) 5196 goto error; 5197 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110); 5198 if (status < 0) 5199 goto error; 5200 5201 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); 5202 if (status < 0) 5203 goto error; 5204 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); 5205 if (status < 0) 5206 goto error; 5207 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); 5208 if (status < 0) 5209 goto error; 5210 5211 5212 /* QAM FSM Tracking Parameters */ 5213 5214 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); 5215 if (status < 0) 5216 goto error; 5217 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74); 5218 if (status < 0) 5219 goto error; 5220 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18); 5221 if (status < 0) 5222 goto error; 5223 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13); 5224 if (status < 0) 5225 goto error; 5226 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7); 5227 if (status < 0) 5228 goto error; 5229 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0); 5230 if (status < 0) 5231 goto error; 5232 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8); 5233 error: 5234 if (status < 0) 5235 pr_err("Error %d on %s\n", status, __func__); 5236 return status; 5237 } 5238 5239 5240 /*============================================================================*/ 5241 /* 5242 * \brief Reset QAM block. 5243 * \param demod: instance of demod. 5244 * \param channel: pointer to channel data. 5245 * \return DRXStatus_t. 5246 */ qam_reset_qam(struct drxk_state * state)5247 static int qam_reset_qam(struct drxk_state *state) 5248 { 5249 int status; 5250 u16 cmd_result; 5251 5252 dprintk(1, "\n"); 5253 /* Stop QAM comstate->m_exec */ 5254 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); 5255 if (status < 0) 5256 goto error; 5257 5258 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM 5259 | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 5260 0, NULL, 1, &cmd_result); 5261 error: 5262 if (status < 0) 5263 pr_err("Error %d on %s\n", status, __func__); 5264 return status; 5265 } 5266 5267 /*============================================================================*/ 5268 5269 /* 5270 * \brief Set QAM symbolrate. 5271 * \param demod: instance of demod. 5272 * \param channel: pointer to channel data. 5273 * \return DRXStatus_t. 5274 */ qam_set_symbolrate(struct drxk_state * state)5275 static int qam_set_symbolrate(struct drxk_state *state) 5276 { 5277 u32 adc_frequency = 0; 5278 u32 symb_freq = 0; 5279 u32 iqm_rc_rate = 0; 5280 u16 ratesel = 0; 5281 u32 lc_symb_rate = 0; 5282 int status; 5283 5284 dprintk(1, "\n"); 5285 /* Select & calculate correct IQM rate */ 5286 adc_frequency = (state->m_sys_clock_freq * 1000) / 3; 5287 ratesel = 0; 5288 if (state->props.symbol_rate <= 1188750) 5289 ratesel = 3; 5290 else if (state->props.symbol_rate <= 2377500) 5291 ratesel = 2; 5292 else if (state->props.symbol_rate <= 4755000) 5293 ratesel = 1; 5294 status = write16(state, IQM_FD_RATESEL__A, ratesel); 5295 if (status < 0) 5296 goto error; 5297 5298 /* 5299 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23) 5300 */ 5301 symb_freq = state->props.symbol_rate * (1 << ratesel); 5302 if (symb_freq == 0) { 5303 /* Divide by zero */ 5304 status = -EINVAL; 5305 goto error; 5306 } 5307 iqm_rc_rate = (adc_frequency / symb_freq) * (1 << 21) + 5308 (Frac28a((adc_frequency % symb_freq), symb_freq) >> 7) - 5309 (1 << 23); 5310 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate); 5311 if (status < 0) 5312 goto error; 5313 state->m_iqm_rc_rate = iqm_rc_rate; 5314 /* 5315 LcSymbFreq = round (.125 * symbolrate / adc_freq * (1<<15)) 5316 */ 5317 symb_freq = state->props.symbol_rate; 5318 if (adc_frequency == 0) { 5319 /* Divide by zero */ 5320 status = -EINVAL; 5321 goto error; 5322 } 5323 lc_symb_rate = (symb_freq / adc_frequency) * (1 << 12) + 5324 (Frac28a((symb_freq % adc_frequency), adc_frequency) >> 5325 16); 5326 if (lc_symb_rate > 511) 5327 lc_symb_rate = 511; 5328 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate); 5329 5330 error: 5331 if (status < 0) 5332 pr_err("Error %d on %s\n", status, __func__); 5333 return status; 5334 } 5335 5336 /*============================================================================*/ 5337 5338 /* 5339 * \brief Get QAM lock status. 5340 * \param demod: instance of demod. 5341 * \param channel: pointer to channel data. 5342 * \return DRXStatus_t. 5343 */ 5344 get_qam_lock_status(struct drxk_state * state,u32 * p_lock_status)5345 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status) 5346 { 5347 int status; 5348 u16 result[2] = { 0, 0 }; 5349 5350 dprintk(1, "\n"); 5351 *p_lock_status = NOT_LOCKED; 5352 status = scu_command(state, 5353 SCU_RAM_COMMAND_STANDARD_QAM | 5354 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2, 5355 result); 5356 if (status < 0) 5357 pr_err("Error %d on %s\n", status, __func__); 5358 5359 if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) { 5360 /* 0x0000 NOT LOCKED */ 5361 } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) { 5362 /* 0x4000 DEMOD LOCKED */ 5363 *p_lock_status = DEMOD_LOCK; 5364 } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) { 5365 /* 0x8000 DEMOD + FEC LOCKED (system lock) */ 5366 *p_lock_status = MPEG_LOCK; 5367 } else { 5368 /* 0xC000 NEVER LOCKED */ 5369 /* (system will never be able to lock to the signal) */ 5370 /* 5371 * TODO: check this, intermediate & standard specific lock 5372 * states are not taken into account here 5373 */ 5374 *p_lock_status = NEVER_LOCK; 5375 } 5376 return status; 5377 } 5378 5379 #define QAM_MIRROR__M 0x03 5380 #define QAM_MIRROR_NORMAL 0x00 5381 #define QAM_MIRRORED 0x01 5382 #define QAM_MIRROR_AUTO_ON 0x02 5383 #define QAM_LOCKRANGE__M 0x10 5384 #define QAM_LOCKRANGE_NORMAL 0x10 5385 qam_demodulator_command(struct drxk_state * state,int number_of_parameters)5386 static int qam_demodulator_command(struct drxk_state *state, 5387 int number_of_parameters) 5388 { 5389 int status; 5390 u16 cmd_result; 5391 u16 set_param_parameters[4] = { 0, 0, 0, 0 }; 5392 5393 set_param_parameters[0] = state->m_constellation; /* modulation */ 5394 set_param_parameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ 5395 5396 if (number_of_parameters == 2) { 5397 u16 set_env_parameters[1] = { 0 }; 5398 5399 if (state->m_operation_mode == OM_QAM_ITU_C) 5400 set_env_parameters[0] = QAM_TOP_ANNEX_C; 5401 else 5402 set_env_parameters[0] = QAM_TOP_ANNEX_A; 5403 5404 status = scu_command(state, 5405 SCU_RAM_COMMAND_STANDARD_QAM 5406 | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 5407 1, set_env_parameters, 1, &cmd_result); 5408 if (status < 0) 5409 goto error; 5410 5411 status = scu_command(state, 5412 SCU_RAM_COMMAND_STANDARD_QAM 5413 | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 5414 number_of_parameters, set_param_parameters, 5415 1, &cmd_result); 5416 } else if (number_of_parameters == 4) { 5417 if (state->m_operation_mode == OM_QAM_ITU_C) 5418 set_param_parameters[2] = QAM_TOP_ANNEX_C; 5419 else 5420 set_param_parameters[2] = QAM_TOP_ANNEX_A; 5421 5422 set_param_parameters[3] |= (QAM_MIRROR_AUTO_ON); 5423 /* Env parameters */ 5424 /* check for LOCKRANGE Extented */ 5425 /* set_param_parameters[3] |= QAM_LOCKRANGE_NORMAL; */ 5426 5427 status = scu_command(state, 5428 SCU_RAM_COMMAND_STANDARD_QAM 5429 | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 5430 number_of_parameters, set_param_parameters, 5431 1, &cmd_result); 5432 } else { 5433 pr_warn("Unknown QAM demodulator parameter count %d\n", 5434 number_of_parameters); 5435 status = -EINVAL; 5436 } 5437 5438 error: 5439 if (status < 0) 5440 pr_warn("Warning %d on %s\n", status, __func__); 5441 return status; 5442 } 5443 set_qam(struct drxk_state * state,u16 intermediate_freqk_hz,s32 tuner_freq_offset)5444 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, 5445 s32 tuner_freq_offset) 5446 { 5447 int status; 5448 u16 cmd_result; 5449 int qam_demod_param_count = state->qam_demod_parameter_count; 5450 5451 dprintk(1, "\n"); 5452 /* 5453 * STEP 1: reset demodulator 5454 * resets FEC DI and FEC RS 5455 * resets QAM block 5456 * resets SCU variables 5457 */ 5458 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP); 5459 if (status < 0) 5460 goto error; 5461 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP); 5462 if (status < 0) 5463 goto error; 5464 status = qam_reset_qam(state); 5465 if (status < 0) 5466 goto error; 5467 5468 /* 5469 * STEP 2: configure demodulator 5470 * -set params; resets IQM,QAM,FEC HW; initializes some 5471 * SCU variables 5472 */ 5473 status = qam_set_symbolrate(state); 5474 if (status < 0) 5475 goto error; 5476 5477 /* Set params */ 5478 switch (state->props.modulation) { 5479 case QAM_256: 5480 state->m_constellation = DRX_CONSTELLATION_QAM256; 5481 break; 5482 case QAM_AUTO: 5483 case QAM_64: 5484 state->m_constellation = DRX_CONSTELLATION_QAM64; 5485 break; 5486 case QAM_16: 5487 state->m_constellation = DRX_CONSTELLATION_QAM16; 5488 break; 5489 case QAM_32: 5490 state->m_constellation = DRX_CONSTELLATION_QAM32; 5491 break; 5492 case QAM_128: 5493 state->m_constellation = DRX_CONSTELLATION_QAM128; 5494 break; 5495 default: 5496 status = -EINVAL; 5497 break; 5498 } 5499 if (status < 0) 5500 goto error; 5501 5502 /* Use the 4-parameter if it's requested or we're probing for 5503 * the correct command. */ 5504 if (state->qam_demod_parameter_count == 4 5505 || !state->qam_demod_parameter_count) { 5506 qam_demod_param_count = 4; 5507 status = qam_demodulator_command(state, qam_demod_param_count); 5508 } 5509 5510 /* Use the 2-parameter command if it was requested or if we're 5511 * probing for the correct command and the 4-parameter command 5512 * failed. */ 5513 if (state->qam_demod_parameter_count == 2 5514 || (!state->qam_demod_parameter_count && status < 0)) { 5515 qam_demod_param_count = 2; 5516 status = qam_demodulator_command(state, qam_demod_param_count); 5517 } 5518 5519 if (status < 0) { 5520 dprintk(1, "Could not set demodulator parameters.\n"); 5521 dprintk(1, 5522 "Make sure qam_demod_parameter_count (%d) is correct for your firmware (%s).\n", 5523 state->qam_demod_parameter_count, 5524 state->microcode_name); 5525 goto error; 5526 } else if (!state->qam_demod_parameter_count) { 5527 dprintk(1, 5528 "Auto-probing the QAM command parameters was successful - using %d parameters.\n", 5529 qam_demod_param_count); 5530 5531 /* 5532 * One of our commands was successful. We don't need to 5533 * auto-probe anymore, now that we got the correct command. 5534 */ 5535 state->qam_demod_parameter_count = qam_demod_param_count; 5536 } 5537 5538 /* 5539 * STEP 3: enable the system in a mode where the ADC provides valid 5540 * signal setup modulation independent registers 5541 */ 5542 #if 0 5543 status = set_frequency(channel, tuner_freq_offset)); 5544 if (status < 0) 5545 goto error; 5546 #endif 5547 status = set_frequency_shifter(state, intermediate_freqk_hz, 5548 tuner_freq_offset, true); 5549 if (status < 0) 5550 goto error; 5551 5552 /* Setup BER measurement */ 5553 status = set_qam_measurement(state, state->m_constellation, 5554 state->props.symbol_rate); 5555 if (status < 0) 5556 goto error; 5557 5558 /* Reset default values */ 5559 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE); 5560 if (status < 0) 5561 goto error; 5562 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE); 5563 if (status < 0) 5564 goto error; 5565 5566 /* Reset default LC values */ 5567 status = write16(state, QAM_LC_RATE_LIMIT__A, 3); 5568 if (status < 0) 5569 goto error; 5570 status = write16(state, QAM_LC_LPF_FACTORP__A, 4); 5571 if (status < 0) 5572 goto error; 5573 status = write16(state, QAM_LC_LPF_FACTORI__A, 4); 5574 if (status < 0) 5575 goto error; 5576 status = write16(state, QAM_LC_MODE__A, 7); 5577 if (status < 0) 5578 goto error; 5579 5580 status = write16(state, QAM_LC_QUAL_TAB0__A, 1); 5581 if (status < 0) 5582 goto error; 5583 status = write16(state, QAM_LC_QUAL_TAB1__A, 1); 5584 if (status < 0) 5585 goto error; 5586 status = write16(state, QAM_LC_QUAL_TAB2__A, 1); 5587 if (status < 0) 5588 goto error; 5589 status = write16(state, QAM_LC_QUAL_TAB3__A, 1); 5590 if (status < 0) 5591 goto error; 5592 status = write16(state, QAM_LC_QUAL_TAB4__A, 2); 5593 if (status < 0) 5594 goto error; 5595 status = write16(state, QAM_LC_QUAL_TAB5__A, 2); 5596 if (status < 0) 5597 goto error; 5598 status = write16(state, QAM_LC_QUAL_TAB6__A, 2); 5599 if (status < 0) 5600 goto error; 5601 status = write16(state, QAM_LC_QUAL_TAB8__A, 2); 5602 if (status < 0) 5603 goto error; 5604 status = write16(state, QAM_LC_QUAL_TAB9__A, 2); 5605 if (status < 0) 5606 goto error; 5607 status = write16(state, QAM_LC_QUAL_TAB10__A, 2); 5608 if (status < 0) 5609 goto error; 5610 status = write16(state, QAM_LC_QUAL_TAB12__A, 2); 5611 if (status < 0) 5612 goto error; 5613 status = write16(state, QAM_LC_QUAL_TAB15__A, 3); 5614 if (status < 0) 5615 goto error; 5616 status = write16(state, QAM_LC_QUAL_TAB16__A, 3); 5617 if (status < 0) 5618 goto error; 5619 status = write16(state, QAM_LC_QUAL_TAB20__A, 4); 5620 if (status < 0) 5621 goto error; 5622 status = write16(state, QAM_LC_QUAL_TAB25__A, 4); 5623 if (status < 0) 5624 goto error; 5625 5626 /* Mirroring, QAM-block starting point not inverted */ 5627 status = write16(state, QAM_SY_SP_INV__A, 5628 QAM_SY_SP_INV_SPECTRUM_INV_DIS); 5629 if (status < 0) 5630 goto error; 5631 5632 /* Halt SCU to enable safe non-atomic accesses */ 5633 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); 5634 if (status < 0) 5635 goto error; 5636 5637 /* STEP 4: modulation specific setup */ 5638 switch (state->props.modulation) { 5639 case QAM_16: 5640 status = set_qam16(state); 5641 break; 5642 case QAM_32: 5643 status = set_qam32(state); 5644 break; 5645 case QAM_AUTO: 5646 case QAM_64: 5647 status = set_qam64(state); 5648 break; 5649 case QAM_128: 5650 status = set_qam128(state); 5651 break; 5652 case QAM_256: 5653 status = set_qam256(state); 5654 break; 5655 default: 5656 status = -EINVAL; 5657 break; 5658 } 5659 if (status < 0) 5660 goto error; 5661 5662 /* Activate SCU to enable SCU commands */ 5663 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 5664 if (status < 0) 5665 goto error; 5666 5667 /* Re-configure MPEG output, requires knowledge of channel bitrate */ 5668 /* extAttr->currentChannel.modulation = channel->modulation; */ 5669 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */ 5670 status = mpegts_dto_setup(state, state->m_operation_mode); 5671 if (status < 0) 5672 goto error; 5673 5674 /* start processes */ 5675 status = mpegts_start(state); 5676 if (status < 0) 5677 goto error; 5678 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); 5679 if (status < 0) 5680 goto error; 5681 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE); 5682 if (status < 0) 5683 goto error; 5684 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE); 5685 if (status < 0) 5686 goto error; 5687 5688 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ 5689 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM 5690 | SCU_RAM_COMMAND_CMD_DEMOD_START, 5691 0, NULL, 1, &cmd_result); 5692 if (status < 0) 5693 goto error; 5694 5695 /* update global DRXK data container */ 5696 /*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */ 5697 5698 error: 5699 if (status < 0) 5700 pr_err("Error %d on %s\n", status, __func__); 5701 return status; 5702 } 5703 set_qam_standard(struct drxk_state * state,enum operation_mode o_mode)5704 static int set_qam_standard(struct drxk_state *state, 5705 enum operation_mode o_mode) 5706 { 5707 int status; 5708 #ifdef DRXK_QAM_TAPS 5709 #define DRXK_QAMA_TAPS_SELECT 5710 #include "drxk_filters.h" 5711 #undef DRXK_QAMA_TAPS_SELECT 5712 #endif 5713 5714 dprintk(1, "\n"); 5715 5716 /* added antenna switch */ 5717 switch_antenna_to_qam(state); 5718 5719 /* Ensure correct power-up mode */ 5720 status = power_up_qam(state); 5721 if (status < 0) 5722 goto error; 5723 /* Reset QAM block */ 5724 status = qam_reset_qam(state); 5725 if (status < 0) 5726 goto error; 5727 5728 /* Setup IQM */ 5729 5730 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); 5731 if (status < 0) 5732 goto error; 5733 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); 5734 if (status < 0) 5735 goto error; 5736 5737 /* Upload IQM Channel Filter settings by 5738 boot loader from ROM table */ 5739 switch (o_mode) { 5740 case OM_QAM_ITU_A: 5741 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, 5742 DRXK_BLCC_NR_ELEMENTS_TAPS, 5743 DRXK_BLC_TIMEOUT); 5744 break; 5745 case OM_QAM_ITU_C: 5746 status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A, 5747 DRXK_BL_ROM_OFFSET_TAPS_ITU_C, 5748 DRXK_BLDC_NR_ELEMENTS_TAPS, 5749 DRXK_BLC_TIMEOUT); 5750 if (status < 0) 5751 goto error; 5752 status = bl_direct_cmd(state, 5753 IQM_CF_TAP_IM0__A, 5754 DRXK_BL_ROM_OFFSET_TAPS_ITU_C, 5755 DRXK_BLDC_NR_ELEMENTS_TAPS, 5756 DRXK_BLC_TIMEOUT); 5757 break; 5758 default: 5759 status = -EINVAL; 5760 } 5761 if (status < 0) 5762 goto error; 5763 5764 status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B); 5765 if (status < 0) 5766 goto error; 5767 status = write16(state, IQM_CF_SYMMETRIC__A, 0); 5768 if (status < 0) 5769 goto error; 5770 status = write16(state, IQM_CF_MIDTAP__A, 5771 ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B))); 5772 if (status < 0) 5773 goto error; 5774 5775 status = write16(state, IQM_RC_STRETCH__A, 21); 5776 if (status < 0) 5777 goto error; 5778 status = write16(state, IQM_AF_CLP_LEN__A, 0); 5779 if (status < 0) 5780 goto error; 5781 status = write16(state, IQM_AF_CLP_TH__A, 448); 5782 if (status < 0) 5783 goto error; 5784 status = write16(state, IQM_AF_SNS_LEN__A, 0); 5785 if (status < 0) 5786 goto error; 5787 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0); 5788 if (status < 0) 5789 goto error; 5790 5791 status = write16(state, IQM_FS_ADJ_SEL__A, 1); 5792 if (status < 0) 5793 goto error; 5794 status = write16(state, IQM_RC_ADJ_SEL__A, 1); 5795 if (status < 0) 5796 goto error; 5797 status = write16(state, IQM_CF_ADJ_SEL__A, 1); 5798 if (status < 0) 5799 goto error; 5800 status = write16(state, IQM_AF_UPD_SEL__A, 0); 5801 if (status < 0) 5802 goto error; 5803 5804 /* IQM Impulse Noise Processing Unit */ 5805 status = write16(state, IQM_CF_CLP_VAL__A, 500); 5806 if (status < 0) 5807 goto error; 5808 status = write16(state, IQM_CF_DATATH__A, 1000); 5809 if (status < 0) 5810 goto error; 5811 status = write16(state, IQM_CF_BYPASSDET__A, 1); 5812 if (status < 0) 5813 goto error; 5814 status = write16(state, IQM_CF_DET_LCT__A, 0); 5815 if (status < 0) 5816 goto error; 5817 status = write16(state, IQM_CF_WND_LEN__A, 1); 5818 if (status < 0) 5819 goto error; 5820 status = write16(state, IQM_CF_PKDTH__A, 1); 5821 if (status < 0) 5822 goto error; 5823 status = write16(state, IQM_AF_INC_BYPASS__A, 1); 5824 if (status < 0) 5825 goto error; 5826 5827 /* turn on IQMAF. Must be done before setAgc**() */ 5828 status = set_iqm_af(state, true); 5829 if (status < 0) 5830 goto error; 5831 status = write16(state, IQM_AF_START_LOCK__A, 0x01); 5832 if (status < 0) 5833 goto error; 5834 5835 /* IQM will not be reset from here, sync ADC and update/init AGC */ 5836 status = adc_synchronization(state); 5837 if (status < 0) 5838 goto error; 5839 5840 /* Set the FSM step period */ 5841 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000); 5842 if (status < 0) 5843 goto error; 5844 5845 /* Halt SCU to enable safe non-atomic accesses */ 5846 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); 5847 if (status < 0) 5848 goto error; 5849 5850 /* No more resets of the IQM, current standard correctly set => 5851 now AGCs can be configured. */ 5852 5853 status = init_agc(state, true); 5854 if (status < 0) 5855 goto error; 5856 status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg)); 5857 if (status < 0) 5858 goto error; 5859 5860 /* Configure AGC's */ 5861 status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true); 5862 if (status < 0) 5863 goto error; 5864 status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true); 5865 if (status < 0) 5866 goto error; 5867 5868 /* Activate SCU to enable SCU commands */ 5869 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 5870 error: 5871 if (status < 0) 5872 pr_err("Error %d on %s\n", status, __func__); 5873 return status; 5874 } 5875 write_gpio(struct drxk_state * state)5876 static int write_gpio(struct drxk_state *state) 5877 { 5878 int status; 5879 u16 value = 0; 5880 5881 dprintk(1, "\n"); 5882 /* stop lock indicator process */ 5883 status = write16(state, SCU_RAM_GPIO__A, 5884 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 5885 if (status < 0) 5886 goto error; 5887 5888 /* Write magic word to enable pdr reg write */ 5889 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); 5890 if (status < 0) 5891 goto error; 5892 5893 if (state->m_has_sawsw) { 5894 if (state->uio_mask & 0x0001) { /* UIO-1 */ 5895 /* write to io pad configuration register - output mode */ 5896 status = write16(state, SIO_PDR_SMA_TX_CFG__A, 5897 state->m_gpio_cfg); 5898 if (status < 0) 5899 goto error; 5900 5901 /* use corresponding bit in io data output registar */ 5902 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); 5903 if (status < 0) 5904 goto error; 5905 if ((state->m_gpio & 0x0001) == 0) 5906 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ 5907 else 5908 value |= 0x8000; /* write one to 15th bit - 1st UIO */ 5909 /* write back to io data output register */ 5910 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); 5911 if (status < 0) 5912 goto error; 5913 } 5914 if (state->uio_mask & 0x0002) { /* UIO-2 */ 5915 /* write to io pad configuration register - output mode */ 5916 status = write16(state, SIO_PDR_SMA_RX_CFG__A, 5917 state->m_gpio_cfg); 5918 if (status < 0) 5919 goto error; 5920 5921 /* use corresponding bit in io data output registar */ 5922 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); 5923 if (status < 0) 5924 goto error; 5925 if ((state->m_gpio & 0x0002) == 0) 5926 value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */ 5927 else 5928 value |= 0x4000; /* write one to 14th bit - 2st UIO */ 5929 /* write back to io data output register */ 5930 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); 5931 if (status < 0) 5932 goto error; 5933 } 5934 if (state->uio_mask & 0x0004) { /* UIO-3 */ 5935 /* write to io pad configuration register - output mode */ 5936 status = write16(state, SIO_PDR_GPIO_CFG__A, 5937 state->m_gpio_cfg); 5938 if (status < 0) 5939 goto error; 5940 5941 /* use corresponding bit in io data output registar */ 5942 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); 5943 if (status < 0) 5944 goto error; 5945 if ((state->m_gpio & 0x0004) == 0) 5946 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */ 5947 else 5948 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ 5949 /* write back to io data output register */ 5950 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); 5951 if (status < 0) 5952 goto error; 5953 } 5954 } 5955 /* Write magic word to disable pdr reg write */ 5956 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); 5957 error: 5958 if (status < 0) 5959 pr_err("Error %d on %s\n", status, __func__); 5960 return status; 5961 } 5962 switch_antenna_to_qam(struct drxk_state * state)5963 static int switch_antenna_to_qam(struct drxk_state *state) 5964 { 5965 int status = 0; 5966 bool gpio_state; 5967 5968 dprintk(1, "\n"); 5969 5970 if (!state->antenna_gpio) 5971 return 0; 5972 5973 gpio_state = state->m_gpio & state->antenna_gpio; 5974 5975 if (state->antenna_dvbt ^ gpio_state) { 5976 /* Antenna is on DVB-T mode. Switch */ 5977 if (state->antenna_dvbt) 5978 state->m_gpio &= ~state->antenna_gpio; 5979 else 5980 state->m_gpio |= state->antenna_gpio; 5981 status = write_gpio(state); 5982 } 5983 if (status < 0) 5984 pr_err("Error %d on %s\n", status, __func__); 5985 return status; 5986 } 5987 switch_antenna_to_dvbt(struct drxk_state * state)5988 static int switch_antenna_to_dvbt(struct drxk_state *state) 5989 { 5990 int status = 0; 5991 bool gpio_state; 5992 5993 dprintk(1, "\n"); 5994 5995 if (!state->antenna_gpio) 5996 return 0; 5997 5998 gpio_state = state->m_gpio & state->antenna_gpio; 5999 6000 if (!(state->antenna_dvbt ^ gpio_state)) { 6001 /* Antenna is on DVB-C mode. Switch */ 6002 if (state->antenna_dvbt) 6003 state->m_gpio |= state->antenna_gpio; 6004 else 6005 state->m_gpio &= ~state->antenna_gpio; 6006 status = write_gpio(state); 6007 } 6008 if (status < 0) 6009 pr_err("Error %d on %s\n", status, __func__); 6010 return status; 6011 } 6012 6013 power_down_device(struct drxk_state * state)6014 static int power_down_device(struct drxk_state *state) 6015 { 6016 /* Power down to requested mode */ 6017 /* Backup some register settings */ 6018 /* Set pins with possible pull-ups connected to them in input mode */ 6019 /* Analog power down */ 6020 /* ADC power down */ 6021 /* Power down device */ 6022 int status; 6023 6024 dprintk(1, "\n"); 6025 if (state->m_b_p_down_open_bridge) { 6026 /* Open I2C bridge before power down of DRXK */ 6027 status = ConfigureI2CBridge(state, true); 6028 if (status < 0) 6029 goto error; 6030 } 6031 /* driver 0.9.0 */ 6032 status = dvbt_enable_ofdm_token_ring(state, false); 6033 if (status < 0) 6034 goto error; 6035 6036 status = write16(state, SIO_CC_PWD_MODE__A, 6037 SIO_CC_PWD_MODE_LEVEL_CLOCK); 6038 if (status < 0) 6039 goto error; 6040 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); 6041 if (status < 0) 6042 goto error; 6043 state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; 6044 status = hi_cfg_command(state); 6045 error: 6046 if (status < 0) 6047 pr_err("Error %d on %s\n", status, __func__); 6048 6049 return status; 6050 } 6051 init_drxk(struct drxk_state * state)6052 static int init_drxk(struct drxk_state *state) 6053 { 6054 int status = 0, n = 0; 6055 enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM; 6056 u16 driver_version; 6057 6058 dprintk(1, "\n"); 6059 if (state->m_drxk_state == DRXK_UNINITIALIZED) { 6060 drxk_i2c_lock(state); 6061 status = power_up_device(state); 6062 if (status < 0) 6063 goto error; 6064 status = drxx_open(state); 6065 if (status < 0) 6066 goto error; 6067 /* Soft reset of OFDM-, sys- and osc-clockdomain */ 6068 status = write16(state, SIO_CC_SOFT_RST__A, 6069 SIO_CC_SOFT_RST_OFDM__M 6070 | SIO_CC_SOFT_RST_SYS__M 6071 | SIO_CC_SOFT_RST_OSC__M); 6072 if (status < 0) 6073 goto error; 6074 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); 6075 if (status < 0) 6076 goto error; 6077 /* 6078 * TODO is this needed? If yes, how much delay in 6079 * worst case scenario 6080 */ 6081 usleep_range(1000, 2000); 6082 state->m_drxk_a3_patch_code = true; 6083 status = get_device_capabilities(state); 6084 if (status < 0) 6085 goto error; 6086 6087 /* Bridge delay, uses oscilator clock */ 6088 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */ 6089 /* SDA brdige delay */ 6090 state->m_hi_cfg_bridge_delay = 6091 (u16) ((state->m_osc_clock_freq / 1000) * 6092 HI_I2C_BRIDGE_DELAY) / 1000; 6093 /* Clipping */ 6094 if (state->m_hi_cfg_bridge_delay > 6095 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) { 6096 state->m_hi_cfg_bridge_delay = 6097 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; 6098 } 6099 /* SCL bridge delay, same as SDA for now */ 6100 state->m_hi_cfg_bridge_delay += 6101 state->m_hi_cfg_bridge_delay << 6102 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B; 6103 6104 status = init_hi(state); 6105 if (status < 0) 6106 goto error; 6107 /* disable various processes */ 6108 #if NOA1ROM 6109 if (!(state->m_DRXK_A1_ROM_CODE) 6110 && !(state->m_DRXK_A2_ROM_CODE)) 6111 #endif 6112 { 6113 status = write16(state, SCU_RAM_GPIO__A, 6114 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); 6115 if (status < 0) 6116 goto error; 6117 } 6118 6119 /* disable MPEG port */ 6120 status = mpegts_disable(state); 6121 if (status < 0) 6122 goto error; 6123 6124 /* Stop AUD and SCU */ 6125 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP); 6126 if (status < 0) 6127 goto error; 6128 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP); 6129 if (status < 0) 6130 goto error; 6131 6132 /* enable token-ring bus through OFDM block for possible ucode upload */ 6133 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, 6134 SIO_OFDM_SH_OFDM_RING_ENABLE_ON); 6135 if (status < 0) 6136 goto error; 6137 6138 /* include boot loader section */ 6139 status = write16(state, SIO_BL_COMM_EXEC__A, 6140 SIO_BL_COMM_EXEC_ACTIVE); 6141 if (status < 0) 6142 goto error; 6143 status = bl_chain_cmd(state, 0, 6, 100); 6144 if (status < 0) 6145 goto error; 6146 6147 if (state->fw) { 6148 status = download_microcode(state, state->fw->data, 6149 state->fw->size); 6150 if (status < 0) 6151 goto error; 6152 } 6153 6154 /* disable token-ring bus through OFDM block for possible ucode upload */ 6155 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, 6156 SIO_OFDM_SH_OFDM_RING_ENABLE_OFF); 6157 if (status < 0) 6158 goto error; 6159 6160 /* Run SCU for a little while to initialize microcode version numbers */ 6161 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); 6162 if (status < 0) 6163 goto error; 6164 status = drxx_open(state); 6165 if (status < 0) 6166 goto error; 6167 /* added for test */ 6168 msleep(30); 6169 6170 power_mode = DRXK_POWER_DOWN_OFDM; 6171 status = ctrl_power_mode(state, &power_mode); 6172 if (status < 0) 6173 goto error; 6174 6175 /* Stamp driver version number in SCU data RAM in BCD code 6176 Done to enable field application engineers to retrieve drxdriver version 6177 via I2C from SCU RAM. 6178 Not using SCU command interface for SCU register access since no 6179 microcode may be present. 6180 */ 6181 driver_version = 6182 (((DRXK_VERSION_MAJOR / 100) % 10) << 12) + 6183 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) + 6184 ((DRXK_VERSION_MAJOR % 10) << 4) + 6185 (DRXK_VERSION_MINOR % 10); 6186 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, 6187 driver_version); 6188 if (status < 0) 6189 goto error; 6190 driver_version = 6191 (((DRXK_VERSION_PATCH / 1000) % 10) << 12) + 6192 (((DRXK_VERSION_PATCH / 100) % 10) << 8) + 6193 (((DRXK_VERSION_PATCH / 10) % 10) << 4) + 6194 (DRXK_VERSION_PATCH % 10); 6195 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, 6196 driver_version); 6197 if (status < 0) 6198 goto error; 6199 6200 pr_info("DRXK driver version %d.%d.%d\n", 6201 DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR, 6202 DRXK_VERSION_PATCH); 6203 6204 /* 6205 * Dirty fix of default values for ROM/PATCH microcode 6206 * Dirty because this fix makes it impossible to setup 6207 * suitable values before calling DRX_Open. This solution 6208 * requires changes to RF AGC speed to be done via the CTRL 6209 * function after calling DRX_Open 6210 */ 6211 6212 /* m_dvbt_rf_agc_cfg.speed = 3; */ 6213 6214 /* Reset driver debug flags to 0 */ 6215 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0); 6216 if (status < 0) 6217 goto error; 6218 /* driver 0.9.0 */ 6219 /* Setup FEC OC: 6220 NOTE: No more full FEC resets allowed afterwards!! */ 6221 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); 6222 if (status < 0) 6223 goto error; 6224 /* MPEGTS functions are still the same */ 6225 status = mpegts_dto_init(state); 6226 if (status < 0) 6227 goto error; 6228 status = mpegts_stop(state); 6229 if (status < 0) 6230 goto error; 6231 status = mpegts_configure_polarity(state); 6232 if (status < 0) 6233 goto error; 6234 status = mpegts_configure_pins(state, state->m_enable_mpeg_output); 6235 if (status < 0) 6236 goto error; 6237 /* added: configure GPIO */ 6238 status = write_gpio(state); 6239 if (status < 0) 6240 goto error; 6241 6242 state->m_drxk_state = DRXK_STOPPED; 6243 6244 if (state->m_b_power_down) { 6245 status = power_down_device(state); 6246 if (status < 0) 6247 goto error; 6248 state->m_drxk_state = DRXK_POWERED_DOWN; 6249 } else 6250 state->m_drxk_state = DRXK_STOPPED; 6251 6252 /* Initialize the supported delivery systems */ 6253 n = 0; 6254 if (state->m_has_dvbc) { 6255 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A; 6256 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C; 6257 strlcat(state->frontend.ops.info.name, " DVB-C", 6258 sizeof(state->frontend.ops.info.name)); 6259 } 6260 if (state->m_has_dvbt) { 6261 state->frontend.ops.delsys[n++] = SYS_DVBT; 6262 strlcat(state->frontend.ops.info.name, " DVB-T", 6263 sizeof(state->frontend.ops.info.name)); 6264 } 6265 drxk_i2c_unlock(state); 6266 } 6267 error: 6268 if (status < 0) { 6269 state->m_drxk_state = DRXK_NO_DEV; 6270 drxk_i2c_unlock(state); 6271 pr_err("Error %d on %s\n", status, __func__); 6272 } 6273 6274 return status; 6275 } 6276 load_firmware_cb(const struct firmware * fw,void * context)6277 static void load_firmware_cb(const struct firmware *fw, 6278 void *context) 6279 { 6280 struct drxk_state *state = context; 6281 6282 dprintk(1, ": %s\n", fw ? "firmware loaded" : "firmware not loaded"); 6283 if (!fw) { 6284 pr_err("Could not load firmware file %s.\n", 6285 state->microcode_name); 6286 pr_info("Copy %s to your hotplug directory!\n", 6287 state->microcode_name); 6288 state->microcode_name = NULL; 6289 6290 /* 6291 * As firmware is now load asynchronous, it is not possible 6292 * anymore to fail at frontend attach. We might silently 6293 * return here, and hope that the driver won't crash. 6294 * We might also change all DVB callbacks to return -ENODEV 6295 * if the device is not initialized. 6296 * As the DRX-K devices have their own internal firmware, 6297 * let's just hope that it will match a firmware revision 6298 * compatible with this driver and proceed. 6299 */ 6300 } 6301 state->fw = fw; 6302 6303 init_drxk(state); 6304 } 6305 drxk_release(struct dvb_frontend * fe)6306 static void drxk_release(struct dvb_frontend *fe) 6307 { 6308 struct drxk_state *state = fe->demodulator_priv; 6309 6310 dprintk(1, "\n"); 6311 release_firmware(state->fw); 6312 6313 kfree(state); 6314 } 6315 drxk_sleep(struct dvb_frontend * fe)6316 static int drxk_sleep(struct dvb_frontend *fe) 6317 { 6318 struct drxk_state *state = fe->demodulator_priv; 6319 6320 dprintk(1, "\n"); 6321 6322 if (state->m_drxk_state == DRXK_NO_DEV) 6323 return -ENODEV; 6324 if (state->m_drxk_state == DRXK_UNINITIALIZED) 6325 return 0; 6326 6327 shut_down(state); 6328 return 0; 6329 } 6330 drxk_gate_ctrl(struct dvb_frontend * fe,int enable)6331 static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable) 6332 { 6333 struct drxk_state *state = fe->demodulator_priv; 6334 6335 dprintk(1, ": %s\n", enable ? "enable" : "disable"); 6336 6337 if (state->m_drxk_state == DRXK_NO_DEV) 6338 return -ENODEV; 6339 6340 return ConfigureI2CBridge(state, enable ? true : false); 6341 } 6342 drxk_set_parameters(struct dvb_frontend * fe)6343 static int drxk_set_parameters(struct dvb_frontend *fe) 6344 { 6345 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 6346 u32 delsys = p->delivery_system, old_delsys; 6347 struct drxk_state *state = fe->demodulator_priv; 6348 u32 IF; 6349 6350 dprintk(1, "\n"); 6351 6352 if (state->m_drxk_state == DRXK_NO_DEV) 6353 return -ENODEV; 6354 6355 if (state->m_drxk_state == DRXK_UNINITIALIZED) 6356 return -EAGAIN; 6357 6358 if (!fe->ops.tuner_ops.get_if_frequency) { 6359 pr_err("Error: get_if_frequency() not defined at tuner. Can't work without it!\n"); 6360 return -EINVAL; 6361 } 6362 6363 if (fe->ops.i2c_gate_ctrl) 6364 fe->ops.i2c_gate_ctrl(fe, 1); 6365 if (fe->ops.tuner_ops.set_params) 6366 fe->ops.tuner_ops.set_params(fe); 6367 if (fe->ops.i2c_gate_ctrl) 6368 fe->ops.i2c_gate_ctrl(fe, 0); 6369 6370 old_delsys = state->props.delivery_system; 6371 state->props = *p; 6372 6373 if (old_delsys != delsys) { 6374 shut_down(state); 6375 switch (delsys) { 6376 case SYS_DVBC_ANNEX_A: 6377 case SYS_DVBC_ANNEX_C: 6378 if (!state->m_has_dvbc) 6379 return -EINVAL; 6380 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? 6381 true : false; 6382 if (state->m_itut_annex_c) 6383 setoperation_mode(state, OM_QAM_ITU_C); 6384 else 6385 setoperation_mode(state, OM_QAM_ITU_A); 6386 break; 6387 case SYS_DVBT: 6388 if (!state->m_has_dvbt) 6389 return -EINVAL; 6390 setoperation_mode(state, OM_DVBT); 6391 break; 6392 default: 6393 return -EINVAL; 6394 } 6395 } 6396 6397 fe->ops.tuner_ops.get_if_frequency(fe, &IF); 6398 start(state, 0, IF); 6399 6400 /* After set_frontend, stats aren't available */ 6401 p->strength.stat[0].scale = FE_SCALE_RELATIVE; 6402 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6403 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6404 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6405 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6406 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6407 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6408 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6409 6410 /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */ 6411 6412 return 0; 6413 } 6414 get_strength(struct drxk_state * state,u64 * strength)6415 static int get_strength(struct drxk_state *state, u64 *strength) 6416 { 6417 int status; 6418 struct s_cfg_agc rf_agc, if_agc; 6419 u32 total_gain = 0; 6420 u32 atten = 0; 6421 u32 agc_range = 0; 6422 u16 scu_lvl = 0; 6423 u16 scu_coc = 0; 6424 /* FIXME: those are part of the tuner presets */ 6425 u16 tuner_rf_gain = 50; /* Default value on az6007 driver */ 6426 u16 tuner_if_gain = 40; /* Default value on az6007 driver */ 6427 6428 *strength = 0; 6429 6430 if (is_dvbt(state)) { 6431 rf_agc = state->m_dvbt_rf_agc_cfg; 6432 if_agc = state->m_dvbt_if_agc_cfg; 6433 } else if (is_qam(state)) { 6434 rf_agc = state->m_qam_rf_agc_cfg; 6435 if_agc = state->m_qam_if_agc_cfg; 6436 } else { 6437 rf_agc = state->m_atv_rf_agc_cfg; 6438 if_agc = state->m_atv_if_agc_cfg; 6439 } 6440 6441 if (rf_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) { 6442 /* SCU output_level */ 6443 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl); 6444 if (status < 0) 6445 return status; 6446 6447 /* SCU c.o.c. */ 6448 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc); 6449 if (status < 0) 6450 return status; 6451 6452 if (((u32) scu_lvl + (u32) scu_coc) < 0xffff) 6453 rf_agc.output_level = scu_lvl + scu_coc; 6454 else 6455 rf_agc.output_level = 0xffff; 6456 6457 /* Take RF gain into account */ 6458 total_gain += tuner_rf_gain; 6459 6460 /* clip output value */ 6461 if (rf_agc.output_level < rf_agc.min_output_level) 6462 rf_agc.output_level = rf_agc.min_output_level; 6463 if (rf_agc.output_level > rf_agc.max_output_level) 6464 rf_agc.output_level = rf_agc.max_output_level; 6465 6466 agc_range = (u32) (rf_agc.max_output_level - rf_agc.min_output_level); 6467 if (agc_range > 0) { 6468 atten += 100UL * 6469 ((u32)(tuner_rf_gain)) * 6470 ((u32)(rf_agc.output_level - rf_agc.min_output_level)) 6471 / agc_range; 6472 } 6473 } 6474 6475 if (if_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) { 6476 status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 6477 &if_agc.output_level); 6478 if (status < 0) 6479 return status; 6480 6481 status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, 6482 &if_agc.top); 6483 if (status < 0) 6484 return status; 6485 6486 /* Take IF gain into account */ 6487 total_gain += (u32) tuner_if_gain; 6488 6489 /* clip output value */ 6490 if (if_agc.output_level < if_agc.min_output_level) 6491 if_agc.output_level = if_agc.min_output_level; 6492 if (if_agc.output_level > if_agc.max_output_level) 6493 if_agc.output_level = if_agc.max_output_level; 6494 6495 agc_range = (u32)(if_agc.max_output_level - if_agc.min_output_level); 6496 if (agc_range > 0) { 6497 atten += 100UL * 6498 ((u32)(tuner_if_gain)) * 6499 ((u32)(if_agc.output_level - if_agc.min_output_level)) 6500 / agc_range; 6501 } 6502 } 6503 6504 /* 6505 * Convert to 0..65535 scale. 6506 * If it can't be measured (AGC is disabled), just show 100%. 6507 */ 6508 if (total_gain > 0) 6509 *strength = (65535UL * atten / total_gain / 100); 6510 else 6511 *strength = 65535; 6512 6513 return 0; 6514 } 6515 drxk_get_stats(struct dvb_frontend * fe)6516 static int drxk_get_stats(struct dvb_frontend *fe) 6517 { 6518 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 6519 struct drxk_state *state = fe->demodulator_priv; 6520 int status; 6521 u32 stat; 6522 u16 reg16; 6523 u32 post_bit_count; 6524 u32 post_bit_err_count; 6525 u32 post_bit_error_scale; 6526 u32 pre_bit_err_count; 6527 u32 pre_bit_count; 6528 u32 pkt_count; 6529 u32 pkt_error_count; 6530 s32 cnr; 6531 6532 if (state->m_drxk_state == DRXK_NO_DEV) 6533 return -ENODEV; 6534 if (state->m_drxk_state == DRXK_UNINITIALIZED) 6535 return -EAGAIN; 6536 6537 /* get status */ 6538 state->fe_status = 0; 6539 get_lock_status(state, &stat); 6540 if (stat == MPEG_LOCK) 6541 state->fe_status |= 0x1f; 6542 if (stat == FEC_LOCK) 6543 state->fe_status |= 0x0f; 6544 if (stat == DEMOD_LOCK) 6545 state->fe_status |= 0x07; 6546 6547 /* 6548 * Estimate signal strength from AGC 6549 */ 6550 get_strength(state, &c->strength.stat[0].uvalue); 6551 c->strength.stat[0].scale = FE_SCALE_RELATIVE; 6552 6553 6554 if (stat >= DEMOD_LOCK) { 6555 get_signal_to_noise(state, &cnr); 6556 c->cnr.stat[0].svalue = cnr * 100; 6557 c->cnr.stat[0].scale = FE_SCALE_DECIBEL; 6558 } else { 6559 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6560 } 6561 6562 if (stat < FEC_LOCK) { 6563 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6564 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6565 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6566 c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6567 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6568 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6569 return 0; 6570 } 6571 6572 /* Get post BER */ 6573 6574 /* BER measurement is valid if at least FEC lock is achieved */ 6575 6576 /* 6577 * OFDM_EC_VD_REQ_SMB_CNT__A and/or OFDM_EC_VD_REQ_BIT_CNT can be 6578 * written to set nr of symbols or bits over which to measure 6579 * EC_VD_REG_ERR_BIT_CNT__A . See CtrlSetCfg(). 6580 */ 6581 6582 /* Read registers for post/preViterbi BER calculation */ 6583 status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, ®16); 6584 if (status < 0) 6585 goto error; 6586 pre_bit_err_count = reg16; 6587 6588 status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , ®16); 6589 if (status < 0) 6590 goto error; 6591 pre_bit_count = reg16; 6592 6593 /* Number of bit-errors */ 6594 status = read16(state, FEC_RS_NR_BIT_ERRORS__A, ®16); 6595 if (status < 0) 6596 goto error; 6597 post_bit_err_count = reg16; 6598 6599 status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, ®16); 6600 if (status < 0) 6601 goto error; 6602 post_bit_error_scale = reg16; 6603 6604 status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, ®16); 6605 if (status < 0) 6606 goto error; 6607 pkt_count = reg16; 6608 6609 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, ®16); 6610 if (status < 0) 6611 goto error; 6612 pkt_error_count = reg16; 6613 write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); 6614 6615 post_bit_err_count *= post_bit_error_scale; 6616 6617 post_bit_count = pkt_count * 204 * 8; 6618 6619 /* Store the results */ 6620 c->block_error.stat[0].scale = FE_SCALE_COUNTER; 6621 c->block_error.stat[0].uvalue += pkt_error_count; 6622 c->block_count.stat[0].scale = FE_SCALE_COUNTER; 6623 c->block_count.stat[0].uvalue += pkt_count; 6624 6625 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; 6626 c->pre_bit_error.stat[0].uvalue += pre_bit_err_count; 6627 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; 6628 c->pre_bit_count.stat[0].uvalue += pre_bit_count; 6629 6630 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; 6631 c->post_bit_error.stat[0].uvalue += post_bit_err_count; 6632 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 6633 c->post_bit_count.stat[0].uvalue += post_bit_count; 6634 6635 error: 6636 return status; 6637 } 6638 6639 drxk_read_status(struct dvb_frontend * fe,enum fe_status * status)6640 static int drxk_read_status(struct dvb_frontend *fe, enum fe_status *status) 6641 { 6642 struct drxk_state *state = fe->demodulator_priv; 6643 int rc; 6644 6645 dprintk(1, "\n"); 6646 6647 rc = drxk_get_stats(fe); 6648 if (rc < 0) 6649 return rc; 6650 6651 *status = state->fe_status; 6652 6653 return 0; 6654 } 6655 drxk_read_signal_strength(struct dvb_frontend * fe,u16 * strength)6656 static int drxk_read_signal_strength(struct dvb_frontend *fe, 6657 u16 *strength) 6658 { 6659 struct drxk_state *state = fe->demodulator_priv; 6660 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 6661 6662 dprintk(1, "\n"); 6663 6664 if (state->m_drxk_state == DRXK_NO_DEV) 6665 return -ENODEV; 6666 if (state->m_drxk_state == DRXK_UNINITIALIZED) 6667 return -EAGAIN; 6668 6669 *strength = c->strength.stat[0].uvalue; 6670 return 0; 6671 } 6672 drxk_read_snr(struct dvb_frontend * fe,u16 * snr)6673 static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr) 6674 { 6675 struct drxk_state *state = fe->demodulator_priv; 6676 s32 snr2; 6677 6678 dprintk(1, "\n"); 6679 6680 if (state->m_drxk_state == DRXK_NO_DEV) 6681 return -ENODEV; 6682 if (state->m_drxk_state == DRXK_UNINITIALIZED) 6683 return -EAGAIN; 6684 6685 get_signal_to_noise(state, &snr2); 6686 6687 /* No negative SNR, clip to zero */ 6688 if (snr2 < 0) 6689 snr2 = 0; 6690 *snr = snr2 & 0xffff; 6691 return 0; 6692 } 6693 drxk_read_ucblocks(struct dvb_frontend * fe,u32 * ucblocks)6694 static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 6695 { 6696 struct drxk_state *state = fe->demodulator_priv; 6697 u16 err; 6698 6699 dprintk(1, "\n"); 6700 6701 if (state->m_drxk_state == DRXK_NO_DEV) 6702 return -ENODEV; 6703 if (state->m_drxk_state == DRXK_UNINITIALIZED) 6704 return -EAGAIN; 6705 6706 dvbtqam_get_acc_pkt_err(state, &err); 6707 *ucblocks = (u32) err; 6708 return 0; 6709 } 6710 drxk_get_tune_settings(struct dvb_frontend * fe,struct dvb_frontend_tune_settings * sets)6711 static int drxk_get_tune_settings(struct dvb_frontend *fe, 6712 struct dvb_frontend_tune_settings *sets) 6713 { 6714 struct drxk_state *state = fe->demodulator_priv; 6715 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 6716 6717 dprintk(1, "\n"); 6718 6719 if (state->m_drxk_state == DRXK_NO_DEV) 6720 return -ENODEV; 6721 if (state->m_drxk_state == DRXK_UNINITIALIZED) 6722 return -EAGAIN; 6723 6724 switch (p->delivery_system) { 6725 case SYS_DVBC_ANNEX_A: 6726 case SYS_DVBC_ANNEX_C: 6727 case SYS_DVBT: 6728 sets->min_delay_ms = 3000; 6729 sets->max_drift = 0; 6730 sets->step_size = 0; 6731 return 0; 6732 default: 6733 return -EINVAL; 6734 } 6735 } 6736 6737 static const struct dvb_frontend_ops drxk_ops = { 6738 /* .delsys will be filled dynamically */ 6739 .info = { 6740 .name = "DRXK", 6741 .frequency_min_hz = 47 * MHz, 6742 .frequency_max_hz = 865 * MHz, 6743 /* For DVB-C */ 6744 .symbol_rate_min = 870000, 6745 .symbol_rate_max = 11700000, 6746 /* For DVB-T */ 6747 .frequency_stepsize_hz = 166667, 6748 6749 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | 6750 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO | 6751 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 6752 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS | 6753 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER | 6754 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO 6755 }, 6756 6757 .release = drxk_release, 6758 .sleep = drxk_sleep, 6759 .i2c_gate_ctrl = drxk_gate_ctrl, 6760 6761 .set_frontend = drxk_set_parameters, 6762 .get_tune_settings = drxk_get_tune_settings, 6763 6764 .read_status = drxk_read_status, 6765 .read_signal_strength = drxk_read_signal_strength, 6766 .read_snr = drxk_read_snr, 6767 .read_ucblocks = drxk_read_ucblocks, 6768 }; 6769 drxk_attach(const struct drxk_config * config,struct i2c_adapter * i2c)6770 struct dvb_frontend *drxk_attach(const struct drxk_config *config, 6771 struct i2c_adapter *i2c) 6772 { 6773 struct dtv_frontend_properties *p; 6774 struct drxk_state *state = NULL; 6775 u8 adr = config->adr; 6776 int status; 6777 6778 dprintk(1, "\n"); 6779 state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL); 6780 if (!state) 6781 return NULL; 6782 6783 state->i2c = i2c; 6784 state->demod_address = adr; 6785 state->single_master = config->single_master; 6786 state->microcode_name = config->microcode_name; 6787 state->qam_demod_parameter_count = config->qam_demod_parameter_count; 6788 state->no_i2c_bridge = config->no_i2c_bridge; 6789 state->antenna_gpio = config->antenna_gpio; 6790 state->antenna_dvbt = config->antenna_dvbt; 6791 state->m_chunk_size = config->chunk_size; 6792 state->enable_merr_cfg = config->enable_merr_cfg; 6793 6794 if (config->dynamic_clk) { 6795 state->m_dvbt_static_clk = false; 6796 state->m_dvbc_static_clk = false; 6797 } else { 6798 state->m_dvbt_static_clk = true; 6799 state->m_dvbc_static_clk = true; 6800 } 6801 6802 6803 if (config->mpeg_out_clk_strength) 6804 state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07; 6805 else 6806 state->m_ts_clockk_strength = 0x06; 6807 6808 if (config->parallel_ts) 6809 state->m_enable_parallel = true; 6810 else 6811 state->m_enable_parallel = false; 6812 6813 /* NOTE: as more UIO bits will be used, add them to the mask */ 6814 state->uio_mask = config->antenna_gpio; 6815 6816 /* Default gpio to DVB-C */ 6817 if (!state->antenna_dvbt && state->antenna_gpio) 6818 state->m_gpio |= state->antenna_gpio; 6819 else 6820 state->m_gpio &= ~state->antenna_gpio; 6821 6822 mutex_init(&state->mutex); 6823 6824 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops)); 6825 state->frontend.demodulator_priv = state; 6826 6827 init_state(state); 6828 6829 /* Load firmware and initialize DRX-K */ 6830 if (state->microcode_name) { 6831 const struct firmware *fw = NULL; 6832 6833 status = request_firmware(&fw, state->microcode_name, 6834 state->i2c->dev.parent); 6835 if (status < 0) 6836 fw = NULL; 6837 load_firmware_cb(fw, state); 6838 } else if (init_drxk(state) < 0) 6839 goto error; 6840 6841 6842 /* Initialize stats */ 6843 p = &state->frontend.dtv_property_cache; 6844 p->strength.len = 1; 6845 p->cnr.len = 1; 6846 p->block_error.len = 1; 6847 p->block_count.len = 1; 6848 p->pre_bit_error.len = 1; 6849 p->pre_bit_count.len = 1; 6850 p->post_bit_error.len = 1; 6851 p->post_bit_count.len = 1; 6852 6853 p->strength.stat[0].scale = FE_SCALE_RELATIVE; 6854 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6855 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6856 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6857 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6858 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6859 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6860 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 6861 6862 pr_info("frontend initialized.\n"); 6863 return &state->frontend; 6864 6865 error: 6866 pr_err("not found\n"); 6867 kfree(state); 6868 return NULL; 6869 } 6870 EXPORT_SYMBOL(drxk_attach); 6871 6872 MODULE_DESCRIPTION("DRX-K driver"); 6873 MODULE_AUTHOR("Ralph Metzler"); 6874 MODULE_LICENSE("GPL"); 6875
