1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4 #include "ixgbe.h"
5 #include <linux/ptp_classify.h>
6 #include <linux/clocksource.h>
7
8 /*
9 * The 82599 and the X540 do not have true 64bit nanosecond scale
10 * counter registers. Instead, SYSTIME is defined by a fixed point
11 * system which allows the user to define the scale counter increment
12 * value at every level change of the oscillator driving the SYSTIME
13 * value. For both devices the TIMINCA:IV field defines this
14 * increment. On the X540 device, 31 bits are provided. However on the
15 * 82599 only provides 24 bits. The time unit is determined by the
16 * clock frequency of the oscillator in combination with the TIMINCA
17 * register. When these devices link at 10Gb the oscillator has a
18 * period of 6.4ns. In order to convert the scale counter into
19 * nanoseconds the cyclecounter and timecounter structures are
20 * used. The SYSTIME registers need to be converted to ns values by use
21 * of only a right shift (division by power of 2). The following math
22 * determines the largest incvalue that will fit into the available
23 * bits in the TIMINCA register.
24 *
25 * PeriodWidth: Number of bits to store the clock period
26 * MaxWidth: The maximum width value of the TIMINCA register
27 * Period: The clock period for the oscillator
28 * round(): discard the fractional portion of the calculation
29 *
30 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
31 *
32 * For the X540, MaxWidth is 31 bits, and the base period is 6.4 ns
33 * For the 82599, MaxWidth is 24 bits, and the base period is 6.4 ns
34 *
35 * The period also changes based on the link speed:
36 * At 10Gb link or no link, the period remains the same.
37 * At 1Gb link, the period is multiplied by 10. (64ns)
38 * At 100Mb link, the period is multiplied by 100. (640ns)
39 *
40 * The calculated value allows us to right shift the SYSTIME register
41 * value in order to quickly convert it into a nanosecond clock,
42 * while allowing for the maximum possible adjustment value.
43 *
44 * These diagrams are only for the 10Gb link period
45 *
46 * SYSTIMEH SYSTIMEL
47 * +--------------+ +--------------+
48 * X540 | 32 | | 1 | 3 | 28 |
49 * *--------------+ +--------------+
50 * \________ 36 bits ______/ fract
51 *
52 * +--------------+ +--------------+
53 * 82599 | 32 | | 8 | 3 | 21 |
54 * *--------------+ +--------------+
55 * \________ 43 bits ______/ fract
56 *
57 * The 36 bit X540 SYSTIME overflows every
58 * 2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds
59 *
60 * The 43 bit 82599 SYSTIME overflows every
61 * 2^43 * 10^-9 / 3600 = 2.4 hours
62 */
63 #define IXGBE_INCVAL_10GB 0x66666666
64 #define IXGBE_INCVAL_1GB 0x40000000
65 #define IXGBE_INCVAL_100 0x50000000
66
67 #define IXGBE_INCVAL_SHIFT_10GB 28
68 #define IXGBE_INCVAL_SHIFT_1GB 24
69 #define IXGBE_INCVAL_SHIFT_100 21
70
71 #define IXGBE_INCVAL_SHIFT_82599 7
72 #define IXGBE_INCPER_SHIFT_82599 24
73
74 #define IXGBE_OVERFLOW_PERIOD (HZ * 30)
75 #define IXGBE_PTP_TX_TIMEOUT (HZ * 15)
76
77 /* half of a one second clock period, for use with PPS signal. We have to use
78 * this instead of something pre-defined like IXGBE_PTP_PPS_HALF_SECOND, in
79 * order to force at least 64bits of precision for shifting
80 */
81 #define IXGBE_PTP_PPS_HALF_SECOND 500000000ULL
82
83 /* In contrast, the X550 controller has two registers, SYSTIMEH and SYSTIMEL
84 * which contain measurements of seconds and nanoseconds respectively. This
85 * matches the standard linux representation of time in the kernel. In addition,
86 * the X550 also has a SYSTIMER register which represents residue, or
87 * subnanosecond overflow adjustments. To control clock adjustment, the TIMINCA
88 * register is used, but it is unlike the X540 and 82599 devices. TIMINCA
89 * represents units of 2^-32 nanoseconds, and uses 31 bits for this, with the
90 * high bit representing whether the adjustent is positive or negative. Every
91 * clock cycle, the X550 will add 12.5 ns + TIMINCA which can result in a range
92 * of 12 to 13 nanoseconds adjustment. Unlike the 82599 and X540 devices, the
93 * X550's clock for purposes of SYSTIME generation is constant and not dependent
94 * on the link speed.
95 *
96 * SYSTIMEH SYSTIMEL SYSTIMER
97 * +--------------+ +--------------+ +-------------+
98 * X550 | 32 | | 32 | | 32 |
99 * *--------------+ +--------------+ +-------------+
100 * \____seconds___/ \_nanoseconds_/ \__2^-32 ns__/
101 *
102 * This results in a full 96 bits to represent the clock, with 32 bits for
103 * seconds, 32 bits for nanoseconds (largest value is 0d999999999 or just under
104 * 1 second) and an additional 32 bits to measure sub nanosecond adjustments for
105 * underflow of adjustments.
106 *
107 * The 32 bits of seconds for the X550 overflows every
108 * 2^32 / ( 365.25 * 24 * 60 * 60 ) = ~136 years.
109 *
110 * In order to adjust the clock frequency for the X550, the TIMINCA register is
111 * provided. This register represents a + or minus nearly 0.5 ns adjustment to
112 * the base frequency. It is measured in 2^-32 ns units, with the high bit being
113 * the sign bit. This register enables software to calculate frequency
114 * adjustments and apply them directly to the clock rate.
115 *
116 * The math for converting ppb into TIMINCA values is fairly straightforward.
117 * TIMINCA value = ( Base_Frequency * ppb ) / 1000000000ULL
118 *
119 * This assumes that ppb is never high enough to create a value bigger than
120 * TIMINCA's 31 bits can store. This is ensured by the stack. Calculating this
121 * value is also simple.
122 * Max ppb = ( Max Adjustment / Base Frequency ) / 1000000000ULL
123 *
124 * For the X550, the Max adjustment is +/- 0.5 ns, and the base frequency is
125 * 12.5 nanoseconds. This means that the Max ppb is 39999999
126 * Note: We subtract one in order to ensure no overflow, because the TIMINCA
127 * register can only hold slightly under 0.5 nanoseconds.
128 *
129 * Because TIMINCA is measured in 2^-32 ns units, we have to convert 12.5 ns
130 * into 2^-32 units, which is
131 *
132 * 12.5 * 2^32 = C80000000
133 *
134 * Some revisions of hardware have a faster base frequency than the registers
135 * were defined for. To fix this, we use a timecounter structure with the
136 * proper mult and shift to convert the cycles into nanoseconds of time.
137 */
138 #define IXGBE_X550_BASE_PERIOD 0xC80000000ULL
139 #define INCVALUE_MASK 0x7FFFFFFF
140 #define ISGN 0x80000000
141 #define MAX_TIMADJ 0x7FFFFFFF
142
143 /**
144 * ixgbe_ptp_setup_sdp_x540
145 * @adapter: private adapter structure
146 *
147 * this function enables or disables the clock out feature on SDP0 for
148 * the X540 device. It will create a 1second periodic output that can
149 * be used as the PPS (via an interrupt).
150 *
151 * It calculates when the systime will be on an exact second, and then
152 * aligns the start of the PPS signal to that value. The shift is
153 * necessary because it can change based on the link speed.
154 */
ixgbe_ptp_setup_sdp_x540(struct ixgbe_adapter * adapter)155 static void ixgbe_ptp_setup_sdp_x540(struct ixgbe_adapter *adapter)
156 {
157 struct ixgbe_hw *hw = &adapter->hw;
158 int shift = adapter->hw_cc.shift;
159 u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem;
160 u64 ns = 0, clock_edge = 0;
161
162 /* disable the pin first */
163 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
164 IXGBE_WRITE_FLUSH(hw);
165
166 if (!(adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED))
167 return;
168
169 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
170
171 /* enable the SDP0 pin as output, and connected to the
172 * native function for Timesync (ClockOut)
173 */
174 esdp |= IXGBE_ESDP_SDP0_DIR |
175 IXGBE_ESDP_SDP0_NATIVE;
176
177 /* enable the Clock Out feature on SDP0, and allow
178 * interrupts to occur when the pin changes
179 */
180 tsauxc = IXGBE_TSAUXC_EN_CLK |
181 IXGBE_TSAUXC_SYNCLK |
182 IXGBE_TSAUXC_SDP0_INT;
183
184 /* clock period (or pulse length) */
185 clktiml = (u32)(IXGBE_PTP_PPS_HALF_SECOND << shift);
186 clktimh = (u32)((IXGBE_PTP_PPS_HALF_SECOND << shift) >> 32);
187
188 /* Account for the cyclecounter wrap-around value by
189 * using the converted ns value of the current time to
190 * check for when the next aligned second would occur.
191 */
192 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
193 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
194 ns = timecounter_cyc2time(&adapter->hw_tc, clock_edge);
195
196 div_u64_rem(ns, IXGBE_PTP_PPS_HALF_SECOND, &rem);
197 clock_edge += ((IXGBE_PTP_PPS_HALF_SECOND - (u64)rem) << shift);
198
199 /* specify the initial clock start time */
200 trgttiml = (u32)clock_edge;
201 trgttimh = (u32)(clock_edge >> 32);
202
203 IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
204 IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
205 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
206 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
207
208 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
209 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
210
211 IXGBE_WRITE_FLUSH(hw);
212 }
213
214 /**
215 * ixgbe_ptp_read_X550 - read cycle counter value
216 * @hw_cc: cyclecounter structure
217 *
218 * This function reads SYSTIME registers. It is called by the cyclecounter
219 * structure to convert from internal representation into nanoseconds. We need
220 * this for X550 since some skews do not have expected clock frequency and
221 * result of SYSTIME is 32bits of "billions of cycles" and 32 bits of
222 * "cycles", rather than seconds and nanoseconds.
223 */
ixgbe_ptp_read_X550(const struct cyclecounter * hw_cc)224 static u64 ixgbe_ptp_read_X550(const struct cyclecounter *hw_cc)
225 {
226 struct ixgbe_adapter *adapter =
227 container_of(hw_cc, struct ixgbe_adapter, hw_cc);
228 struct ixgbe_hw *hw = &adapter->hw;
229 struct timespec64 ts;
230
231 /* storage is 32 bits of 'billions of cycles' and 32 bits of 'cycles'.
232 * Some revisions of hardware run at a higher frequency and so the
233 * cycles are not guaranteed to be nanoseconds. The timespec64 created
234 * here is used for its math/conversions but does not necessarily
235 * represent nominal time.
236 *
237 * It should be noted that this cyclecounter will overflow at a
238 * non-bitmask field since we have to convert our billions of cycles
239 * into an actual cycles count. This results in some possible weird
240 * situations at high cycle counter stamps. However given that 32 bits
241 * of "seconds" is ~138 years this isn't a problem. Even at the
242 * increased frequency of some revisions, this is still ~103 years.
243 * Since the SYSTIME values start at 0 and we never write them, it is
244 * highly unlikely for the cyclecounter to overflow in practice.
245 */
246 IXGBE_READ_REG(hw, IXGBE_SYSTIMR);
247 ts.tv_nsec = IXGBE_READ_REG(hw, IXGBE_SYSTIML);
248 ts.tv_sec = IXGBE_READ_REG(hw, IXGBE_SYSTIMH);
249
250 return (u64)timespec64_to_ns(&ts);
251 }
252
253 /**
254 * ixgbe_ptp_read_82599 - read raw cycle counter (to be used by time counter)
255 * @cc: the cyclecounter structure
256 *
257 * this function reads the cyclecounter registers and is called by the
258 * cyclecounter structure used to construct a ns counter from the
259 * arbitrary fixed point registers
260 */
ixgbe_ptp_read_82599(const struct cyclecounter * cc)261 static u64 ixgbe_ptp_read_82599(const struct cyclecounter *cc)
262 {
263 struct ixgbe_adapter *adapter =
264 container_of(cc, struct ixgbe_adapter, hw_cc);
265 struct ixgbe_hw *hw = &adapter->hw;
266 u64 stamp = 0;
267
268 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
269 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
270
271 return stamp;
272 }
273
274 /**
275 * ixgbe_ptp_convert_to_hwtstamp - convert register value to hw timestamp
276 * @adapter: private adapter structure
277 * @hwtstamp: stack timestamp structure
278 * @timestamp: unsigned 64bit system time value
279 *
280 * We need to convert the adapter's RX/TXSTMP registers into a hwtstamp value
281 * which can be used by the stack's ptp functions.
282 *
283 * The lock is used to protect consistency of the cyclecounter and the SYSTIME
284 * registers. However, it does not need to protect against the Rx or Tx
285 * timestamp registers, as there can't be a new timestamp until the old one is
286 * unlatched by reading.
287 *
288 * In addition to the timestamp in hardware, some controllers need a software
289 * overflow cyclecounter, and this function takes this into account as well.
290 **/
ixgbe_ptp_convert_to_hwtstamp(struct ixgbe_adapter * adapter,struct skb_shared_hwtstamps * hwtstamp,u64 timestamp)291 static void ixgbe_ptp_convert_to_hwtstamp(struct ixgbe_adapter *adapter,
292 struct skb_shared_hwtstamps *hwtstamp,
293 u64 timestamp)
294 {
295 unsigned long flags;
296 struct timespec64 systime;
297 u64 ns;
298
299 memset(hwtstamp, 0, sizeof(*hwtstamp));
300
301 switch (adapter->hw.mac.type) {
302 /* X550 and later hardware supposedly represent time using a seconds
303 * and nanoseconds counter, instead of raw 64bits nanoseconds. We need
304 * to convert the timestamp into cycles before it can be fed to the
305 * cyclecounter. We need an actual cyclecounter because some revisions
306 * of hardware run at a higher frequency and thus the counter does
307 * not represent seconds/nanoseconds. Instead it can be thought of as
308 * cycles and billions of cycles.
309 */
310 case ixgbe_mac_X550:
311 case ixgbe_mac_X550EM_x:
312 case ixgbe_mac_x550em_a:
313 /* Upper 32 bits represent billions of cycles, lower 32 bits
314 * represent cycles. However, we use timespec64_to_ns for the
315 * correct math even though the units haven't been corrected
316 * yet.
317 */
318 systime.tv_sec = timestamp >> 32;
319 systime.tv_nsec = timestamp & 0xFFFFFFFF;
320
321 timestamp = timespec64_to_ns(&systime);
322 break;
323 default:
324 break;
325 }
326
327 spin_lock_irqsave(&adapter->tmreg_lock, flags);
328 ns = timecounter_cyc2time(&adapter->hw_tc, timestamp);
329 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
330
331 hwtstamp->hwtstamp = ns_to_ktime(ns);
332 }
333
334 /**
335 * ixgbe_ptp_adjfreq_82599
336 * @ptp: the ptp clock structure
337 * @ppb: parts per billion adjustment from base
338 *
339 * adjust the frequency of the ptp cycle counter by the
340 * indicated ppb from the base frequency.
341 */
ixgbe_ptp_adjfreq_82599(struct ptp_clock_info * ptp,s32 ppb)342 static int ixgbe_ptp_adjfreq_82599(struct ptp_clock_info *ptp, s32 ppb)
343 {
344 struct ixgbe_adapter *adapter =
345 container_of(ptp, struct ixgbe_adapter, ptp_caps);
346 struct ixgbe_hw *hw = &adapter->hw;
347 u64 freq, incval;
348 u32 diff;
349 int neg_adj = 0;
350
351 if (ppb < 0) {
352 neg_adj = 1;
353 ppb = -ppb;
354 }
355
356 smp_mb();
357 incval = READ_ONCE(adapter->base_incval);
358
359 freq = incval;
360 freq *= ppb;
361 diff = div_u64(freq, 1000000000ULL);
362
363 incval = neg_adj ? (incval - diff) : (incval + diff);
364
365 switch (hw->mac.type) {
366 case ixgbe_mac_X540:
367 if (incval > 0xFFFFFFFFULL)
368 e_dev_warn("PTP ppb adjusted SYSTIME rate overflowed!\n");
369 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, (u32)incval);
370 break;
371 case ixgbe_mac_82599EB:
372 if (incval > 0x00FFFFFFULL)
373 e_dev_warn("PTP ppb adjusted SYSTIME rate overflowed!\n");
374 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
375 BIT(IXGBE_INCPER_SHIFT_82599) |
376 ((u32)incval & 0x00FFFFFFUL));
377 break;
378 default:
379 break;
380 }
381
382 return 0;
383 }
384
385 /**
386 * ixgbe_ptp_adjfreq_X550
387 * @ptp: the ptp clock structure
388 * @ppb: parts per billion adjustment from base
389 *
390 * adjust the frequency of the SYSTIME registers by the indicated ppb from base
391 * frequency
392 */
ixgbe_ptp_adjfreq_X550(struct ptp_clock_info * ptp,s32 ppb)393 static int ixgbe_ptp_adjfreq_X550(struct ptp_clock_info *ptp, s32 ppb)
394 {
395 struct ixgbe_adapter *adapter =
396 container_of(ptp, struct ixgbe_adapter, ptp_caps);
397 struct ixgbe_hw *hw = &adapter->hw;
398 int neg_adj = 0;
399 u64 rate = IXGBE_X550_BASE_PERIOD;
400 u32 inca;
401
402 if (ppb < 0) {
403 neg_adj = 1;
404 ppb = -ppb;
405 }
406 rate *= ppb;
407 rate = div_u64(rate, 1000000000ULL);
408
409 /* warn if rate is too large */
410 if (rate >= INCVALUE_MASK)
411 e_dev_warn("PTP ppb adjusted SYSTIME rate overflowed!\n");
412
413 inca = rate & INCVALUE_MASK;
414 if (neg_adj)
415 inca |= ISGN;
416
417 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, inca);
418
419 return 0;
420 }
421
422 /**
423 * ixgbe_ptp_adjtime
424 * @ptp: the ptp clock structure
425 * @delta: offset to adjust the cycle counter by
426 *
427 * adjust the timer by resetting the timecounter structure.
428 */
ixgbe_ptp_adjtime(struct ptp_clock_info * ptp,s64 delta)429 static int ixgbe_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
430 {
431 struct ixgbe_adapter *adapter =
432 container_of(ptp, struct ixgbe_adapter, ptp_caps);
433 unsigned long flags;
434
435 spin_lock_irqsave(&adapter->tmreg_lock, flags);
436 timecounter_adjtime(&adapter->hw_tc, delta);
437 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
438
439 if (adapter->ptp_setup_sdp)
440 adapter->ptp_setup_sdp(adapter);
441
442 return 0;
443 }
444
445 /**
446 * ixgbe_ptp_gettime
447 * @ptp: the ptp clock structure
448 * @ts: timespec structure to hold the current time value
449 *
450 * read the timecounter and return the correct value on ns,
451 * after converting it into a struct timespec.
452 */
ixgbe_ptp_gettime(struct ptp_clock_info * ptp,struct timespec64 * ts)453 static int ixgbe_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
454 {
455 struct ixgbe_adapter *adapter =
456 container_of(ptp, struct ixgbe_adapter, ptp_caps);
457 unsigned long flags;
458 u64 ns;
459
460 spin_lock_irqsave(&adapter->tmreg_lock, flags);
461 ns = timecounter_read(&adapter->hw_tc);
462 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
463
464 *ts = ns_to_timespec64(ns);
465
466 return 0;
467 }
468
469 /**
470 * ixgbe_ptp_settime
471 * @ptp: the ptp clock structure
472 * @ts: the timespec containing the new time for the cycle counter
473 *
474 * reset the timecounter to use a new base value instead of the kernel
475 * wall timer value.
476 */
ixgbe_ptp_settime(struct ptp_clock_info * ptp,const struct timespec64 * ts)477 static int ixgbe_ptp_settime(struct ptp_clock_info *ptp,
478 const struct timespec64 *ts)
479 {
480 struct ixgbe_adapter *adapter =
481 container_of(ptp, struct ixgbe_adapter, ptp_caps);
482 unsigned long flags;
483 u64 ns = timespec64_to_ns(ts);
484
485 /* reset the timecounter */
486 spin_lock_irqsave(&adapter->tmreg_lock, flags);
487 timecounter_init(&adapter->hw_tc, &adapter->hw_cc, ns);
488 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
489
490 if (adapter->ptp_setup_sdp)
491 adapter->ptp_setup_sdp(adapter);
492 return 0;
493 }
494
495 /**
496 * ixgbe_ptp_feature_enable
497 * @ptp: the ptp clock structure
498 * @rq: the requested feature to change
499 * @on: whether to enable or disable the feature
500 *
501 * enable (or disable) ancillary features of the phc subsystem.
502 * our driver only supports the PPS feature on the X540
503 */
ixgbe_ptp_feature_enable(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)504 static int ixgbe_ptp_feature_enable(struct ptp_clock_info *ptp,
505 struct ptp_clock_request *rq, int on)
506 {
507 struct ixgbe_adapter *adapter =
508 container_of(ptp, struct ixgbe_adapter, ptp_caps);
509
510 /**
511 * When PPS is enabled, unmask the interrupt for the ClockOut
512 * feature, so that the interrupt handler can send the PPS
513 * event when the clock SDP triggers. Clear mask when PPS is
514 * disabled
515 */
516 if (rq->type != PTP_CLK_REQ_PPS || !adapter->ptp_setup_sdp)
517 return -ENOTSUPP;
518
519 if (on)
520 adapter->flags2 |= IXGBE_FLAG2_PTP_PPS_ENABLED;
521 else
522 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
523
524 adapter->ptp_setup_sdp(adapter);
525 return 0;
526 }
527
528 /**
529 * ixgbe_ptp_check_pps_event
530 * @adapter: the private adapter structure
531 *
532 * This function is called by the interrupt routine when checking for
533 * interrupts. It will check and handle a pps event.
534 */
ixgbe_ptp_check_pps_event(struct ixgbe_adapter * adapter)535 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter)
536 {
537 struct ixgbe_hw *hw = &adapter->hw;
538 struct ptp_clock_event event;
539
540 event.type = PTP_CLOCK_PPS;
541
542 /* this check is necessary in case the interrupt was enabled via some
543 * alternative means (ex. debug_fs). Better to check here than
544 * everywhere that calls this function.
545 */
546 if (!adapter->ptp_clock)
547 return;
548
549 switch (hw->mac.type) {
550 case ixgbe_mac_X540:
551 ptp_clock_event(adapter->ptp_clock, &event);
552 break;
553 default:
554 break;
555 }
556 }
557
558 /**
559 * ixgbe_ptp_overflow_check - watchdog task to detect SYSTIME overflow
560 * @adapter: private adapter struct
561 *
562 * this watchdog task periodically reads the timecounter
563 * in order to prevent missing when the system time registers wrap
564 * around. This needs to be run approximately twice a minute.
565 */
ixgbe_ptp_overflow_check(struct ixgbe_adapter * adapter)566 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter)
567 {
568 bool timeout = time_is_before_jiffies(adapter->last_overflow_check +
569 IXGBE_OVERFLOW_PERIOD);
570 struct timespec64 ts;
571
572 if (timeout) {
573 ixgbe_ptp_gettime(&adapter->ptp_caps, &ts);
574 adapter->last_overflow_check = jiffies;
575 }
576 }
577
578 /**
579 * ixgbe_ptp_rx_hang - detect error case when Rx timestamp registers latched
580 * @adapter: private network adapter structure
581 *
582 * this watchdog task is scheduled to detect error case where hardware has
583 * dropped an Rx packet that was timestamped when the ring is full. The
584 * particular error is rare but leaves the device in a state unable to timestamp
585 * any future packets.
586 */
ixgbe_ptp_rx_hang(struct ixgbe_adapter * adapter)587 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter)
588 {
589 struct ixgbe_hw *hw = &adapter->hw;
590 u32 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
591 struct ixgbe_ring *rx_ring;
592 unsigned long rx_event;
593 int n;
594
595 /* if we don't have a valid timestamp in the registers, just update the
596 * timeout counter and exit
597 */
598 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID)) {
599 adapter->last_rx_ptp_check = jiffies;
600 return;
601 }
602
603 /* determine the most recent watchdog or rx_timestamp event */
604 rx_event = adapter->last_rx_ptp_check;
605 for (n = 0; n < adapter->num_rx_queues; n++) {
606 rx_ring = adapter->rx_ring[n];
607 if (time_after(rx_ring->last_rx_timestamp, rx_event))
608 rx_event = rx_ring->last_rx_timestamp;
609 }
610
611 /* only need to read the high RXSTMP register to clear the lock */
612 if (time_is_before_jiffies(rx_event + 5 * HZ)) {
613 IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
614 adapter->last_rx_ptp_check = jiffies;
615
616 adapter->rx_hwtstamp_cleared++;
617 e_warn(drv, "clearing RX Timestamp hang\n");
618 }
619 }
620
621 /**
622 * ixgbe_ptp_clear_tx_timestamp - utility function to clear Tx timestamp state
623 * @adapter: the private adapter structure
624 *
625 * This function should be called whenever the state related to a Tx timestamp
626 * needs to be cleared. This helps ensure that all related bits are reset for
627 * the next Tx timestamp event.
628 */
ixgbe_ptp_clear_tx_timestamp(struct ixgbe_adapter * adapter)629 static void ixgbe_ptp_clear_tx_timestamp(struct ixgbe_adapter *adapter)
630 {
631 struct ixgbe_hw *hw = &adapter->hw;
632
633 IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
634 if (adapter->ptp_tx_skb) {
635 dev_kfree_skb_any(adapter->ptp_tx_skb);
636 adapter->ptp_tx_skb = NULL;
637 }
638 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
639 }
640
641 /**
642 * ixgbe_ptp_tx_hang - detect error case where Tx timestamp never finishes
643 * @adapter: private network adapter structure
644 */
ixgbe_ptp_tx_hang(struct ixgbe_adapter * adapter)645 void ixgbe_ptp_tx_hang(struct ixgbe_adapter *adapter)
646 {
647 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
648 IXGBE_PTP_TX_TIMEOUT);
649
650 if (!adapter->ptp_tx_skb)
651 return;
652
653 if (!test_bit(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state))
654 return;
655
656 /* If we haven't received a timestamp within the timeout, it is
657 * reasonable to assume that it will never occur, so we can unlock the
658 * timestamp bit when this occurs.
659 */
660 if (timeout) {
661 cancel_work_sync(&adapter->ptp_tx_work);
662 ixgbe_ptp_clear_tx_timestamp(adapter);
663 adapter->tx_hwtstamp_timeouts++;
664 e_warn(drv, "clearing Tx timestamp hang\n");
665 }
666 }
667
668 /**
669 * ixgbe_ptp_tx_hwtstamp - utility function which checks for TX time stamp
670 * @adapter: the private adapter struct
671 *
672 * if the timestamp is valid, we convert it into the timecounter ns
673 * value, then store that result into the shhwtstamps structure which
674 * is passed up the network stack
675 */
ixgbe_ptp_tx_hwtstamp(struct ixgbe_adapter * adapter)676 static void ixgbe_ptp_tx_hwtstamp(struct ixgbe_adapter *adapter)
677 {
678 struct sk_buff *skb = adapter->ptp_tx_skb;
679 struct ixgbe_hw *hw = &adapter->hw;
680 struct skb_shared_hwtstamps shhwtstamps;
681 u64 regval = 0;
682
683 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
684 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32;
685 ixgbe_ptp_convert_to_hwtstamp(adapter, &shhwtstamps, regval);
686
687 /* Handle cleanup of the ptp_tx_skb ourselves, and unlock the state
688 * bit prior to notifying the stack via skb_tstamp_tx(). This prevents
689 * well behaved applications from attempting to timestamp again prior
690 * to the lock bit being clear.
691 */
692 adapter->ptp_tx_skb = NULL;
693 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
694
695 /* Notify the stack and then free the skb after we've unlocked */
696 skb_tstamp_tx(skb, &shhwtstamps);
697 dev_kfree_skb_any(skb);
698 }
699
700 /**
701 * ixgbe_ptp_tx_hwtstamp_work
702 * @work: pointer to the work struct
703 *
704 * This work item polls TSYNCTXCTL valid bit to determine when a Tx hardware
705 * timestamp has been taken for the current skb. It is necessary, because the
706 * descriptor's "done" bit does not correlate with the timestamp event.
707 */
ixgbe_ptp_tx_hwtstamp_work(struct work_struct * work)708 static void ixgbe_ptp_tx_hwtstamp_work(struct work_struct *work)
709 {
710 struct ixgbe_adapter *adapter = container_of(work, struct ixgbe_adapter,
711 ptp_tx_work);
712 struct ixgbe_hw *hw = &adapter->hw;
713 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
714 IXGBE_PTP_TX_TIMEOUT);
715 u32 tsynctxctl;
716
717 /* we have to have a valid skb to poll for a timestamp */
718 if (!adapter->ptp_tx_skb) {
719 ixgbe_ptp_clear_tx_timestamp(adapter);
720 return;
721 }
722
723 /* stop polling once we have a valid timestamp */
724 tsynctxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
725 if (tsynctxctl & IXGBE_TSYNCTXCTL_VALID) {
726 ixgbe_ptp_tx_hwtstamp(adapter);
727 return;
728 }
729
730 if (timeout) {
731 ixgbe_ptp_clear_tx_timestamp(adapter);
732 adapter->tx_hwtstamp_timeouts++;
733 e_warn(drv, "clearing Tx Timestamp hang\n");
734 } else {
735 /* reschedule to keep checking if it's not available yet */
736 schedule_work(&adapter->ptp_tx_work);
737 }
738 }
739
740 /**
741 * ixgbe_ptp_rx_pktstamp - utility function to get RX time stamp from buffer
742 * @q_vector: structure containing interrupt and ring information
743 * @skb: the packet
744 *
745 * This function will be called by the Rx routine of the timestamp for this
746 * packet is stored in the buffer. The value is stored in little endian format
747 * starting at the end of the packet data.
748 */
ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector * q_vector,struct sk_buff * skb)749 void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *q_vector,
750 struct sk_buff *skb)
751 {
752 __le64 regval;
753
754 /* copy the bits out of the skb, and then trim the skb length */
755 skb_copy_bits(skb, skb->len - IXGBE_TS_HDR_LEN, ®val,
756 IXGBE_TS_HDR_LEN);
757 __pskb_trim(skb, skb->len - IXGBE_TS_HDR_LEN);
758
759 /* The timestamp is recorded in little endian format, and is stored at
760 * the end of the packet.
761 *
762 * DWORD: N N + 1 N + 2
763 * Field: End of Packet SYSTIMH SYSTIML
764 */
765 ixgbe_ptp_convert_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb),
766 le64_to_cpu(regval));
767 }
768
769 /**
770 * ixgbe_ptp_rx_rgtstamp - utility function which checks for RX time stamp
771 * @q_vector: structure containing interrupt and ring information
772 * @skb: particular skb to send timestamp with
773 *
774 * if the timestamp is valid, we convert it into the timecounter ns
775 * value, then store that result into the shhwtstamps structure which
776 * is passed up the network stack
777 */
ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector * q_vector,struct sk_buff * skb)778 void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *q_vector,
779 struct sk_buff *skb)
780 {
781 struct ixgbe_adapter *adapter;
782 struct ixgbe_hw *hw;
783 u64 regval = 0;
784 u32 tsyncrxctl;
785
786 /* we cannot process timestamps on a ring without a q_vector */
787 if (!q_vector || !q_vector->adapter)
788 return;
789
790 adapter = q_vector->adapter;
791 hw = &adapter->hw;
792
793 /* Read the tsyncrxctl register afterwards in order to prevent taking an
794 * I/O hit on every packet.
795 */
796
797 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
798 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID))
799 return;
800
801 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
802 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32;
803
804 ixgbe_ptp_convert_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
805 }
806
ixgbe_ptp_get_ts_config(struct ixgbe_adapter * adapter,struct ifreq * ifr)807 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
808 {
809 struct hwtstamp_config *config = &adapter->tstamp_config;
810
811 return copy_to_user(ifr->ifr_data, config,
812 sizeof(*config)) ? -EFAULT : 0;
813 }
814
815 /**
816 * ixgbe_ptp_set_timestamp_mode - setup the hardware for the requested mode
817 * @adapter: the private ixgbe adapter structure
818 * @config: the hwtstamp configuration requested
819 *
820 * Outgoing time stamping can be enabled and disabled. Play nice and
821 * disable it when requested, although it shouldn't cause any overhead
822 * when no packet needs it. At most one packet in the queue may be
823 * marked for time stamping, otherwise it would be impossible to tell
824 * for sure to which packet the hardware time stamp belongs.
825 *
826 * Incoming time stamping has to be configured via the hardware
827 * filters. Not all combinations are supported, in particular event
828 * type has to be specified. Matching the kind of event packet is
829 * not supported, with the exception of "all V2 events regardless of
830 * level 2 or 4".
831 *
832 * Since hardware always timestamps Path delay packets when timestamping V2
833 * packets, regardless of the type specified in the register, only use V2
834 * Event mode. This more accurately tells the user what the hardware is going
835 * to do anyways.
836 *
837 * Note: this may modify the hwtstamp configuration towards a more general
838 * mode, if required to support the specifically requested mode.
839 */
ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter * adapter,struct hwtstamp_config * config)840 static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter,
841 struct hwtstamp_config *config)
842 {
843 struct ixgbe_hw *hw = &adapter->hw;
844 u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED;
845 u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED;
846 u32 tsync_rx_mtrl = PTP_EV_PORT << 16;
847 bool is_l2 = false;
848 u32 regval;
849
850 /* reserved for future extensions */
851 if (config->flags)
852 return -EINVAL;
853
854 switch (config->tx_type) {
855 case HWTSTAMP_TX_OFF:
856 tsync_tx_ctl = 0;
857 case HWTSTAMP_TX_ON:
858 break;
859 default:
860 return -ERANGE;
861 }
862
863 switch (config->rx_filter) {
864 case HWTSTAMP_FILTER_NONE:
865 tsync_rx_ctl = 0;
866 tsync_rx_mtrl = 0;
867 adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
868 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
869 break;
870 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
871 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
872 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_SYNC_MSG;
873 adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
874 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
875 break;
876 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
877 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
878 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_DELAY_REQ_MSG;
879 adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
880 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
881 break;
882 case HWTSTAMP_FILTER_PTP_V2_EVENT:
883 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
884 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
885 case HWTSTAMP_FILTER_PTP_V2_SYNC:
886 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
887 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
888 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
889 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
890 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
891 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2;
892 is_l2 = true;
893 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
894 adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
895 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
896 break;
897 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
898 case HWTSTAMP_FILTER_NTP_ALL:
899 case HWTSTAMP_FILTER_ALL:
900 /* The X550 controller is capable of timestamping all packets,
901 * which allows it to accept any filter.
902 */
903 if (hw->mac.type >= ixgbe_mac_X550) {
904 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_ALL;
905 config->rx_filter = HWTSTAMP_FILTER_ALL;
906 adapter->flags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED;
907 break;
908 }
909 /* fall through */
910 default:
911 /*
912 * register RXMTRL must be set in order to do V1 packets,
913 * therefore it is not possible to time stamp both V1 Sync and
914 * Delay_Req messages and hardware does not support
915 * timestamping all packets => return error
916 */
917 adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
918 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
919 config->rx_filter = HWTSTAMP_FILTER_NONE;
920 return -ERANGE;
921 }
922
923 if (hw->mac.type == ixgbe_mac_82598EB) {
924 adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
925 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
926 if (tsync_rx_ctl | tsync_tx_ctl)
927 return -ERANGE;
928 return 0;
929 }
930
931 /* Per-packet timestamping only works if the filter is set to all
932 * packets. Since this is desired, always timestamp all packets as long
933 * as any Rx filter was configured.
934 */
935 switch (hw->mac.type) {
936 case ixgbe_mac_X550:
937 case ixgbe_mac_X550EM_x:
938 case ixgbe_mac_x550em_a:
939 /* enable timestamping all packets only if at least some
940 * packets were requested. Otherwise, play nice and disable
941 * timestamping
942 */
943 if (config->rx_filter == HWTSTAMP_FILTER_NONE)
944 break;
945
946 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED |
947 IXGBE_TSYNCRXCTL_TYPE_ALL |
948 IXGBE_TSYNCRXCTL_TSIP_UT_EN;
949 config->rx_filter = HWTSTAMP_FILTER_ALL;
950 adapter->flags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED;
951 adapter->flags &= ~IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER;
952 is_l2 = true;
953 break;
954 default:
955 break;
956 }
957
958 /* define ethertype filter for timestamping L2 packets */
959 if (is_l2)
960 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
961 (IXGBE_ETQF_FILTER_EN | /* enable filter */
962 IXGBE_ETQF_1588 | /* enable timestamping */
963 ETH_P_1588)); /* 1588 eth protocol type */
964 else
965 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
966
967 /* enable/disable TX */
968 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
969 regval &= ~IXGBE_TSYNCTXCTL_ENABLED;
970 regval |= tsync_tx_ctl;
971 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval);
972
973 /* enable/disable RX */
974 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
975 regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK);
976 regval |= tsync_rx_ctl;
977 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval);
978
979 /* define which PTP packets are time stamped */
980 IXGBE_WRITE_REG(hw, IXGBE_RXMTRL, tsync_rx_mtrl);
981
982 IXGBE_WRITE_FLUSH(hw);
983
984 /* clear TX/RX time stamp registers, just to be sure */
985 ixgbe_ptp_clear_tx_timestamp(adapter);
986 IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
987
988 return 0;
989 }
990
991 /**
992 * ixgbe_ptp_set_ts_config - user entry point for timestamp mode
993 * @adapter: pointer to adapter struct
994 * @ifr: ioctl data
995 *
996 * Set hardware to requested mode. If unsupported, return an error with no
997 * changes. Otherwise, store the mode for future reference.
998 */
ixgbe_ptp_set_ts_config(struct ixgbe_adapter * adapter,struct ifreq * ifr)999 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
1000 {
1001 struct hwtstamp_config config;
1002 int err;
1003
1004 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1005 return -EFAULT;
1006
1007 err = ixgbe_ptp_set_timestamp_mode(adapter, &config);
1008 if (err)
1009 return err;
1010
1011 /* save these settings for future reference */
1012 memcpy(&adapter->tstamp_config, &config,
1013 sizeof(adapter->tstamp_config));
1014
1015 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1016 -EFAULT : 0;
1017 }
1018
ixgbe_ptp_link_speed_adjust(struct ixgbe_adapter * adapter,u32 * shift,u32 * incval)1019 static void ixgbe_ptp_link_speed_adjust(struct ixgbe_adapter *adapter,
1020 u32 *shift, u32 *incval)
1021 {
1022 /**
1023 * Scale the NIC cycle counter by a large factor so that
1024 * relatively small corrections to the frequency can be added
1025 * or subtracted. The drawbacks of a large factor include
1026 * (a) the clock register overflows more quickly, (b) the cycle
1027 * counter structure must be able to convert the systime value
1028 * to nanoseconds using only a multiplier and a right-shift,
1029 * and (c) the value must fit within the timinca register space
1030 * => math based on internal DMA clock rate and available bits
1031 *
1032 * Note that when there is no link, internal DMA clock is same as when
1033 * link speed is 10Gb. Set the registers correctly even when link is
1034 * down to preserve the clock setting
1035 */
1036 switch (adapter->link_speed) {
1037 case IXGBE_LINK_SPEED_100_FULL:
1038 *shift = IXGBE_INCVAL_SHIFT_100;
1039 *incval = IXGBE_INCVAL_100;
1040 break;
1041 case IXGBE_LINK_SPEED_1GB_FULL:
1042 *shift = IXGBE_INCVAL_SHIFT_1GB;
1043 *incval = IXGBE_INCVAL_1GB;
1044 break;
1045 case IXGBE_LINK_SPEED_10GB_FULL:
1046 default:
1047 *shift = IXGBE_INCVAL_SHIFT_10GB;
1048 *incval = IXGBE_INCVAL_10GB;
1049 break;
1050 }
1051 }
1052
1053 /**
1054 * ixgbe_ptp_start_cyclecounter - create the cycle counter from hw
1055 * @adapter: pointer to the adapter structure
1056 *
1057 * This function should be called to set the proper values for the TIMINCA
1058 * register and tell the cyclecounter structure what the tick rate of SYSTIME
1059 * is. It does not directly modify SYSTIME registers or the timecounter
1060 * structure. It should be called whenever a new TIMINCA value is necessary,
1061 * such as during initialization or when the link speed changes.
1062 */
ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter * adapter)1063 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter)
1064 {
1065 struct ixgbe_hw *hw = &adapter->hw;
1066 struct cyclecounter cc;
1067 unsigned long flags;
1068 u32 incval = 0;
1069 u32 tsauxc = 0;
1070 u32 fuse0 = 0;
1071
1072 /* For some of the boards below this mask is technically incorrect.
1073 * The timestamp mask overflows at approximately 61bits. However the
1074 * particular hardware does not overflow on an even bitmask value.
1075 * Instead, it overflows due to conversion of upper 32bits billions of
1076 * cycles. Timecounters are not really intended for this purpose so
1077 * they do not properly function if the overflow point isn't 2^N-1.
1078 * However, the actual SYSTIME values in question take ~138 years to
1079 * overflow. In practice this means they won't actually overflow. A
1080 * proper fix to this problem would require modification of the
1081 * timecounter delta calculations.
1082 */
1083 cc.mask = CLOCKSOURCE_MASK(64);
1084 cc.mult = 1;
1085 cc.shift = 0;
1086
1087 switch (hw->mac.type) {
1088 case ixgbe_mac_X550EM_x:
1089 /* SYSTIME assumes X550EM_x board frequency is 300Mhz, and is
1090 * designed to represent seconds and nanoseconds when this is
1091 * the case. However, some revisions of hardware have a 400Mhz
1092 * clock and we have to compensate for this frequency
1093 * variation using corrected mult and shift values.
1094 */
1095 fuse0 = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));
1096 if (!(fuse0 & IXGBE_FUSES0_300MHZ)) {
1097 cc.mult = 3;
1098 cc.shift = 2;
1099 }
1100 /* fallthrough */
1101 case ixgbe_mac_x550em_a:
1102 case ixgbe_mac_X550:
1103 cc.read = ixgbe_ptp_read_X550;
1104
1105 /* enable SYSTIME counter */
1106 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMR, 0);
1107 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0);
1108 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0);
1109 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
1110 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC,
1111 tsauxc & ~IXGBE_TSAUXC_DISABLE_SYSTIME);
1112 IXGBE_WRITE_REG(hw, IXGBE_TSIM, IXGBE_TSIM_TXTS);
1113 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_TIMESYNC);
1114
1115 IXGBE_WRITE_FLUSH(hw);
1116 break;
1117 case ixgbe_mac_X540:
1118 cc.read = ixgbe_ptp_read_82599;
1119
1120 ixgbe_ptp_link_speed_adjust(adapter, &cc.shift, &incval);
1121 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
1122 break;
1123 case ixgbe_mac_82599EB:
1124 cc.read = ixgbe_ptp_read_82599;
1125
1126 ixgbe_ptp_link_speed_adjust(adapter, &cc.shift, &incval);
1127 incval >>= IXGBE_INCVAL_SHIFT_82599;
1128 cc.shift -= IXGBE_INCVAL_SHIFT_82599;
1129 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
1130 BIT(IXGBE_INCPER_SHIFT_82599) | incval);
1131 break;
1132 default:
1133 /* other devices aren't supported */
1134 return;
1135 }
1136
1137 /* update the base incval used to calculate frequency adjustment */
1138 WRITE_ONCE(adapter->base_incval, incval);
1139 smp_mb();
1140
1141 /* need lock to prevent incorrect read while modifying cyclecounter */
1142 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1143 memcpy(&adapter->hw_cc, &cc, sizeof(adapter->hw_cc));
1144 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1145 }
1146
1147 /**
1148 * ixgbe_ptp_reset
1149 * @adapter: the ixgbe private board structure
1150 *
1151 * When the MAC resets, all the hardware bits for timesync are reset. This
1152 * function is used to re-enable the device for PTP based on current settings.
1153 * We do lose the current clock time, so just reset the cyclecounter to the
1154 * system real clock time.
1155 *
1156 * This function will maintain hwtstamp_config settings, and resets the SDP
1157 * output if it was enabled.
1158 */
ixgbe_ptp_reset(struct ixgbe_adapter * adapter)1159 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter)
1160 {
1161 struct ixgbe_hw *hw = &adapter->hw;
1162 unsigned long flags;
1163
1164 /* reset the hardware timestamping mode */
1165 ixgbe_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1166
1167 /* 82598 does not support PTP */
1168 if (hw->mac.type == ixgbe_mac_82598EB)
1169 return;
1170
1171 ixgbe_ptp_start_cyclecounter(adapter);
1172
1173 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1174 timecounter_init(&adapter->hw_tc, &adapter->hw_cc,
1175 ktime_to_ns(ktime_get_real()));
1176 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1177
1178 adapter->last_overflow_check = jiffies;
1179
1180 /* Now that the shift has been calculated and the systime
1181 * registers reset, (re-)enable the Clock out feature
1182 */
1183 if (adapter->ptp_setup_sdp)
1184 adapter->ptp_setup_sdp(adapter);
1185 }
1186
1187 /**
1188 * ixgbe_ptp_create_clock
1189 * @adapter: the ixgbe private adapter structure
1190 *
1191 * This function performs setup of the user entry point function table and
1192 * initializes the PTP clock device, which is used to access the clock-like
1193 * features of the PTP core. It will be called by ixgbe_ptp_init, and may
1194 * reuse a previously initialized clock (such as during a suspend/resume
1195 * cycle).
1196 */
ixgbe_ptp_create_clock(struct ixgbe_adapter * adapter)1197 static long ixgbe_ptp_create_clock(struct ixgbe_adapter *adapter)
1198 {
1199 struct net_device *netdev = adapter->netdev;
1200 long err;
1201
1202 /* do nothing if we already have a clock device */
1203 if (!IS_ERR_OR_NULL(adapter->ptp_clock))
1204 return 0;
1205
1206 switch (adapter->hw.mac.type) {
1207 case ixgbe_mac_X540:
1208 snprintf(adapter->ptp_caps.name,
1209 sizeof(adapter->ptp_caps.name),
1210 "%s", netdev->name);
1211 adapter->ptp_caps.owner = THIS_MODULE;
1212 adapter->ptp_caps.max_adj = 250000000;
1213 adapter->ptp_caps.n_alarm = 0;
1214 adapter->ptp_caps.n_ext_ts = 0;
1215 adapter->ptp_caps.n_per_out = 0;
1216 adapter->ptp_caps.pps = 1;
1217 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq_82599;
1218 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
1219 adapter->ptp_caps.gettime64 = ixgbe_ptp_gettime;
1220 adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
1221 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
1222 adapter->ptp_setup_sdp = ixgbe_ptp_setup_sdp_x540;
1223 break;
1224 case ixgbe_mac_82599EB:
1225 snprintf(adapter->ptp_caps.name,
1226 sizeof(adapter->ptp_caps.name),
1227 "%s", netdev->name);
1228 adapter->ptp_caps.owner = THIS_MODULE;
1229 adapter->ptp_caps.max_adj = 250000000;
1230 adapter->ptp_caps.n_alarm = 0;
1231 adapter->ptp_caps.n_ext_ts = 0;
1232 adapter->ptp_caps.n_per_out = 0;
1233 adapter->ptp_caps.pps = 0;
1234 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq_82599;
1235 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
1236 adapter->ptp_caps.gettime64 = ixgbe_ptp_gettime;
1237 adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
1238 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
1239 break;
1240 case ixgbe_mac_X550:
1241 case ixgbe_mac_X550EM_x:
1242 case ixgbe_mac_x550em_a:
1243 snprintf(adapter->ptp_caps.name, 16, "%s", netdev->name);
1244 adapter->ptp_caps.owner = THIS_MODULE;
1245 adapter->ptp_caps.max_adj = 30000000;
1246 adapter->ptp_caps.n_alarm = 0;
1247 adapter->ptp_caps.n_ext_ts = 0;
1248 adapter->ptp_caps.n_per_out = 0;
1249 adapter->ptp_caps.pps = 0;
1250 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq_X550;
1251 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
1252 adapter->ptp_caps.gettime64 = ixgbe_ptp_gettime;
1253 adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
1254 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
1255 adapter->ptp_setup_sdp = NULL;
1256 break;
1257 default:
1258 adapter->ptp_clock = NULL;
1259 adapter->ptp_setup_sdp = NULL;
1260 return -EOPNOTSUPP;
1261 }
1262
1263 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1264 &adapter->pdev->dev);
1265 if (IS_ERR(adapter->ptp_clock)) {
1266 err = PTR_ERR(adapter->ptp_clock);
1267 adapter->ptp_clock = NULL;
1268 e_dev_err("ptp_clock_register failed\n");
1269 return err;
1270 } else if (adapter->ptp_clock)
1271 e_dev_info("registered PHC device on %s\n", netdev->name);
1272
1273 /* set default timestamp mode to disabled here. We do this in
1274 * create_clock instead of init, because we don't want to override the
1275 * previous settings during a resume cycle.
1276 */
1277 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1278 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1279
1280 return 0;
1281 }
1282
1283 /**
1284 * ixgbe_ptp_init
1285 * @adapter: the ixgbe private adapter structure
1286 *
1287 * This function performs the required steps for enabling PTP
1288 * support. If PTP support has already been loaded it simply calls the
1289 * cyclecounter init routine and exits.
1290 */
ixgbe_ptp_init(struct ixgbe_adapter * adapter)1291 void ixgbe_ptp_init(struct ixgbe_adapter *adapter)
1292 {
1293 /* initialize the spin lock first since we can't control when a user
1294 * will call the entry functions once we have initialized the clock
1295 * device
1296 */
1297 spin_lock_init(&adapter->tmreg_lock);
1298
1299 /* obtain a PTP device, or re-use an existing device */
1300 if (ixgbe_ptp_create_clock(adapter))
1301 return;
1302
1303 /* we have a clock so we can initialize work now */
1304 INIT_WORK(&adapter->ptp_tx_work, ixgbe_ptp_tx_hwtstamp_work);
1305
1306 /* reset the PTP related hardware bits */
1307 ixgbe_ptp_reset(adapter);
1308
1309 /* enter the IXGBE_PTP_RUNNING state */
1310 set_bit(__IXGBE_PTP_RUNNING, &adapter->state);
1311
1312 return;
1313 }
1314
1315 /**
1316 * ixgbe_ptp_suspend - stop PTP work items
1317 * @adapter: pointer to adapter struct
1318 *
1319 * this function suspends PTP activity, and prevents more PTP work from being
1320 * generated, but does not destroy the PTP clock device.
1321 */
ixgbe_ptp_suspend(struct ixgbe_adapter * adapter)1322 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter)
1323 {
1324 /* Leave the IXGBE_PTP_RUNNING state. */
1325 if (!test_and_clear_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1326 return;
1327
1328 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
1329 if (adapter->ptp_setup_sdp)
1330 adapter->ptp_setup_sdp(adapter);
1331
1332 /* ensure that we cancel any pending PTP Tx work item in progress */
1333 cancel_work_sync(&adapter->ptp_tx_work);
1334 ixgbe_ptp_clear_tx_timestamp(adapter);
1335 }
1336
1337 /**
1338 * ixgbe_ptp_stop - close the PTP device
1339 * @adapter: pointer to adapter struct
1340 *
1341 * completely destroy the PTP device, should only be called when the device is
1342 * being fully closed.
1343 */
ixgbe_ptp_stop(struct ixgbe_adapter * adapter)1344 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter)
1345 {
1346 /* first, suspend PTP activity */
1347 ixgbe_ptp_suspend(adapter);
1348
1349 /* disable the PTP clock device */
1350 if (adapter->ptp_clock) {
1351 ptp_clock_unregister(adapter->ptp_clock);
1352 adapter->ptp_clock = NULL;
1353 e_dev_info("removed PHC on %s\n",
1354 adapter->netdev->name);
1355 }
1356 }
1357
