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64 #ifndef __iwl_trans_h__
65 #define __iwl_trans_h__
66 
67 #include <linux/ieee80211.h>
68 #include <linux/mm.h> /* for page_address */
69 #include <linux/lockdep.h>
70 #include <linux/kernel.h>
71 
72 #include "iwl-debug.h"
73 #include "iwl-config.h"
74 #include "fw/img.h"
75 #include "iwl-op-mode.h"
76 #include "fw/api/cmdhdr.h"
77 #include "fw/api/txq.h"
78 #include "fw/api/dbg-tlv.h"
79 #include "iwl-dbg-tlv.h"
80 
81 /**
82  * DOC: Transport layer - what is it ?
83  *
84  * The transport layer is the layer that deals with the HW directly. It provides
85  * an abstraction of the underlying HW to the upper layer. The transport layer
86  * doesn't provide any policy, algorithm or anything of this kind, but only
87  * mechanisms to make the HW do something. It is not completely stateless but
88  * close to it.
89  * We will have an implementation for each different supported bus.
90  */
91 
92 /**
93  * DOC: Life cycle of the transport layer
94  *
95  * The transport layer has a very precise life cycle.
96  *
97  *	1) A helper function is called during the module initialization and
98  *	   registers the bus driver's ops with the transport's alloc function.
99  *	2) Bus's probe calls to the transport layer's allocation functions.
100  *	   Of course this function is bus specific.
101  *	3) This allocation functions will spawn the upper layer which will
102  *	   register mac80211.
103  *
104  *	4) At some point (i.e. mac80211's start call), the op_mode will call
105  *	   the following sequence:
106  *	   start_hw
107  *	   start_fw
108  *
109  *	5) Then when finished (or reset):
110  *	   stop_device
111  *
112  *	6) Eventually, the free function will be called.
113  */
114 
115 #define FH_RSCSR_FRAME_SIZE_MSK		0x00003FFF	/* bits 0-13 */
116 #define FH_RSCSR_FRAME_INVALID		0x55550000
117 #define FH_RSCSR_FRAME_ALIGN		0x40
118 #define FH_RSCSR_RPA_EN			BIT(25)
119 #define FH_RSCSR_RADA_EN		BIT(26)
120 #define FH_RSCSR_RXQ_POS		16
121 #define FH_RSCSR_RXQ_MASK		0x3F0000
122 
123 struct iwl_rx_packet {
124 	/*
125 	 * The first 4 bytes of the RX frame header contain both the RX frame
126 	 * size and some flags.
127 	 * Bit fields:
128 	 * 31:    flag flush RB request
129 	 * 30:    flag ignore TC (terminal counter) request
130 	 * 29:    flag fast IRQ request
131 	 * 28-27: Reserved
132 	 * 26:    RADA enabled
133 	 * 25:    Offload enabled
134 	 * 24:    RPF enabled
135 	 * 23:    RSS enabled
136 	 * 22:    Checksum enabled
137 	 * 21-16: RX queue
138 	 * 15-14: Reserved
139 	 * 13-00: RX frame size
140 	 */
141 	__le32 len_n_flags;
142 	struct iwl_cmd_header hdr;
143 	u8 data[];
144 } __packed;
145 
iwl_rx_packet_len(const struct iwl_rx_packet * pkt)146 static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt)
147 {
148 	return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
149 }
150 
iwl_rx_packet_payload_len(const struct iwl_rx_packet * pkt)151 static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt)
152 {
153 	return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr);
154 }
155 
156 /**
157  * enum CMD_MODE - how to send the host commands ?
158  *
159  * @CMD_ASYNC: Return right away and don't wait for the response
160  * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of
161  *	the response. The caller needs to call iwl_free_resp when done.
162  * @CMD_WANT_ASYNC_CALLBACK: the op_mode's async callback function must be
163  *	called after this command completes. Valid only with CMD_ASYNC.
164  */
165 enum CMD_MODE {
166 	CMD_ASYNC		= BIT(0),
167 	CMD_WANT_SKB		= BIT(1),
168 	CMD_SEND_IN_RFKILL	= BIT(2),
169 	CMD_WANT_ASYNC_CALLBACK	= BIT(3),
170 };
171 
172 #define DEF_CMD_PAYLOAD_SIZE 320
173 
174 /**
175  * struct iwl_device_cmd
176  *
177  * For allocation of the command and tx queues, this establishes the overall
178  * size of the largest command we send to uCode, except for commands that
179  * aren't fully copied and use other TFD space.
180  */
181 struct iwl_device_cmd {
182 	union {
183 		struct {
184 			struct iwl_cmd_header hdr;	/* uCode API */
185 			u8 payload[DEF_CMD_PAYLOAD_SIZE];
186 		};
187 		struct {
188 			struct iwl_cmd_header_wide hdr_wide;
189 			u8 payload_wide[DEF_CMD_PAYLOAD_SIZE -
190 					sizeof(struct iwl_cmd_header_wide) +
191 					sizeof(struct iwl_cmd_header)];
192 		};
193 	};
194 } __packed;
195 
196 #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
197 
198 /*
199  * number of transfer buffers (fragments) per transmit frame descriptor;
200  * this is just the driver's idea, the hardware supports 20
201  */
202 #define IWL_MAX_CMD_TBS_PER_TFD	2
203 
204 /**
205  * enum iwl_hcmd_dataflag - flag for each one of the chunks of the command
206  *
207  * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's
208  *	ring. The transport layer doesn't map the command's buffer to DMA, but
209  *	rather copies it to a previously allocated DMA buffer. This flag tells
210  *	the transport layer not to copy the command, but to map the existing
211  *	buffer (that is passed in) instead. This saves the memcpy and allows
212  *	commands that are bigger than the fixed buffer to be submitted.
213  *	Note that a TFD entry after a NOCOPY one cannot be a normal copied one.
214  * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this
215  *	chunk internally and free it again after the command completes. This
216  *	can (currently) be used only once per command.
217  *	Note that a TFD entry after a DUP one cannot be a normal copied one.
218  */
219 enum iwl_hcmd_dataflag {
220 	IWL_HCMD_DFL_NOCOPY	= BIT(0),
221 	IWL_HCMD_DFL_DUP	= BIT(1),
222 };
223 
224 enum iwl_error_event_table_status {
225 	IWL_ERROR_EVENT_TABLE_LMAC1 = BIT(0),
226 	IWL_ERROR_EVENT_TABLE_LMAC2 = BIT(1),
227 	IWL_ERROR_EVENT_TABLE_UMAC = BIT(2),
228 };
229 
230 /**
231  * struct iwl_host_cmd - Host command to the uCode
232  *
233  * @data: array of chunks that composes the data of the host command
234  * @resp_pkt: response packet, if %CMD_WANT_SKB was set
235  * @_rx_page_order: (internally used to free response packet)
236  * @_rx_page_addr: (internally used to free response packet)
237  * @flags: can be CMD_*
238  * @len: array of the lengths of the chunks in data
239  * @dataflags: IWL_HCMD_DFL_*
240  * @id: command id of the host command, for wide commands encoding the
241  *	version and group as well
242  */
243 struct iwl_host_cmd {
244 	const void *data[IWL_MAX_CMD_TBS_PER_TFD];
245 	struct iwl_rx_packet *resp_pkt;
246 	unsigned long _rx_page_addr;
247 	u32 _rx_page_order;
248 
249 	u32 flags;
250 	u32 id;
251 	u16 len[IWL_MAX_CMD_TBS_PER_TFD];
252 	u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD];
253 };
254 
iwl_free_resp(struct iwl_host_cmd * cmd)255 static inline void iwl_free_resp(struct iwl_host_cmd *cmd)
256 {
257 	free_pages(cmd->_rx_page_addr, cmd->_rx_page_order);
258 }
259 
260 struct iwl_rx_cmd_buffer {
261 	struct page *_page;
262 	int _offset;
263 	bool _page_stolen;
264 	u32 _rx_page_order;
265 	unsigned int truesize;
266 };
267 
rxb_addr(struct iwl_rx_cmd_buffer * r)268 static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r)
269 {
270 	return (void *)((unsigned long)page_address(r->_page) + r->_offset);
271 }
272 
rxb_offset(struct iwl_rx_cmd_buffer * r)273 static inline int rxb_offset(struct iwl_rx_cmd_buffer *r)
274 {
275 	return r->_offset;
276 }
277 
rxb_steal_page(struct iwl_rx_cmd_buffer * r)278 static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r)
279 {
280 	r->_page_stolen = true;
281 	get_page(r->_page);
282 	return r->_page;
283 }
284 
iwl_free_rxb(struct iwl_rx_cmd_buffer * r)285 static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r)
286 {
287 	__free_pages(r->_page, r->_rx_page_order);
288 }
289 
290 #define MAX_NO_RECLAIM_CMDS	6
291 
292 #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
293 
294 /*
295  * Maximum number of HW queues the transport layer
296  * currently supports
297  */
298 #define IWL_MAX_HW_QUEUES		32
299 #define IWL_MAX_TVQM_QUEUES		512
300 
301 #define IWL_MAX_TID_COUNT	8
302 #define IWL_MGMT_TID		15
303 #define IWL_FRAME_LIMIT	64
304 #define IWL_MAX_RX_HW_QUEUES	16
305 
306 /**
307  * enum iwl_wowlan_status - WoWLAN image/device status
308  * @IWL_D3_STATUS_ALIVE: firmware is still running after resume
309  * @IWL_D3_STATUS_RESET: device was reset while suspended
310  */
311 enum iwl_d3_status {
312 	IWL_D3_STATUS_ALIVE,
313 	IWL_D3_STATUS_RESET,
314 };
315 
316 /**
317  * enum iwl_trans_status: transport status flags
318  * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed
319  * @STATUS_DEVICE_ENABLED: APM is enabled
320  * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up)
321  * @STATUS_INT_ENABLED: interrupts are enabled
322  * @STATUS_RFKILL_HW: the actual HW state of the RF-kill switch
323  * @STATUS_RFKILL_OPMODE: RF-kill state reported to opmode
324  * @STATUS_FW_ERROR: the fw is in error state
325  * @STATUS_TRANS_GOING_IDLE: shutting down the trans, only special commands
326  *	are sent
327  * @STATUS_TRANS_IDLE: the trans is idle - general commands are not to be sent
328  * @STATUS_TRANS_DEAD: trans is dead - avoid any read/write operation
329  */
330 enum iwl_trans_status {
331 	STATUS_SYNC_HCMD_ACTIVE,
332 	STATUS_DEVICE_ENABLED,
333 	STATUS_TPOWER_PMI,
334 	STATUS_INT_ENABLED,
335 	STATUS_RFKILL_HW,
336 	STATUS_RFKILL_OPMODE,
337 	STATUS_FW_ERROR,
338 	STATUS_TRANS_GOING_IDLE,
339 	STATUS_TRANS_IDLE,
340 	STATUS_TRANS_DEAD,
341 };
342 
343 static inline int
iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size)344 iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size)
345 {
346 	switch (rb_size) {
347 	case IWL_AMSDU_2K:
348 		return get_order(2 * 1024);
349 	case IWL_AMSDU_4K:
350 		return get_order(4 * 1024);
351 	case IWL_AMSDU_8K:
352 		return get_order(8 * 1024);
353 	case IWL_AMSDU_12K:
354 		return get_order(12 * 1024);
355 	default:
356 		WARN_ON(1);
357 		return -1;
358 	}
359 }
360 
361 struct iwl_hcmd_names {
362 	u8 cmd_id;
363 	const char *const cmd_name;
364 };
365 
366 #define HCMD_NAME(x)	\
367 	{ .cmd_id = x, .cmd_name = #x }
368 
369 struct iwl_hcmd_arr {
370 	const struct iwl_hcmd_names *arr;
371 	int size;
372 };
373 
374 #define HCMD_ARR(x)	\
375 	{ .arr = x, .size = ARRAY_SIZE(x) }
376 
377 /**
378  * struct iwl_trans_config - transport configuration
379  *
380  * @op_mode: pointer to the upper layer.
381  * @cmd_queue: the index of the command queue.
382  *	Must be set before start_fw.
383  * @cmd_fifo: the fifo for host commands
384  * @cmd_q_wdg_timeout: the timeout of the watchdog timer for the command queue.
385  * @no_reclaim_cmds: Some devices erroneously don't set the
386  *	SEQ_RX_FRAME bit on some notifications, this is the
387  *	list of such notifications to filter. Max length is
388  *	%MAX_NO_RECLAIM_CMDS.
389  * @n_no_reclaim_cmds: # of commands in list
390  * @rx_buf_size: RX buffer size needed for A-MSDUs
391  *	if unset 4k will be the RX buffer size
392  * @bc_table_dword: set to true if the BC table expects the byte count to be
393  *	in DWORD (as opposed to bytes)
394  * @scd_set_active: should the transport configure the SCD for HCMD queue
395  * @sw_csum_tx: transport should compute the TCP checksum
396  * @command_groups: array of command groups, each member is an array of the
397  *	commands in the group; for debugging only
398  * @command_groups_size: number of command groups, to avoid illegal access
399  * @cb_data_offs: offset inside skb->cb to store transport data at, must have
400  *	space for at least two pointers
401  */
402 struct iwl_trans_config {
403 	struct iwl_op_mode *op_mode;
404 
405 	u8 cmd_queue;
406 	u8 cmd_fifo;
407 	unsigned int cmd_q_wdg_timeout;
408 	const u8 *no_reclaim_cmds;
409 	unsigned int n_no_reclaim_cmds;
410 
411 	enum iwl_amsdu_size rx_buf_size;
412 	bool bc_table_dword;
413 	bool scd_set_active;
414 	bool sw_csum_tx;
415 	const struct iwl_hcmd_arr *command_groups;
416 	int command_groups_size;
417 
418 	u8 cb_data_offs;
419 };
420 
421 struct iwl_trans_dump_data {
422 	u32 len;
423 	u8 data[];
424 };
425 
426 struct iwl_trans;
427 
428 struct iwl_trans_txq_scd_cfg {
429 	u8 fifo;
430 	u8 sta_id;
431 	u8 tid;
432 	bool aggregate;
433 	int frame_limit;
434 };
435 
436 /**
437  * struct iwl_trans_rxq_dma_data - RX queue DMA data
438  * @fr_bd_cb: DMA address of free BD cyclic buffer
439  * @fr_bd_wid: Initial write index of the free BD cyclic buffer
440  * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr
441  * @ur_bd_cb: DMA address of used BD cyclic buffer
442  */
443 struct iwl_trans_rxq_dma_data {
444 	u64 fr_bd_cb;
445 	u32 fr_bd_wid;
446 	u64 urbd_stts_wrptr;
447 	u64 ur_bd_cb;
448 };
449 
450 /**
451  * struct iwl_trans_ops - transport specific operations
452  *
453  * All the handlers MUST be implemented
454  *
455  * @start_hw: starts the HW. From that point on, the HW can send interrupts.
456  *	May sleep.
457  * @op_mode_leave: Turn off the HW RF kill indication if on
458  *	May sleep
459  * @start_fw: allocates and inits all the resources for the transport
460  *	layer. Also kick a fw image.
461  *	May sleep
462  * @fw_alive: called when the fw sends alive notification. If the fw provides
463  *	the SCD base address in SRAM, then provide it here, or 0 otherwise.
464  *	May sleep
465  * @stop_device: stops the whole device (embedded CPU put to reset) and stops
466  *	the HW. From that point on, the HW will be stopped but will still issue
467  *	an interrupt if the HW RF kill switch is triggered.
468  *	This callback must do the right thing and not crash even if %start_hw()
469  *	was called but not &start_fw(). May sleep.
470  * @d3_suspend: put the device into the correct mode for WoWLAN during
471  *	suspend. This is optional, if not implemented WoWLAN will not be
472  *	supported. This callback may sleep.
473  * @d3_resume: resume the device after WoWLAN, enabling the opmode to
474  *	talk to the WoWLAN image to get its status. This is optional, if not
475  *	implemented WoWLAN will not be supported. This callback may sleep.
476  * @send_cmd:send a host command. Must return -ERFKILL if RFkill is asserted.
477  *	If RFkill is asserted in the middle of a SYNC host command, it must
478  *	return -ERFKILL straight away.
479  *	May sleep only if CMD_ASYNC is not set
480  * @tx: send an skb. The transport relies on the op_mode to zero the
481  *	the ieee80211_tx_info->driver_data. If the MPDU is an A-MSDU, all
482  *	the CSUM will be taken care of (TCP CSUM and IP header in case of
483  *	IPv4). If the MPDU is a single MSDU, the op_mode must compute the IP
484  *	header if it is IPv4.
485  *	Must be atomic
486  * @reclaim: free packet until ssn. Returns a list of freed packets.
487  *	Must be atomic
488  * @txq_enable: setup a queue. To setup an AC queue, use the
489  *	iwl_trans_ac_txq_enable wrapper. fw_alive must have been called before
490  *	this one. The op_mode must not configure the HCMD queue. The scheduler
491  *	configuration may be %NULL, in which case the hardware will not be
492  *	configured. If true is returned, the operation mode needs to increment
493  *	the sequence number of the packets routed to this queue because of a
494  *	hardware scheduler bug. May sleep.
495  * @txq_disable: de-configure a Tx queue to send AMPDUs
496  *	Must be atomic
497  * @txq_set_shared_mode: change Tx queue shared/unshared marking
498  * @wait_tx_queues_empty: wait until tx queues are empty. May sleep.
499  * @wait_txq_empty: wait until specific tx queue is empty. May sleep.
500  * @freeze_txq_timer: prevents the timer of the queue from firing until the
501  *	queue is set to awake. Must be atomic.
502  * @block_txq_ptrs: stop updating the write pointers of the Tx queues. Note
503  *	that the transport needs to refcount the calls since this function
504  *	will be called several times with block = true, and then the queues
505  *	need to be unblocked only after the same number of calls with
506  *	block = false.
507  * @write8: write a u8 to a register at offset ofs from the BAR
508  * @write32: write a u32 to a register at offset ofs from the BAR
509  * @read32: read a u32 register at offset ofs from the BAR
510  * @read_prph: read a DWORD from a periphery register
511  * @write_prph: write a DWORD to a periphery register
512  * @read_mem: read device's SRAM in DWORD
513  * @write_mem: write device's SRAM in DWORD. If %buf is %NULL, then the memory
514  *	will be zeroed.
515  * @configure: configure parameters required by the transport layer from
516  *	the op_mode. May be called several times before start_fw, can't be
517  *	called after that.
518  * @set_pmi: set the power pmi state
519  * @grab_nic_access: wake the NIC to be able to access non-HBUS regs.
520  *	Sleeping is not allowed between grab_nic_access and
521  *	release_nic_access.
522  * @release_nic_access: let the NIC go to sleep. The "flags" parameter
523  *	must be the same one that was sent before to the grab_nic_access.
524  * @set_bits_mask - set SRAM register according to value and mask.
525  * @dump_data: return a vmalloc'ed buffer with debug data, maybe containing last
526  *	TX'ed commands and similar. The buffer will be vfree'd by the caller.
527  *	Note that the transport must fill in the proper file headers.
528  * @debugfs_cleanup: used in the driver unload flow to make a proper cleanup
529  *	of the trans debugfs
530  */
531 struct iwl_trans_ops {
532 
533 	int (*start_hw)(struct iwl_trans *iwl_trans);
534 	void (*op_mode_leave)(struct iwl_trans *iwl_trans);
535 	int (*start_fw)(struct iwl_trans *trans, const struct fw_img *fw,
536 			bool run_in_rfkill);
537 	void (*fw_alive)(struct iwl_trans *trans, u32 scd_addr);
538 	void (*stop_device)(struct iwl_trans *trans);
539 
540 	int (*d3_suspend)(struct iwl_trans *trans, bool test, bool reset);
541 	int (*d3_resume)(struct iwl_trans *trans, enum iwl_d3_status *status,
542 			 bool test, bool reset);
543 
544 	int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
545 
546 	int (*tx)(struct iwl_trans *trans, struct sk_buff *skb,
547 		  struct iwl_device_cmd *dev_cmd, int queue);
548 	void (*reclaim)(struct iwl_trans *trans, int queue, int ssn,
549 			struct sk_buff_head *skbs);
550 
551 	void (*set_q_ptrs)(struct iwl_trans *trans, int queue, int ptr);
552 
553 	bool (*txq_enable)(struct iwl_trans *trans, int queue, u16 ssn,
554 			   const struct iwl_trans_txq_scd_cfg *cfg,
555 			   unsigned int queue_wdg_timeout);
556 	void (*txq_disable)(struct iwl_trans *trans, int queue,
557 			    bool configure_scd);
558 	/* 22000 functions */
559 	int (*txq_alloc)(struct iwl_trans *trans,
560 			 __le16 flags, u8 sta_id, u8 tid,
561 			 int cmd_id, int size,
562 			 unsigned int queue_wdg_timeout);
563 	void (*txq_free)(struct iwl_trans *trans, int queue);
564 	int (*rxq_dma_data)(struct iwl_trans *trans, int queue,
565 			    struct iwl_trans_rxq_dma_data *data);
566 
567 	void (*txq_set_shared_mode)(struct iwl_trans *trans, u32 txq_id,
568 				    bool shared);
569 
570 	int (*wait_tx_queues_empty)(struct iwl_trans *trans, u32 txq_bm);
571 	int (*wait_txq_empty)(struct iwl_trans *trans, int queue);
572 	void (*freeze_txq_timer)(struct iwl_trans *trans, unsigned long txqs,
573 				 bool freeze);
574 	void (*block_txq_ptrs)(struct iwl_trans *trans, bool block);
575 
576 	void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val);
577 	void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val);
578 	u32 (*read32)(struct iwl_trans *trans, u32 ofs);
579 	u32 (*read_prph)(struct iwl_trans *trans, u32 ofs);
580 	void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val);
581 	int (*read_mem)(struct iwl_trans *trans, u32 addr,
582 			void *buf, int dwords);
583 	int (*write_mem)(struct iwl_trans *trans, u32 addr,
584 			 const void *buf, int dwords);
585 	void (*configure)(struct iwl_trans *trans,
586 			  const struct iwl_trans_config *trans_cfg);
587 	void (*set_pmi)(struct iwl_trans *trans, bool state);
588 	void (*sw_reset)(struct iwl_trans *trans);
589 	bool (*grab_nic_access)(struct iwl_trans *trans, unsigned long *flags);
590 	void (*release_nic_access)(struct iwl_trans *trans,
591 				   unsigned long *flags);
592 	void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask,
593 			      u32 value);
594 	int  (*suspend)(struct iwl_trans *trans);
595 	void (*resume)(struct iwl_trans *trans);
596 
597 	struct iwl_trans_dump_data *(*dump_data)(struct iwl_trans *trans,
598 						 u32 dump_mask);
599 	void (*debugfs_cleanup)(struct iwl_trans *trans);
600 	void (*sync_nmi)(struct iwl_trans *trans);
601 };
602 
603 /**
604  * enum iwl_trans_state - state of the transport layer
605  *
606  * @IWL_TRANS_NO_FW: no fw has sent an alive response
607  * @IWL_TRANS_FW_ALIVE: a fw has sent an alive response
608  */
609 enum iwl_trans_state {
610 	IWL_TRANS_NO_FW = 0,
611 	IWL_TRANS_FW_ALIVE	= 1,
612 };
613 
614 /**
615  * DOC: Platform power management
616  *
617  * In system-wide power management the entire platform goes into a low
618  * power state (e.g. idle or suspend to RAM) at the same time and the
619  * device is configured as a wakeup source for the entire platform.
620  * This is usually triggered by userspace activity (e.g. the user
621  * presses the suspend button or a power management daemon decides to
622  * put the platform in low power mode).  The device's behavior in this
623  * mode is dictated by the wake-on-WLAN configuration.
624  *
625  * The terms used for the device's behavior are as follows:
626  *
627  *	- D0: the device is fully powered and the host is awake;
628  *	- D3: the device is in low power mode and only reacts to
629  *		specific events (e.g. magic-packet received or scan
630  *		results found);
631  *
632  * These terms reflect the power modes in the firmware and are not to
633  * be confused with the physical device power state.
634  */
635 
636 /**
637  * enum iwl_plat_pm_mode - platform power management mode
638  *
639  * This enumeration describes the device's platform power management
640  * behavior when in system-wide suspend (i.e WoWLAN).
641  *
642  * @IWL_PLAT_PM_MODE_DISABLED: power management is disabled for this
643  *	device.  In system-wide suspend mode, it means that the all
644  *	connections will be closed automatically by mac80211 before
645  *	the platform is suspended.
646  * @IWL_PLAT_PM_MODE_D3: the device goes into D3 mode (i.e. WoWLAN).
647  */
648 enum iwl_plat_pm_mode {
649 	IWL_PLAT_PM_MODE_DISABLED,
650 	IWL_PLAT_PM_MODE_D3,
651 };
652 
653 /**
654  * enum iwl_ini_cfg_state
655  * @IWL_INI_CFG_STATE_NOT_LOADED: no debug cfg was given
656  * @IWL_INI_CFG_STATE_LOADED: debug cfg was found and loaded
657  * @IWL_INI_CFG_STATE_CORRUPTED: debug cfg was found and some of the TLVs
658  *	are corrupted. The rest of the debug TLVs will still be used
659  */
660 enum iwl_ini_cfg_state {
661 	IWL_INI_CFG_STATE_NOT_LOADED,
662 	IWL_INI_CFG_STATE_LOADED,
663 	IWL_INI_CFG_STATE_CORRUPTED,
664 };
665 
666 /* Max time to wait for nmi interrupt */
667 #define IWL_TRANS_NMI_TIMEOUT (HZ / 4)
668 
669 /**
670  * struct iwl_dram_data
671  * @physical: page phy pointer
672  * @block: pointer to the allocated block/page
673  * @size: size of the block/page
674  */
675 struct iwl_dram_data {
676 	dma_addr_t physical;
677 	void *block;
678 	int size;
679 };
680 
681 /**
682  * struct iwl_self_init_dram - dram data used by self init process
683  * @fw: lmac and umac dram data
684  * @fw_cnt: total number of items in array
685  * @paging: paging dram data
686  * @paging_cnt: total number of items in array
687  */
688 struct iwl_self_init_dram {
689 	struct iwl_dram_data *fw;
690 	int fw_cnt;
691 	struct iwl_dram_data *paging;
692 	int paging_cnt;
693 };
694 
695 /**
696  * struct iwl_trans_debug - transport debug related data
697  *
698  * @n_dest_reg: num of reg_ops in %dbg_dest_tlv
699  * @rec_on: true iff there is a fw debug recording currently active
700  * @dest_tlv: points to the destination TLV for debug
701  * @conf_tlv: array of pointers to configuration TLVs for debug
702  * @trigger_tlv: array of pointers to triggers TLVs for debug
703  * @lmac_error_event_table: addrs of lmacs error tables
704  * @umac_error_event_table: addr of umac error table
705  * @error_event_table_tlv_status: bitmap that indicates what error table
706  *	pointers was recevied via TLV. uses enum &iwl_error_event_table_status
707  * @internal_ini_cfg: internal debug cfg state. Uses &enum iwl_ini_cfg_state
708  * @external_ini_cfg: external debug cfg state. Uses &enum iwl_ini_cfg_state
709  * @num_blocks: number of blocks in fw_mon
710  * @fw_mon: address of the buffers for firmware monitor
711  * @hw_error: equals true if hw error interrupt was received from the FW
712  * @ini_dest: debug monitor destination uses &enum iwl_fw_ini_buffer_location
713  */
714 struct iwl_trans_debug {
715 	u8 n_dest_reg;
716 	bool rec_on;
717 
718 	const struct iwl_fw_dbg_dest_tlv_v1 *dest_tlv;
719 	const struct iwl_fw_dbg_conf_tlv *conf_tlv[FW_DBG_CONF_MAX];
720 	struct iwl_fw_dbg_trigger_tlv * const *trigger_tlv;
721 
722 	u32 lmac_error_event_table[2];
723 	u32 umac_error_event_table;
724 	unsigned int error_event_table_tlv_status;
725 
726 	enum iwl_ini_cfg_state internal_ini_cfg;
727 	enum iwl_ini_cfg_state external_ini_cfg;
728 
729 	int num_blocks;
730 	struct iwl_dram_data fw_mon[IWL_FW_INI_ALLOCATION_NUM];
731 
732 	bool hw_error;
733 	enum iwl_fw_ini_buffer_location ini_dest;
734 };
735 
736 /**
737  * struct iwl_trans - transport common data
738  *
739  * @ops - pointer to iwl_trans_ops
740  * @op_mode - pointer to the op_mode
741  * @trans_cfg: the trans-specific configuration part
742  * @cfg - pointer to the configuration
743  * @drv - pointer to iwl_drv
744  * @status: a bit-mask of transport status flags
745  * @dev - pointer to struct device * that represents the device
746  * @max_skb_frags: maximum number of fragments an SKB can have when transmitted.
747  *	0 indicates that frag SKBs (NETIF_F_SG) aren't supported.
748  * @hw_rf_id a u32 with the device RF ID
749  * @hw_id: a u32 with the ID of the device / sub-device.
750  *	Set during transport allocation.
751  * @hw_id_str: a string with info about HW ID. Set during transport allocation.
752  * @pm_support: set to true in start_hw if link pm is supported
753  * @ltr_enabled: set to true if the LTR is enabled
754  * @wide_cmd_header: true when ucode supports wide command header format
755  * @num_rx_queues: number of RX queues allocated by the transport;
756  *	the transport must set this before calling iwl_drv_start()
757  * @iml_len: the length of the image loader
758  * @iml: a pointer to the image loader itself
759  * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only.
760  *	The user should use iwl_trans_{alloc,free}_tx_cmd.
761  * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before
762  *	starting the firmware, used for tracing
763  * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the
764  *	start of the 802.11 header in the @rx_mpdu_cmd
765  * @dflt_pwr_limit: default power limit fetched from the platform (ACPI)
766  * @system_pm_mode: the system-wide power management mode in use.
767  *	This mode is set dynamically, depending on the WoWLAN values
768  *	configured from the userspace at runtime.
769  */
770 struct iwl_trans {
771 	const struct iwl_trans_ops *ops;
772 	struct iwl_op_mode *op_mode;
773 	const struct iwl_cfg_trans_params *trans_cfg;
774 	const struct iwl_cfg *cfg;
775 	struct iwl_drv *drv;
776 	enum iwl_trans_state state;
777 	unsigned long status;
778 
779 	struct device *dev;
780 	u32 max_skb_frags;
781 	u32 hw_rev;
782 	u32 hw_rf_id;
783 	u32 hw_id;
784 	char hw_id_str[52];
785 
786 	u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size;
787 
788 	bool pm_support;
789 	bool ltr_enabled;
790 
791 	const struct iwl_hcmd_arr *command_groups;
792 	int command_groups_size;
793 	bool wide_cmd_header;
794 
795 	u8 num_rx_queues;
796 
797 	size_t iml_len;
798 	u8 *iml;
799 
800 	/* The following fields are internal only */
801 	struct kmem_cache *dev_cmd_pool;
802 	char dev_cmd_pool_name[50];
803 
804 	struct dentry *dbgfs_dir;
805 
806 #ifdef CONFIG_LOCKDEP
807 	struct lockdep_map sync_cmd_lockdep_map;
808 #endif
809 
810 	struct iwl_trans_debug dbg;
811 	struct iwl_self_init_dram init_dram;
812 
813 	enum iwl_plat_pm_mode system_pm_mode;
814 
815 	/* pointer to trans specific struct */
816 	/*Ensure that this pointer will always be aligned to sizeof pointer */
817 	char trans_specific[0] __aligned(sizeof(void *));
818 };
819 
820 const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id);
821 int iwl_cmd_groups_verify_sorted(const struct iwl_trans_config *trans);
822 
iwl_trans_configure(struct iwl_trans * trans,const struct iwl_trans_config * trans_cfg)823 static inline void iwl_trans_configure(struct iwl_trans *trans,
824 				       const struct iwl_trans_config *trans_cfg)
825 {
826 	trans->op_mode = trans_cfg->op_mode;
827 
828 	trans->ops->configure(trans, trans_cfg);
829 	WARN_ON(iwl_cmd_groups_verify_sorted(trans_cfg));
830 }
831 
iwl_trans_start_hw(struct iwl_trans * trans)832 static inline int iwl_trans_start_hw(struct iwl_trans *trans)
833 {
834 	might_sleep();
835 
836 	return trans->ops->start_hw(trans);
837 }
838 
iwl_trans_op_mode_leave(struct iwl_trans * trans)839 static inline void iwl_trans_op_mode_leave(struct iwl_trans *trans)
840 {
841 	might_sleep();
842 
843 	if (trans->ops->op_mode_leave)
844 		trans->ops->op_mode_leave(trans);
845 
846 	trans->op_mode = NULL;
847 
848 	trans->state = IWL_TRANS_NO_FW;
849 }
850 
iwl_trans_fw_alive(struct iwl_trans * trans,u32 scd_addr)851 static inline void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr)
852 {
853 	might_sleep();
854 
855 	trans->state = IWL_TRANS_FW_ALIVE;
856 
857 	trans->ops->fw_alive(trans, scd_addr);
858 }
859 
iwl_trans_start_fw(struct iwl_trans * trans,const struct fw_img * fw,bool run_in_rfkill)860 static inline int iwl_trans_start_fw(struct iwl_trans *trans,
861 				     const struct fw_img *fw,
862 				     bool run_in_rfkill)
863 {
864 	might_sleep();
865 
866 	WARN_ON_ONCE(!trans->rx_mpdu_cmd);
867 
868 	clear_bit(STATUS_FW_ERROR, &trans->status);
869 	return trans->ops->start_fw(trans, fw, run_in_rfkill);
870 }
871 
iwl_trans_stop_device(struct iwl_trans * trans)872 static inline void iwl_trans_stop_device(struct iwl_trans *trans)
873 {
874 	might_sleep();
875 
876 	trans->ops->stop_device(trans);
877 
878 	trans->state = IWL_TRANS_NO_FW;
879 }
880 
iwl_trans_d3_suspend(struct iwl_trans * trans,bool test,bool reset)881 static inline int iwl_trans_d3_suspend(struct iwl_trans *trans, bool test,
882 				       bool reset)
883 {
884 	might_sleep();
885 	if (!trans->ops->d3_suspend)
886 		return 0;
887 
888 	return trans->ops->d3_suspend(trans, test, reset);
889 }
890 
iwl_trans_d3_resume(struct iwl_trans * trans,enum iwl_d3_status * status,bool test,bool reset)891 static inline int iwl_trans_d3_resume(struct iwl_trans *trans,
892 				      enum iwl_d3_status *status,
893 				      bool test, bool reset)
894 {
895 	might_sleep();
896 	if (!trans->ops->d3_resume)
897 		return 0;
898 
899 	return trans->ops->d3_resume(trans, status, test, reset);
900 }
901 
iwl_trans_suspend(struct iwl_trans * trans)902 static inline int iwl_trans_suspend(struct iwl_trans *trans)
903 {
904 	if (!trans->ops->suspend)
905 		return 0;
906 
907 	return trans->ops->suspend(trans);
908 }
909 
iwl_trans_resume(struct iwl_trans * trans)910 static inline void iwl_trans_resume(struct iwl_trans *trans)
911 {
912 	if (trans->ops->resume)
913 		trans->ops->resume(trans);
914 }
915 
916 static inline struct iwl_trans_dump_data *
iwl_trans_dump_data(struct iwl_trans * trans,u32 dump_mask)917 iwl_trans_dump_data(struct iwl_trans *trans, u32 dump_mask)
918 {
919 	if (!trans->ops->dump_data)
920 		return NULL;
921 	return trans->ops->dump_data(trans, dump_mask);
922 }
923 
924 static inline struct iwl_device_cmd *
iwl_trans_alloc_tx_cmd(struct iwl_trans * trans)925 iwl_trans_alloc_tx_cmd(struct iwl_trans *trans)
926 {
927 	return kmem_cache_alloc(trans->dev_cmd_pool, GFP_ATOMIC);
928 }
929 
930 int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
931 
iwl_trans_free_tx_cmd(struct iwl_trans * trans,struct iwl_device_cmd * dev_cmd)932 static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans,
933 					 struct iwl_device_cmd *dev_cmd)
934 {
935 	kmem_cache_free(trans->dev_cmd_pool, dev_cmd);
936 }
937 
iwl_trans_tx(struct iwl_trans * trans,struct sk_buff * skb,struct iwl_device_cmd * dev_cmd,int queue)938 static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb,
939 			       struct iwl_device_cmd *dev_cmd, int queue)
940 {
941 	if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status)))
942 		return -EIO;
943 
944 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
945 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
946 		return -EIO;
947 	}
948 
949 	return trans->ops->tx(trans, skb, dev_cmd, queue);
950 }
951 
iwl_trans_reclaim(struct iwl_trans * trans,int queue,int ssn,struct sk_buff_head * skbs)952 static inline void iwl_trans_reclaim(struct iwl_trans *trans, int queue,
953 				     int ssn, struct sk_buff_head *skbs)
954 {
955 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
956 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
957 		return;
958 	}
959 
960 	trans->ops->reclaim(trans, queue, ssn, skbs);
961 }
962 
iwl_trans_set_q_ptrs(struct iwl_trans * trans,int queue,int ptr)963 static inline void iwl_trans_set_q_ptrs(struct iwl_trans *trans, int queue,
964 					int ptr)
965 {
966 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
967 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
968 		return;
969 	}
970 
971 	trans->ops->set_q_ptrs(trans, queue, ptr);
972 }
973 
iwl_trans_txq_disable(struct iwl_trans * trans,int queue,bool configure_scd)974 static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue,
975 					 bool configure_scd)
976 {
977 	trans->ops->txq_disable(trans, queue, configure_scd);
978 }
979 
980 static inline bool
iwl_trans_txq_enable_cfg(struct iwl_trans * trans,int queue,u16 ssn,const struct iwl_trans_txq_scd_cfg * cfg,unsigned int queue_wdg_timeout)981 iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn,
982 			 const struct iwl_trans_txq_scd_cfg *cfg,
983 			 unsigned int queue_wdg_timeout)
984 {
985 	might_sleep();
986 
987 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
988 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
989 		return false;
990 	}
991 
992 	return trans->ops->txq_enable(trans, queue, ssn,
993 				      cfg, queue_wdg_timeout);
994 }
995 
996 static inline int
iwl_trans_get_rxq_dma_data(struct iwl_trans * trans,int queue,struct iwl_trans_rxq_dma_data * data)997 iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue,
998 			   struct iwl_trans_rxq_dma_data *data)
999 {
1000 	if (WARN_ON_ONCE(!trans->ops->rxq_dma_data))
1001 		return -ENOTSUPP;
1002 
1003 	return trans->ops->rxq_dma_data(trans, queue, data);
1004 }
1005 
1006 static inline void
iwl_trans_txq_free(struct iwl_trans * trans,int queue)1007 iwl_trans_txq_free(struct iwl_trans *trans, int queue)
1008 {
1009 	if (WARN_ON_ONCE(!trans->ops->txq_free))
1010 		return;
1011 
1012 	trans->ops->txq_free(trans, queue);
1013 }
1014 
1015 static inline int
iwl_trans_txq_alloc(struct iwl_trans * trans,__le16 flags,u8 sta_id,u8 tid,int cmd_id,int size,unsigned int wdg_timeout)1016 iwl_trans_txq_alloc(struct iwl_trans *trans,
1017 		    __le16 flags, u8 sta_id, u8 tid,
1018 		    int cmd_id, int size,
1019 		    unsigned int wdg_timeout)
1020 {
1021 	might_sleep();
1022 
1023 	if (WARN_ON_ONCE(!trans->ops->txq_alloc))
1024 		return -ENOTSUPP;
1025 
1026 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1027 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1028 		return -EIO;
1029 	}
1030 
1031 	return trans->ops->txq_alloc(trans, flags, sta_id, tid,
1032 				     cmd_id, size, wdg_timeout);
1033 }
1034 
iwl_trans_txq_set_shared_mode(struct iwl_trans * trans,int queue,bool shared_mode)1035 static inline void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans,
1036 						 int queue, bool shared_mode)
1037 {
1038 	if (trans->ops->txq_set_shared_mode)
1039 		trans->ops->txq_set_shared_mode(trans, queue, shared_mode);
1040 }
1041 
iwl_trans_txq_enable(struct iwl_trans * trans,int queue,int fifo,int sta_id,int tid,int frame_limit,u16 ssn,unsigned int queue_wdg_timeout)1042 static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue,
1043 					int fifo, int sta_id, int tid,
1044 					int frame_limit, u16 ssn,
1045 					unsigned int queue_wdg_timeout)
1046 {
1047 	struct iwl_trans_txq_scd_cfg cfg = {
1048 		.fifo = fifo,
1049 		.sta_id = sta_id,
1050 		.tid = tid,
1051 		.frame_limit = frame_limit,
1052 		.aggregate = sta_id >= 0,
1053 	};
1054 
1055 	iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout);
1056 }
1057 
1058 static inline
iwl_trans_ac_txq_enable(struct iwl_trans * trans,int queue,int fifo,unsigned int queue_wdg_timeout)1059 void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo,
1060 			     unsigned int queue_wdg_timeout)
1061 {
1062 	struct iwl_trans_txq_scd_cfg cfg = {
1063 		.fifo = fifo,
1064 		.sta_id = -1,
1065 		.tid = IWL_MAX_TID_COUNT,
1066 		.frame_limit = IWL_FRAME_LIMIT,
1067 		.aggregate = false,
1068 	};
1069 
1070 	iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout);
1071 }
1072 
iwl_trans_freeze_txq_timer(struct iwl_trans * trans,unsigned long txqs,bool freeze)1073 static inline void iwl_trans_freeze_txq_timer(struct iwl_trans *trans,
1074 					      unsigned long txqs,
1075 					      bool freeze)
1076 {
1077 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1078 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1079 		return;
1080 	}
1081 
1082 	if (trans->ops->freeze_txq_timer)
1083 		trans->ops->freeze_txq_timer(trans, txqs, freeze);
1084 }
1085 
iwl_trans_block_txq_ptrs(struct iwl_trans * trans,bool block)1086 static inline void iwl_trans_block_txq_ptrs(struct iwl_trans *trans,
1087 					    bool block)
1088 {
1089 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1090 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1091 		return;
1092 	}
1093 
1094 	if (trans->ops->block_txq_ptrs)
1095 		trans->ops->block_txq_ptrs(trans, block);
1096 }
1097 
iwl_trans_wait_tx_queues_empty(struct iwl_trans * trans,u32 txqs)1098 static inline int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans,
1099 						 u32 txqs)
1100 {
1101 	if (WARN_ON_ONCE(!trans->ops->wait_tx_queues_empty))
1102 		return -ENOTSUPP;
1103 
1104 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1105 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1106 		return -EIO;
1107 	}
1108 
1109 	return trans->ops->wait_tx_queues_empty(trans, txqs);
1110 }
1111 
iwl_trans_wait_txq_empty(struct iwl_trans * trans,int queue)1112 static inline int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue)
1113 {
1114 	if (WARN_ON_ONCE(!trans->ops->wait_txq_empty))
1115 		return -ENOTSUPP;
1116 
1117 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1118 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1119 		return -EIO;
1120 	}
1121 
1122 	return trans->ops->wait_txq_empty(trans, queue);
1123 }
1124 
iwl_trans_write8(struct iwl_trans * trans,u32 ofs,u8 val)1125 static inline void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1126 {
1127 	trans->ops->write8(trans, ofs, val);
1128 }
1129 
iwl_trans_write32(struct iwl_trans * trans,u32 ofs,u32 val)1130 static inline void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1131 {
1132 	trans->ops->write32(trans, ofs, val);
1133 }
1134 
iwl_trans_read32(struct iwl_trans * trans,u32 ofs)1135 static inline u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs)
1136 {
1137 	return trans->ops->read32(trans, ofs);
1138 }
1139 
iwl_trans_read_prph(struct iwl_trans * trans,u32 ofs)1140 static inline u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs)
1141 {
1142 	return trans->ops->read_prph(trans, ofs);
1143 }
1144 
iwl_trans_write_prph(struct iwl_trans * trans,u32 ofs,u32 val)1145 static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs,
1146 					u32 val)
1147 {
1148 	return trans->ops->write_prph(trans, ofs, val);
1149 }
1150 
iwl_trans_read_mem(struct iwl_trans * trans,u32 addr,void * buf,int dwords)1151 static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr,
1152 				     void *buf, int dwords)
1153 {
1154 	return trans->ops->read_mem(trans, addr, buf, dwords);
1155 }
1156 
1157 #define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize)		      \
1158 	do {								      \
1159 		if (__builtin_constant_p(bufsize))			      \
1160 			BUILD_BUG_ON((bufsize) % sizeof(u32));		      \
1161 		iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\
1162 	} while (0)
1163 
iwl_trans_read_mem32(struct iwl_trans * trans,u32 addr)1164 static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr)
1165 {
1166 	u32 value;
1167 
1168 	if (WARN_ON(iwl_trans_read_mem(trans, addr, &value, 1)))
1169 		return 0xa5a5a5a5;
1170 
1171 	return value;
1172 }
1173 
iwl_trans_write_mem(struct iwl_trans * trans,u32 addr,const void * buf,int dwords)1174 static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr,
1175 				      const void *buf, int dwords)
1176 {
1177 	return trans->ops->write_mem(trans, addr, buf, dwords);
1178 }
1179 
iwl_trans_write_mem32(struct iwl_trans * trans,u32 addr,u32 val)1180 static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr,
1181 					u32 val)
1182 {
1183 	return iwl_trans_write_mem(trans, addr, &val, 1);
1184 }
1185 
iwl_trans_set_pmi(struct iwl_trans * trans,bool state)1186 static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state)
1187 {
1188 	if (trans->ops->set_pmi)
1189 		trans->ops->set_pmi(trans, state);
1190 }
1191 
iwl_trans_sw_reset(struct iwl_trans * trans)1192 static inline void iwl_trans_sw_reset(struct iwl_trans *trans)
1193 {
1194 	if (trans->ops->sw_reset)
1195 		trans->ops->sw_reset(trans);
1196 }
1197 
1198 static inline void
iwl_trans_set_bits_mask(struct iwl_trans * trans,u32 reg,u32 mask,u32 value)1199 iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value)
1200 {
1201 	trans->ops->set_bits_mask(trans, reg, mask, value);
1202 }
1203 
1204 #define iwl_trans_grab_nic_access(trans, flags)	\
1205 	__cond_lock(nic_access,				\
1206 		    likely((trans)->ops->grab_nic_access(trans, flags)))
1207 
__releases(nic_access)1208 static inline void __releases(nic_access)
1209 iwl_trans_release_nic_access(struct iwl_trans *trans, unsigned long *flags)
1210 {
1211 	trans->ops->release_nic_access(trans, flags);
1212 	__release(nic_access);
1213 }
1214 
iwl_trans_fw_error(struct iwl_trans * trans)1215 static inline void iwl_trans_fw_error(struct iwl_trans *trans)
1216 {
1217 	if (WARN_ON_ONCE(!trans->op_mode))
1218 		return;
1219 
1220 	/* prevent double restarts due to the same erroneous FW */
1221 	if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status))
1222 		iwl_op_mode_nic_error(trans->op_mode);
1223 }
1224 
iwl_trans_sync_nmi(struct iwl_trans * trans)1225 static inline void iwl_trans_sync_nmi(struct iwl_trans *trans)
1226 {
1227 	if (trans->ops->sync_nmi)
1228 		trans->ops->sync_nmi(trans);
1229 }
1230 
iwl_trans_dbg_ini_valid(struct iwl_trans * trans)1231 static inline bool iwl_trans_dbg_ini_valid(struct iwl_trans *trans)
1232 {
1233 	return trans->dbg.internal_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED ||
1234 		trans->dbg.external_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED;
1235 }
1236 
1237 /*****************************************************
1238  * transport helper functions
1239  *****************************************************/
1240 struct iwl_trans *iwl_trans_alloc(unsigned int priv_size,
1241 				  struct device *dev,
1242 				  const struct iwl_trans_ops *ops);
1243 void iwl_trans_free(struct iwl_trans *trans);
1244 
1245 /*****************************************************
1246 * driver (transport) register/unregister functions
1247 ******************************************************/
1248 int __must_check iwl_pci_register_driver(void);
1249 void iwl_pci_unregister_driver(void);
1250 
1251 #endif /* __iwl_trans_h__ */
1252