1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2018 - 2020 Intel Corporation
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * BSD LICENSE
20 *
21 * Copyright(c) 2018 - 2020 Intel Corporation
22 * All rights reserved.
23 *
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
26 * are met:
27 *
28 * * Redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer.
30 * * Redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in
32 * the documentation and/or other materials provided with the
33 * distribution.
34 * * Neither the name Intel Corporation nor the names of its
35 * contributors may be used to endorse or promote products derived
36 * from this software without specific prior written permission.
37 *
38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
39 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
41 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
42 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
43 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
44 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
45 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
46 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
47 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
49 *
50 *****************************************************************************/
51
52 #include "iwl-trans.h"
53 #include "iwl-fh.h"
54 #include "iwl-context-info-gen3.h"
55 #include "internal.h"
56 #include "iwl-prph.h"
57
58 static void
iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans * trans,struct iwl_prph_scratch_hwm_cfg * dbg_cfg,u32 * control_flags)59 iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans *trans,
60 struct iwl_prph_scratch_hwm_cfg *dbg_cfg,
61 u32 *control_flags)
62 {
63 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;
64 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg;
65 u32 dbg_flags = 0;
66
67 if (!iwl_trans_dbg_ini_valid(trans)) {
68 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
69
70 iwl_pcie_alloc_fw_monitor(trans, 0);
71
72 if (fw_mon->size) {
73 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM;
74
75 IWL_DEBUG_FW(trans,
76 "WRT: Applying DRAM buffer destination\n");
77
78 dbg_cfg->hwm_base_addr = cpu_to_le64(fw_mon->physical);
79 dbg_cfg->hwm_size = cpu_to_le32(fw_mon->size);
80 }
81
82 goto out;
83 }
84
85 fw_mon_cfg = &trans->dbg.fw_mon_cfg[alloc_id];
86
87 switch (le32_to_cpu(fw_mon_cfg->buf_location)) {
88 case IWL_FW_INI_LOCATION_SRAM_PATH:
89 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL;
90 IWL_DEBUG_FW(trans,
91 "WRT: Applying SMEM buffer destination\n");
92 break;
93
94 case IWL_FW_INI_LOCATION_NPK_PATH:
95 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF;
96 IWL_DEBUG_FW(trans,
97 "WRT: Applying NPK buffer destination\n");
98 break;
99
100 case IWL_FW_INI_LOCATION_DRAM_PATH:
101 if (trans->dbg.fw_mon_ini[alloc_id].num_frags) {
102 struct iwl_dram_data *frag =
103 &trans->dbg.fw_mon_ini[alloc_id].frags[0];
104 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM;
105 dbg_cfg->hwm_base_addr = cpu_to_le64(frag->physical);
106 dbg_cfg->hwm_size = cpu_to_le32(frag->size);
107 IWL_DEBUG_FW(trans,
108 "WRT: Applying DRAM destination (alloc_id=%u, num_frags=%u)\n",
109 alloc_id,
110 trans->dbg.fw_mon_ini[alloc_id].num_frags);
111 }
112 break;
113 default:
114 IWL_ERR(trans, "WRT: Invalid buffer destination\n");
115 }
116 out:
117 if (dbg_flags)
118 *control_flags |= IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | dbg_flags;
119 }
120
iwl_pcie_ctxt_info_gen3_init(struct iwl_trans * trans,const struct fw_img * fw)121 int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
122 const struct fw_img *fw)
123 {
124 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
125 struct iwl_context_info_gen3 *ctxt_info_gen3;
126 struct iwl_prph_scratch *prph_scratch;
127 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl;
128 struct iwl_prph_info *prph_info;
129 void *iml_img;
130 u32 control_flags = 0;
131 int ret;
132 int cmdq_size = max_t(u32, IWL_CMD_QUEUE_SIZE,
133 trans->cfg->min_txq_size);
134
135 switch (trans_pcie->rx_buf_size) {
136 case IWL_AMSDU_DEF:
137 return -EINVAL;
138 case IWL_AMSDU_2K:
139 break;
140 case IWL_AMSDU_4K:
141 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
142 break;
143 case IWL_AMSDU_8K:
144 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
145 /* if firmware supports the ext size, tell it */
146 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K;
147 break;
148 case IWL_AMSDU_12K:
149 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
150 /* if firmware supports the ext size, tell it */
151 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K;
152 break;
153 }
154
155 /* Allocate prph scratch */
156 prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch),
157 &trans_pcie->prph_scratch_dma_addr,
158 GFP_KERNEL);
159 if (!prph_scratch)
160 return -ENOMEM;
161
162 prph_sc_ctrl = &prph_scratch->ctrl_cfg;
163
164 prph_sc_ctrl->version.version = 0;
165 prph_sc_ctrl->version.mac_id =
166 cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV));
167 prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4);
168
169 control_flags |= IWL_PRPH_SCRATCH_MTR_MODE;
170 control_flags |= IWL_PRPH_MTR_FORMAT_256B & IWL_PRPH_SCRATCH_MTR_FORMAT;
171
172 /* initialize RX default queue */
173 prph_sc_ctrl->rbd_cfg.free_rbd_addr =
174 cpu_to_le64(trans_pcie->rxq->bd_dma);
175
176 iwl_pcie_ctxt_info_dbg_enable(trans, &prph_sc_ctrl->hwm_cfg,
177 &control_flags);
178 prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags);
179
180 /* allocate ucode sections in dram and set addresses */
181 ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram);
182 if (ret)
183 goto err_free_prph_scratch;
184
185
186 /* Allocate prph information
187 * currently we don't assign to the prph info anything, but it would get
188 * assigned later */
189 prph_info = dma_alloc_coherent(trans->dev, sizeof(*prph_info),
190 &trans_pcie->prph_info_dma_addr,
191 GFP_KERNEL);
192 if (!prph_info) {
193 ret = -ENOMEM;
194 goto err_free_prph_scratch;
195 }
196
197 /* Allocate context info */
198 ctxt_info_gen3 = dma_alloc_coherent(trans->dev,
199 sizeof(*ctxt_info_gen3),
200 &trans_pcie->ctxt_info_dma_addr,
201 GFP_KERNEL);
202 if (!ctxt_info_gen3) {
203 ret = -ENOMEM;
204 goto err_free_prph_info;
205 }
206
207 ctxt_info_gen3->prph_info_base_addr =
208 cpu_to_le64(trans_pcie->prph_info_dma_addr);
209 ctxt_info_gen3->prph_scratch_base_addr =
210 cpu_to_le64(trans_pcie->prph_scratch_dma_addr);
211 ctxt_info_gen3->prph_scratch_size =
212 cpu_to_le32(sizeof(*prph_scratch));
213 ctxt_info_gen3->cr_head_idx_arr_base_addr =
214 cpu_to_le64(trans_pcie->rxq->rb_stts_dma);
215 ctxt_info_gen3->tr_tail_idx_arr_base_addr =
216 cpu_to_le64(trans_pcie->rxq->tr_tail_dma);
217 ctxt_info_gen3->cr_tail_idx_arr_base_addr =
218 cpu_to_le64(trans_pcie->rxq->cr_tail_dma);
219 ctxt_info_gen3->cr_idx_arr_size =
220 cpu_to_le16(IWL_NUM_OF_COMPLETION_RINGS);
221 ctxt_info_gen3->tr_idx_arr_size =
222 cpu_to_le16(IWL_NUM_OF_TRANSFER_RINGS);
223 ctxt_info_gen3->mtr_base_addr =
224 cpu_to_le64(trans->txqs.txq[trans->txqs.cmd.q_id]->dma_addr);
225 ctxt_info_gen3->mcr_base_addr =
226 cpu_to_le64(trans_pcie->rxq->used_bd_dma);
227 ctxt_info_gen3->mtr_size =
228 cpu_to_le16(TFD_QUEUE_CB_SIZE(cmdq_size));
229 ctxt_info_gen3->mcr_size =
230 cpu_to_le16(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds));
231
232 trans_pcie->ctxt_info_gen3 = ctxt_info_gen3;
233 trans_pcie->prph_info = prph_info;
234 trans_pcie->prph_scratch = prph_scratch;
235
236 /* Allocate IML */
237 iml_img = dma_alloc_coherent(trans->dev, trans->iml_len,
238 &trans_pcie->iml_dma_addr, GFP_KERNEL);
239 if (!iml_img)
240 return -ENOMEM;
241
242 memcpy(iml_img, trans->iml, trans->iml_len);
243
244 iwl_enable_fw_load_int_ctx_info(trans);
245
246 /* kick FW self load */
247 iwl_write64(trans, CSR_CTXT_INFO_ADDR,
248 trans_pcie->ctxt_info_dma_addr);
249 iwl_write64(trans, CSR_IML_DATA_ADDR,
250 trans_pcie->iml_dma_addr);
251 iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len);
252
253 iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL,
254 CSR_AUTO_FUNC_BOOT_ENA);
255
256 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) {
257 /*
258 * The firmware initializes this again later (to a smaller
259 * value), but for the boot process initialize the LTR to
260 * ~250 usec.
261 */
262 u32 val = CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ |
263 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
264 CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE) |
265 u32_encode_bits(250,
266 CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL) |
267 CSR_LTR_LONG_VAL_AD_SNOOP_REQ |
268 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
269 CSR_LTR_LONG_VAL_AD_SNOOP_SCALE) |
270 u32_encode_bits(250, CSR_LTR_LONG_VAL_AD_SNOOP_VAL);
271
272 iwl_write32(trans, CSR_LTR_LONG_VAL_AD, val);
273 }
274
275 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
276 iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1);
277 else
278 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_AUTO_FUNC_INIT);
279
280 return 0;
281
282 err_free_prph_info:
283 dma_free_coherent(trans->dev,
284 sizeof(*prph_info),
285 prph_info,
286 trans_pcie->prph_info_dma_addr);
287
288 err_free_prph_scratch:
289 dma_free_coherent(trans->dev,
290 sizeof(*prph_scratch),
291 prph_scratch,
292 trans_pcie->prph_scratch_dma_addr);
293 return ret;
294
295 }
296
iwl_pcie_ctxt_info_gen3_free(struct iwl_trans * trans)297 void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans)
298 {
299 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
300
301 if (!trans_pcie->ctxt_info_gen3)
302 return;
303
304 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3),
305 trans_pcie->ctxt_info_gen3,
306 trans_pcie->ctxt_info_dma_addr);
307 trans_pcie->ctxt_info_dma_addr = 0;
308 trans_pcie->ctxt_info_gen3 = NULL;
309
310 iwl_pcie_ctxt_info_free_fw_img(trans);
311
312 dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch),
313 trans_pcie->prph_scratch,
314 trans_pcie->prph_scratch_dma_addr);
315 trans_pcie->prph_scratch_dma_addr = 0;
316 trans_pcie->prph_scratch = NULL;
317
318 dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_info),
319 trans_pcie->prph_info,
320 trans_pcie->prph_info_dma_addr);
321 trans_pcie->prph_info_dma_addr = 0;
322 trans_pcie->prph_info = NULL;
323 }
324
iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans * trans,const void * data,u32 len)325 int iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans,
326 const void *data, u32 len)
327 {
328 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
329 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
330 &trans_pcie->prph_scratch->ctrl_cfg;
331 int ret;
332
333 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
334 return 0;
335
336 ret = iwl_pcie_ctxt_info_alloc_dma(trans, data, len,
337 &trans_pcie->pnvm_dram);
338 if (ret < 0) {
339 IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA %d.\n",
340 ret);
341 return ret;
342 }
343
344 prph_sc_ctrl->pnvm_cfg.pnvm_base_addr =
345 cpu_to_le64(trans_pcie->pnvm_dram.physical);
346 prph_sc_ctrl->pnvm_cfg.pnvm_size =
347 cpu_to_le32(trans_pcie->pnvm_dram.size);
348
349 return 0;
350 }
351
