1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2018 Intel Corporation
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23 * USA
24 *
25 * The full GNU General Public License is included in this distribution
26 * in the file called COPYING.
27 *
28 * Contact Information:
29 * Intel Linux Wireless <linuxwifi@intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 *
32 * BSD LICENSE
33 *
34 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
35 * Copyright(c) 2018 Intel Corporation
36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 *
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *****************************************************************************/
64 #include <linux/types.h>
65 #include <linux/slab.h>
66 #include <linux/export.h>
67
68 #include "iwl-drv.h"
69 #include "iwl-debug.h"
70 #include "iwl-eeprom-read.h"
71 #include "iwl-io.h"
72 #include "iwl-prph.h"
73 #include "iwl-csr.h"
74
75 /*
76 * EEPROM access time values:
77 *
78 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
79 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
80 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
81 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
82 */
83 #define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
84
85 #define IWL_EEPROM_SEM_TIMEOUT 10 /* microseconds */
86 #define IWL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
87
88
89 /*
90 * The device's EEPROM semaphore prevents conflicts between driver and uCode
91 * when accessing the EEPROM; each access is a series of pulses to/from the
92 * EEPROM chip, not a single event, so even reads could conflict if they
93 * weren't arbitrated by the semaphore.
94 */
95
96 #define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
97 #define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
98
iwl_eeprom_acquire_semaphore(struct iwl_trans * trans)99 static int iwl_eeprom_acquire_semaphore(struct iwl_trans *trans)
100 {
101 u16 count;
102 int ret;
103
104 for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
105 /* Request semaphore */
106 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
107 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
108
109 /* See if we got it */
110 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
111 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
112 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
113 EEPROM_SEM_TIMEOUT);
114 if (ret >= 0) {
115 IWL_DEBUG_EEPROM(trans->dev,
116 "Acquired semaphore after %d tries.\n",
117 count+1);
118 return ret;
119 }
120 }
121
122 return ret;
123 }
124
iwl_eeprom_release_semaphore(struct iwl_trans * trans)125 static void iwl_eeprom_release_semaphore(struct iwl_trans *trans)
126 {
127 iwl_clear_bit(trans, CSR_HW_IF_CONFIG_REG,
128 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
129 }
130
iwl_eeprom_verify_signature(struct iwl_trans * trans,bool nvm_is_otp)131 static int iwl_eeprom_verify_signature(struct iwl_trans *trans, bool nvm_is_otp)
132 {
133 u32 gp = iwl_read32(trans, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
134
135 IWL_DEBUG_EEPROM(trans->dev, "EEPROM signature=0x%08x\n", gp);
136
137 switch (gp) {
138 case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP:
139 if (!nvm_is_otp) {
140 IWL_ERR(trans, "EEPROM with bad signature: 0x%08x\n",
141 gp);
142 return -ENOENT;
143 }
144 return 0;
145 case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
146 case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
147 if (nvm_is_otp) {
148 IWL_ERR(trans, "OTP with bad signature: 0x%08x\n", gp);
149 return -ENOENT;
150 }
151 return 0;
152 case CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP:
153 default:
154 IWL_ERR(trans,
155 "bad EEPROM/OTP signature, type=%s, EEPROM_GP=0x%08x\n",
156 nvm_is_otp ? "OTP" : "EEPROM", gp);
157 return -ENOENT;
158 }
159 }
160
161 /******************************************************************************
162 *
163 * OTP related functions
164 *
165 ******************************************************************************/
166
iwl_set_otp_access_absolute(struct iwl_trans * trans)167 static void iwl_set_otp_access_absolute(struct iwl_trans *trans)
168 {
169 iwl_read32(trans, CSR_OTP_GP_REG);
170
171 iwl_clear_bit(trans, CSR_OTP_GP_REG,
172 CSR_OTP_GP_REG_OTP_ACCESS_MODE);
173 }
174
iwl_nvm_is_otp(struct iwl_trans * trans)175 static int iwl_nvm_is_otp(struct iwl_trans *trans)
176 {
177 u32 otpgp;
178
179 /* OTP only valid for CP/PP and after */
180 switch (trans->hw_rev & CSR_HW_REV_TYPE_MSK) {
181 case CSR_HW_REV_TYPE_NONE:
182 IWL_ERR(trans, "Unknown hardware type\n");
183 return -EIO;
184 case CSR_HW_REV_TYPE_5300:
185 case CSR_HW_REV_TYPE_5350:
186 case CSR_HW_REV_TYPE_5100:
187 case CSR_HW_REV_TYPE_5150:
188 return 0;
189 default:
190 otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
191 if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT)
192 return 1;
193 return 0;
194 }
195 }
196
iwl_init_otp_access(struct iwl_trans * trans)197 static int iwl_init_otp_access(struct iwl_trans *trans)
198 {
199 int ret;
200
201 /* Enable 40MHz radio clock */
202 iwl_write32(trans, CSR_GP_CNTRL,
203 iwl_read32(trans, CSR_GP_CNTRL) |
204 BIT(trans->cfg->csr->flag_init_done));
205
206 /* wait for clock to be ready */
207 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
208 BIT(trans->cfg->csr->flag_mac_clock_ready),
209 BIT(trans->cfg->csr->flag_mac_clock_ready),
210 25000);
211 if (ret < 0) {
212 IWL_ERR(trans, "Time out access OTP\n");
213 } else {
214 iwl_set_bits_prph(trans, APMG_PS_CTRL_REG,
215 APMG_PS_CTRL_VAL_RESET_REQ);
216 udelay(5);
217 iwl_clear_bits_prph(trans, APMG_PS_CTRL_REG,
218 APMG_PS_CTRL_VAL_RESET_REQ);
219
220 /*
221 * CSR auto clock gate disable bit -
222 * this is only applicable for HW with OTP shadow RAM
223 */
224 if (trans->cfg->base_params->shadow_ram_support)
225 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
226 CSR_RESET_LINK_PWR_MGMT_DISABLED);
227 }
228 return ret;
229 }
230
iwl_read_otp_word(struct iwl_trans * trans,u16 addr,__le16 * eeprom_data)231 static int iwl_read_otp_word(struct iwl_trans *trans, u16 addr,
232 __le16 *eeprom_data)
233 {
234 int ret = 0;
235 u32 r;
236 u32 otpgp;
237
238 iwl_write32(trans, CSR_EEPROM_REG,
239 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
240 ret = iwl_poll_bit(trans, CSR_EEPROM_REG,
241 CSR_EEPROM_REG_READ_VALID_MSK,
242 CSR_EEPROM_REG_READ_VALID_MSK,
243 IWL_EEPROM_ACCESS_TIMEOUT);
244 if (ret < 0) {
245 IWL_ERR(trans, "Time out reading OTP[%d]\n", addr);
246 return ret;
247 }
248 r = iwl_read32(trans, CSR_EEPROM_REG);
249 /* check for ECC errors: */
250 otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
251 if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
252 /* stop in this case */
253 /* set the uncorrectable OTP ECC bit for acknowledgment */
254 iwl_set_bit(trans, CSR_OTP_GP_REG,
255 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
256 IWL_ERR(trans, "Uncorrectable OTP ECC error, abort OTP read\n");
257 return -EINVAL;
258 }
259 if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
260 /* continue in this case */
261 /* set the correctable OTP ECC bit for acknowledgment */
262 iwl_set_bit(trans, CSR_OTP_GP_REG,
263 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
264 IWL_ERR(trans, "Correctable OTP ECC error, continue read\n");
265 }
266 *eeprom_data = cpu_to_le16(r >> 16);
267 return 0;
268 }
269
270 /*
271 * iwl_is_otp_empty: check for empty OTP
272 */
iwl_is_otp_empty(struct iwl_trans * trans)273 static bool iwl_is_otp_empty(struct iwl_trans *trans)
274 {
275 u16 next_link_addr = 0;
276 __le16 link_value;
277 bool is_empty = false;
278
279 /* locate the beginning of OTP link list */
280 if (!iwl_read_otp_word(trans, next_link_addr, &link_value)) {
281 if (!link_value) {
282 IWL_ERR(trans, "OTP is empty\n");
283 is_empty = true;
284 }
285 } else {
286 IWL_ERR(trans, "Unable to read first block of OTP list.\n");
287 is_empty = true;
288 }
289
290 return is_empty;
291 }
292
293
294 /*
295 * iwl_find_otp_image: find EEPROM image in OTP
296 * finding the OTP block that contains the EEPROM image.
297 * the last valid block on the link list (the block _before_ the last block)
298 * is the block we should read and used to configure the device.
299 * If all the available OTP blocks are full, the last block will be the block
300 * we should read and used to configure the device.
301 * only perform this operation if shadow RAM is disabled
302 */
iwl_find_otp_image(struct iwl_trans * trans,u16 * validblockaddr)303 static int iwl_find_otp_image(struct iwl_trans *trans,
304 u16 *validblockaddr)
305 {
306 u16 next_link_addr = 0, valid_addr;
307 __le16 link_value = 0;
308 int usedblocks = 0;
309
310 /* set addressing mode to absolute to traverse the link list */
311 iwl_set_otp_access_absolute(trans);
312
313 /* checking for empty OTP or error */
314 if (iwl_is_otp_empty(trans))
315 return -EINVAL;
316
317 /*
318 * start traverse link list
319 * until reach the max number of OTP blocks
320 * different devices have different number of OTP blocks
321 */
322 do {
323 /* save current valid block address
324 * check for more block on the link list
325 */
326 valid_addr = next_link_addr;
327 next_link_addr = le16_to_cpu(link_value) * sizeof(u16);
328 IWL_DEBUG_EEPROM(trans->dev, "OTP blocks %d addr 0x%x\n",
329 usedblocks, next_link_addr);
330 if (iwl_read_otp_word(trans, next_link_addr, &link_value))
331 return -EINVAL;
332 if (!link_value) {
333 /*
334 * reach the end of link list, return success and
335 * set address point to the starting address
336 * of the image
337 */
338 *validblockaddr = valid_addr;
339 /* skip first 2 bytes (link list pointer) */
340 *validblockaddr += 2;
341 return 0;
342 }
343 /* more in the link list, continue */
344 usedblocks++;
345 } while (usedblocks <= trans->cfg->base_params->max_ll_items);
346
347 /* OTP has no valid blocks */
348 IWL_DEBUG_EEPROM(trans->dev, "OTP has no valid blocks\n");
349 return -EINVAL;
350 }
351
352 /**
353 * iwl_read_eeprom - read EEPROM contents
354 *
355 * Load the EEPROM contents from adapter and return it
356 * and its size.
357 *
358 * NOTE: This routine uses the non-debug IO access functions.
359 */
iwl_read_eeprom(struct iwl_trans * trans,u8 ** eeprom,size_t * eeprom_size)360 int iwl_read_eeprom(struct iwl_trans *trans, u8 **eeprom, size_t *eeprom_size)
361 {
362 __le16 *e;
363 u32 gp = iwl_read32(trans, CSR_EEPROM_GP);
364 int sz;
365 int ret;
366 u16 addr;
367 u16 validblockaddr = 0;
368 u16 cache_addr = 0;
369 int nvm_is_otp;
370
371 if (!eeprom || !eeprom_size)
372 return -EINVAL;
373
374 nvm_is_otp = iwl_nvm_is_otp(trans);
375 if (nvm_is_otp < 0)
376 return nvm_is_otp;
377
378 sz = trans->cfg->base_params->eeprom_size;
379 IWL_DEBUG_EEPROM(trans->dev, "NVM size = %d\n", sz);
380
381 e = kmalloc(sz, GFP_KERNEL);
382 if (!e)
383 return -ENOMEM;
384
385 ret = iwl_eeprom_verify_signature(trans, nvm_is_otp);
386 if (ret < 0) {
387 IWL_ERR(trans, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
388 goto err_free;
389 }
390
391 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
392 ret = iwl_eeprom_acquire_semaphore(trans);
393 if (ret < 0) {
394 IWL_ERR(trans, "Failed to acquire EEPROM semaphore.\n");
395 goto err_free;
396 }
397
398 if (nvm_is_otp) {
399 ret = iwl_init_otp_access(trans);
400 if (ret) {
401 IWL_ERR(trans, "Failed to initialize OTP access.\n");
402 goto err_unlock;
403 }
404
405 iwl_write32(trans, CSR_EEPROM_GP,
406 iwl_read32(trans, CSR_EEPROM_GP) &
407 ~CSR_EEPROM_GP_IF_OWNER_MSK);
408
409 iwl_set_bit(trans, CSR_OTP_GP_REG,
410 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
411 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
412 /* traversing the linked list if no shadow ram supported */
413 if (!trans->cfg->base_params->shadow_ram_support) {
414 ret = iwl_find_otp_image(trans, &validblockaddr);
415 if (ret)
416 goto err_unlock;
417 }
418 for (addr = validblockaddr; addr < validblockaddr + sz;
419 addr += sizeof(u16)) {
420 __le16 eeprom_data;
421
422 ret = iwl_read_otp_word(trans, addr, &eeprom_data);
423 if (ret)
424 goto err_unlock;
425 e[cache_addr / 2] = eeprom_data;
426 cache_addr += sizeof(u16);
427 }
428 } else {
429 /* eeprom is an array of 16bit values */
430 for (addr = 0; addr < sz; addr += sizeof(u16)) {
431 u32 r;
432
433 iwl_write32(trans, CSR_EEPROM_REG,
434 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
435
436 ret = iwl_poll_bit(trans, CSR_EEPROM_REG,
437 CSR_EEPROM_REG_READ_VALID_MSK,
438 CSR_EEPROM_REG_READ_VALID_MSK,
439 IWL_EEPROM_ACCESS_TIMEOUT);
440 if (ret < 0) {
441 IWL_ERR(trans,
442 "Time out reading EEPROM[%d]\n", addr);
443 goto err_unlock;
444 }
445 r = iwl_read32(trans, CSR_EEPROM_REG);
446 e[addr / 2] = cpu_to_le16(r >> 16);
447 }
448 }
449
450 IWL_DEBUG_EEPROM(trans->dev, "NVM Type: %s\n",
451 nvm_is_otp ? "OTP" : "EEPROM");
452
453 iwl_eeprom_release_semaphore(trans);
454
455 *eeprom_size = sz;
456 *eeprom = (u8 *)e;
457 return 0;
458
459 err_unlock:
460 iwl_eeprom_release_semaphore(trans);
461 err_free:
462 kfree(e);
463
464 return ret;
465 }
466 IWL_EXPORT_SYMBOL(iwl_read_eeprom);
467
