1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved.
4 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
5 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
6 * Copyright(c) 2018 Intel Corporation
7 *
8 * Portions of this file are derived from the ipw3945 project, as well
9 * as portions of the ieee80211 subsystem header files.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 *
20 * You should have received a copy of the GNU General Public License along with
21 * this program.
22 *
23 * The full GNU General Public License is included in this distribution in the
24 * file called LICENSE.
25 *
26 * Contact Information:
27 * Intel Linux Wireless <linuxwifi@intel.com>
28 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
29 *
30 *****************************************************************************/
31 #ifndef __iwl_trans_int_pcie_h__
32 #define __iwl_trans_int_pcie_h__
33
34 #include <linux/spinlock.h>
35 #include <linux/interrupt.h>
36 #include <linux/skbuff.h>
37 #include <linux/wait.h>
38 #include <linux/pci.h>
39 #include <linux/timer.h>
40 #include <linux/cpu.h>
41
42 #include "iwl-fh.h"
43 #include "iwl-csr.h"
44 #include "iwl-trans.h"
45 #include "iwl-debug.h"
46 #include "iwl-io.h"
47 #include "iwl-op-mode.h"
48 #include "iwl-drv.h"
49
50 /* We need 2 entries for the TX command and header, and another one might
51 * be needed for potential data in the SKB's head. The remaining ones can
52 * be used for frags.
53 */
54 #define IWL_PCIE_MAX_FRAGS(x) (x->max_tbs - 3)
55
56 /*
57 * RX related structures and functions
58 */
59 #define RX_NUM_QUEUES 1
60 #define RX_POST_REQ_ALLOC 2
61 #define RX_CLAIM_REQ_ALLOC 8
62 #define RX_PENDING_WATERMARK 16
63 #define FIRST_RX_QUEUE 512
64
65 struct iwl_host_cmd;
66
67 /*This file includes the declaration that are internal to the
68 * trans_pcie layer */
69
70 /**
71 * struct iwl_rx_mem_buffer
72 * @page_dma: bus address of rxb page
73 * @page: driver's pointer to the rxb page
74 * @invalid: rxb is in driver ownership - not owned by HW
75 * @vid: index of this rxb in the global table
76 * @size: size used from the buffer
77 */
78 struct iwl_rx_mem_buffer {
79 dma_addr_t page_dma;
80 struct page *page;
81 u16 vid;
82 bool invalid;
83 struct list_head list;
84 u32 size;
85 };
86
87 /**
88 * struct isr_statistics - interrupt statistics
89 *
90 */
91 struct isr_statistics {
92 u32 hw;
93 u32 sw;
94 u32 err_code;
95 u32 sch;
96 u32 alive;
97 u32 rfkill;
98 u32 ctkill;
99 u32 wakeup;
100 u32 rx;
101 u32 tx;
102 u32 unhandled;
103 };
104
105 #define IWL_CD_STTS_OPTIMIZED_POS 0
106 #define IWL_CD_STTS_OPTIMIZED_MSK 0x01
107 #define IWL_CD_STTS_TRANSFER_STATUS_POS 1
108 #define IWL_CD_STTS_TRANSFER_STATUS_MSK 0x0E
109 #define IWL_CD_STTS_WIFI_STATUS_POS 4
110 #define IWL_CD_STTS_WIFI_STATUS_MSK 0xF0
111
112 /**
113 * enum iwl_completion_desc_transfer_status - transfer status (bits 1-3)
114 * @IWL_CD_STTS_END_TRANSFER: successful transfer complete.
115 * In sniffer mode, when split is used, set in last CD completion. (RX)
116 * @IWL_CD_STTS_OVERFLOW: In sniffer mode, when using split - used for
117 * all CD completion. (RX)
118 * @IWL_CD_STTS_ABORTED: CR abort / close flow. (RX)
119 */
120 enum iwl_completion_desc_transfer_status {
121 IWL_CD_STTS_UNUSED,
122 IWL_CD_STTS_UNUSED_2,
123 IWL_CD_STTS_END_TRANSFER,
124 IWL_CD_STTS_OVERFLOW,
125 IWL_CD_STTS_ABORTED,
126 IWL_CD_STTS_ERROR,
127 };
128
129 /**
130 * enum iwl_completion_desc_wifi_status - wifi status (bits 4-7)
131 * @IWL_CD_STTS_VALID: the packet is valid (RX)
132 * @IWL_CD_STTS_FCS_ERR: frame check sequence error (RX)
133 * @IWL_CD_STTS_SEC_KEY_ERR: error handling the security key of rx (RX)
134 * @IWL_CD_STTS_DECRYPTION_ERR: error decrypting the frame (RX)
135 * @IWL_CD_STTS_DUP: duplicate packet (RX)
136 * @IWL_CD_STTS_ICV_MIC_ERR: MIC error (RX)
137 * @IWL_CD_STTS_INTERNAL_SNAP_ERR: problems removing the snap (RX)
138 * @IWL_CD_STTS_SEC_PORT_FAIL: security port fail (RX)
139 * @IWL_CD_STTS_BA_OLD_SN: block ack received old SN (RX)
140 * @IWL_CD_STTS_QOS_NULL: QoS null packet (RX)
141 * @IWL_CD_STTS_MAC_HDR_ERR: MAC header conversion error (RX)
142 * @IWL_CD_STTS_MAX_RETRANS: reached max number of retransmissions (TX)
143 * @IWL_CD_STTS_EX_LIFETIME: exceeded lifetime (TX)
144 * @IWL_CD_STTS_NOT_USED: completed but not used (RX)
145 * @IWL_CD_STTS_REPLAY_ERR: pn check failed, replay error (RX)
146 */
147 enum iwl_completion_desc_wifi_status {
148 IWL_CD_STTS_VALID,
149 IWL_CD_STTS_FCS_ERR,
150 IWL_CD_STTS_SEC_KEY_ERR,
151 IWL_CD_STTS_DECRYPTION_ERR,
152 IWL_CD_STTS_DUP,
153 IWL_CD_STTS_ICV_MIC_ERR,
154 IWL_CD_STTS_INTERNAL_SNAP_ERR,
155 IWL_CD_STTS_SEC_PORT_FAIL,
156 IWL_CD_STTS_BA_OLD_SN,
157 IWL_CD_STTS_QOS_NULL,
158 IWL_CD_STTS_MAC_HDR_ERR,
159 IWL_CD_STTS_MAX_RETRANS,
160 IWL_CD_STTS_EX_LIFETIME,
161 IWL_CD_STTS_NOT_USED,
162 IWL_CD_STTS_REPLAY_ERR,
163 };
164
165 #define IWL_RX_TD_TYPE_MSK 0xff000000
166 #define IWL_RX_TD_SIZE_MSK 0x00ffffff
167 #define IWL_RX_TD_SIZE_2K BIT(11)
168 #define IWL_RX_TD_TYPE 0
169
170 /**
171 * struct iwl_rx_transfer_desc - transfer descriptor
172 * @type_n_size: buffer type (bit 0: external buff valid,
173 * bit 1: optional footer valid, bit 2-7: reserved)
174 * and buffer size
175 * @addr: ptr to free buffer start address
176 * @rbid: unique tag of the buffer
177 * @reserved: reserved
178 */
179 struct iwl_rx_transfer_desc {
180 __le32 type_n_size;
181 __le64 addr;
182 __le16 rbid;
183 __le16 reserved;
184 } __packed;
185
186 #define IWL_RX_CD_SIZE 0xffffff00
187
188 /**
189 * struct iwl_rx_completion_desc - completion descriptor
190 * @type: buffer type (bit 0: external buff valid,
191 * bit 1: optional footer valid, bit 2-7: reserved)
192 * @status: status of the completion
193 * @reserved1: reserved
194 * @rbid: unique tag of the received buffer
195 * @size: buffer size, masked by IWL_RX_CD_SIZE
196 * @reserved2: reserved
197 */
198 struct iwl_rx_completion_desc {
199 u8 type;
200 u8 status;
201 __le16 reserved1;
202 __le16 rbid;
203 __le32 size;
204 u8 reserved2[22];
205 } __packed;
206
207 /**
208 * struct iwl_rxq - Rx queue
209 * @id: queue index
210 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd).
211 * Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices.
212 * In 22560 devices it is a pointer to a list of iwl_rx_transfer_desc's
213 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
214 * @ubd: driver's pointer to buffer of used receive buffer descriptors (rbd)
215 * @ubd_dma: physical address of buffer of used receive buffer descriptors (rbd)
216 * @tr_tail: driver's pointer to the transmission ring tail buffer
217 * @tr_tail_dma: physical address of the buffer for the transmission ring tail
218 * @cr_tail: driver's pointer to the completion ring tail buffer
219 * @cr_tail_dma: physical address of the buffer for the completion ring tail
220 * @read: Shared index to newest available Rx buffer
221 * @write: Shared index to oldest written Rx packet
222 * @free_count: Number of pre-allocated buffers in rx_free
223 * @used_count: Number of RBDs handled to allocator to use for allocation
224 * @write_actual:
225 * @rx_free: list of RBDs with allocated RB ready for use
226 * @rx_used: list of RBDs with no RB attached
227 * @need_update: flag to indicate we need to update read/write index
228 * @rb_stts: driver's pointer to receive buffer status
229 * @rb_stts_dma: bus address of receive buffer status
230 * @lock:
231 * @queue: actual rx queue. Not used for multi-rx queue.
232 *
233 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
234 */
235 struct iwl_rxq {
236 int id;
237 void *bd;
238 dma_addr_t bd_dma;
239 union {
240 void *used_bd;
241 __le32 *bd_32;
242 struct iwl_rx_completion_desc *cd;
243 };
244 dma_addr_t used_bd_dma;
245 __le16 *tr_tail;
246 dma_addr_t tr_tail_dma;
247 __le16 *cr_tail;
248 dma_addr_t cr_tail_dma;
249 u32 read;
250 u32 write;
251 u32 free_count;
252 u32 used_count;
253 u32 write_actual;
254 u32 queue_size;
255 struct list_head rx_free;
256 struct list_head rx_used;
257 bool need_update;
258 void *rb_stts;
259 dma_addr_t rb_stts_dma;
260 spinlock_t lock;
261 struct napi_struct napi;
262 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
263 };
264
265 /**
266 * struct iwl_rb_allocator - Rx allocator
267 * @req_pending: number of requests the allcator had not processed yet
268 * @req_ready: number of requests honored and ready for claiming
269 * @rbd_allocated: RBDs with pages allocated and ready to be handled to
270 * the queue. This is a list of &struct iwl_rx_mem_buffer
271 * @rbd_empty: RBDs with no page attached for allocator use. This is a list
272 * of &struct iwl_rx_mem_buffer
273 * @lock: protects the rbd_allocated and rbd_empty lists
274 * @alloc_wq: work queue for background calls
275 * @rx_alloc: work struct for background calls
276 */
277 struct iwl_rb_allocator {
278 atomic_t req_pending;
279 atomic_t req_ready;
280 struct list_head rbd_allocated;
281 struct list_head rbd_empty;
282 spinlock_t lock;
283 struct workqueue_struct *alloc_wq;
284 struct work_struct rx_alloc;
285 };
286
287 struct iwl_dma_ptr {
288 dma_addr_t dma;
289 void *addr;
290 size_t size;
291 };
292
293 /**
294 * iwl_queue_inc_wrap - increment queue index, wrap back to beginning
295 * @index -- current index
296 */
iwl_queue_inc_wrap(struct iwl_trans * trans,int index)297 static inline int iwl_queue_inc_wrap(struct iwl_trans *trans, int index)
298 {
299 return ++index & (trans->cfg->base_params->max_tfd_queue_size - 1);
300 }
301
302 /**
303 * iwl_get_closed_rb_stts - get closed rb stts from different structs
304 * @rxq - the rxq to get the rb stts from
305 */
iwl_get_closed_rb_stts(struct iwl_trans * trans,struct iwl_rxq * rxq)306 static inline __le16 iwl_get_closed_rb_stts(struct iwl_trans *trans,
307 struct iwl_rxq *rxq)
308 {
309 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) {
310 __le16 *rb_stts = rxq->rb_stts;
311
312 return READ_ONCE(*rb_stts);
313 } else {
314 struct iwl_rb_status *rb_stts = rxq->rb_stts;
315
316 return READ_ONCE(rb_stts->closed_rb_num);
317 }
318 }
319
320 /**
321 * iwl_queue_dec_wrap - decrement queue index, wrap back to end
322 * @index -- current index
323 */
iwl_queue_dec_wrap(struct iwl_trans * trans,int index)324 static inline int iwl_queue_dec_wrap(struct iwl_trans *trans, int index)
325 {
326 return --index & (trans->cfg->base_params->max_tfd_queue_size - 1);
327 }
328
329 struct iwl_cmd_meta {
330 /* only for SYNC commands, iff the reply skb is wanted */
331 struct iwl_host_cmd *source;
332 u32 flags;
333 u32 tbs;
334 };
335
336
337 #define TFD_TX_CMD_SLOTS 256
338 #define TFD_CMD_SLOTS 32
339
340 /*
341 * The FH will write back to the first TB only, so we need to copy some data
342 * into the buffer regardless of whether it should be mapped or not.
343 * This indicates how big the first TB must be to include the scratch buffer
344 * and the assigned PN.
345 * Since PN location is 8 bytes at offset 12, it's 20 now.
346 * If we make it bigger then allocations will be bigger and copy slower, so
347 * that's probably not useful.
348 */
349 #define IWL_FIRST_TB_SIZE 20
350 #define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64)
351
352 struct iwl_pcie_txq_entry {
353 struct iwl_device_cmd *cmd;
354 struct sk_buff *skb;
355 /* buffer to free after command completes */
356 const void *free_buf;
357 struct iwl_cmd_meta meta;
358 };
359
360 struct iwl_pcie_first_tb_buf {
361 u8 buf[IWL_FIRST_TB_SIZE_ALIGN];
362 };
363
364 /**
365 * struct iwl_txq - Tx Queue for DMA
366 * @q: generic Rx/Tx queue descriptor
367 * @tfds: transmit frame descriptors (DMA memory)
368 * @first_tb_bufs: start of command headers, including scratch buffers, for
369 * the writeback -- this is DMA memory and an array holding one buffer
370 * for each command on the queue
371 * @first_tb_dma: DMA address for the first_tb_bufs start
372 * @entries: transmit entries (driver state)
373 * @lock: queue lock
374 * @stuck_timer: timer that fires if queue gets stuck
375 * @trans_pcie: pointer back to transport (for timer)
376 * @need_update: indicates need to update read/write index
377 * @ampdu: true if this queue is an ampdu queue for an specific RA/TID
378 * @wd_timeout: queue watchdog timeout (jiffies) - per queue
379 * @frozen: tx stuck queue timer is frozen
380 * @frozen_expiry_remainder: remember how long until the timer fires
381 * @bc_tbl: byte count table of the queue (relevant only for gen2 transport)
382 * @write_ptr: 1-st empty entry (index) host_w
383 * @read_ptr: last used entry (index) host_r
384 * @dma_addr: physical addr for BD's
385 * @n_window: safe queue window
386 * @id: queue id
387 * @low_mark: low watermark, resume queue if free space more than this
388 * @high_mark: high watermark, stop queue if free space less than this
389 *
390 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
391 * descriptors) and required locking structures.
392 *
393 * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware
394 * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless
395 * there might be HW changes in the future). For the normal TX
396 * queues, n_window, which is the size of the software queue data
397 * is also 256; however, for the command queue, n_window is only
398 * 32 since we don't need so many commands pending. Since the HW
399 * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256.
400 * This means that we end up with the following:
401 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
402 * SW entries: | 0 | ... | 31 |
403 * where N is a number between 0 and 7. This means that the SW
404 * data is a window overlayed over the HW queue.
405 */
406 struct iwl_txq {
407 void *tfds;
408 struct iwl_pcie_first_tb_buf *first_tb_bufs;
409 dma_addr_t first_tb_dma;
410 struct iwl_pcie_txq_entry *entries;
411 spinlock_t lock;
412 unsigned long frozen_expiry_remainder;
413 struct timer_list stuck_timer;
414 struct iwl_trans_pcie *trans_pcie;
415 bool need_update;
416 bool frozen;
417 bool ampdu;
418 int block;
419 unsigned long wd_timeout;
420 struct sk_buff_head overflow_q;
421 struct iwl_dma_ptr bc_tbl;
422
423 int write_ptr;
424 int read_ptr;
425 dma_addr_t dma_addr;
426 int n_window;
427 u32 id;
428 int low_mark;
429 int high_mark;
430 };
431
432 static inline dma_addr_t
iwl_pcie_get_first_tb_dma(struct iwl_txq * txq,int idx)433 iwl_pcie_get_first_tb_dma(struct iwl_txq *txq, int idx)
434 {
435 return txq->first_tb_dma +
436 sizeof(struct iwl_pcie_first_tb_buf) * idx;
437 }
438
439 struct iwl_tso_hdr_page {
440 struct page *page;
441 u8 *pos;
442 };
443
444 /**
445 * enum iwl_shared_irq_flags - level of sharing for irq
446 * @IWL_SHARED_IRQ_NON_RX: interrupt vector serves non rx causes.
447 * @IWL_SHARED_IRQ_FIRST_RSS: interrupt vector serves first RSS queue.
448 */
449 enum iwl_shared_irq_flags {
450 IWL_SHARED_IRQ_NON_RX = BIT(0),
451 IWL_SHARED_IRQ_FIRST_RSS = BIT(1),
452 };
453
454 /**
455 * enum iwl_image_response_code - image response values
456 * @IWL_IMAGE_RESP_DEF: the default value of the register
457 * @IWL_IMAGE_RESP_SUCCESS: iml was read successfully
458 * @IWL_IMAGE_RESP_FAIL: iml reading failed
459 */
460 enum iwl_image_response_code {
461 IWL_IMAGE_RESP_DEF = 0,
462 IWL_IMAGE_RESP_SUCCESS = 1,
463 IWL_IMAGE_RESP_FAIL = 2,
464 };
465
466 /**
467 * struct iwl_dram_data
468 * @physical: page phy pointer
469 * @block: pointer to the allocated block/page
470 * @size: size of the block/page
471 */
472 struct iwl_dram_data {
473 dma_addr_t physical;
474 void *block;
475 int size;
476 };
477
478 /**
479 * struct iwl_self_init_dram - dram data used by self init process
480 * @fw: lmac and umac dram data
481 * @fw_cnt: total number of items in array
482 * @paging: paging dram data
483 * @paging_cnt: total number of items in array
484 */
485 struct iwl_self_init_dram {
486 struct iwl_dram_data *fw;
487 int fw_cnt;
488 struct iwl_dram_data *paging;
489 int paging_cnt;
490 };
491
492 /**
493 * struct iwl_trans_pcie - PCIe transport specific data
494 * @rxq: all the RX queue data
495 * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues
496 * @global_table: table mapping received VID from hw to rxb
497 * @rba: allocator for RX replenishing
498 * @ctxt_info: context information for FW self init
499 * @ctxt_info_gen3: context information for gen3 devices
500 * @prph_info: prph info for self init
501 * @prph_scratch: prph scratch for self init
502 * @ctxt_info_dma_addr: dma addr of context information
503 * @prph_info_dma_addr: dma addr of prph info
504 * @prph_scratch_dma_addr: dma addr of prph scratch
505 * @ctxt_info_dma_addr: dma addr of context information
506 * @init_dram: DRAM data of firmware image (including paging).
507 * Context information addresses will be taken from here.
508 * This is driver's local copy for keeping track of size and
509 * count for allocating and freeing the memory.
510 * @trans: pointer to the generic transport area
511 * @scd_base_addr: scheduler sram base address in SRAM
512 * @scd_bc_tbls: pointer to the byte count table of the scheduler
513 * @kw: keep warm address
514 * @pci_dev: basic pci-network driver stuff
515 * @hw_base: pci hardware address support
516 * @ucode_write_complete: indicates that the ucode has been copied.
517 * @ucode_write_waitq: wait queue for uCode load
518 * @cmd_queue - command queue number
519 * @rx_buf_size: Rx buffer size
520 * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes)
521 * @scd_set_active: should the transport configure the SCD for HCMD queue
522 * @sw_csum_tx: if true, then the transport will compute the csum of the TXed
523 * frame.
524 * @rx_page_order: page order for receive buffer size
525 * @reg_lock: protect hw register access
526 * @mutex: to protect stop_device / start_fw / start_hw
527 * @cmd_in_flight: true when we have a host command in flight
528 * @fw_mon_phys: physical address of the buffer for the firmware monitor
529 * @fw_mon_page: points to the first page of the buffer for the firmware monitor
530 * @fw_mon_size: size of the buffer for the firmware monitor
531 * @msix_entries: array of MSI-X entries
532 * @msix_enabled: true if managed to enable MSI-X
533 * @shared_vec_mask: the type of causes the shared vector handles
534 * (see iwl_shared_irq_flags).
535 * @alloc_vecs: the number of interrupt vectors allocated by the OS
536 * @def_irq: default irq for non rx causes
537 * @fh_init_mask: initial unmasked fh causes
538 * @hw_init_mask: initial unmasked hw causes
539 * @fh_mask: current unmasked fh causes
540 * @hw_mask: current unmasked hw causes
541 * @in_rescan: true if we have triggered a device rescan
542 * @scheduled_for_removal: true if we have scheduled a device removal
543 */
544 struct iwl_trans_pcie {
545 struct iwl_rxq *rxq;
546 struct iwl_rx_mem_buffer rx_pool[RX_POOL_SIZE];
547 struct iwl_rx_mem_buffer *global_table[RX_POOL_SIZE];
548 struct iwl_rb_allocator rba;
549 union {
550 struct iwl_context_info *ctxt_info;
551 struct iwl_context_info_gen3 *ctxt_info_gen3;
552 };
553 struct iwl_prph_info *prph_info;
554 struct iwl_prph_scratch *prph_scratch;
555 dma_addr_t ctxt_info_dma_addr;
556 dma_addr_t prph_info_dma_addr;
557 dma_addr_t prph_scratch_dma_addr;
558 dma_addr_t iml_dma_addr;
559 struct iwl_self_init_dram init_dram;
560 struct iwl_trans *trans;
561
562 struct net_device napi_dev;
563
564 struct __percpu iwl_tso_hdr_page *tso_hdr_page;
565
566 /* INT ICT Table */
567 __le32 *ict_tbl;
568 dma_addr_t ict_tbl_dma;
569 int ict_index;
570 bool use_ict;
571 bool is_down, opmode_down;
572 bool debug_rfkill;
573 struct isr_statistics isr_stats;
574
575 spinlock_t irq_lock;
576 struct mutex mutex;
577 u32 inta_mask;
578 u32 scd_base_addr;
579 struct iwl_dma_ptr scd_bc_tbls;
580 struct iwl_dma_ptr kw;
581
582 struct iwl_txq *txq_memory;
583 struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES];
584 unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)];
585 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)];
586
587 /* PCI bus related data */
588 struct pci_dev *pci_dev;
589 void __iomem *hw_base;
590
591 bool ucode_write_complete;
592 wait_queue_head_t ucode_write_waitq;
593 wait_queue_head_t wait_command_queue;
594 wait_queue_head_t d0i3_waitq;
595
596 u8 page_offs, dev_cmd_offs;
597
598 u8 cmd_queue;
599 u8 cmd_fifo;
600 unsigned int cmd_q_wdg_timeout;
601 u8 n_no_reclaim_cmds;
602 u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];
603 u8 max_tbs;
604 u16 tfd_size;
605
606 enum iwl_amsdu_size rx_buf_size;
607 bool bc_table_dword;
608 bool scd_set_active;
609 bool sw_csum_tx;
610 bool pcie_dbg_dumped_once;
611 u32 rx_page_order;
612
613 /*protect hw register */
614 spinlock_t reg_lock;
615 bool cmd_hold_nic_awake;
616 bool ref_cmd_in_flight;
617
618 dma_addr_t fw_mon_phys;
619 struct page *fw_mon_page;
620 u32 fw_mon_size;
621
622 struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES];
623 bool msix_enabled;
624 u8 shared_vec_mask;
625 u32 alloc_vecs;
626 u32 def_irq;
627 u32 fh_init_mask;
628 u32 hw_init_mask;
629 u32 fh_mask;
630 u32 hw_mask;
631 cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES];
632 u16 tx_cmd_queue_size;
633 bool in_rescan;
634 bool scheduled_for_removal;
635 };
636
637 static inline struct iwl_trans_pcie *
IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans * trans)638 IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans)
639 {
640 return (void *)trans->trans_specific;
641 }
642
iwl_pcie_clear_irq(struct iwl_trans * trans,struct msix_entry * entry)643 static inline void iwl_pcie_clear_irq(struct iwl_trans *trans,
644 struct msix_entry *entry)
645 {
646 /*
647 * Before sending the interrupt the HW disables it to prevent
648 * a nested interrupt. This is done by writing 1 to the corresponding
649 * bit in the mask register. After handling the interrupt, it should be
650 * re-enabled by clearing this bit. This register is defined as
651 * write 1 clear (W1C) register, meaning that it's being clear
652 * by writing 1 to the bit.
653 */
654 iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry));
655 }
656
657 static inline struct iwl_trans *
iwl_trans_pcie_get_trans(struct iwl_trans_pcie * trans_pcie)658 iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
659 {
660 return container_of((void *)trans_pcie, struct iwl_trans,
661 trans_specific);
662 }
663
664 /*
665 * Convention: trans API functions: iwl_trans_pcie_XXX
666 * Other functions: iwl_pcie_XXX
667 */
668 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
669 const struct pci_device_id *ent,
670 const struct iwl_cfg *cfg);
671 void iwl_trans_pcie_free(struct iwl_trans *trans);
672
673 /*****************************************************
674 * RX
675 ******************************************************/
676 int iwl_pcie_rx_init(struct iwl_trans *trans);
677 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans);
678 irqreturn_t iwl_pcie_msix_isr(int irq, void *data);
679 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id);
680 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id);
681 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id);
682 int iwl_pcie_rx_stop(struct iwl_trans *trans);
683 void iwl_pcie_rx_free(struct iwl_trans *trans);
684 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans);
685 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq);
686 int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget);
687 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
688 struct iwl_rxq *rxq);
689
690 /*****************************************************
691 * ICT - interrupt handling
692 ******************************************************/
693 irqreturn_t iwl_pcie_isr(int irq, void *data);
694 int iwl_pcie_alloc_ict(struct iwl_trans *trans);
695 void iwl_pcie_free_ict(struct iwl_trans *trans);
696 void iwl_pcie_reset_ict(struct iwl_trans *trans);
697 void iwl_pcie_disable_ict(struct iwl_trans *trans);
698
699 /*****************************************************
700 * TX / HCMD
701 ******************************************************/
702 int iwl_pcie_tx_init(struct iwl_trans *trans);
703 int iwl_pcie_gen2_tx_init(struct iwl_trans *trans);
704 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr);
705 int iwl_pcie_tx_stop(struct iwl_trans *trans);
706 void iwl_pcie_tx_free(struct iwl_trans *trans);
707 bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn,
708 const struct iwl_trans_txq_scd_cfg *cfg,
709 unsigned int wdg_timeout);
710 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue,
711 bool configure_scd);
712 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
713 bool shared_mode);
714 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans,
715 struct iwl_txq *txq);
716 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
717 struct iwl_device_cmd *dev_cmd, int txq_id);
718 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans);
719 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
720 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
721 struct iwl_rx_cmd_buffer *rxb);
722 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
723 struct sk_buff_head *skbs);
724 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans);
725
iwl_pcie_tfd_tb_get_len(struct iwl_trans * trans,void * _tfd,u8 idx)726 static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_trans *trans, void *_tfd,
727 u8 idx)
728 {
729 if (trans->cfg->use_tfh) {
730 struct iwl_tfh_tfd *tfd = _tfd;
731 struct iwl_tfh_tb *tb = &tfd->tbs[idx];
732
733 return le16_to_cpu(tb->tb_len);
734 } else {
735 struct iwl_tfd *tfd = _tfd;
736 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
737
738 return le16_to_cpu(tb->hi_n_len) >> 4;
739 }
740 }
741
742 /*****************************************************
743 * Error handling
744 ******************************************************/
745 void iwl_pcie_dump_csr(struct iwl_trans *trans);
746
747 /*****************************************************
748 * Helpers
749 ******************************************************/
_iwl_disable_interrupts(struct iwl_trans * trans)750 static inline void _iwl_disable_interrupts(struct iwl_trans *trans)
751 {
752 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
753
754 clear_bit(STATUS_INT_ENABLED, &trans->status);
755 if (!trans_pcie->msix_enabled) {
756 /* disable interrupts from uCode/NIC to host */
757 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
758
759 /* acknowledge/clear/reset any interrupts still pending
760 * from uCode or flow handler (Rx/Tx DMA) */
761 iwl_write32(trans, CSR_INT, 0xffffffff);
762 iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
763 } else {
764 /* disable all the interrupt we might use */
765 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
766 trans_pcie->fh_init_mask);
767 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
768 trans_pcie->hw_init_mask);
769 }
770 IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
771 }
772
773 #define IWL_NUM_OF_COMPLETION_RINGS 31
774 #define IWL_NUM_OF_TRANSFER_RINGS 527
775
iwl_pcie_get_num_sections(const struct fw_img * fw,int start)776 static inline int iwl_pcie_get_num_sections(const struct fw_img *fw,
777 int start)
778 {
779 int i = 0;
780
781 while (start < fw->num_sec &&
782 fw->sec[start].offset != CPU1_CPU2_SEPARATOR_SECTION &&
783 fw->sec[start].offset != PAGING_SEPARATOR_SECTION) {
784 start++;
785 i++;
786 }
787
788 return i;
789 }
790
iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans * trans,const struct fw_desc * sec,struct iwl_dram_data * dram)791 static inline int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans,
792 const struct fw_desc *sec,
793 struct iwl_dram_data *dram)
794 {
795 dram->block = dma_alloc_coherent(trans->dev, sec->len,
796 &dram->physical,
797 GFP_KERNEL);
798 if (!dram->block)
799 return -ENOMEM;
800
801 dram->size = sec->len;
802 memcpy(dram->block, sec->data, sec->len);
803
804 return 0;
805 }
806
iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans * trans)807 static inline void iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans *trans)
808 {
809 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
810 struct iwl_self_init_dram *dram = &trans_pcie->init_dram;
811 int i;
812
813 if (!dram->fw) {
814 WARN_ON(dram->fw_cnt);
815 return;
816 }
817
818 for (i = 0; i < dram->fw_cnt; i++)
819 dma_free_coherent(trans->dev, dram->fw[i].size,
820 dram->fw[i].block, dram->fw[i].physical);
821
822 kfree(dram->fw);
823 dram->fw_cnt = 0;
824 dram->fw = NULL;
825 }
826
iwl_disable_interrupts(struct iwl_trans * trans)827 static inline void iwl_disable_interrupts(struct iwl_trans *trans)
828 {
829 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
830
831 spin_lock(&trans_pcie->irq_lock);
832 _iwl_disable_interrupts(trans);
833 spin_unlock(&trans_pcie->irq_lock);
834 }
835
_iwl_enable_interrupts(struct iwl_trans * trans)836 static inline void _iwl_enable_interrupts(struct iwl_trans *trans)
837 {
838 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
839
840 IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
841 set_bit(STATUS_INT_ENABLED, &trans->status);
842 if (!trans_pcie->msix_enabled) {
843 trans_pcie->inta_mask = CSR_INI_SET_MASK;
844 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
845 } else {
846 /*
847 * fh/hw_mask keeps all the unmasked causes.
848 * Unlike msi, in msix cause is enabled when it is unset.
849 */
850 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
851 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
852 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
853 ~trans_pcie->fh_mask);
854 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
855 ~trans_pcie->hw_mask);
856 }
857 }
858
iwl_enable_interrupts(struct iwl_trans * trans)859 static inline void iwl_enable_interrupts(struct iwl_trans *trans)
860 {
861 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
862
863 spin_lock(&trans_pcie->irq_lock);
864 _iwl_enable_interrupts(trans);
865 spin_unlock(&trans_pcie->irq_lock);
866 }
iwl_enable_hw_int_msk_msix(struct iwl_trans * trans,u32 msk)867 static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk)
868 {
869 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
870
871 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk);
872 trans_pcie->hw_mask = msk;
873 }
874
iwl_enable_fh_int_msk_msix(struct iwl_trans * trans,u32 msk)875 static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk)
876 {
877 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
878
879 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk);
880 trans_pcie->fh_mask = msk;
881 }
882
iwl_enable_fw_load_int(struct iwl_trans * trans)883 static inline void iwl_enable_fw_load_int(struct iwl_trans *trans)
884 {
885 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
886
887 IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n");
888 if (!trans_pcie->msix_enabled) {
889 trans_pcie->inta_mask = CSR_INT_BIT_FH_TX;
890 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
891 } else {
892 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
893 trans_pcie->hw_init_mask);
894 iwl_enable_fh_int_msk_msix(trans,
895 MSIX_FH_INT_CAUSES_D2S_CH0_NUM);
896 }
897 }
898
iwl_pcie_get_cmd_index(const struct iwl_txq * q,u32 index)899 static inline u16 iwl_pcie_get_cmd_index(const struct iwl_txq *q, u32 index)
900 {
901 return index & (q->n_window - 1);
902 }
903
iwl_pcie_get_tfd(struct iwl_trans * trans,struct iwl_txq * txq,int idx)904 static inline void *iwl_pcie_get_tfd(struct iwl_trans *trans,
905 struct iwl_txq *txq, int idx)
906 {
907 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
908
909 if (trans->cfg->use_tfh)
910 idx = iwl_pcie_get_cmd_index(txq, idx);
911
912 return txq->tfds + trans_pcie->tfd_size * idx;
913 }
914
queue_name(struct device * dev,struct iwl_trans_pcie * trans_p,int i)915 static inline const char *queue_name(struct device *dev,
916 struct iwl_trans_pcie *trans_p, int i)
917 {
918 if (trans_p->shared_vec_mask) {
919 int vec = trans_p->shared_vec_mask &
920 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
921
922 if (i == 0)
923 return DRV_NAME ": shared IRQ";
924
925 return devm_kasprintf(dev, GFP_KERNEL,
926 DRV_NAME ": queue %d", i + vec);
927 }
928 if (i == 0)
929 return DRV_NAME ": default queue";
930
931 if (i == trans_p->alloc_vecs - 1)
932 return DRV_NAME ": exception";
933
934 return devm_kasprintf(dev, GFP_KERNEL,
935 DRV_NAME ": queue %d", i);
936 }
937
iwl_enable_rfkill_int(struct iwl_trans * trans)938 static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
939 {
940 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
941
942 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
943 if (!trans_pcie->msix_enabled) {
944 trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL;
945 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
946 } else {
947 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
948 trans_pcie->fh_init_mask);
949 iwl_enable_hw_int_msk_msix(trans,
950 MSIX_HW_INT_CAUSES_REG_RF_KILL);
951 }
952
953 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_9000) {
954 /*
955 * On 9000-series devices this bit isn't enabled by default, so
956 * when we power down the device we need set the bit to allow it
957 * to wake up the PCI-E bus for RF-kill interrupts.
958 */
959 iwl_set_bit(trans, CSR_GP_CNTRL,
960 CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN);
961 }
962 }
963
964 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans);
965
iwl_wake_queue(struct iwl_trans * trans,struct iwl_txq * txq)966 static inline void iwl_wake_queue(struct iwl_trans *trans,
967 struct iwl_txq *txq)
968 {
969 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
970
971 if (test_and_clear_bit(txq->id, trans_pcie->queue_stopped)) {
972 IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->id);
973 iwl_op_mode_queue_not_full(trans->op_mode, txq->id);
974 }
975 }
976
iwl_stop_queue(struct iwl_trans * trans,struct iwl_txq * txq)977 static inline void iwl_stop_queue(struct iwl_trans *trans,
978 struct iwl_txq *txq)
979 {
980 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
981
982 if (!test_and_set_bit(txq->id, trans_pcie->queue_stopped)) {
983 iwl_op_mode_queue_full(trans->op_mode, txq->id);
984 IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->id);
985 } else
986 IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n",
987 txq->id);
988 }
989
iwl_queue_used(const struct iwl_txq * q,int i)990 static inline bool iwl_queue_used(const struct iwl_txq *q, int i)
991 {
992 int index = iwl_pcie_get_cmd_index(q, i);
993 int r = iwl_pcie_get_cmd_index(q, q->read_ptr);
994 int w = iwl_pcie_get_cmd_index(q, q->write_ptr);
995
996 return w >= r ?
997 (index >= r && index < w) :
998 !(index < r && index >= w);
999 }
1000
iwl_is_rfkill_set(struct iwl_trans * trans)1001 static inline bool iwl_is_rfkill_set(struct iwl_trans *trans)
1002 {
1003 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1004
1005 lockdep_assert_held(&trans_pcie->mutex);
1006
1007 if (trans_pcie->debug_rfkill)
1008 return true;
1009
1010 return !(iwl_read32(trans, CSR_GP_CNTRL) &
1011 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1012 }
1013
__iwl_trans_pcie_set_bits_mask(struct iwl_trans * trans,u32 reg,u32 mask,u32 value)1014 static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans,
1015 u32 reg, u32 mask, u32 value)
1016 {
1017 u32 v;
1018
1019 #ifdef CONFIG_IWLWIFI_DEBUG
1020 WARN_ON_ONCE(value & ~mask);
1021 #endif
1022
1023 v = iwl_read32(trans, reg);
1024 v &= ~mask;
1025 v |= value;
1026 iwl_write32(trans, reg, v);
1027 }
1028
__iwl_trans_pcie_clear_bit(struct iwl_trans * trans,u32 reg,u32 mask)1029 static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans,
1030 u32 reg, u32 mask)
1031 {
1032 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0);
1033 }
1034
__iwl_trans_pcie_set_bit(struct iwl_trans * trans,u32 reg,u32 mask)1035 static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
1036 u32 reg, u32 mask)
1037 {
1038 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
1039 }
1040
1041 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state);
1042
1043 #ifdef CONFIG_IWLWIFI_DEBUGFS
1044 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans);
1045 #else
iwl_trans_pcie_dbgfs_register(struct iwl_trans * trans)1046 static inline int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
1047 {
1048 return 0;
1049 }
1050 #endif
1051
1052 int iwl_pci_fw_exit_d0i3(struct iwl_trans *trans);
1053 int iwl_pci_fw_enter_d0i3(struct iwl_trans *trans);
1054
1055 void iwl_pcie_enable_rx_wake(struct iwl_trans *trans, bool enable);
1056
1057 void iwl_pcie_rx_allocator_work(struct work_struct *data);
1058
1059 /* common functions that are used by gen2 transport */
1060 void iwl_pcie_apm_config(struct iwl_trans *trans);
1061 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans);
1062 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans);
1063 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans);
1064 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1065 bool was_in_rfkill);
1066 void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq);
1067 int iwl_queue_space(struct iwl_trans *trans, const struct iwl_txq *q);
1068 void iwl_pcie_apm_stop_master(struct iwl_trans *trans);
1069 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie);
1070 int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
1071 int slots_num, bool cmd_queue);
1072 int iwl_pcie_txq_alloc(struct iwl_trans *trans,
1073 struct iwl_txq *txq, int slots_num, bool cmd_queue);
1074 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
1075 struct iwl_dma_ptr *ptr, size_t size);
1076 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr);
1077 void iwl_pcie_apply_destination(struct iwl_trans *trans);
1078 void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie,
1079 struct sk_buff *skb);
1080 #ifdef CONFIG_INET
1081 struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len);
1082 #endif
1083
1084 /* common functions that are used by gen3 transport */
1085 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power);
1086
1087 /* transport gen 2 exported functions */
1088 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
1089 const struct fw_img *fw, bool run_in_rfkill);
1090 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr);
1091 int iwl_trans_pcie_dyn_txq_alloc(struct iwl_trans *trans,
1092 struct iwl_tx_queue_cfg_cmd *cmd,
1093 int cmd_id, int size,
1094 unsigned int timeout);
1095 void iwl_trans_pcie_dyn_txq_free(struct iwl_trans *trans, int queue);
1096 int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb,
1097 struct iwl_device_cmd *dev_cmd, int txq_id);
1098 int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans,
1099 struct iwl_host_cmd *cmd);
1100 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans,
1101 bool low_power);
1102 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, bool low_power);
1103 void iwl_pcie_gen2_txq_unmap(struct iwl_trans *trans, int txq_id);
1104 void iwl_pcie_gen2_tx_free(struct iwl_trans *trans);
1105 void iwl_pcie_gen2_tx_stop(struct iwl_trans *trans);
1106 #endif /* __iwl_trans_int_pcie_h__ */
1107