1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright (C) 2018 - 2020 Intel Corporation
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program.
21 *
22 * The full GNU General Public License is included in this distribution
23 * in the file called COPYING.
24 *
25 * Contact Information:
26 * Intel Linux Wireless <linuxwifi@intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *
29 * BSD LICENSE
30 *
31 * Copyright (C) 2018 - 2020 Intel Corporation
32 * All rights reserved.
33 *
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
36 * are met:
37 *
38 * * Redistributions of source code must retain the above copyright
39 * notice, this list of conditions and the following disclaimer.
40 * * Redistributions in binary form must reproduce the above copyright
41 * notice, this list of conditions and the following disclaimer in
42 * the documentation and/or other materials provided with the
43 * distribution.
44 * * Neither the name Intel Corporation nor the names of its
45 * contributors may be used to endorse or promote products derived
46 * from this software without specific prior written permission.
47 *
48 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
49 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
50 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
51 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
52 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
53 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
54 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
55 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
56 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
57 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
58 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
59 *
60 *****************************************************************************/
61
62 #include <linux/firmware.h>
63 #include "iwl-drv.h"
64 #include "iwl-trans.h"
65 #include "iwl-dbg-tlv.h"
66 #include "fw/dbg.h"
67 #include "fw/runtime.h"
68
69 /**
70 * enum iwl_dbg_tlv_type - debug TLV types
71 * @IWL_DBG_TLV_TYPE_DEBUG_INFO: debug info TLV
72 * @IWL_DBG_TLV_TYPE_BUF_ALLOC: buffer allocation TLV
73 * @IWL_DBG_TLV_TYPE_HCMD: host command TLV
74 * @IWL_DBG_TLV_TYPE_REGION: region TLV
75 * @IWL_DBG_TLV_TYPE_TRIGGER: trigger TLV
76 * @IWL_DBG_TLV_TYPE_NUM: number of debug TLVs
77 */
78 enum iwl_dbg_tlv_type {
79 IWL_DBG_TLV_TYPE_DEBUG_INFO =
80 IWL_UCODE_TLV_TYPE_DEBUG_INFO - IWL_UCODE_TLV_DEBUG_BASE,
81 IWL_DBG_TLV_TYPE_BUF_ALLOC,
82 IWL_DBG_TLV_TYPE_HCMD,
83 IWL_DBG_TLV_TYPE_REGION,
84 IWL_DBG_TLV_TYPE_TRIGGER,
85 IWL_DBG_TLV_TYPE_NUM,
86 };
87
88 /**
89 * struct iwl_dbg_tlv_ver_data - debug TLV version struct
90 * @min_ver: min version supported
91 * @max_ver: max version supported
92 */
93 struct iwl_dbg_tlv_ver_data {
94 int min_ver;
95 int max_ver;
96 };
97
98 /**
99 * struct iwl_dbg_tlv_timer_node - timer node struct
100 * @list: list of &struct iwl_dbg_tlv_timer_node
101 * @timer: timer
102 * @fwrt: &struct iwl_fw_runtime
103 * @tlv: TLV attach to the timer node
104 */
105 struct iwl_dbg_tlv_timer_node {
106 struct list_head list;
107 struct timer_list timer;
108 struct iwl_fw_runtime *fwrt;
109 struct iwl_ucode_tlv *tlv;
110 };
111
112 static const struct iwl_dbg_tlv_ver_data
113 dbg_ver_table[IWL_DBG_TLV_TYPE_NUM] = {
114 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = {.min_ver = 1, .max_ver = 1,},
115 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = {.min_ver = 1, .max_ver = 1,},
116 [IWL_DBG_TLV_TYPE_HCMD] = {.min_ver = 1, .max_ver = 1,},
117 [IWL_DBG_TLV_TYPE_REGION] = {.min_ver = 1, .max_ver = 1,},
118 [IWL_DBG_TLV_TYPE_TRIGGER] = {.min_ver = 1, .max_ver = 1,},
119 };
120
iwl_dbg_tlv_add(struct iwl_ucode_tlv * tlv,struct list_head * list)121 static int iwl_dbg_tlv_add(struct iwl_ucode_tlv *tlv, struct list_head *list)
122 {
123 u32 len = le32_to_cpu(tlv->length);
124 struct iwl_dbg_tlv_node *node;
125
126 node = kzalloc(sizeof(*node) + len, GFP_KERNEL);
127 if (!node)
128 return -ENOMEM;
129
130 memcpy(&node->tlv, tlv, sizeof(node->tlv) + len);
131 list_add_tail(&node->list, list);
132
133 return 0;
134 }
135
iwl_dbg_tlv_ver_support(struct iwl_ucode_tlv * tlv)136 static bool iwl_dbg_tlv_ver_support(struct iwl_ucode_tlv *tlv)
137 {
138 struct iwl_fw_ini_header *hdr = (void *)&tlv->data[0];
139 u32 type = le32_to_cpu(tlv->type);
140 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE;
141 u32 ver = le32_to_cpu(hdr->version);
142
143 if (ver < dbg_ver_table[tlv_idx].min_ver ||
144 ver > dbg_ver_table[tlv_idx].max_ver)
145 return false;
146
147 return true;
148 }
149
iwl_dbg_tlv_alloc_debug_info(struct iwl_trans * trans,struct iwl_ucode_tlv * tlv)150 static int iwl_dbg_tlv_alloc_debug_info(struct iwl_trans *trans,
151 struct iwl_ucode_tlv *tlv)
152 {
153 struct iwl_fw_ini_debug_info_tlv *debug_info = (void *)tlv->data;
154
155 if (le32_to_cpu(tlv->length) != sizeof(*debug_info))
156 return -EINVAL;
157
158 IWL_DEBUG_FW(trans, "WRT: Loading debug cfg: %s\n",
159 debug_info->debug_cfg_name);
160
161 return iwl_dbg_tlv_add(tlv, &trans->dbg.debug_info_tlv_list);
162 }
163
iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans * trans,struct iwl_ucode_tlv * tlv)164 static int iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans *trans,
165 struct iwl_ucode_tlv *tlv)
166 {
167 struct iwl_fw_ini_allocation_tlv *alloc = (void *)tlv->data;
168 u32 buf_location;
169 u32 alloc_id;
170
171 if (le32_to_cpu(tlv->length) != sizeof(*alloc))
172 return -EINVAL;
173
174 buf_location = le32_to_cpu(alloc->buf_location);
175 alloc_id = le32_to_cpu(alloc->alloc_id);
176
177 if (buf_location == IWL_FW_INI_LOCATION_INVALID ||
178 buf_location >= IWL_FW_INI_LOCATION_NUM)
179 goto err;
180
181 if (alloc_id == IWL_FW_INI_ALLOCATION_INVALID ||
182 alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
183 goto err;
184
185 if (buf_location == IWL_FW_INI_LOCATION_NPK_PATH &&
186 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1)
187 goto err;
188
189 if (buf_location == IWL_FW_INI_LOCATION_SRAM_PATH &&
190 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1 &&
191 alloc_id != IWL_FW_INI_ALLOCATION_ID_INTERNAL)
192 goto err;
193
194 trans->dbg.fw_mon_cfg[alloc_id] = *alloc;
195
196 return 0;
197 err:
198 IWL_ERR(trans,
199 "WRT: Invalid allocation id %u and/or location id %u for allocation TLV\n",
200 alloc_id, buf_location);
201 return -EINVAL;
202 }
203
iwl_dbg_tlv_alloc_hcmd(struct iwl_trans * trans,struct iwl_ucode_tlv * tlv)204 static int iwl_dbg_tlv_alloc_hcmd(struct iwl_trans *trans,
205 struct iwl_ucode_tlv *tlv)
206 {
207 struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)tlv->data;
208 u32 tp = le32_to_cpu(hcmd->time_point);
209
210 if (le32_to_cpu(tlv->length) <= sizeof(*hcmd))
211 return -EINVAL;
212
213 /* Host commands can not be sent in early time point since the FW
214 * is not ready
215 */
216 if (tp == IWL_FW_INI_TIME_POINT_INVALID ||
217 tp >= IWL_FW_INI_TIME_POINT_NUM ||
218 tp == IWL_FW_INI_TIME_POINT_EARLY) {
219 IWL_ERR(trans,
220 "WRT: Invalid time point %u for host command TLV\n",
221 tp);
222 return -EINVAL;
223 }
224
225 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].hcmd_list);
226 }
227
iwl_dbg_tlv_alloc_region(struct iwl_trans * trans,struct iwl_ucode_tlv * tlv)228 static int iwl_dbg_tlv_alloc_region(struct iwl_trans *trans,
229 struct iwl_ucode_tlv *tlv)
230 {
231 struct iwl_fw_ini_region_tlv *reg = (void *)tlv->data;
232 struct iwl_ucode_tlv **active_reg;
233 u32 id = le32_to_cpu(reg->id);
234 u32 type = le32_to_cpu(reg->type);
235 u32 tlv_len = sizeof(*tlv) + le32_to_cpu(tlv->length);
236
237 if (le32_to_cpu(tlv->length) < sizeof(*reg))
238 return -EINVAL;
239
240 /* For safe using a string from FW make sure we have a
241 * null terminator
242 */
243 reg->name[IWL_FW_INI_MAX_NAME - 1] = 0;
244
245 IWL_DEBUG_FW(trans, "WRT: parsing region: %s\n", reg->name);
246
247 if (id >= IWL_FW_INI_MAX_REGION_ID) {
248 IWL_ERR(trans, "WRT: Invalid region id %u\n", id);
249 return -EINVAL;
250 }
251
252 if (type <= IWL_FW_INI_REGION_INVALID ||
253 type >= IWL_FW_INI_REGION_NUM) {
254 IWL_ERR(trans, "WRT: Invalid region type %u\n", type);
255 return -EINVAL;
256 }
257
258 if (type == IWL_FW_INI_REGION_PCI_IOSF_CONFIG &&
259 !trans->ops->read_config32) {
260 IWL_ERR(trans, "WRT: Unsupported region type %u\n", type);
261 return -EOPNOTSUPP;
262 }
263
264 active_reg = &trans->dbg.active_regions[id];
265 if (*active_reg) {
266 IWL_WARN(trans, "WRT: Overriding region id %u\n", id);
267
268 kfree(*active_reg);
269 }
270
271 *active_reg = kmemdup(tlv, tlv_len, GFP_KERNEL);
272 if (!*active_reg)
273 return -ENOMEM;
274
275 IWL_DEBUG_FW(trans, "WRT: Enabling region id %u type %u\n", id, type);
276
277 return 0;
278 }
279
iwl_dbg_tlv_alloc_trigger(struct iwl_trans * trans,struct iwl_ucode_tlv * tlv)280 static int iwl_dbg_tlv_alloc_trigger(struct iwl_trans *trans,
281 struct iwl_ucode_tlv *tlv)
282 {
283 struct iwl_fw_ini_trigger_tlv *trig = (void *)tlv->data;
284 u32 tp = le32_to_cpu(trig->time_point);
285 struct iwl_ucode_tlv *dup = NULL;
286 int ret;
287
288 if (le32_to_cpu(tlv->length) < sizeof(*trig))
289 return -EINVAL;
290
291 if (tp <= IWL_FW_INI_TIME_POINT_INVALID ||
292 tp >= IWL_FW_INI_TIME_POINT_NUM) {
293 IWL_ERR(trans,
294 "WRT: Invalid time point %u for trigger TLV\n",
295 tp);
296 return -EINVAL;
297 }
298
299 if (!le32_to_cpu(trig->occurrences)) {
300 dup = kmemdup(tlv, sizeof(*tlv) + le32_to_cpu(tlv->length),
301 GFP_KERNEL);
302 if (!dup)
303 return -ENOMEM;
304 trig = (void *)dup->data;
305 trig->occurrences = cpu_to_le32(-1);
306 tlv = dup;
307 }
308
309 ret = iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].trig_list);
310 kfree(dup);
311
312 return ret;
313 }
314
315 static int (*dbg_tlv_alloc[])(struct iwl_trans *trans,
316 struct iwl_ucode_tlv *tlv) = {
317 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = iwl_dbg_tlv_alloc_debug_info,
318 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = iwl_dbg_tlv_alloc_buf_alloc,
319 [IWL_DBG_TLV_TYPE_HCMD] = iwl_dbg_tlv_alloc_hcmd,
320 [IWL_DBG_TLV_TYPE_REGION] = iwl_dbg_tlv_alloc_region,
321 [IWL_DBG_TLV_TYPE_TRIGGER] = iwl_dbg_tlv_alloc_trigger,
322 };
323
iwl_dbg_tlv_alloc(struct iwl_trans * trans,struct iwl_ucode_tlv * tlv,bool ext)324 void iwl_dbg_tlv_alloc(struct iwl_trans *trans, struct iwl_ucode_tlv *tlv,
325 bool ext)
326 {
327 struct iwl_fw_ini_header *hdr = (void *)&tlv->data[0];
328 u32 type = le32_to_cpu(tlv->type);
329 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE;
330 u32 domain = le32_to_cpu(hdr->domain);
331 enum iwl_ini_cfg_state *cfg_state = ext ?
332 &trans->dbg.external_ini_cfg : &trans->dbg.internal_ini_cfg;
333 int ret;
334
335 if (domain != IWL_FW_INI_DOMAIN_ALWAYS_ON &&
336 !(domain & trans->dbg.domains_bitmap)) {
337 IWL_DEBUG_FW(trans,
338 "WRT: Skipping TLV with disabled domain 0x%0x (0x%0x)\n",
339 domain, trans->dbg.domains_bitmap);
340 return;
341 }
342
343 if (tlv_idx >= ARRAY_SIZE(dbg_tlv_alloc) || !dbg_tlv_alloc[tlv_idx]) {
344 IWL_ERR(trans, "WRT: Unsupported TLV type 0x%x\n", type);
345 goto out_err;
346 }
347
348 if (!iwl_dbg_tlv_ver_support(tlv)) {
349 IWL_ERR(trans, "WRT: Unsupported TLV 0x%x version %u\n", type,
350 le32_to_cpu(hdr->version));
351 goto out_err;
352 }
353
354 ret = dbg_tlv_alloc[tlv_idx](trans, tlv);
355 if (ret) {
356 IWL_ERR(trans,
357 "WRT: Failed to allocate TLV 0x%x, ret %d, (ext=%d)\n",
358 type, ret, ext);
359 goto out_err;
360 }
361
362 if (*cfg_state == IWL_INI_CFG_STATE_NOT_LOADED)
363 *cfg_state = IWL_INI_CFG_STATE_LOADED;
364
365 return;
366
367 out_err:
368 *cfg_state = IWL_INI_CFG_STATE_CORRUPTED;
369 }
370
iwl_dbg_tlv_del_timers(struct iwl_trans * trans)371 void iwl_dbg_tlv_del_timers(struct iwl_trans *trans)
372 {
373 struct list_head *timer_list = &trans->dbg.periodic_trig_list;
374 struct iwl_dbg_tlv_timer_node *node, *tmp;
375
376 list_for_each_entry_safe(node, tmp, timer_list, list) {
377 del_timer(&node->timer);
378 list_del(&node->list);
379 kfree(node);
380 }
381 }
382 IWL_EXPORT_SYMBOL(iwl_dbg_tlv_del_timers);
383
iwl_dbg_tlv_fragments_free(struct iwl_trans * trans,enum iwl_fw_ini_allocation_id alloc_id)384 static void iwl_dbg_tlv_fragments_free(struct iwl_trans *trans,
385 enum iwl_fw_ini_allocation_id alloc_id)
386 {
387 struct iwl_fw_mon *fw_mon;
388 int i;
389
390 if (alloc_id <= IWL_FW_INI_ALLOCATION_INVALID ||
391 alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
392 return;
393
394 fw_mon = &trans->dbg.fw_mon_ini[alloc_id];
395
396 for (i = 0; i < fw_mon->num_frags; i++) {
397 struct iwl_dram_data *frag = &fw_mon->frags[i];
398
399 dma_free_coherent(trans->dev, frag->size, frag->block,
400 frag->physical);
401
402 frag->physical = 0;
403 frag->block = NULL;
404 frag->size = 0;
405 }
406
407 kfree(fw_mon->frags);
408 fw_mon->frags = NULL;
409 fw_mon->num_frags = 0;
410 }
411
iwl_dbg_tlv_free(struct iwl_trans * trans)412 void iwl_dbg_tlv_free(struct iwl_trans *trans)
413 {
414 struct iwl_dbg_tlv_node *tlv_node, *tlv_node_tmp;
415 int i;
416
417 iwl_dbg_tlv_del_timers(trans);
418
419 for (i = 0; i < ARRAY_SIZE(trans->dbg.active_regions); i++) {
420 struct iwl_ucode_tlv **active_reg =
421 &trans->dbg.active_regions[i];
422
423 kfree(*active_reg);
424 *active_reg = NULL;
425 }
426
427 list_for_each_entry_safe(tlv_node, tlv_node_tmp,
428 &trans->dbg.debug_info_tlv_list, list) {
429 list_del(&tlv_node->list);
430 kfree(tlv_node);
431 }
432
433 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) {
434 struct iwl_dbg_tlv_time_point_data *tp =
435 &trans->dbg.time_point[i];
436
437 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->trig_list,
438 list) {
439 list_del(&tlv_node->list);
440 kfree(tlv_node);
441 }
442
443 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->hcmd_list,
444 list) {
445 list_del(&tlv_node->list);
446 kfree(tlv_node);
447 }
448
449 list_for_each_entry_safe(tlv_node, tlv_node_tmp,
450 &tp->active_trig_list, list) {
451 list_del(&tlv_node->list);
452 kfree(tlv_node);
453 }
454 }
455
456 for (i = 0; i < ARRAY_SIZE(trans->dbg.fw_mon_ini); i++)
457 iwl_dbg_tlv_fragments_free(trans, i);
458 }
459
iwl_dbg_tlv_parse_bin(struct iwl_trans * trans,const u8 * data,size_t len)460 static int iwl_dbg_tlv_parse_bin(struct iwl_trans *trans, const u8 *data,
461 size_t len)
462 {
463 struct iwl_ucode_tlv *tlv;
464 u32 tlv_len;
465
466 while (len >= sizeof(*tlv)) {
467 len -= sizeof(*tlv);
468 tlv = (void *)data;
469
470 tlv_len = le32_to_cpu(tlv->length);
471
472 if (len < tlv_len) {
473 IWL_ERR(trans, "invalid TLV len: %zd/%u\n",
474 len, tlv_len);
475 return -EINVAL;
476 }
477 len -= ALIGN(tlv_len, 4);
478 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
479
480 iwl_dbg_tlv_alloc(trans, tlv, true);
481 }
482
483 return 0;
484 }
485
iwl_dbg_tlv_load_bin(struct device * dev,struct iwl_trans * trans)486 void iwl_dbg_tlv_load_bin(struct device *dev, struct iwl_trans *trans)
487 {
488 const struct firmware *fw;
489 int res;
490
491 if (!iwlwifi_mod_params.enable_ini)
492 return;
493
494 res = firmware_request_nowarn(&fw, "iwl-debug-yoyo.bin", dev);
495 if (res)
496 return;
497
498 iwl_dbg_tlv_parse_bin(trans, fw->data, fw->size);
499
500 release_firmware(fw);
501 }
502
iwl_dbg_tlv_init(struct iwl_trans * trans)503 void iwl_dbg_tlv_init(struct iwl_trans *trans)
504 {
505 int i;
506
507 INIT_LIST_HEAD(&trans->dbg.debug_info_tlv_list);
508 INIT_LIST_HEAD(&trans->dbg.periodic_trig_list);
509
510 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) {
511 struct iwl_dbg_tlv_time_point_data *tp =
512 &trans->dbg.time_point[i];
513
514 INIT_LIST_HEAD(&tp->trig_list);
515 INIT_LIST_HEAD(&tp->hcmd_list);
516 INIT_LIST_HEAD(&tp->active_trig_list);
517 }
518 }
519
iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime * fwrt,struct iwl_dram_data * frag,u32 pages)520 static int iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime *fwrt,
521 struct iwl_dram_data *frag, u32 pages)
522 {
523 void *block = NULL;
524 dma_addr_t physical;
525
526 if (!frag || frag->size || !pages)
527 return -EIO;
528
529 /*
530 * We try to allocate as many pages as we can, starting with
531 * the requested amount and going down until we can allocate
532 * something. Because of DIV_ROUND_UP(), pages will never go
533 * down to 0 and stop the loop, so stop when pages reaches 1,
534 * which is too small anyway.
535 */
536 while (pages > 1) {
537 block = dma_alloc_coherent(fwrt->dev, pages * PAGE_SIZE,
538 &physical,
539 GFP_KERNEL | __GFP_NOWARN);
540 if (block)
541 break;
542
543 IWL_WARN(fwrt, "WRT: Failed to allocate fragment size %lu\n",
544 pages * PAGE_SIZE);
545
546 pages = DIV_ROUND_UP(pages, 2);
547 }
548
549 if (!block)
550 return -ENOMEM;
551
552 frag->physical = physical;
553 frag->block = block;
554 frag->size = pages * PAGE_SIZE;
555
556 return pages;
557 }
558
iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime * fwrt,enum iwl_fw_ini_allocation_id alloc_id)559 static int iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime *fwrt,
560 enum iwl_fw_ini_allocation_id alloc_id)
561 {
562 struct iwl_fw_mon *fw_mon;
563 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg;
564 u32 num_frags, remain_pages, frag_pages;
565 int i;
566
567 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID ||
568 alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
569 return -EIO;
570
571 fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id];
572 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
573
574 if (fw_mon->num_frags ||
575 fw_mon_cfg->buf_location !=
576 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH))
577 return 0;
578
579 num_frags = le32_to_cpu(fw_mon_cfg->max_frags_num);
580 if (!fw_has_capa(&fwrt->fw->ucode_capa,
581 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP)) {
582 if (alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1)
583 return -EIO;
584 num_frags = 1;
585 }
586
587 remain_pages = DIV_ROUND_UP(le32_to_cpu(fw_mon_cfg->req_size),
588 PAGE_SIZE);
589 num_frags = min_t(u32, num_frags, BUF_ALLOC_MAX_NUM_FRAGS);
590 num_frags = min_t(u32, num_frags, remain_pages);
591 frag_pages = DIV_ROUND_UP(remain_pages, num_frags);
592
593 fw_mon->frags = kcalloc(num_frags, sizeof(*fw_mon->frags), GFP_KERNEL);
594 if (!fw_mon->frags)
595 return -ENOMEM;
596
597 for (i = 0; i < num_frags; i++) {
598 int pages = min_t(u32, frag_pages, remain_pages);
599
600 IWL_DEBUG_FW(fwrt,
601 "WRT: Allocating DRAM buffer (alloc_id=%u, fragment=%u, size=0x%lx)\n",
602 alloc_id, i, pages * PAGE_SIZE);
603
604 pages = iwl_dbg_tlv_alloc_fragment(fwrt, &fw_mon->frags[i],
605 pages);
606 if (pages < 0) {
607 u32 alloc_size = le32_to_cpu(fw_mon_cfg->req_size) -
608 (remain_pages * PAGE_SIZE);
609
610 if (alloc_size < le32_to_cpu(fw_mon_cfg->min_size)) {
611 iwl_dbg_tlv_fragments_free(fwrt->trans,
612 alloc_id);
613 return pages;
614 }
615 break;
616 }
617
618 remain_pages -= pages;
619 fw_mon->num_frags++;
620 }
621
622 return 0;
623 }
624
iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime * fwrt,enum iwl_fw_ini_allocation_id alloc_id)625 static int iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime *fwrt,
626 enum iwl_fw_ini_allocation_id alloc_id)
627 {
628 struct iwl_fw_mon *fw_mon;
629 u32 remain_frags, num_commands;
630 int i, fw_mon_idx = 0;
631
632 if (!fw_has_capa(&fwrt->fw->ucode_capa,
633 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP))
634 return 0;
635
636 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID ||
637 alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
638 return -EIO;
639
640 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) !=
641 IWL_FW_INI_LOCATION_DRAM_PATH)
642 return 0;
643
644 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
645
646 /* the first fragment of DBGC1 is given to the FW via register
647 * or context info
648 */
649 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1)
650 fw_mon_idx++;
651
652 remain_frags = fw_mon->num_frags - fw_mon_idx;
653 if (!remain_frags)
654 return 0;
655
656 num_commands = DIV_ROUND_UP(remain_frags, BUF_ALLOC_MAX_NUM_FRAGS);
657
658 IWL_DEBUG_FW(fwrt, "WRT: Applying DRAM destination (alloc_id=%u)\n",
659 alloc_id);
660
661 for (i = 0; i < num_commands; i++) {
662 u32 num_frags = min_t(u32, remain_frags,
663 BUF_ALLOC_MAX_NUM_FRAGS);
664 struct iwl_buf_alloc_cmd data = {
665 .alloc_id = cpu_to_le32(alloc_id),
666 .num_frags = cpu_to_le32(num_frags),
667 .buf_location =
668 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH),
669 };
670 struct iwl_host_cmd hcmd = {
671 .id = WIDE_ID(DEBUG_GROUP, BUFFER_ALLOCATION),
672 .data[0] = &data,
673 .len[0] = sizeof(data),
674 };
675 int ret, j;
676
677 for (j = 0; j < num_frags; j++) {
678 struct iwl_buf_alloc_frag *frag = &data.frags[j];
679 struct iwl_dram_data *fw_mon_frag =
680 &fw_mon->frags[fw_mon_idx++];
681
682 frag->addr = cpu_to_le64(fw_mon_frag->physical);
683 frag->size = cpu_to_le32(fw_mon_frag->size);
684 }
685 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd);
686 if (ret)
687 return ret;
688
689 remain_frags -= num_frags;
690 }
691
692 return 0;
693 }
694
iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime * fwrt)695 static void iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime *fwrt)
696 {
697 int ret, i;
698
699 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) {
700 ret = iwl_dbg_tlv_apply_buffer(fwrt, i);
701 if (ret)
702 IWL_WARN(fwrt,
703 "WRT: Failed to apply DRAM buffer for allocation id %d, ret=%d\n",
704 i, ret);
705 }
706 }
707
iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime * fwrt,struct list_head * hcmd_list)708 static void iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime *fwrt,
709 struct list_head *hcmd_list)
710 {
711 struct iwl_dbg_tlv_node *node;
712
713 list_for_each_entry(node, hcmd_list, list) {
714 struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)node->tlv.data;
715 struct iwl_fw_ini_hcmd *hcmd_data = &hcmd->hcmd;
716 u16 hcmd_len = le32_to_cpu(node->tlv.length) - sizeof(*hcmd);
717 struct iwl_host_cmd cmd = {
718 .id = WIDE_ID(hcmd_data->group, hcmd_data->id),
719 .len = { hcmd_len, },
720 .data = { hcmd_data->data, },
721 };
722
723 iwl_trans_send_cmd(fwrt->trans, &cmd);
724 }
725 }
726
iwl_dbg_tlv_periodic_trig_handler(struct timer_list * t)727 static void iwl_dbg_tlv_periodic_trig_handler(struct timer_list *t)
728 {
729 struct iwl_dbg_tlv_timer_node *timer_node =
730 from_timer(timer_node, t, timer);
731 struct iwl_fwrt_dump_data dump_data = {
732 .trig = (void *)timer_node->tlv->data,
733 };
734 int ret;
735
736 ret = iwl_fw_dbg_ini_collect(timer_node->fwrt, &dump_data);
737 if (!ret || ret == -EBUSY) {
738 u32 occur = le32_to_cpu(dump_data.trig->occurrences);
739 u32 collect_interval = le32_to_cpu(dump_data.trig->data[0]);
740
741 if (!occur)
742 return;
743
744 mod_timer(t, jiffies + msecs_to_jiffies(collect_interval));
745 }
746 }
747
iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime * fwrt)748 static void iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime *fwrt)
749 {
750 struct iwl_dbg_tlv_node *node;
751 struct list_head *trig_list =
752 &fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list;
753
754 list_for_each_entry(node, trig_list, list) {
755 struct iwl_fw_ini_trigger_tlv *trig = (void *)node->tlv.data;
756 struct iwl_dbg_tlv_timer_node *timer_node;
757 u32 occur = le32_to_cpu(trig->occurrences), collect_interval;
758 u32 min_interval = 100;
759
760 if (!occur)
761 continue;
762
763 /* make sure there is at least one dword of data for the
764 * interval value
765 */
766 if (le32_to_cpu(node->tlv.length) <
767 sizeof(*trig) + sizeof(__le32)) {
768 IWL_ERR(fwrt,
769 "WRT: Invalid periodic trigger data was not given\n");
770 continue;
771 }
772
773 if (le32_to_cpu(trig->data[0]) < min_interval) {
774 IWL_WARN(fwrt,
775 "WRT: Override min interval from %u to %u msec\n",
776 le32_to_cpu(trig->data[0]), min_interval);
777 trig->data[0] = cpu_to_le32(min_interval);
778 }
779
780 collect_interval = le32_to_cpu(trig->data[0]);
781
782 timer_node = kzalloc(sizeof(*timer_node), GFP_KERNEL);
783 if (!timer_node) {
784 IWL_ERR(fwrt,
785 "WRT: Failed to allocate periodic trigger\n");
786 continue;
787 }
788
789 timer_node->fwrt = fwrt;
790 timer_node->tlv = &node->tlv;
791 timer_setup(&timer_node->timer,
792 iwl_dbg_tlv_periodic_trig_handler, 0);
793
794 list_add_tail(&timer_node->list,
795 &fwrt->trans->dbg.periodic_trig_list);
796
797 IWL_DEBUG_FW(fwrt, "WRT: Enabling periodic trigger\n");
798
799 mod_timer(&timer_node->timer,
800 jiffies + msecs_to_jiffies(collect_interval));
801 }
802 }
803
is_trig_data_contained(struct iwl_ucode_tlv * new,struct iwl_ucode_tlv * old)804 static bool is_trig_data_contained(struct iwl_ucode_tlv *new,
805 struct iwl_ucode_tlv *old)
806 {
807 struct iwl_fw_ini_trigger_tlv *new_trig = (void *)new->data;
808 struct iwl_fw_ini_trigger_tlv *old_trig = (void *)old->data;
809 __le32 *new_data = new_trig->data, *old_data = old_trig->data;
810 u32 new_dwords_num = iwl_tlv_array_len(new, new_trig, data);
811 u32 old_dwords_num = iwl_tlv_array_len(new, new_trig, data);
812 int i, j;
813
814 for (i = 0; i < new_dwords_num; i++) {
815 bool match = false;
816
817 for (j = 0; j < old_dwords_num; j++) {
818 if (new_data[i] == old_data[j]) {
819 match = true;
820 break;
821 }
822 }
823 if (!match)
824 return false;
825 }
826
827 return true;
828 }
829
iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime * fwrt,struct iwl_ucode_tlv * trig_tlv,struct iwl_dbg_tlv_node * node)830 static int iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime *fwrt,
831 struct iwl_ucode_tlv *trig_tlv,
832 struct iwl_dbg_tlv_node *node)
833 {
834 struct iwl_ucode_tlv *node_tlv = &node->tlv;
835 struct iwl_fw_ini_trigger_tlv *node_trig = (void *)node_tlv->data;
836 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data;
837 u32 policy = le32_to_cpu(trig->apply_policy);
838 u32 size = le32_to_cpu(trig_tlv->length);
839 u32 trig_data_len = size - sizeof(*trig);
840 u32 offset = 0;
841
842 if (!(policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_DATA)) {
843 u32 data_len = le32_to_cpu(node_tlv->length) -
844 sizeof(*node_trig);
845
846 IWL_DEBUG_FW(fwrt,
847 "WRT: Appending trigger data (time point %u)\n",
848 le32_to_cpu(trig->time_point));
849
850 offset += data_len;
851 size += data_len;
852 } else {
853 IWL_DEBUG_FW(fwrt,
854 "WRT: Overriding trigger data (time point %u)\n",
855 le32_to_cpu(trig->time_point));
856 }
857
858 if (size != le32_to_cpu(node_tlv->length)) {
859 struct list_head *prev = node->list.prev;
860 struct iwl_dbg_tlv_node *tmp;
861
862 list_del(&node->list);
863
864 tmp = krealloc(node, sizeof(*node) + size, GFP_KERNEL);
865 if (!tmp) {
866 IWL_WARN(fwrt,
867 "WRT: No memory to override trigger (time point %u)\n",
868 le32_to_cpu(trig->time_point));
869
870 list_add(&node->list, prev);
871
872 return -ENOMEM;
873 }
874
875 list_add(&tmp->list, prev);
876 node_tlv = &tmp->tlv;
877 node_trig = (void *)node_tlv->data;
878 }
879
880 memcpy(node_trig->data + offset, trig->data, trig_data_len);
881 node_tlv->length = cpu_to_le32(size);
882
883 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_CFG) {
884 IWL_DEBUG_FW(fwrt,
885 "WRT: Overriding trigger configuration (time point %u)\n",
886 le32_to_cpu(trig->time_point));
887
888 /* the first 11 dwords are configuration related */
889 memcpy(node_trig, trig, sizeof(__le32) * 11);
890 }
891
892 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_REGIONS) {
893 IWL_DEBUG_FW(fwrt,
894 "WRT: Overriding trigger regions (time point %u)\n",
895 le32_to_cpu(trig->time_point));
896
897 node_trig->regions_mask = trig->regions_mask;
898 } else {
899 IWL_DEBUG_FW(fwrt,
900 "WRT: Appending trigger regions (time point %u)\n",
901 le32_to_cpu(trig->time_point));
902
903 node_trig->regions_mask |= trig->regions_mask;
904 }
905
906 return 0;
907 }
908
909 static int
iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime * fwrt,struct list_head * trig_list,struct iwl_ucode_tlv * trig_tlv)910 iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime *fwrt,
911 struct list_head *trig_list,
912 struct iwl_ucode_tlv *trig_tlv)
913 {
914 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data;
915 struct iwl_dbg_tlv_node *node, *match = NULL;
916 u32 policy = le32_to_cpu(trig->apply_policy);
917
918 list_for_each_entry(node, trig_list, list) {
919 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_TIME_POINT))
920 break;
921
922 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_DATA) ||
923 is_trig_data_contained(trig_tlv, &node->tlv)) {
924 match = node;
925 break;
926 }
927 }
928
929 if (!match) {
930 IWL_DEBUG_FW(fwrt, "WRT: Enabling trigger (time point %u)\n",
931 le32_to_cpu(trig->time_point));
932 return iwl_dbg_tlv_add(trig_tlv, trig_list);
933 }
934
935 return iwl_dbg_tlv_override_trig_node(fwrt, trig_tlv, match);
936 }
937
938 static void
iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime * fwrt,struct iwl_dbg_tlv_time_point_data * tp)939 iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime *fwrt,
940 struct iwl_dbg_tlv_time_point_data *tp)
941 {
942 struct iwl_dbg_tlv_node *node;
943 struct list_head *trig_list = &tp->trig_list;
944 struct list_head *active_trig_list = &tp->active_trig_list;
945
946 list_for_each_entry(node, trig_list, list) {
947 struct iwl_ucode_tlv *tlv = &node->tlv;
948
949 iwl_dbg_tlv_add_active_trigger(fwrt, active_trig_list, tlv);
950 }
951 }
952
iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data,union iwl_dbg_tlv_tp_data * tp_data,u32 trig_data)953 static bool iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime *fwrt,
954 struct iwl_fwrt_dump_data *dump_data,
955 union iwl_dbg_tlv_tp_data *tp_data,
956 u32 trig_data)
957 {
958 struct iwl_rx_packet *pkt = tp_data->fw_pkt;
959 struct iwl_cmd_header *wanted_hdr = (void *)&trig_data;
960
961 if (pkt && (pkt->hdr.cmd == wanted_hdr->cmd &&
962 pkt->hdr.group_id == wanted_hdr->group_id)) {
963 struct iwl_rx_packet *fw_pkt =
964 kmemdup(pkt,
965 sizeof(*pkt) + iwl_rx_packet_payload_len(pkt),
966 GFP_ATOMIC);
967
968 if (!fw_pkt)
969 return false;
970
971 dump_data->fw_pkt = fw_pkt;
972
973 return true;
974 }
975
976 return false;
977 }
978
979 static int
iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime * fwrt,struct list_head * active_trig_list,union iwl_dbg_tlv_tp_data * tp_data,bool (* data_check)(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data,union iwl_dbg_tlv_tp_data * tp_data,u32 trig_data))980 iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime *fwrt,
981 struct list_head *active_trig_list,
982 union iwl_dbg_tlv_tp_data *tp_data,
983 bool (*data_check)(struct iwl_fw_runtime *fwrt,
984 struct iwl_fwrt_dump_data *dump_data,
985 union iwl_dbg_tlv_tp_data *tp_data,
986 u32 trig_data))
987 {
988 struct iwl_dbg_tlv_node *node;
989
990 list_for_each_entry(node, active_trig_list, list) {
991 struct iwl_fwrt_dump_data dump_data = {
992 .trig = (void *)node->tlv.data,
993 };
994 u32 num_data = iwl_tlv_array_len(&node->tlv, dump_data.trig,
995 data);
996 int ret, i;
997
998 if (!num_data) {
999 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data);
1000 if (ret)
1001 return ret;
1002 }
1003
1004 for (i = 0; i < num_data; i++) {
1005 if (!data_check ||
1006 data_check(fwrt, &dump_data, tp_data,
1007 le32_to_cpu(dump_data.trig->data[i]))) {
1008 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data);
1009 if (ret)
1010 return ret;
1011
1012 break;
1013 }
1014 }
1015 }
1016
1017 return 0;
1018 }
1019
iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime * fwrt)1020 static void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt)
1021 {
1022 enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest;
1023 int ret, i;
1024
1025 if (*ini_dest != IWL_FW_INI_LOCATION_INVALID)
1026 return;
1027
1028 IWL_DEBUG_FW(fwrt,
1029 "WRT: Generating active triggers list, domain 0x%x\n",
1030 fwrt->trans->dbg.domains_bitmap);
1031
1032 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) {
1033 struct iwl_dbg_tlv_time_point_data *tp =
1034 &fwrt->trans->dbg.time_point[i];
1035
1036 iwl_dbg_tlv_gen_active_trig_list(fwrt, tp);
1037 }
1038
1039 *ini_dest = IWL_FW_INI_LOCATION_INVALID;
1040 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) {
1041 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg =
1042 &fwrt->trans->dbg.fw_mon_cfg[i];
1043 u32 dest = le32_to_cpu(fw_mon_cfg->buf_location);
1044
1045 if (dest == IWL_FW_INI_LOCATION_INVALID)
1046 continue;
1047
1048 if (*ini_dest == IWL_FW_INI_LOCATION_INVALID)
1049 *ini_dest = dest;
1050
1051 if (dest != *ini_dest)
1052 continue;
1053
1054 ret = iwl_dbg_tlv_alloc_fragments(fwrt, i);
1055 if (ret)
1056 IWL_WARN(fwrt,
1057 "WRT: Failed to allocate DRAM buffer for allocation id %d, ret=%d\n",
1058 i, ret);
1059 }
1060 }
1061
iwl_dbg_tlv_time_point(struct iwl_fw_runtime * fwrt,enum iwl_fw_ini_time_point tp_id,union iwl_dbg_tlv_tp_data * tp_data)1062 void iwl_dbg_tlv_time_point(struct iwl_fw_runtime *fwrt,
1063 enum iwl_fw_ini_time_point tp_id,
1064 union iwl_dbg_tlv_tp_data *tp_data)
1065 {
1066 struct list_head *hcmd_list, *trig_list;
1067
1068 if (!iwl_trans_dbg_ini_valid(fwrt->trans) ||
1069 tp_id == IWL_FW_INI_TIME_POINT_INVALID ||
1070 tp_id >= IWL_FW_INI_TIME_POINT_NUM)
1071 return;
1072
1073 hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list;
1074 trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list;
1075
1076 switch (tp_id) {
1077 case IWL_FW_INI_TIME_POINT_EARLY:
1078 iwl_dbg_tlv_init_cfg(fwrt);
1079 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL);
1080 break;
1081 case IWL_FW_INI_TIME_POINT_AFTER_ALIVE:
1082 iwl_dbg_tlv_apply_buffers(fwrt);
1083 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1084 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL);
1085 break;
1086 case IWL_FW_INI_TIME_POINT_PERIODIC:
1087 iwl_dbg_tlv_set_periodic_trigs(fwrt);
1088 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1089 break;
1090 case IWL_FW_INI_TIME_POINT_FW_RSP_OR_NOTIF:
1091 case IWL_FW_INI_TIME_POINT_MISSED_BEACONS:
1092 case IWL_FW_INI_TIME_POINT_FW_DHC_NOTIFICATION:
1093 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1094 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data,
1095 iwl_dbg_tlv_check_fw_pkt);
1096 break;
1097 default:
1098 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1099 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL);
1100 break;
1101 }
1102 }
1103 IWL_EXPORT_SYMBOL(iwl_dbg_tlv_time_point);
1104
