1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2015-2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2021 Intel Corporation 5 */ 6 #include <linux/module.h> 7 #include <linux/stringify.h> 8 #include "iwl-config.h" 9 #include "iwl-prph.h" 10 11 /* Highest firmware API version supported */ 12 #define IWL_22000_UCODE_API_MAX 66 13 14 /* Lowest firmware API version supported */ 15 #define IWL_22000_UCODE_API_MIN 39 16 17 /* NVM versions */ 18 #define IWL_22000_NVM_VERSION 0x0a1d 19 20 /* Memory offsets and lengths */ 21 #define IWL_22000_DCCM_OFFSET 0x800000 /* LMAC1 */ 22 #define IWL_22000_DCCM_LEN 0x10000 /* LMAC1 */ 23 #define IWL_22000_DCCM2_OFFSET 0x880000 24 #define IWL_22000_DCCM2_LEN 0x8000 25 #define IWL_22000_SMEM_OFFSET 0x400000 26 #define IWL_22000_SMEM_LEN 0xD0000 27 28 #define IWL_QU_B_HR_B_FW_PRE "iwlwifi-Qu-b0-hr-b0-" 29 #define IWL_QNJ_B_HR_B_FW_PRE "iwlwifi-QuQnj-b0-hr-b0-" 30 #define IWL_QU_C_HR_B_FW_PRE "iwlwifi-Qu-c0-hr-b0-" 31 #define IWL_QU_B_JF_B_FW_PRE "iwlwifi-Qu-b0-jf-b0-" 32 #define IWL_QU_C_JF_B_FW_PRE "iwlwifi-Qu-c0-jf-b0-" 33 #define IWL_QUZ_A_HR_B_FW_PRE "iwlwifi-QuZ-a0-hr-b0-" 34 #define IWL_QUZ_A_JF_B_FW_PRE "iwlwifi-QuZ-a0-jf-b0-" 35 #define IWL_QNJ_B_JF_B_FW_PRE "iwlwifi-QuQnj-b0-jf-b0-" 36 #define IWL_CC_A_FW_PRE "iwlwifi-cc-a0-" 37 #define IWL_SO_A_JF_B_FW_PRE "iwlwifi-so-a0-jf-b0-" 38 #define IWL_SO_A_HR_B_FW_PRE "iwlwifi-so-a0-hr-b0-" 39 #define IWL_SO_A_GF_A_FW_PRE "iwlwifi-so-a0-gf-a0-" 40 #define IWL_TY_A_GF_A_FW_PRE "iwlwifi-ty-a0-gf-a0-" 41 #define IWL_SO_A_GF4_A_FW_PRE "iwlwifi-so-a0-gf4-a0-" 42 #define IWL_SNJ_A_GF4_A_FW_PRE "iwlwifi-SoSnj-a0-gf4-a0-" 43 #define IWL_SNJ_A_GF_A_FW_PRE "iwlwifi-SoSnj-a0-gf-a0-" 44 #define IWL_SNJ_A_HR_B_FW_PRE "iwlwifi-SoSnj-a0-hr-b0-" 45 #define IWL_SNJ_A_JF_B_FW_PRE "iwlwifi-SoSnj-a0-jf-b0-" 46 #define IWL_MA_A_HR_B_FW_PRE "iwlwifi-ma-a0-hr-b0-" 47 #define IWL_MA_A_GF_A_FW_PRE "iwlwifi-ma-a0-gf-a0-" 48 #define IWL_MA_A_GF4_A_FW_PRE "iwlwifi-ma-a0-gf4-a0-" 49 #define IWL_MA_A_MR_A_FW_PRE "iwlwifi-ma-a0-mr-a0-" 50 #define IWL_MA_A_FM_A_FW_PRE "iwlwifi-ma-a0-fm-a0-" 51 #define IWL_SNJ_A_MR_A_FW_PRE "iwlwifi-SoSnj-a0-mr-a0-" 52 #define IWL_BZ_A_HR_B_FW_PRE "iwlwifi-bz-a0-hr-b0-" 53 #define IWL_BZ_A_GF_A_FW_PRE "iwlwifi-bz-a0-gf-a0-" 54 #define IWL_BZ_A_GF4_A_FW_PRE "iwlwifi-bz-a0-gf4-a0-" 55 #define IWL_BZ_A_MR_A_FW_PRE "iwlwifi-bz-a0-mr-a0-" 56 57 #define IWL_QU_B_HR_B_MODULE_FIRMWARE(api) \ 58 IWL_QU_B_HR_B_FW_PRE __stringify(api) ".ucode" 59 #define IWL_QNJ_B_HR_B_MODULE_FIRMWARE(api) \ 60 IWL_QNJ_B_HR_B_FW_PRE __stringify(api) ".ucode" 61 #define IWL_QUZ_A_HR_B_MODULE_FIRMWARE(api) \ 62 IWL_QUZ_A_HR_B_FW_PRE __stringify(api) ".ucode" 63 #define IWL_QUZ_A_JF_B_MODULE_FIRMWARE(api) \ 64 IWL_QUZ_A_JF_B_FW_PRE __stringify(api) ".ucode" 65 #define IWL_QU_C_HR_B_MODULE_FIRMWARE(api) \ 66 IWL_QU_C_HR_B_FW_PRE __stringify(api) ".ucode" 67 #define IWL_QU_B_JF_B_MODULE_FIRMWARE(api) \ 68 IWL_QU_B_JF_B_FW_PRE __stringify(api) ".ucode" 69 #define IWL_QNJ_B_JF_B_MODULE_FIRMWARE(api) \ 70 IWL_QNJ_B_JF_B_FW_PRE __stringify(api) ".ucode" 71 #define IWL_CC_A_MODULE_FIRMWARE(api) \ 72 IWL_CC_A_FW_PRE __stringify(api) ".ucode" 73 #define IWL_SO_A_JF_B_MODULE_FIRMWARE(api) \ 74 IWL_SO_A_JF_B_FW_PRE __stringify(api) ".ucode" 75 #define IWL_SO_A_HR_B_MODULE_FIRMWARE(api) \ 76 IWL_SO_A_HR_B_FW_PRE __stringify(api) ".ucode" 77 #define IWL_SO_A_GF_A_MODULE_FIRMWARE(api) \ 78 IWL_SO_A_GF_A_FW_PRE __stringify(api) ".ucode" 79 #define IWL_TY_A_GF_A_MODULE_FIRMWARE(api) \ 80 IWL_TY_A_GF_A_FW_PRE __stringify(api) ".ucode" 81 #define IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(api) \ 82 IWL_SNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 83 #define IWL_SNJ_A_GF_A_MODULE_FIRMWARE(api) \ 84 IWL_SNJ_A_GF_A_FW_PRE __stringify(api) ".ucode" 85 #define IWL_SNJ_A_HR_B_MODULE_FIRMWARE(api) \ 86 IWL_SNJ_A_HR_B_FW_PRE __stringify(api) ".ucode" 87 #define IWL_SNJ_A_JF_B_MODULE_FIRMWARE(api) \ 88 IWL_SNJ_A_JF_B_FW_PRE __stringify(api) ".ucode" 89 #define IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(api) \ 90 IWL_MA_A_HR_B_FW_PRE __stringify(api) ".ucode" 91 #define IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(api) \ 92 IWL_MA_A_GF_A_FW_PRE __stringify(api) ".ucode" 93 #define IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(api) \ 94 IWL_MA_A_GF4_A_FW_PRE __stringify(api) ".ucode" 95 #define IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(api) \ 96 IWL_MA_A_MR_A_FW_PRE __stringify(api) ".ucode" 97 #define IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(api) \ 98 IWL_MA_A_FM_A_FW_PRE __stringify(api) ".ucode" 99 #define IWL_SNJ_A_MR_A_MODULE_FIRMWARE(api) \ 100 IWL_SNJ_A_MR_A_FW_PRE __stringify(api) ".ucode" 101 #define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \ 102 IWL_BZ_A_HR_B_FW_PRE __stringify(api) ".ucode" 103 #define IWL_BZ_A_GF_A_MODULE_FIRMWARE(api) \ 104 IWL_BZ_A_GF_A_FW_PRE __stringify(api) ".ucode" 105 #define IWL_BZ_A_GF4_A_MODULE_FIRMWARE(api) \ 106 IWL_BZ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 107 #define IWL_BZ_A_MR_A_MODULE_FIRMWARE(api) \ 108 IWL_BZ_A_MR_A_FW_PRE __stringify(api) ".ucode" 109 110 static const struct iwl_base_params iwl_22000_base_params = { 111 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 112 .num_of_queues = 512, 113 .max_tfd_queue_size = 256, 114 .shadow_ram_support = true, 115 .led_compensation = 57, 116 .wd_timeout = IWL_LONG_WD_TIMEOUT, 117 .max_event_log_size = 512, 118 .shadow_reg_enable = true, 119 .pcie_l1_allowed = true, 120 }; 121 122 static const struct iwl_base_params iwl_ax210_base_params = { 123 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 124 .num_of_queues = 512, 125 .max_tfd_queue_size = 65536, 126 .shadow_ram_support = true, 127 .led_compensation = 57, 128 .wd_timeout = IWL_LONG_WD_TIMEOUT, 129 .max_event_log_size = 512, 130 .shadow_reg_enable = true, 131 .pcie_l1_allowed = true, 132 }; 133 134 static const struct iwl_ht_params iwl_22000_ht_params = { 135 .stbc = true, 136 .ldpc = true, 137 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) | 138 BIT(NL80211_BAND_6GHZ), 139 }; 140 141 #define IWL_DEVICE_22000_COMMON \ 142 .ucode_api_max = IWL_22000_UCODE_API_MAX, \ 143 .ucode_api_min = IWL_22000_UCODE_API_MIN, \ 144 .led_mode = IWL_LED_RF_STATE, \ 145 .nvm_hw_section_num = 10, \ 146 .non_shared_ant = ANT_B, \ 147 .dccm_offset = IWL_22000_DCCM_OFFSET, \ 148 .dccm_len = IWL_22000_DCCM_LEN, \ 149 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \ 150 .dccm2_len = IWL_22000_DCCM2_LEN, \ 151 .smem_offset = IWL_22000_SMEM_OFFSET, \ 152 .smem_len = IWL_22000_SMEM_LEN, \ 153 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, \ 154 .apmg_not_supported = true, \ 155 .trans.mq_rx_supported = true, \ 156 .vht_mu_mimo_supported = true, \ 157 .mac_addr_from_csr = 0x380, \ 158 .ht_params = &iwl_22000_ht_params, \ 159 .nvm_ver = IWL_22000_NVM_VERSION, \ 160 .trans.use_tfh = true, \ 161 .trans.rf_id = true, \ 162 .trans.gen2 = true, \ 163 .nvm_type = IWL_NVM_EXT, \ 164 .dbgc_supported = true, \ 165 .min_umac_error_event_table = 0x400000, \ 166 .d3_debug_data_base_addr = 0x401000, \ 167 .d3_debug_data_length = 60 * 1024, \ 168 .mon_smem_regs = { \ 169 .write_ptr = { \ 170 .addr = LDBG_M2S_BUF_WPTR, \ 171 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 172 }, \ 173 .cycle_cnt = { \ 174 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 175 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 176 }, \ 177 } 178 179 #define IWL_DEVICE_22500 \ 180 IWL_DEVICE_22000_COMMON, \ 181 .trans.device_family = IWL_DEVICE_FAMILY_22000, \ 182 .trans.base_params = &iwl_22000_base_params, \ 183 .gp2_reg_addr = 0xa02c68, \ 184 .mon_dram_regs = { \ 185 .write_ptr = { \ 186 .addr = MON_BUFF_WRPTR_VER2, \ 187 .mask = 0xffffffff, \ 188 }, \ 189 .cycle_cnt = { \ 190 .addr = MON_BUFF_CYCLE_CNT_VER2, \ 191 .mask = 0xffffffff, \ 192 }, \ 193 } 194 195 #define IWL_DEVICE_AX210 \ 196 IWL_DEVICE_22000_COMMON, \ 197 .trans.umac_prph_offset = 0x300000, \ 198 .trans.device_family = IWL_DEVICE_FAMILY_AX210, \ 199 .trans.base_params = &iwl_ax210_base_params, \ 200 .min_txq_size = 128, \ 201 .gp2_reg_addr = 0xd02c68, \ 202 .min_256_ba_txq_size = 1024, \ 203 .mon_dram_regs = { \ 204 .write_ptr = { \ 205 .addr = DBGC_CUR_DBGBUF_STATUS, \ 206 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 207 }, \ 208 .cycle_cnt = { \ 209 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 210 .mask = 0xffffffff, \ 211 }, \ 212 .cur_frag = { \ 213 .addr = DBGC_CUR_DBGBUF_STATUS, \ 214 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 215 }, \ 216 } 217 218 #define IWL_DEVICE_BZ_COMMON \ 219 .ucode_api_max = IWL_22000_UCODE_API_MAX, \ 220 .ucode_api_min = IWL_22000_UCODE_API_MIN, \ 221 .led_mode = IWL_LED_RF_STATE, \ 222 .nvm_hw_section_num = 10, \ 223 .non_shared_ant = ANT_B, \ 224 .dccm_offset = IWL_22000_DCCM_OFFSET, \ 225 .dccm_len = IWL_22000_DCCM_LEN, \ 226 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \ 227 .dccm2_len = IWL_22000_DCCM2_LEN, \ 228 .smem_offset = IWL_22000_SMEM_OFFSET, \ 229 .smem_len = IWL_22000_SMEM_LEN, \ 230 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, \ 231 .apmg_not_supported = true, \ 232 .trans.mq_rx_supported = true, \ 233 .vht_mu_mimo_supported = true, \ 234 .mac_addr_from_csr = 0x30, \ 235 .ht_params = &iwl_22000_ht_params, \ 236 .nvm_ver = IWL_22000_NVM_VERSION, \ 237 .trans.use_tfh = true, \ 238 .trans.rf_id = true, \ 239 .trans.gen2 = true, \ 240 .nvm_type = IWL_NVM_EXT, \ 241 .dbgc_supported = true, \ 242 .min_umac_error_event_table = 0x400000, \ 243 .d3_debug_data_base_addr = 0x401000, \ 244 .d3_debug_data_length = 60 * 1024, \ 245 .mon_smem_regs = { \ 246 .write_ptr = { \ 247 .addr = LDBG_M2S_BUF_WPTR, \ 248 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 249 }, \ 250 .cycle_cnt = { \ 251 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 252 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 253 }, \ 254 } 255 256 #define IWL_DEVICE_BZ \ 257 IWL_DEVICE_BZ_COMMON, \ 258 .trans.umac_prph_offset = 0x300000, \ 259 .trans.device_family = IWL_DEVICE_FAMILY_BZ, \ 260 .trans.base_params = &iwl_ax210_base_params, \ 261 .min_txq_size = 128, \ 262 .gp2_reg_addr = 0xd02c68, \ 263 .min_256_ba_txq_size = 1024, \ 264 .mon_dram_regs = { \ 265 .write_ptr = { \ 266 .addr = DBGC_CUR_DBGBUF_STATUS, \ 267 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 268 }, \ 269 .cycle_cnt = { \ 270 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 271 .mask = 0xffffffff, \ 272 }, \ 273 .cur_frag = { \ 274 .addr = DBGC_CUR_DBGBUF_STATUS, \ 275 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 276 }, \ 277 } 278 279 const struct iwl_cfg_trans_params iwl_qnj_trans_cfg = { 280 .mq_rx_supported = true, 281 .use_tfh = true, 282 .rf_id = true, 283 .gen2 = true, 284 .device_family = IWL_DEVICE_FAMILY_22000, 285 .base_params = &iwl_22000_base_params, 286 }; 287 288 const struct iwl_cfg_trans_params iwl_qu_trans_cfg = { 289 .mq_rx_supported = true, 290 .use_tfh = true, 291 .rf_id = true, 292 .gen2 = true, 293 .device_family = IWL_DEVICE_FAMILY_22000, 294 .base_params = &iwl_22000_base_params, 295 .integrated = true, 296 .xtal_latency = 500, 297 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 298 }; 299 300 const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg = { 301 .mq_rx_supported = true, 302 .use_tfh = true, 303 .rf_id = true, 304 .gen2 = true, 305 .device_family = IWL_DEVICE_FAMILY_22000, 306 .base_params = &iwl_22000_base_params, 307 .integrated = true, 308 .xtal_latency = 1820, 309 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_1820US, 310 }; 311 312 const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg = { 313 .mq_rx_supported = true, 314 .use_tfh = true, 315 .rf_id = true, 316 .gen2 = true, 317 .device_family = IWL_DEVICE_FAMILY_22000, 318 .base_params = &iwl_22000_base_params, 319 .integrated = true, 320 .xtal_latency = 12000, 321 .low_latency_xtal = true, 322 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 323 }; 324 325 const struct iwl_cfg_trans_params iwl_snj_trans_cfg = { 326 .mq_rx_supported = true, 327 .use_tfh = true, 328 .rf_id = true, 329 .gen2 = true, 330 .device_family = IWL_DEVICE_FAMILY_AX210, 331 .base_params = &iwl_ax210_base_params, 332 .umac_prph_offset = 0x300000, 333 }; 334 335 const struct iwl_cfg_trans_params iwl_so_trans_cfg = { 336 .mq_rx_supported = true, 337 .use_tfh = true, 338 .rf_id = true, 339 .gen2 = true, 340 .device_family = IWL_DEVICE_FAMILY_AX210, 341 .base_params = &iwl_ax210_base_params, 342 .umac_prph_offset = 0x300000, 343 .integrated = true, 344 /* TODO: the following values need to be checked */ 345 .xtal_latency = 500, 346 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 347 }; 348 349 const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg = { 350 .mq_rx_supported = true, 351 .use_tfh = true, 352 .rf_id = true, 353 .gen2 = true, 354 .device_family = IWL_DEVICE_FAMILY_AX210, 355 .base_params = &iwl_ax210_base_params, 356 .umac_prph_offset = 0x300000, 357 .integrated = true, 358 /* TODO: the following values need to be checked */ 359 .xtal_latency = 12000, 360 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 361 }; 362 363 /* 364 * If the device doesn't support HE, no need to have that many buffers. 365 * 22000 devices can split multiple frames into a single RB, so fewer are 366 * needed; AX210 cannot (but use smaller RBs by default) - these sizes 367 * were picked according to 8 MSDUs inside 256 A-MSDUs in an A-MPDU, with 368 * additional overhead to account for processing time. 369 */ 370 #define IWL_NUM_RBDS_NON_HE 512 371 #define IWL_NUM_RBDS_22000_HE 2048 372 #define IWL_NUM_RBDS_AX210_HE 4096 373 374 /* 375 * All JF radio modules are part of the 9000 series, but the MAC part 376 * looks more like 22000. That's why this device is here, but called 377 * 9560 nevertheless. 378 */ 379 const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg = { 380 .fw_name_pre = IWL_QU_B_JF_B_FW_PRE, 381 IWL_DEVICE_22500, 382 .num_rbds = IWL_NUM_RBDS_NON_HE, 383 }; 384 385 const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg = { 386 .fw_name_pre = IWL_QU_C_JF_B_FW_PRE, 387 IWL_DEVICE_22500, 388 .num_rbds = IWL_NUM_RBDS_NON_HE, 389 }; 390 391 const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg = { 392 .fw_name_pre = IWL_QUZ_A_JF_B_FW_PRE, 393 IWL_DEVICE_22500, 394 /* 395 * This device doesn't support receiving BlockAck with a large bitmap 396 * so we need to restrict the size of transmitted aggregation to the 397 * HT size; mac80211 would otherwise pick the HE max (256) by default. 398 */ 399 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 400 .num_rbds = IWL_NUM_RBDS_NON_HE, 401 }; 402 403 const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg = { 404 .fw_name_pre = IWL_QNJ_B_JF_B_FW_PRE, 405 IWL_DEVICE_22500, 406 /* 407 * This device doesn't support receiving BlockAck with a large bitmap 408 * so we need to restrict the size of transmitted aggregation to the 409 * HT size; mac80211 would otherwise pick the HE max (256) by default. 410 */ 411 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 412 .num_rbds = IWL_NUM_RBDS_NON_HE, 413 }; 414 415 const struct iwl_cfg_trans_params iwl_ax200_trans_cfg = { 416 .device_family = IWL_DEVICE_FAMILY_22000, 417 .base_params = &iwl_22000_base_params, 418 .mq_rx_supported = true, 419 .use_tfh = true, 420 .rf_id = true, 421 .gen2 = true, 422 .bisr_workaround = 1, 423 }; 424 425 const struct iwl_cfg_trans_params iwl_ma_trans_cfg = { 426 .device_family = IWL_DEVICE_FAMILY_AX210, 427 .base_params = &iwl_ax210_base_params, 428 .mq_rx_supported = true, 429 .use_tfh = true, 430 .rf_id = true, 431 .gen2 = true, 432 .integrated = true, 433 .umac_prph_offset = 0x300000 434 }; 435 436 const struct iwl_cfg_trans_params iwl_bz_trans_cfg = { 437 .device_family = IWL_DEVICE_FAMILY_BZ, 438 .base_params = &iwl_ax210_base_params, 439 .mq_rx_supported = true, 440 .use_tfh = true, 441 .rf_id = true, 442 .gen2 = true, 443 .integrated = true, 444 .umac_prph_offset = 0x300000, 445 .xtal_latency = 12000, 446 .low_latency_xtal = true, 447 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 448 }; 449 450 const char iwl_ax101_name[] = "Intel(R) Wi-Fi 6 AX101"; 451 const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz"; 452 const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz"; 453 const char iwl_ax203_name[] = "Intel(R) Wi-Fi 6 AX203"; 454 const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6E AX211 160MHz"; 455 const char iwl_ax221_name[] = "Intel(R) Wi-Fi 6E AX221 160MHz"; 456 const char iwl_ax231_name[] = "Intel(R) Wi-Fi 6E AX231 160MHz"; 457 const char iwl_ax411_name[] = "Intel(R) Wi-Fi 6E AX411 160MHz"; 458 const char iwl_bz_name[] = "Intel(R) TBD Bz device"; 459 460 const char iwl_ax200_killer_1650w_name[] = 461 "Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)"; 462 const char iwl_ax200_killer_1650x_name[] = 463 "Killer(R) Wi-Fi 6 AX1650x 160MHz Wireless Network Adapter (200NGW)"; 464 const char iwl_ax201_killer_1650s_name[] = 465 "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)"; 466 const char iwl_ax201_killer_1650i_name[] = 467 "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)"; 468 const char iwl_ax210_killer_1675w_name[] = 469 "Killer(R) Wi-Fi 6E AX1675w 160MHz Wireless Network Adapter (210D2W)"; 470 const char iwl_ax210_killer_1675x_name[] = 471 "Killer(R) Wi-Fi 6E AX1675x 160MHz Wireless Network Adapter (210NGW)"; 472 473 const struct iwl_cfg iwl_qu_b0_hr1_b0 = { 474 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 475 IWL_DEVICE_22500, 476 /* 477 * This device doesn't support receiving BlockAck with a large bitmap 478 * so we need to restrict the size of transmitted aggregation to the 479 * HT size; mac80211 would otherwise pick the HE max (256) by default. 480 */ 481 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 482 .tx_with_siso_diversity = true, 483 .num_rbds = IWL_NUM_RBDS_22000_HE, 484 }; 485 486 const struct iwl_cfg iwl_qu_b0_hr_b0 = { 487 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 488 IWL_DEVICE_22500, 489 /* 490 * This device doesn't support receiving BlockAck with a large bitmap 491 * so we need to restrict the size of transmitted aggregation to the 492 * HT size; mac80211 would otherwise pick the HE max (256) by default. 493 */ 494 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 495 .num_rbds = IWL_NUM_RBDS_22000_HE, 496 }; 497 498 const struct iwl_cfg iwl_ax201_cfg_qu_hr = { 499 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 500 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 501 IWL_DEVICE_22500, 502 /* 503 * This device doesn't support receiving BlockAck with a large bitmap 504 * so we need to restrict the size of transmitted aggregation to the 505 * HT size; mac80211 would otherwise pick the HE max (256) by default. 506 */ 507 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 508 .num_rbds = IWL_NUM_RBDS_22000_HE, 509 }; 510 511 const struct iwl_cfg iwl_qu_c0_hr1_b0 = { 512 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 513 IWL_DEVICE_22500, 514 /* 515 * This device doesn't support receiving BlockAck with a large bitmap 516 * so we need to restrict the size of transmitted aggregation to the 517 * HT size; mac80211 would otherwise pick the HE max (256) by default. 518 */ 519 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 520 .tx_with_siso_diversity = true, 521 .num_rbds = IWL_NUM_RBDS_22000_HE, 522 }; 523 524 const struct iwl_cfg iwl_qu_c0_hr_b0 = { 525 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 526 IWL_DEVICE_22500, 527 /* 528 * This device doesn't support receiving BlockAck with a large bitmap 529 * so we need to restrict the size of transmitted aggregation to the 530 * HT size; mac80211 would otherwise pick the HE max (256) by default. 531 */ 532 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 533 .num_rbds = IWL_NUM_RBDS_22000_HE, 534 }; 535 536 const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0 = { 537 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 538 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 539 IWL_DEVICE_22500, 540 /* 541 * This device doesn't support receiving BlockAck with a large bitmap 542 * so we need to restrict the size of transmitted aggregation to the 543 * HT size; mac80211 would otherwise pick the HE max (256) by default. 544 */ 545 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 546 .num_rbds = IWL_NUM_RBDS_22000_HE, 547 }; 548 549 const struct iwl_cfg iwl_quz_a0_hr1_b0 = { 550 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 551 IWL_DEVICE_22500, 552 /* 553 * This device doesn't support receiving BlockAck with a large bitmap 554 * so we need to restrict the size of transmitted aggregation to the 555 * HT size; mac80211 would otherwise pick the HE max (256) by default. 556 */ 557 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 558 .tx_with_siso_diversity = true, 559 .num_rbds = IWL_NUM_RBDS_22000_HE, 560 }; 561 562 const struct iwl_cfg iwl_ax201_cfg_quz_hr = { 563 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 564 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 565 IWL_DEVICE_22500, 566 /* 567 * This device doesn't support receiving BlockAck with a large bitmap 568 * so we need to restrict the size of transmitted aggregation to the 569 * HT size; mac80211 would otherwise pick the HE max (256) by default. 570 */ 571 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 572 .num_rbds = IWL_NUM_RBDS_22000_HE, 573 }; 574 575 const struct iwl_cfg iwl_ax1650s_cfg_quz_hr = { 576 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)", 577 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 578 IWL_DEVICE_22500, 579 /* 580 * This device doesn't support receiving BlockAck with a large bitmap 581 * so we need to restrict the size of transmitted aggregation to the 582 * HT size; mac80211 would otherwise pick the HE max (256) by default. 583 */ 584 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 585 .num_rbds = IWL_NUM_RBDS_22000_HE, 586 }; 587 588 const struct iwl_cfg iwl_ax1650i_cfg_quz_hr = { 589 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)", 590 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 591 IWL_DEVICE_22500, 592 /* 593 * This device doesn't support receiving BlockAck with a large bitmap 594 * so we need to restrict the size of transmitted aggregation to the 595 * HT size; mac80211 would otherwise pick the HE max (256) by default. 596 */ 597 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 598 .num_rbds = IWL_NUM_RBDS_22000_HE, 599 }; 600 601 const struct iwl_cfg iwl_ax200_cfg_cc = { 602 .fw_name_pre = IWL_CC_A_FW_PRE, 603 IWL_DEVICE_22500, 604 /* 605 * This device doesn't support receiving BlockAck with a large bitmap 606 * so we need to restrict the size of transmitted aggregation to the 607 * HT size; mac80211 would otherwise pick the HE max (256) by default. 608 */ 609 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 610 .num_rbds = IWL_NUM_RBDS_22000_HE, 611 }; 612 613 const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0 = { 614 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)", 615 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 616 IWL_DEVICE_22500, 617 /* 618 * This device doesn't support receiving BlockAck with a large bitmap 619 * so we need to restrict the size of transmitted aggregation to the 620 * HT size; mac80211 would otherwise pick the HE max (256) by default. 621 */ 622 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 623 .num_rbds = IWL_NUM_RBDS_22000_HE, 624 }; 625 626 const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0 = { 627 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)", 628 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 629 IWL_DEVICE_22500, 630 /* 631 * This device doesn't support receiving BlockAck with a large bitmap 632 * so we need to restrict the size of transmitted aggregation to the 633 * HT size; mac80211 would otherwise pick the HE max (256) by default. 634 */ 635 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 636 .num_rbds = IWL_NUM_RBDS_22000_HE, 637 }; 638 639 const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0 = { 640 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)", 641 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 642 IWL_DEVICE_22500, 643 /* 644 * This device doesn't support receiving BlockAck with a large bitmap 645 * so we need to restrict the size of transmitted aggregation to the 646 * HT size; mac80211 would otherwise pick the HE max (256) by default. 647 */ 648 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 649 .num_rbds = IWL_NUM_RBDS_22000_HE, 650 }; 651 652 const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0 = { 653 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)", 654 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 655 IWL_DEVICE_22500, 656 /* 657 * This device doesn't support receiving BlockAck with a large bitmap 658 * so we need to restrict the size of transmitted aggregation to the 659 * HT size; mac80211 would otherwise pick the HE max (256) by default. 660 */ 661 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 662 .num_rbds = IWL_NUM_RBDS_22000_HE, 663 }; 664 665 const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg = { 666 .fw_name_pre = IWL_QNJ_B_HR_B_FW_PRE, 667 IWL_DEVICE_22500, 668 /* 669 * This device doesn't support receiving BlockAck with a large bitmap 670 * so we need to restrict the size of transmitted aggregation to the 671 * HT size; mac80211 would otherwise pick the HE max (256) by default. 672 */ 673 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 674 .num_rbds = IWL_NUM_RBDS_22000_HE, 675 }; 676 677 const struct iwl_cfg iwlax210_2ax_cfg_so_jf_b0 = { 678 .name = "Intel(R) Wireless-AC 9560 160MHz", 679 .fw_name_pre = IWL_SO_A_JF_B_FW_PRE, 680 IWL_DEVICE_AX210, 681 .num_rbds = IWL_NUM_RBDS_NON_HE, 682 }; 683 684 const struct iwl_cfg iwlax210_2ax_cfg_so_hr_a0 = { 685 .name = "Intel(R) Wi-Fi 6 AX210 160MHz", 686 .fw_name_pre = IWL_SO_A_HR_B_FW_PRE, 687 IWL_DEVICE_AX210, 688 .num_rbds = IWL_NUM_RBDS_AX210_HE, 689 }; 690 691 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0 = { 692 .name = iwl_ax211_name, 693 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 694 .uhb_supported = true, 695 IWL_DEVICE_AX210, 696 .num_rbds = IWL_NUM_RBDS_AX210_HE, 697 }; 698 699 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long = { 700 .name = iwl_ax211_name, 701 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 702 .uhb_supported = true, 703 IWL_DEVICE_AX210, 704 .num_rbds = IWL_NUM_RBDS_AX210_HE, 705 .trans.xtal_latency = 12000, 706 .trans.low_latency_xtal = true, 707 }; 708 709 const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0 = { 710 .name = "Intel(R) Wi-Fi 6 AX210 160MHz", 711 .fw_name_pre = IWL_TY_A_GF_A_FW_PRE, 712 .uhb_supported = true, 713 IWL_DEVICE_AX210, 714 .num_rbds = IWL_NUM_RBDS_AX210_HE, 715 }; 716 717 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0 = { 718 .name = iwl_ax411_name, 719 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 720 .uhb_supported = true, 721 IWL_DEVICE_AX210, 722 .num_rbds = IWL_NUM_RBDS_AX210_HE, 723 }; 724 725 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long = { 726 .name = iwl_ax411_name, 727 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 728 .uhb_supported = true, 729 IWL_DEVICE_AX210, 730 .num_rbds = IWL_NUM_RBDS_AX210_HE, 731 .trans.xtal_latency = 12000, 732 .trans.low_latency_xtal = true, 733 }; 734 735 const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0 = { 736 .name = iwl_ax411_name, 737 .fw_name_pre = IWL_SNJ_A_GF4_A_FW_PRE, 738 .uhb_supported = true, 739 IWL_DEVICE_AX210, 740 .num_rbds = IWL_NUM_RBDS_AX210_HE, 741 }; 742 743 const struct iwl_cfg iwlax211_cfg_snj_gf_a0 = { 744 .name = iwl_ax211_name, 745 .fw_name_pre = IWL_SNJ_A_GF_A_FW_PRE, 746 .uhb_supported = true, 747 IWL_DEVICE_AX210, 748 .num_rbds = IWL_NUM_RBDS_AX210_HE, 749 }; 750 751 const struct iwl_cfg iwl_cfg_snj_hr_b0 = { 752 .fw_name_pre = IWL_SNJ_A_HR_B_FW_PRE, 753 .uhb_supported = true, 754 IWL_DEVICE_AX210, 755 .num_rbds = IWL_NUM_RBDS_AX210_HE, 756 }; 757 758 const struct iwl_cfg iwl_cfg_snj_a0_jf_b0 = { 759 .fw_name_pre = IWL_SNJ_A_JF_B_FW_PRE, 760 .uhb_supported = true, 761 IWL_DEVICE_AX210, 762 .num_rbds = IWL_NUM_RBDS_AX210_HE, 763 }; 764 765 const struct iwl_cfg iwl_cfg_ma_a0_hr_b0 = { 766 .fw_name_pre = IWL_MA_A_HR_B_FW_PRE, 767 .uhb_supported = true, 768 IWL_DEVICE_AX210, 769 .num_rbds = IWL_NUM_RBDS_AX210_HE, 770 }; 771 772 const struct iwl_cfg iwl_cfg_ma_a0_gf_a0 = { 773 .fw_name_pre = IWL_MA_A_GF_A_FW_PRE, 774 .uhb_supported = true, 775 IWL_DEVICE_AX210, 776 .num_rbds = IWL_NUM_RBDS_AX210_HE, 777 }; 778 779 const struct iwl_cfg iwl_cfg_ma_a0_gf4_a0 = { 780 .fw_name_pre = IWL_MA_A_GF4_A_FW_PRE, 781 .uhb_supported = true, 782 IWL_DEVICE_AX210, 783 .num_rbds = IWL_NUM_RBDS_AX210_HE, 784 }; 785 786 const struct iwl_cfg iwl_cfg_ma_a0_mr_a0 = { 787 .fw_name_pre = IWL_MA_A_MR_A_FW_PRE, 788 .uhb_supported = true, 789 IWL_DEVICE_AX210, 790 .num_rbds = IWL_NUM_RBDS_AX210_HE, 791 }; 792 793 const struct iwl_cfg iwl_cfg_ma_a0_fm_a0 = { 794 .fw_name_pre = IWL_MA_A_FM_A_FW_PRE, 795 .uhb_supported = true, 796 IWL_DEVICE_AX210, 797 .num_rbds = IWL_NUM_RBDS_AX210_HE, 798 }; 799 800 const struct iwl_cfg iwl_cfg_snj_a0_mr_a0 = { 801 .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE, 802 .uhb_supported = true, 803 IWL_DEVICE_AX210, 804 .num_rbds = IWL_NUM_RBDS_AX210_HE, 805 }; 806 807 const struct iwl_cfg iwl_cfg_so_a0_hr_a0 = { 808 .fw_name_pre = IWL_SO_A_HR_B_FW_PRE, 809 IWL_DEVICE_AX210, 810 .num_rbds = IWL_NUM_RBDS_AX210_HE, 811 }; 812 813 const struct iwl_cfg iwl_cfg_quz_a0_hr_b0 = { 814 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 815 IWL_DEVICE_22500, 816 /* 817 * This device doesn't support receiving BlockAck with a large bitmap 818 * so we need to restrict the size of transmitted aggregation to the 819 * HT size; mac80211 would otherwise pick the HE max (256) by default. 820 */ 821 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 822 .num_rbds = IWL_NUM_RBDS_22000_HE, 823 }; 824 825 const struct iwl_cfg iwl_cfg_bz_a0_hr_b0 = { 826 .fw_name_pre = IWL_BZ_A_HR_B_FW_PRE, 827 .uhb_supported = true, 828 IWL_DEVICE_BZ, 829 .num_rbds = IWL_NUM_RBDS_AX210_HE, 830 }; 831 832 const struct iwl_cfg iwl_cfg_bz_a0_gf_a0 = { 833 .fw_name_pre = IWL_BZ_A_GF_A_FW_PRE, 834 .uhb_supported = true, 835 IWL_DEVICE_BZ, 836 .num_rbds = IWL_NUM_RBDS_AX210_HE, 837 }; 838 839 const struct iwl_cfg iwl_cfg_bz_a0_gf4_a0 = { 840 .fw_name_pre = IWL_BZ_A_GF4_A_FW_PRE, 841 .uhb_supported = true, 842 IWL_DEVICE_BZ, 843 .num_rbds = IWL_NUM_RBDS_AX210_HE, 844 }; 845 846 const struct iwl_cfg iwl_cfg_bz_a0_mr_a0 = { 847 .fw_name_pre = IWL_BZ_A_MR_A_FW_PRE, 848 .uhb_supported = true, 849 IWL_DEVICE_BZ, 850 .num_rbds = IWL_NUM_RBDS_AX210_HE, 851 }; 852 853 MODULE_FIRMWARE(IWL_QU_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 854 MODULE_FIRMWARE(IWL_QNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 855 MODULE_FIRMWARE(IWL_QU_C_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 856 MODULE_FIRMWARE(IWL_QU_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 857 MODULE_FIRMWARE(IWL_QUZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 858 MODULE_FIRMWARE(IWL_QUZ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 859 MODULE_FIRMWARE(IWL_QNJ_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 860 MODULE_FIRMWARE(IWL_CC_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 861 MODULE_FIRMWARE(IWL_SO_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 862 MODULE_FIRMWARE(IWL_SO_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 863 MODULE_FIRMWARE(IWL_SO_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 864 MODULE_FIRMWARE(IWL_TY_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 865 MODULE_FIRMWARE(IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 866 MODULE_FIRMWARE(IWL_SNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 867 MODULE_FIRMWARE(IWL_SNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 868 MODULE_FIRMWARE(IWL_SNJ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 869 MODULE_FIRMWARE(IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 870 MODULE_FIRMWARE(IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 871 MODULE_FIRMWARE(IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 872 MODULE_FIRMWARE(IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 873 MODULE_FIRMWARE(IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 874 MODULE_FIRMWARE(IWL_SNJ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 875 MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 876 MODULE_FIRMWARE(IWL_BZ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 877 MODULE_FIRMWARE(IWL_BZ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 878 MODULE_FIRMWARE(IWL_BZ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 879
