1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * H/W layer of ISHTP provider device (ISH)
4 *
5 * Copyright (c) 2014-2016, Intel Corporation.
6 */
7
8 #include <linux/devm-helpers.h>
9 #include <linux/sched.h>
10 #include <linux/spinlock.h>
11 #include <linux/delay.h>
12 #include <linux/jiffies.h>
13 #include "client.h"
14 #include "hw-ish.h"
15 #include "hbm.h"
16
17 /* For FW reset flow */
18 static struct work_struct fw_reset_work;
19 static struct ishtp_device *ishtp_dev;
20
21 /**
22 * ish_reg_read() - Read register
23 * @dev: ISHTP device pointer
24 * @offset: Register offset
25 *
26 * Read 32 bit register at a given offset
27 *
28 * Return: Read register value
29 */
ish_reg_read(const struct ishtp_device * dev,unsigned long offset)30 static inline uint32_t ish_reg_read(const struct ishtp_device *dev,
31 unsigned long offset)
32 {
33 struct ish_hw *hw = to_ish_hw(dev);
34
35 return readl(hw->mem_addr + offset);
36 }
37
38 /**
39 * ish_reg_write() - Write register
40 * @dev: ISHTP device pointer
41 * @offset: Register offset
42 * @value: Value to write
43 *
44 * Writes 32 bit register at a give offset
45 */
ish_reg_write(struct ishtp_device * dev,unsigned long offset,uint32_t value)46 static inline void ish_reg_write(struct ishtp_device *dev,
47 unsigned long offset,
48 uint32_t value)
49 {
50 struct ish_hw *hw = to_ish_hw(dev);
51
52 writel(value, hw->mem_addr + offset);
53 }
54
55 /**
56 * _ish_read_fw_sts_reg() - Read FW status register
57 * @dev: ISHTP device pointer
58 *
59 * Read FW status register
60 *
61 * Return: Read register value
62 */
_ish_read_fw_sts_reg(struct ishtp_device * dev)63 static inline uint32_t _ish_read_fw_sts_reg(struct ishtp_device *dev)
64 {
65 return ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS);
66 }
67
68 /**
69 * check_generated_interrupt() - Check if ISH interrupt
70 * @dev: ISHTP device pointer
71 *
72 * Check if an interrupt was generated for ISH
73 *
74 * Return: Read true or false
75 */
check_generated_interrupt(struct ishtp_device * dev)76 static bool check_generated_interrupt(struct ishtp_device *dev)
77 {
78 bool interrupt_generated = true;
79 uint32_t pisr_val = 0;
80
81 if (dev->pdev->device == CHV_DEVICE_ID) {
82 pisr_val = ish_reg_read(dev, IPC_REG_PISR_CHV_AB);
83 interrupt_generated =
84 IPC_INT_FROM_ISH_TO_HOST_CHV_AB(pisr_val);
85 } else {
86 pisr_val = ish_reg_read(dev, IPC_REG_PISR_BXT);
87 interrupt_generated = !!pisr_val;
88 /* only busy-clear bit is RW, others are RO */
89 if (pisr_val)
90 ish_reg_write(dev, IPC_REG_PISR_BXT, pisr_val);
91 }
92
93 return interrupt_generated;
94 }
95
96 /**
97 * ish_is_input_ready() - Check if FW ready for RX
98 * @dev: ISHTP device pointer
99 *
100 * Check if ISH FW is ready for receiving data
101 *
102 * Return: Read true or false
103 */
ish_is_input_ready(struct ishtp_device * dev)104 static bool ish_is_input_ready(struct ishtp_device *dev)
105 {
106 uint32_t doorbell_val;
107
108 doorbell_val = ish_reg_read(dev, IPC_REG_HOST2ISH_DRBL);
109 return !IPC_IS_BUSY(doorbell_val);
110 }
111
112 /**
113 * set_host_ready() - Indicate host ready
114 * @dev: ISHTP device pointer
115 *
116 * Set host ready indication to FW
117 */
set_host_ready(struct ishtp_device * dev)118 static void set_host_ready(struct ishtp_device *dev)
119 {
120 if (dev->pdev->device == CHV_DEVICE_ID) {
121 if (dev->pdev->revision == REVISION_ID_CHT_A0 ||
122 (dev->pdev->revision & REVISION_ID_SI_MASK) ==
123 REVISION_ID_CHT_Ax_SI)
124 ish_reg_write(dev, IPC_REG_HOST_COMM, 0x81);
125 else if (dev->pdev->revision == REVISION_ID_CHT_B0 ||
126 (dev->pdev->revision & REVISION_ID_SI_MASK) ==
127 REVISION_ID_CHT_Bx_SI ||
128 (dev->pdev->revision & REVISION_ID_SI_MASK) ==
129 REVISION_ID_CHT_Kx_SI ||
130 (dev->pdev->revision & REVISION_ID_SI_MASK) ==
131 REVISION_ID_CHT_Dx_SI) {
132 uint32_t host_comm_val;
133
134 host_comm_val = ish_reg_read(dev, IPC_REG_HOST_COMM);
135 host_comm_val |= IPC_HOSTCOMM_INT_EN_BIT_CHV_AB | 0x81;
136 ish_reg_write(dev, IPC_REG_HOST_COMM, host_comm_val);
137 }
138 } else {
139 uint32_t host_pimr_val;
140
141 host_pimr_val = ish_reg_read(dev, IPC_REG_PIMR_BXT);
142 host_pimr_val |= IPC_PIMR_INT_EN_BIT_BXT;
143 /*
144 * disable interrupt generated instead of
145 * RX_complete_msg
146 */
147 host_pimr_val &= ~IPC_HOST2ISH_BUSYCLEAR_MASK_BIT;
148
149 ish_reg_write(dev, IPC_REG_PIMR_BXT, host_pimr_val);
150 }
151 }
152
153 /**
154 * ishtp_fw_is_ready() - Check if FW ready
155 * @dev: ISHTP device pointer
156 *
157 * Check if ISH FW is ready
158 *
159 * Return: Read true or false
160 */
ishtp_fw_is_ready(struct ishtp_device * dev)161 static bool ishtp_fw_is_ready(struct ishtp_device *dev)
162 {
163 uint32_t ish_status = _ish_read_fw_sts_reg(dev);
164
165 return IPC_IS_ISH_ILUP(ish_status) &&
166 IPC_IS_ISH_ISHTP_READY(ish_status);
167 }
168
169 /**
170 * ish_set_host_rdy() - Indicate host ready
171 * @dev: ISHTP device pointer
172 *
173 * Set host ready indication to FW
174 */
ish_set_host_rdy(struct ishtp_device * dev)175 static void ish_set_host_rdy(struct ishtp_device *dev)
176 {
177 uint32_t host_status = ish_reg_read(dev, IPC_REG_HOST_COMM);
178
179 IPC_SET_HOST_READY(host_status);
180 ish_reg_write(dev, IPC_REG_HOST_COMM, host_status);
181 }
182
183 /**
184 * ish_clr_host_rdy() - Indicate host not ready
185 * @dev: ISHTP device pointer
186 *
187 * Send host not ready indication to FW
188 */
ish_clr_host_rdy(struct ishtp_device * dev)189 static void ish_clr_host_rdy(struct ishtp_device *dev)
190 {
191 uint32_t host_status = ish_reg_read(dev, IPC_REG_HOST_COMM);
192
193 IPC_CLEAR_HOST_READY(host_status);
194 ish_reg_write(dev, IPC_REG_HOST_COMM, host_status);
195 }
196
ish_chk_host_rdy(struct ishtp_device * dev)197 static bool ish_chk_host_rdy(struct ishtp_device *dev)
198 {
199 uint32_t host_status = ish_reg_read(dev, IPC_REG_HOST_COMM);
200
201 return (host_status & IPC_HOSTCOMM_READY_BIT);
202 }
203
204 /**
205 * ish_set_host_ready() - reconfig ipc host registers
206 * @dev: ishtp device pointer
207 *
208 * Set host to ready state
209 * This API is called in some case:
210 * fw is still on, but ipc is powered down.
211 * such as OOB case.
212 *
213 * Return: 0 for success else error fault code
214 */
ish_set_host_ready(struct ishtp_device * dev)215 void ish_set_host_ready(struct ishtp_device *dev)
216 {
217 if (ish_chk_host_rdy(dev))
218 return;
219
220 ish_set_host_rdy(dev);
221 set_host_ready(dev);
222 }
223
224 /**
225 * _ishtp_read_hdr() - Read message header
226 * @dev: ISHTP device pointer
227 *
228 * Read header of 32bit length
229 *
230 * Return: Read register value
231 */
_ishtp_read_hdr(const struct ishtp_device * dev)232 static uint32_t _ishtp_read_hdr(const struct ishtp_device *dev)
233 {
234 return ish_reg_read(dev, IPC_REG_ISH2HOST_MSG);
235 }
236
237 /**
238 * _ishtp_read - Read message
239 * @dev: ISHTP device pointer
240 * @buffer: message buffer
241 * @buffer_length: length of message buffer
242 *
243 * Read message from FW
244 *
245 * Return: Always 0
246 */
_ishtp_read(struct ishtp_device * dev,unsigned char * buffer,unsigned long buffer_length)247 static int _ishtp_read(struct ishtp_device *dev, unsigned char *buffer,
248 unsigned long buffer_length)
249 {
250 uint32_t i;
251 uint32_t *r_buf = (uint32_t *)buffer;
252 uint32_t msg_offs;
253
254 msg_offs = IPC_REG_ISH2HOST_MSG + sizeof(struct ishtp_msg_hdr);
255 for (i = 0; i < buffer_length; i += sizeof(uint32_t))
256 *r_buf++ = ish_reg_read(dev, msg_offs + i);
257
258 return 0;
259 }
260
261 /**
262 * write_ipc_from_queue() - try to write ipc msg from Tx queue to device
263 * @dev: ishtp device pointer
264 *
265 * Check if DRBL is cleared. if it is - write the first IPC msg, then call
266 * the callback function (unless it's NULL)
267 *
268 * Return: 0 for success else failure code
269 */
write_ipc_from_queue(struct ishtp_device * dev)270 static int write_ipc_from_queue(struct ishtp_device *dev)
271 {
272 struct wr_msg_ctl_info *ipc_link;
273 unsigned long length;
274 unsigned long rem;
275 unsigned long flags;
276 uint32_t doorbell_val;
277 uint32_t *r_buf;
278 uint32_t reg_addr;
279 int i;
280 void (*ipc_send_compl)(void *);
281 void *ipc_send_compl_prm;
282
283 if (dev->dev_state == ISHTP_DEV_DISABLED)
284 return -EINVAL;
285
286 spin_lock_irqsave(&dev->wr_processing_spinlock, flags);
287 if (!ish_is_input_ready(dev)) {
288 spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags);
289 return -EBUSY;
290 }
291
292 /*
293 * if tx send list is empty - return 0;
294 * may happen, as RX_COMPLETE handler doesn't check list emptiness.
295 */
296 if (list_empty(&dev->wr_processing_list)) {
297 spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags);
298 return 0;
299 }
300
301 ipc_link = list_first_entry(&dev->wr_processing_list,
302 struct wr_msg_ctl_info, link);
303 /* first 4 bytes of the data is the doorbell value (IPC header) */
304 length = ipc_link->length - sizeof(uint32_t);
305 doorbell_val = *(uint32_t *)ipc_link->inline_data;
306 r_buf = (uint32_t *)(ipc_link->inline_data + sizeof(uint32_t));
307
308 /* If sending MNG_SYNC_FW_CLOCK, update clock again */
309 if (IPC_HEADER_GET_PROTOCOL(doorbell_val) == IPC_PROTOCOL_MNG &&
310 IPC_HEADER_GET_MNG_CMD(doorbell_val) == MNG_SYNC_FW_CLOCK) {
311 uint64_t usec_system, usec_utc;
312 struct ipc_time_update_msg time_update;
313 struct time_sync_format ts_format;
314
315 usec_system = ktime_to_us(ktime_get_boottime());
316 usec_utc = ktime_to_us(ktime_get_real());
317 ts_format.ts1_source = HOST_SYSTEM_TIME_USEC;
318 ts_format.ts2_source = HOST_UTC_TIME_USEC;
319 ts_format.reserved = 0;
320
321 time_update.primary_host_time = usec_system;
322 time_update.secondary_host_time = usec_utc;
323 time_update.sync_info = ts_format;
324
325 memcpy(r_buf, &time_update,
326 sizeof(struct ipc_time_update_msg));
327 }
328
329 for (i = 0, reg_addr = IPC_REG_HOST2ISH_MSG; i < length >> 2; i++,
330 reg_addr += 4)
331 ish_reg_write(dev, reg_addr, r_buf[i]);
332
333 rem = length & 0x3;
334 if (rem > 0) {
335 uint32_t reg = 0;
336
337 memcpy(®, &r_buf[length >> 2], rem);
338 ish_reg_write(dev, reg_addr, reg);
339 }
340 ish_reg_write(dev, IPC_REG_HOST2ISH_DRBL, doorbell_val);
341
342 /* Flush writes to msg registers and doorbell */
343 ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS);
344
345 /* Update IPC counters */
346 ++dev->ipc_tx_cnt;
347 dev->ipc_tx_bytes_cnt += IPC_HEADER_GET_LENGTH(doorbell_val);
348
349 ipc_send_compl = ipc_link->ipc_send_compl;
350 ipc_send_compl_prm = ipc_link->ipc_send_compl_prm;
351 list_del_init(&ipc_link->link);
352 list_add(&ipc_link->link, &dev->wr_free_list);
353 spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags);
354
355 /*
356 * callback will be called out of spinlock,
357 * after ipc_link returned to free list
358 */
359 if (ipc_send_compl)
360 ipc_send_compl(ipc_send_compl_prm);
361
362 return 0;
363 }
364
365 /**
366 * write_ipc_to_queue() - write ipc msg to Tx queue
367 * @dev: ishtp device instance
368 * @ipc_send_compl: Send complete callback
369 * @ipc_send_compl_prm: Parameter to send in complete callback
370 * @msg: Pointer to message
371 * @length: Length of message
372 *
373 * Recived msg with IPC (and upper protocol) header and add it to the device
374 * Tx-to-write list then try to send the first IPC waiting msg
375 * (if DRBL is cleared)
376 * This function returns negative value for failure (means free list
377 * is empty, or msg too long) and 0 for success.
378 *
379 * Return: 0 for success else failure code
380 */
write_ipc_to_queue(struct ishtp_device * dev,void (* ipc_send_compl)(void *),void * ipc_send_compl_prm,unsigned char * msg,int length)381 static int write_ipc_to_queue(struct ishtp_device *dev,
382 void (*ipc_send_compl)(void *), void *ipc_send_compl_prm,
383 unsigned char *msg, int length)
384 {
385 struct wr_msg_ctl_info *ipc_link;
386 unsigned long flags;
387
388 if (length > IPC_FULL_MSG_SIZE)
389 return -EMSGSIZE;
390
391 spin_lock_irqsave(&dev->wr_processing_spinlock, flags);
392 if (list_empty(&dev->wr_free_list)) {
393 spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags);
394 return -ENOMEM;
395 }
396 ipc_link = list_first_entry(&dev->wr_free_list,
397 struct wr_msg_ctl_info, link);
398 list_del_init(&ipc_link->link);
399
400 ipc_link->ipc_send_compl = ipc_send_compl;
401 ipc_link->ipc_send_compl_prm = ipc_send_compl_prm;
402 ipc_link->length = length;
403 memcpy(ipc_link->inline_data, msg, length);
404
405 list_add_tail(&ipc_link->link, &dev->wr_processing_list);
406 spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags);
407
408 write_ipc_from_queue(dev);
409
410 return 0;
411 }
412
413 /**
414 * ipc_send_mng_msg() - Send management message
415 * @dev: ishtp device instance
416 * @msg_code: Message code
417 * @msg: Pointer to message
418 * @size: Length of message
419 *
420 * Send management message to FW
421 *
422 * Return: 0 for success else failure code
423 */
ipc_send_mng_msg(struct ishtp_device * dev,uint32_t msg_code,void * msg,size_t size)424 static int ipc_send_mng_msg(struct ishtp_device *dev, uint32_t msg_code,
425 void *msg, size_t size)
426 {
427 unsigned char ipc_msg[IPC_FULL_MSG_SIZE];
428 uint32_t drbl_val = IPC_BUILD_MNG_MSG(msg_code, size);
429
430 memcpy(ipc_msg, &drbl_val, sizeof(uint32_t));
431 memcpy(ipc_msg + sizeof(uint32_t), msg, size);
432 return write_ipc_to_queue(dev, NULL, NULL, ipc_msg,
433 sizeof(uint32_t) + size);
434 }
435
436 #define WAIT_FOR_FW_RDY 0x1
437 #define WAIT_FOR_INPUT_RDY 0x2
438
439 /**
440 * timed_wait_for_timeout() - wait special event with timeout
441 * @dev: ISHTP device pointer
442 * @condition: indicate the condition for waiting
443 * @timeinc: time slice for every wait cycle, in ms
444 * @timeout: time in ms for timeout
445 *
446 * This function will check special event to be ready in a loop, the loop
447 * period is specificd in timeinc. Wait timeout will causes failure.
448 *
449 * Return: 0 for success else failure code
450 */
timed_wait_for_timeout(struct ishtp_device * dev,int condition,unsigned int timeinc,unsigned int timeout)451 static int timed_wait_for_timeout(struct ishtp_device *dev, int condition,
452 unsigned int timeinc, unsigned int timeout)
453 {
454 bool complete = false;
455 int ret;
456
457 do {
458 if (condition == WAIT_FOR_FW_RDY) {
459 complete = ishtp_fw_is_ready(dev);
460 } else if (condition == WAIT_FOR_INPUT_RDY) {
461 complete = ish_is_input_ready(dev);
462 } else {
463 ret = -EINVAL;
464 goto out;
465 }
466
467 if (!complete) {
468 unsigned long left_time;
469
470 left_time = msleep_interruptible(timeinc);
471 timeout -= (timeinc - left_time);
472 }
473 } while (!complete && timeout > 0);
474
475 if (complete)
476 ret = 0;
477 else
478 ret = -EBUSY;
479
480 out:
481 return ret;
482 }
483
484 #define TIME_SLICE_FOR_FW_RDY_MS 100
485 #define TIME_SLICE_FOR_INPUT_RDY_MS 100
486 #define TIMEOUT_FOR_FW_RDY_MS 2000
487 #define TIMEOUT_FOR_INPUT_RDY_MS 2000
488
489 /**
490 * ish_fw_reset_handler() - FW reset handler
491 * @dev: ishtp device pointer
492 *
493 * Handle FW reset
494 *
495 * Return: 0 for success else failure code
496 */
ish_fw_reset_handler(struct ishtp_device * dev)497 static int ish_fw_reset_handler(struct ishtp_device *dev)
498 {
499 uint32_t reset_id;
500 unsigned long flags;
501
502 /* Read reset ID */
503 reset_id = ish_reg_read(dev, IPC_REG_ISH2HOST_MSG) & 0xFFFF;
504
505 /* Clear IPC output queue */
506 spin_lock_irqsave(&dev->wr_processing_spinlock, flags);
507 list_splice_init(&dev->wr_processing_list, &dev->wr_free_list);
508 spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags);
509
510 /* ISHTP notification in IPC_RESET */
511 ishtp_reset_handler(dev);
512
513 if (!ish_is_input_ready(dev))
514 timed_wait_for_timeout(dev, WAIT_FOR_INPUT_RDY,
515 TIME_SLICE_FOR_INPUT_RDY_MS, TIMEOUT_FOR_INPUT_RDY_MS);
516
517 /* ISH FW is dead */
518 if (!ish_is_input_ready(dev))
519 return -EPIPE;
520 /*
521 * Set HOST2ISH.ILUP. Apparently we need this BEFORE sending
522 * RESET_NOTIFY_ACK - FW will be checking for it
523 */
524 ish_set_host_rdy(dev);
525 /* Send RESET_NOTIFY_ACK (with reset_id) */
526 ipc_send_mng_msg(dev, MNG_RESET_NOTIFY_ACK, &reset_id,
527 sizeof(uint32_t));
528
529 /* Wait for ISH FW'es ILUP and ISHTP_READY */
530 timed_wait_for_timeout(dev, WAIT_FOR_FW_RDY,
531 TIME_SLICE_FOR_FW_RDY_MS, TIMEOUT_FOR_FW_RDY_MS);
532 if (!ishtp_fw_is_ready(dev)) {
533 /* ISH FW is dead */
534 uint32_t ish_status;
535
536 ish_status = _ish_read_fw_sts_reg(dev);
537 dev_err(dev->devc,
538 "[ishtp-ish]: completed reset, ISH is dead (FWSTS = %08X)\n",
539 ish_status);
540 return -ENODEV;
541 }
542 return 0;
543 }
544
545 #define TIMEOUT_FOR_HW_RDY_MS 300
546
547 /**
548 * fw_reset_work_fn() - FW reset worker function
549 * @unused: not used
550 *
551 * Call ish_fw_reset_handler to complete FW reset
552 */
fw_reset_work_fn(struct work_struct * unused)553 static void fw_reset_work_fn(struct work_struct *unused)
554 {
555 int rv;
556
557 rv = ish_fw_reset_handler(ishtp_dev);
558 if (!rv) {
559 /* ISH is ILUP & ISHTP-ready. Restart ISHTP */
560 msleep_interruptible(TIMEOUT_FOR_HW_RDY_MS);
561 ishtp_dev->recvd_hw_ready = 1;
562 wake_up_interruptible(&ishtp_dev->wait_hw_ready);
563
564 /* ISHTP notification in IPC_RESET sequence completion */
565 ishtp_reset_compl_handler(ishtp_dev);
566 } else
567 dev_err(ishtp_dev->devc, "[ishtp-ish]: FW reset failed (%d)\n",
568 rv);
569 }
570
571 /**
572 * _ish_sync_fw_clock() -Sync FW clock with the OS clock
573 * @dev: ishtp device pointer
574 *
575 * Sync FW and OS time
576 */
_ish_sync_fw_clock(struct ishtp_device * dev)577 static void _ish_sync_fw_clock(struct ishtp_device *dev)
578 {
579 static unsigned long prev_sync;
580 uint64_t usec;
581
582 if (prev_sync && time_before(jiffies, prev_sync + 20 * HZ))
583 return;
584
585 prev_sync = jiffies;
586 usec = ktime_to_us(ktime_get_boottime());
587 ipc_send_mng_msg(dev, MNG_SYNC_FW_CLOCK, &usec, sizeof(uint64_t));
588 }
589
590 /**
591 * recv_ipc() - Receive and process IPC management messages
592 * @dev: ishtp device instance
593 * @doorbell_val: doorbell value
594 *
595 * This function runs in ISR context.
596 * NOTE: Any other mng command than reset_notify and reset_notify_ack
597 * won't wake BH handler
598 */
recv_ipc(struct ishtp_device * dev,uint32_t doorbell_val)599 static void recv_ipc(struct ishtp_device *dev, uint32_t doorbell_val)
600 {
601 uint32_t mng_cmd;
602
603 mng_cmd = IPC_HEADER_GET_MNG_CMD(doorbell_val);
604
605 switch (mng_cmd) {
606 default:
607 break;
608
609 case MNG_RX_CMPL_INDICATION:
610 if (dev->suspend_flag) {
611 dev->suspend_flag = 0;
612 wake_up_interruptible(&dev->suspend_wait);
613 }
614 if (dev->resume_flag) {
615 dev->resume_flag = 0;
616 wake_up_interruptible(&dev->resume_wait);
617 }
618
619 write_ipc_from_queue(dev);
620 break;
621
622 case MNG_RESET_NOTIFY:
623 if (!ishtp_dev) {
624 ishtp_dev = dev;
625 }
626 schedule_work(&fw_reset_work);
627 break;
628
629 case MNG_RESET_NOTIFY_ACK:
630 dev->recvd_hw_ready = 1;
631 wake_up_interruptible(&dev->wait_hw_ready);
632 break;
633 }
634 }
635
636 /**
637 * ish_irq_handler() - ISH IRQ handler
638 * @irq: irq number
639 * @dev_id: ishtp device pointer
640 *
641 * ISH IRQ handler. If interrupt is generated and is for ISH it will process
642 * the interrupt.
643 */
ish_irq_handler(int irq,void * dev_id)644 irqreturn_t ish_irq_handler(int irq, void *dev_id)
645 {
646 struct ishtp_device *dev = dev_id;
647 uint32_t doorbell_val;
648 bool interrupt_generated;
649
650 /* Check that it's interrupt from ISH (may be shared) */
651 interrupt_generated = check_generated_interrupt(dev);
652
653 if (!interrupt_generated)
654 return IRQ_NONE;
655
656 doorbell_val = ish_reg_read(dev, IPC_REG_ISH2HOST_DRBL);
657 if (!IPC_IS_BUSY(doorbell_val))
658 return IRQ_HANDLED;
659
660 if (dev->dev_state == ISHTP_DEV_DISABLED)
661 return IRQ_HANDLED;
662
663 /* Sanity check: IPC dgram length in header */
664 if (IPC_HEADER_GET_LENGTH(doorbell_val) > IPC_PAYLOAD_SIZE) {
665 dev_err(dev->devc,
666 "IPC hdr - bad length: %u; dropped\n",
667 (unsigned int)IPC_HEADER_GET_LENGTH(doorbell_val));
668 goto eoi;
669 }
670
671 switch (IPC_HEADER_GET_PROTOCOL(doorbell_val)) {
672 default:
673 break;
674 case IPC_PROTOCOL_MNG:
675 recv_ipc(dev, doorbell_val);
676 break;
677 case IPC_PROTOCOL_ISHTP:
678 ishtp_recv(dev);
679 break;
680 }
681
682 eoi:
683 /* Update IPC counters */
684 ++dev->ipc_rx_cnt;
685 dev->ipc_rx_bytes_cnt += IPC_HEADER_GET_LENGTH(doorbell_val);
686
687 ish_reg_write(dev, IPC_REG_ISH2HOST_DRBL, 0);
688 /* Flush write to doorbell */
689 ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS);
690
691 return IRQ_HANDLED;
692 }
693
694 /**
695 * ish_disable_dma() - disable dma communication between host and ISHFW
696 * @dev: ishtp device pointer
697 *
698 * Clear the dma enable bit and wait for dma inactive.
699 *
700 * Return: 0 for success else error code.
701 */
ish_disable_dma(struct ishtp_device * dev)702 int ish_disable_dma(struct ishtp_device *dev)
703 {
704 unsigned int dma_delay;
705
706 /* Clear the dma enable bit */
707 ish_reg_write(dev, IPC_REG_ISH_RMP2, 0);
708
709 /* wait for dma inactive */
710 for (dma_delay = 0; dma_delay < MAX_DMA_DELAY &&
711 _ish_read_fw_sts_reg(dev) & (IPC_ISH_IN_DMA);
712 dma_delay += 5)
713 mdelay(5);
714
715 if (dma_delay >= MAX_DMA_DELAY) {
716 dev_err(dev->devc,
717 "Wait for DMA inactive timeout\n");
718 return -EBUSY;
719 }
720
721 return 0;
722 }
723
724 /**
725 * ish_wakeup() - wakeup ishfw from waiting-for-host state
726 * @dev: ishtp device pointer
727 *
728 * Set the dma enable bit and send a void message to FW,
729 * it wil wakeup FW from waiting-for-host state.
730 */
ish_wakeup(struct ishtp_device * dev)731 static void ish_wakeup(struct ishtp_device *dev)
732 {
733 /* Set dma enable bit */
734 ish_reg_write(dev, IPC_REG_ISH_RMP2, IPC_RMP2_DMA_ENABLED);
735
736 /*
737 * Send 0 IPC message so that ISH FW wakes up if it was already
738 * asleep.
739 */
740 ish_reg_write(dev, IPC_REG_HOST2ISH_DRBL, IPC_DRBL_BUSY_BIT);
741
742 /* Flush writes to doorbell and REMAP2 */
743 ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS);
744 }
745
746 /**
747 * _ish_hw_reset() - HW reset
748 * @dev: ishtp device pointer
749 *
750 * Reset ISH HW to recover if any error
751 *
752 * Return: 0 for success else error fault code
753 */
_ish_hw_reset(struct ishtp_device * dev)754 static int _ish_hw_reset(struct ishtp_device *dev)
755 {
756 struct pci_dev *pdev = dev->pdev;
757 int rv;
758 uint16_t csr;
759
760 if (!pdev)
761 return -ENODEV;
762
763 rv = pci_reset_function(pdev);
764 if (!rv)
765 dev->dev_state = ISHTP_DEV_RESETTING;
766
767 if (!pdev->pm_cap) {
768 dev_err(&pdev->dev, "Can't reset - no PM caps\n");
769 return -EINVAL;
770 }
771
772 /* Disable dma communication between FW and host */
773 if (ish_disable_dma(dev)) {
774 dev_err(&pdev->dev,
775 "Can't reset - stuck with DMA in-progress\n");
776 return -EBUSY;
777 }
778
779 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &csr);
780
781 csr &= ~PCI_PM_CTRL_STATE_MASK;
782 csr |= PCI_D3hot;
783 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, csr);
784
785 mdelay(pdev->d3hot_delay);
786
787 csr &= ~PCI_PM_CTRL_STATE_MASK;
788 csr |= PCI_D0;
789 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, csr);
790
791 /* Now we can enable ISH DMA operation and wakeup ISHFW */
792 ish_wakeup(dev);
793
794 return 0;
795 }
796
797 /**
798 * _ish_ipc_reset() - IPC reset
799 * @dev: ishtp device pointer
800 *
801 * Resets host and fw IPC and upper layers
802 *
803 * Return: 0 for success else error fault code
804 */
_ish_ipc_reset(struct ishtp_device * dev)805 static int _ish_ipc_reset(struct ishtp_device *dev)
806 {
807 struct ipc_rst_payload_type ipc_mng_msg;
808 int rv = 0;
809
810 ipc_mng_msg.reset_id = 1;
811 ipc_mng_msg.reserved = 0;
812
813 set_host_ready(dev);
814
815 /* Clear the incoming doorbell */
816 ish_reg_write(dev, IPC_REG_ISH2HOST_DRBL, 0);
817 /* Flush write to doorbell */
818 ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS);
819
820 dev->recvd_hw_ready = 0;
821
822 /* send message */
823 rv = ipc_send_mng_msg(dev, MNG_RESET_NOTIFY, &ipc_mng_msg,
824 sizeof(struct ipc_rst_payload_type));
825 if (rv) {
826 dev_err(dev->devc, "Failed to send IPC MNG_RESET_NOTIFY\n");
827 return rv;
828 }
829
830 wait_event_interruptible_timeout(dev->wait_hw_ready,
831 dev->recvd_hw_ready, 2 * HZ);
832 if (!dev->recvd_hw_ready) {
833 dev_err(dev->devc, "Timed out waiting for HW ready\n");
834 rv = -ENODEV;
835 }
836
837 return rv;
838 }
839
840 /**
841 * ish_hw_start() -Start ISH HW
842 * @dev: ishtp device pointer
843 *
844 * Set host to ready state and wait for FW reset
845 *
846 * Return: 0 for success else error fault code
847 */
ish_hw_start(struct ishtp_device * dev)848 int ish_hw_start(struct ishtp_device *dev)
849 {
850 ish_set_host_rdy(dev);
851
852 set_host_ready(dev);
853
854 /* After that we can enable ISH DMA operation and wakeup ISHFW */
855 ish_wakeup(dev);
856
857 /* wait for FW-initiated reset flow */
858 if (!dev->recvd_hw_ready)
859 wait_event_interruptible_timeout(dev->wait_hw_ready,
860 dev->recvd_hw_ready,
861 10 * HZ);
862
863 if (!dev->recvd_hw_ready) {
864 dev_err(dev->devc,
865 "[ishtp-ish]: Timed out waiting for FW-initiated reset\n");
866 return -ENODEV;
867 }
868
869 return 0;
870 }
871
872 /**
873 * ish_ipc_get_header() -Get doorbell value
874 * @dev: ishtp device pointer
875 * @length: length of message
876 * @busy: busy status
877 *
878 * Get door bell value from message header
879 *
880 * Return: door bell value
881 */
ish_ipc_get_header(struct ishtp_device * dev,int length,int busy)882 static uint32_t ish_ipc_get_header(struct ishtp_device *dev, int length,
883 int busy)
884 {
885 uint32_t drbl_val;
886
887 drbl_val = IPC_BUILD_HEADER(length, IPC_PROTOCOL_ISHTP, busy);
888
889 return drbl_val;
890 }
891
892 /**
893 * _dma_no_cache_snooping()
894 *
895 * Check on current platform, DMA supports cache snooping or not.
896 * This callback is used to notify uplayer driver if manully cache
897 * flush is needed when do DMA operation.
898 *
899 * Please pay attention to this callback implementation, if declare
900 * having cache snooping on a cache snooping not supported platform
901 * will cause uplayer driver receiving mismatched data; and if
902 * declare no cache snooping on a cache snooping supported platform
903 * will cause cache be flushed twice and performance hit.
904 *
905 * @dev: ishtp device pointer
906 *
907 * Return: false - has cache snooping capability
908 * true - no cache snooping, need manually cache flush
909 */
_dma_no_cache_snooping(struct ishtp_device * dev)910 static bool _dma_no_cache_snooping(struct ishtp_device *dev)
911 {
912 return (dev->pdev->device == EHL_Ax_DEVICE_ID ||
913 dev->pdev->device == TGL_LP_DEVICE_ID ||
914 dev->pdev->device == TGL_H_DEVICE_ID ||
915 dev->pdev->device == ADL_S_DEVICE_ID ||
916 dev->pdev->device == ADL_P_DEVICE_ID);
917 }
918
919 static const struct ishtp_hw_ops ish_hw_ops = {
920 .hw_reset = _ish_hw_reset,
921 .ipc_reset = _ish_ipc_reset,
922 .ipc_get_header = ish_ipc_get_header,
923 .ishtp_read = _ishtp_read,
924 .write = write_ipc_to_queue,
925 .get_fw_status = _ish_read_fw_sts_reg,
926 .sync_fw_clock = _ish_sync_fw_clock,
927 .ishtp_read_hdr = _ishtp_read_hdr,
928 .dma_no_cache_snooping = _dma_no_cache_snooping
929 };
930
931 /**
932 * ish_dev_init() -Initialize ISH devoce
933 * @pdev: PCI device
934 *
935 * Allocate ISHTP device and initialize IPC processing
936 *
937 * Return: ISHTP device instance on success else NULL
938 */
ish_dev_init(struct pci_dev * pdev)939 struct ishtp_device *ish_dev_init(struct pci_dev *pdev)
940 {
941 struct ishtp_device *dev;
942 int i;
943 int ret;
944
945 dev = devm_kzalloc(&pdev->dev,
946 sizeof(struct ishtp_device) + sizeof(struct ish_hw),
947 GFP_KERNEL);
948 if (!dev)
949 return NULL;
950
951 ishtp_device_init(dev);
952
953 init_waitqueue_head(&dev->wait_hw_ready);
954
955 spin_lock_init(&dev->wr_processing_spinlock);
956
957 /* Init IPC processing and free lists */
958 INIT_LIST_HEAD(&dev->wr_processing_list);
959 INIT_LIST_HEAD(&dev->wr_free_list);
960 for (i = 0; i < IPC_TX_FIFO_SIZE; i++) {
961 struct wr_msg_ctl_info *tx_buf;
962
963 tx_buf = devm_kzalloc(&pdev->dev,
964 sizeof(struct wr_msg_ctl_info),
965 GFP_KERNEL);
966 if (!tx_buf) {
967 /*
968 * IPC buffers may be limited or not available
969 * at all - although this shouldn't happen
970 */
971 dev_err(dev->devc,
972 "[ishtp-ish]: failure in Tx FIFO allocations (%d)\n",
973 i);
974 break;
975 }
976 list_add_tail(&tx_buf->link, &dev->wr_free_list);
977 }
978
979 ret = devm_work_autocancel(&pdev->dev, &fw_reset_work, fw_reset_work_fn);
980 if (ret) {
981 dev_err(dev->devc, "Failed to initialise FW reset work\n");
982 return NULL;
983 }
984
985 dev->ops = &ish_hw_ops;
986 dev->devc = &pdev->dev;
987 dev->mtu = IPC_PAYLOAD_SIZE - sizeof(struct ishtp_msg_hdr);
988 return dev;
989 }
990
991 /**
992 * ish_device_disable() - Disable ISH device
993 * @dev: ISHTP device pointer
994 *
995 * Disable ISH by clearing host ready to inform firmware.
996 */
ish_device_disable(struct ishtp_device * dev)997 void ish_device_disable(struct ishtp_device *dev)
998 {
999 struct pci_dev *pdev = dev->pdev;
1000
1001 if (!pdev)
1002 return;
1003
1004 /* Disable dma communication between FW and host */
1005 if (ish_disable_dma(dev)) {
1006 dev_err(&pdev->dev,
1007 "Can't reset - stuck with DMA in-progress\n");
1008 return;
1009 }
1010
1011 /* Put ISH to D3hot state for power saving */
1012 pci_set_power_state(pdev, PCI_D3hot);
1013
1014 dev->dev_state = ISHTP_DEV_DISABLED;
1015 ish_clr_host_rdy(dev);
1016 }
1017
