1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Microchip Image Sensor Controller (ISC) common driver base
4 *
5 * Copyright (C) 2016-2019 Microchip Technology, Inc.
6 *
7 * Author: Songjun Wu
8 * Author: Eugen Hristev <eugen.hristev@microchip.com>
9 *
10 */
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/math64.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_graph.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regmap.h>
20 #include <linux/videodev2.h>
21 #include <linux/atmel-isc-media.h>
22
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-event.h>
26 #include <media/v4l2-image-sizes.h>
27 #include <media/v4l2-ioctl.h>
28 #include <media/v4l2-fwnode.h>
29 #include <media/v4l2-subdev.h>
30 #include <media/videobuf2-dma-contig.h>
31
32 #include "atmel-isc-regs.h"
33 #include "atmel-isc.h"
34
35 static unsigned int debug;
36 module_param(debug, int, 0644);
37 MODULE_PARM_DESC(debug, "debug level (0-2)");
38
39 static unsigned int sensor_preferred = 1;
40 module_param(sensor_preferred, uint, 0644);
41 MODULE_PARM_DESC(sensor_preferred,
42 "Sensor is preferred to output the specified format (1-on 0-off), default 1");
43
44 #define ISC_IS_FORMAT_RAW(mbus_code) \
45 (((mbus_code) & 0xf000) == 0x3000)
46
47 #define ISC_IS_FORMAT_GREY(mbus_code) \
48 (((mbus_code) == MEDIA_BUS_FMT_Y10_1X10) | \
49 (((mbus_code) == MEDIA_BUS_FMT_Y8_1X8)))
50
isc_update_v4l2_ctrls(struct isc_device * isc)51 static inline void isc_update_v4l2_ctrls(struct isc_device *isc)
52 {
53 struct isc_ctrls *ctrls = &isc->ctrls;
54
55 /* In here we set the v4l2 controls w.r.t. our pipeline config */
56 v4l2_ctrl_s_ctrl(isc->r_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_R]);
57 v4l2_ctrl_s_ctrl(isc->b_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_B]);
58 v4l2_ctrl_s_ctrl(isc->gr_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GR]);
59 v4l2_ctrl_s_ctrl(isc->gb_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GB]);
60
61 v4l2_ctrl_s_ctrl(isc->r_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_R]);
62 v4l2_ctrl_s_ctrl(isc->b_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_B]);
63 v4l2_ctrl_s_ctrl(isc->gr_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GR]);
64 v4l2_ctrl_s_ctrl(isc->gb_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GB]);
65 }
66
isc_update_awb_ctrls(struct isc_device * isc)67 static inline void isc_update_awb_ctrls(struct isc_device *isc)
68 {
69 struct isc_ctrls *ctrls = &isc->ctrls;
70
71 /* In here we set our actual hw pipeline config */
72
73 regmap_write(isc->regmap, ISC_WB_O_RGR,
74 ((ctrls->offset[ISC_HIS_CFG_MODE_R])) |
75 ((ctrls->offset[ISC_HIS_CFG_MODE_GR]) << 16));
76 regmap_write(isc->regmap, ISC_WB_O_BGB,
77 ((ctrls->offset[ISC_HIS_CFG_MODE_B])) |
78 ((ctrls->offset[ISC_HIS_CFG_MODE_GB]) << 16));
79 regmap_write(isc->regmap, ISC_WB_G_RGR,
80 ctrls->gain[ISC_HIS_CFG_MODE_R] |
81 (ctrls->gain[ISC_HIS_CFG_MODE_GR] << 16));
82 regmap_write(isc->regmap, ISC_WB_G_BGB,
83 ctrls->gain[ISC_HIS_CFG_MODE_B] |
84 (ctrls->gain[ISC_HIS_CFG_MODE_GB] << 16));
85 }
86
isc_reset_awb_ctrls(struct isc_device * isc)87 static inline void isc_reset_awb_ctrls(struct isc_device *isc)
88 {
89 unsigned int c;
90
91 for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) {
92 /* gains have a fixed point at 9 decimals */
93 isc->ctrls.gain[c] = 1 << 9;
94 /* offsets are in 2's complements */
95 isc->ctrls.offset[c] = 0;
96 }
97 }
98
99
isc_queue_setup(struct vb2_queue * vq,unsigned int * nbuffers,unsigned int * nplanes,unsigned int sizes[],struct device * alloc_devs[])100 static int isc_queue_setup(struct vb2_queue *vq,
101 unsigned int *nbuffers, unsigned int *nplanes,
102 unsigned int sizes[], struct device *alloc_devs[])
103 {
104 struct isc_device *isc = vb2_get_drv_priv(vq);
105 unsigned int size = isc->fmt.fmt.pix.sizeimage;
106
107 if (*nplanes)
108 return sizes[0] < size ? -EINVAL : 0;
109
110 *nplanes = 1;
111 sizes[0] = size;
112
113 return 0;
114 }
115
isc_buffer_prepare(struct vb2_buffer * vb)116 static int isc_buffer_prepare(struct vb2_buffer *vb)
117 {
118 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
119 struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
120 unsigned long size = isc->fmt.fmt.pix.sizeimage;
121
122 if (vb2_plane_size(vb, 0) < size) {
123 v4l2_err(&isc->v4l2_dev, "buffer too small (%lu < %lu)\n",
124 vb2_plane_size(vb, 0), size);
125 return -EINVAL;
126 }
127
128 vb2_set_plane_payload(vb, 0, size);
129
130 vbuf->field = isc->fmt.fmt.pix.field;
131
132 return 0;
133 }
134
isc_crop_pfe(struct isc_device * isc)135 static void isc_crop_pfe(struct isc_device *isc)
136 {
137 struct regmap *regmap = isc->regmap;
138 u32 h, w;
139
140 h = isc->fmt.fmt.pix.height;
141 w = isc->fmt.fmt.pix.width;
142
143 /*
144 * In case the sensor is not RAW, it will output a pixel (12-16 bits)
145 * with two samples on the ISC Data bus (which is 8-12)
146 * ISC will count each sample, so, we need to multiply these values
147 * by two, to get the real number of samples for the required pixels.
148 */
149 if (!ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) {
150 h <<= 1;
151 w <<= 1;
152 }
153
154 /*
155 * We limit the column/row count that the ISC will output according
156 * to the configured resolution that we want.
157 * This will avoid the situation where the sensor is misconfigured,
158 * sending more data, and the ISC will just take it and DMA to memory,
159 * causing corruption.
160 */
161 regmap_write(regmap, ISC_PFE_CFG1,
162 (ISC_PFE_CFG1_COLMIN(0) & ISC_PFE_CFG1_COLMIN_MASK) |
163 (ISC_PFE_CFG1_COLMAX(w - 1) & ISC_PFE_CFG1_COLMAX_MASK));
164
165 regmap_write(regmap, ISC_PFE_CFG2,
166 (ISC_PFE_CFG2_ROWMIN(0) & ISC_PFE_CFG2_ROWMIN_MASK) |
167 (ISC_PFE_CFG2_ROWMAX(h - 1) & ISC_PFE_CFG2_ROWMAX_MASK));
168
169 regmap_update_bits(regmap, ISC_PFE_CFG0,
170 ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN,
171 ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN);
172 }
173
isc_start_dma(struct isc_device * isc)174 static void isc_start_dma(struct isc_device *isc)
175 {
176 struct regmap *regmap = isc->regmap;
177 u32 sizeimage = isc->fmt.fmt.pix.sizeimage;
178 u32 dctrl_dview;
179 dma_addr_t addr0;
180
181 addr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0);
182 regmap_write(regmap, ISC_DAD0 + isc->offsets.dma, addr0);
183
184 switch (isc->config.fourcc) {
185 case V4L2_PIX_FMT_YUV420:
186 regmap_write(regmap, ISC_DAD1 + isc->offsets.dma,
187 addr0 + (sizeimage * 2) / 3);
188 regmap_write(regmap, ISC_DAD2 + isc->offsets.dma,
189 addr0 + (sizeimage * 5) / 6);
190 break;
191 case V4L2_PIX_FMT_YUV422P:
192 regmap_write(regmap, ISC_DAD1 + isc->offsets.dma,
193 addr0 + sizeimage / 2);
194 regmap_write(regmap, ISC_DAD2 + isc->offsets.dma,
195 addr0 + (sizeimage * 3) / 4);
196 break;
197 default:
198 break;
199 }
200
201 dctrl_dview = isc->config.dctrl_dview;
202
203 regmap_write(regmap, ISC_DCTRL + isc->offsets.dma,
204 dctrl_dview | ISC_DCTRL_IE_IS);
205 spin_lock(&isc->awb_lock);
206 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE);
207 spin_unlock(&isc->awb_lock);
208 }
209
isc_set_pipeline(struct isc_device * isc,u32 pipeline)210 static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)
211 {
212 struct regmap *regmap = isc->regmap;
213 struct isc_ctrls *ctrls = &isc->ctrls;
214 u32 val, bay_cfg;
215 const u32 *gamma;
216 unsigned int i;
217
218 /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */
219 for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
220 val = pipeline & BIT(i) ? 1 : 0;
221 regmap_field_write(isc->pipeline[i], val);
222 }
223
224 if (!pipeline)
225 return;
226
227 bay_cfg = isc->config.sd_format->cfa_baycfg;
228
229 regmap_write(regmap, ISC_WB_CFG, bay_cfg);
230 isc_update_awb_ctrls(isc);
231 isc_update_v4l2_ctrls(isc);
232
233 regmap_write(regmap, ISC_CFA_CFG, bay_cfg | ISC_CFA_CFG_EITPOL);
234
235 gamma = &isc->gamma_table[ctrls->gamma_index][0];
236 regmap_bulk_write(regmap, ISC_GAM_BENTRY, gamma, GAMMA_ENTRIES);
237 regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES);
238 regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES);
239
240 isc->config_dpc(isc);
241 isc->config_csc(isc);
242 isc->config_cbc(isc);
243 isc->config_cc(isc);
244 isc->config_gam(isc);
245 }
246
isc_update_profile(struct isc_device * isc)247 static int isc_update_profile(struct isc_device *isc)
248 {
249 struct regmap *regmap = isc->regmap;
250 u32 sr;
251 int counter = 100;
252
253 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_UPPRO);
254
255 regmap_read(regmap, ISC_CTRLSR, &sr);
256 while ((sr & ISC_CTRL_UPPRO) && counter--) {
257 usleep_range(1000, 2000);
258 regmap_read(regmap, ISC_CTRLSR, &sr);
259 }
260
261 if (counter < 0) {
262 v4l2_warn(&isc->v4l2_dev, "Time out to update profile\n");
263 return -ETIMEDOUT;
264 }
265
266 return 0;
267 }
268
isc_set_histogram(struct isc_device * isc,bool enable)269 static void isc_set_histogram(struct isc_device *isc, bool enable)
270 {
271 struct regmap *regmap = isc->regmap;
272 struct isc_ctrls *ctrls = &isc->ctrls;
273
274 if (enable) {
275 regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his,
276 ISC_HIS_CFG_MODE_GR |
277 (isc->config.sd_format->cfa_baycfg
278 << ISC_HIS_CFG_BAYSEL_SHIFT) |
279 ISC_HIS_CFG_RAR);
280 regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his,
281 ISC_HIS_CTRL_EN);
282 regmap_write(regmap, ISC_INTEN, ISC_INT_HISDONE);
283 ctrls->hist_id = ISC_HIS_CFG_MODE_GR;
284 isc_update_profile(isc);
285 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ);
286
287 ctrls->hist_stat = HIST_ENABLED;
288 } else {
289 regmap_write(regmap, ISC_INTDIS, ISC_INT_HISDONE);
290 regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his,
291 ISC_HIS_CTRL_DIS);
292
293 ctrls->hist_stat = HIST_DISABLED;
294 }
295 }
296
isc_configure(struct isc_device * isc)297 static int isc_configure(struct isc_device *isc)
298 {
299 struct regmap *regmap = isc->regmap;
300 u32 pfe_cfg0, dcfg, mask, pipeline;
301 struct isc_subdev_entity *subdev = isc->current_subdev;
302
303 pfe_cfg0 = isc->config.sd_format->pfe_cfg0_bps;
304 pipeline = isc->config.bits_pipeline;
305
306 dcfg = isc->config.dcfg_imode | isc->dcfg;
307
308 pfe_cfg0 |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE;
309 mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW |
310 ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW |
311 ISC_PFE_CFG0_MODE_MASK | ISC_PFE_CFG0_CCIR_CRC |
312 ISC_PFE_CFG0_CCIR656 | ISC_PFE_CFG0_MIPI;
313
314 regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0);
315
316 isc->config_rlp(isc);
317
318 regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg);
319
320 /* Set the pipeline */
321 isc_set_pipeline(isc, pipeline);
322
323 /*
324 * The current implemented histogram is available for RAW R, B, GB, GR
325 * channels. We need to check if sensor is outputting RAW BAYER
326 */
327 if (isc->ctrls.awb &&
328 ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
329 isc_set_histogram(isc, true);
330 else
331 isc_set_histogram(isc, false);
332
333 /* Update profile */
334 return isc_update_profile(isc);
335 }
336
isc_start_streaming(struct vb2_queue * vq,unsigned int count)337 static int isc_start_streaming(struct vb2_queue *vq, unsigned int count)
338 {
339 struct isc_device *isc = vb2_get_drv_priv(vq);
340 struct regmap *regmap = isc->regmap;
341 struct isc_buffer *buf;
342 unsigned long flags;
343 int ret;
344
345 /* Enable stream on the sub device */
346 ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 1);
347 if (ret && ret != -ENOIOCTLCMD) {
348 v4l2_err(&isc->v4l2_dev, "stream on failed in subdev %d\n",
349 ret);
350 goto err_start_stream;
351 }
352
353 ret = pm_runtime_resume_and_get(isc->dev);
354 if (ret < 0) {
355 v4l2_err(&isc->v4l2_dev, "RPM resume failed in subdev %d\n",
356 ret);
357 goto err_pm_get;
358 }
359
360 ret = isc_configure(isc);
361 if (unlikely(ret))
362 goto err_configure;
363
364 /* Enable DMA interrupt */
365 regmap_write(regmap, ISC_INTEN, ISC_INT_DDONE);
366
367 spin_lock_irqsave(&isc->dma_queue_lock, flags);
368
369 isc->sequence = 0;
370 isc->stop = false;
371 reinit_completion(&isc->comp);
372
373 isc->cur_frm = list_first_entry(&isc->dma_queue,
374 struct isc_buffer, list);
375 list_del(&isc->cur_frm->list);
376
377 isc_crop_pfe(isc);
378 isc_start_dma(isc);
379
380 spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
381
382 /* if we streaming from RAW, we can do one-shot white balance adj */
383 if (ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
384 v4l2_ctrl_activate(isc->do_wb_ctrl, true);
385
386 return 0;
387
388 err_configure:
389 pm_runtime_put_sync(isc->dev);
390 err_pm_get:
391 v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
392
393 err_start_stream:
394 spin_lock_irqsave(&isc->dma_queue_lock, flags);
395 list_for_each_entry(buf, &isc->dma_queue, list)
396 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
397 INIT_LIST_HEAD(&isc->dma_queue);
398 spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
399
400 return ret;
401 }
402
isc_stop_streaming(struct vb2_queue * vq)403 static void isc_stop_streaming(struct vb2_queue *vq)
404 {
405 struct isc_device *isc = vb2_get_drv_priv(vq);
406 unsigned long flags;
407 struct isc_buffer *buf;
408 int ret;
409
410 mutex_lock(&isc->awb_mutex);
411 v4l2_ctrl_activate(isc->do_wb_ctrl, false);
412
413 isc->stop = true;
414
415 /* Wait until the end of the current frame */
416 if (isc->cur_frm && !wait_for_completion_timeout(&isc->comp, 5 * HZ))
417 v4l2_err(&isc->v4l2_dev,
418 "Timeout waiting for end of the capture\n");
419
420 mutex_unlock(&isc->awb_mutex);
421
422 /* Disable DMA interrupt */
423 regmap_write(isc->regmap, ISC_INTDIS, ISC_INT_DDONE);
424
425 pm_runtime_put_sync(isc->dev);
426
427 /* Disable stream on the sub device */
428 ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
429 if (ret && ret != -ENOIOCTLCMD)
430 v4l2_err(&isc->v4l2_dev, "stream off failed in subdev\n");
431
432 /* Release all active buffers */
433 spin_lock_irqsave(&isc->dma_queue_lock, flags);
434 if (unlikely(isc->cur_frm)) {
435 vb2_buffer_done(&isc->cur_frm->vb.vb2_buf,
436 VB2_BUF_STATE_ERROR);
437 isc->cur_frm = NULL;
438 }
439 list_for_each_entry(buf, &isc->dma_queue, list)
440 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
441 INIT_LIST_HEAD(&isc->dma_queue);
442 spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
443 }
444
isc_buffer_queue(struct vb2_buffer * vb)445 static void isc_buffer_queue(struct vb2_buffer *vb)
446 {
447 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
448 struct isc_buffer *buf = container_of(vbuf, struct isc_buffer, vb);
449 struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
450 unsigned long flags;
451
452 spin_lock_irqsave(&isc->dma_queue_lock, flags);
453 if (!isc->cur_frm && list_empty(&isc->dma_queue) &&
454 vb2_start_streaming_called(vb->vb2_queue)) {
455 isc->cur_frm = buf;
456 isc_start_dma(isc);
457 } else
458 list_add_tail(&buf->list, &isc->dma_queue);
459 spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
460 }
461
find_format_by_fourcc(struct isc_device * isc,unsigned int fourcc)462 static struct isc_format *find_format_by_fourcc(struct isc_device *isc,
463 unsigned int fourcc)
464 {
465 unsigned int num_formats = isc->num_user_formats;
466 struct isc_format *fmt;
467 unsigned int i;
468
469 for (i = 0; i < num_formats; i++) {
470 fmt = isc->user_formats[i];
471 if (fmt->fourcc == fourcc)
472 return fmt;
473 }
474
475 return NULL;
476 }
477
478 static const struct vb2_ops isc_vb2_ops = {
479 .queue_setup = isc_queue_setup,
480 .wait_prepare = vb2_ops_wait_prepare,
481 .wait_finish = vb2_ops_wait_finish,
482 .buf_prepare = isc_buffer_prepare,
483 .start_streaming = isc_start_streaming,
484 .stop_streaming = isc_stop_streaming,
485 .buf_queue = isc_buffer_queue,
486 };
487
isc_querycap(struct file * file,void * priv,struct v4l2_capability * cap)488 static int isc_querycap(struct file *file, void *priv,
489 struct v4l2_capability *cap)
490 {
491 struct isc_device *isc = video_drvdata(file);
492
493 strscpy(cap->driver, "microchip-isc", sizeof(cap->driver));
494 strscpy(cap->card, "Atmel Image Sensor Controller", sizeof(cap->card));
495 snprintf(cap->bus_info, sizeof(cap->bus_info),
496 "platform:%s", isc->v4l2_dev.name);
497
498 return 0;
499 }
500
isc_enum_fmt_vid_cap(struct file * file,void * priv,struct v4l2_fmtdesc * f)501 static int isc_enum_fmt_vid_cap(struct file *file, void *priv,
502 struct v4l2_fmtdesc *f)
503 {
504 struct isc_device *isc = video_drvdata(file);
505 u32 index = f->index;
506 u32 i, supported_index;
507
508 if (index < isc->controller_formats_size) {
509 f->pixelformat = isc->controller_formats[index].fourcc;
510 return 0;
511 }
512
513 index -= isc->controller_formats_size;
514
515 supported_index = 0;
516
517 for (i = 0; i < isc->formats_list_size; i++) {
518 if (!ISC_IS_FORMAT_RAW(isc->formats_list[i].mbus_code) ||
519 !isc->formats_list[i].sd_support)
520 continue;
521 if (supported_index == index) {
522 f->pixelformat = isc->formats_list[i].fourcc;
523 return 0;
524 }
525 supported_index++;
526 }
527
528 return -EINVAL;
529 }
530
isc_g_fmt_vid_cap(struct file * file,void * priv,struct v4l2_format * fmt)531 static int isc_g_fmt_vid_cap(struct file *file, void *priv,
532 struct v4l2_format *fmt)
533 {
534 struct isc_device *isc = video_drvdata(file);
535
536 *fmt = isc->fmt;
537
538 return 0;
539 }
540
541 /*
542 * Checks the current configured format, if ISC can output it,
543 * considering which type of format the ISC receives from the sensor
544 */
isc_try_validate_formats(struct isc_device * isc)545 static int isc_try_validate_formats(struct isc_device *isc)
546 {
547 int ret;
548 bool bayer = false, yuv = false, rgb = false, grey = false;
549
550 /* all formats supported by the RLP module are OK */
551 switch (isc->try_config.fourcc) {
552 case V4L2_PIX_FMT_SBGGR8:
553 case V4L2_PIX_FMT_SGBRG8:
554 case V4L2_PIX_FMT_SGRBG8:
555 case V4L2_PIX_FMT_SRGGB8:
556 case V4L2_PIX_FMT_SBGGR10:
557 case V4L2_PIX_FMT_SGBRG10:
558 case V4L2_PIX_FMT_SGRBG10:
559 case V4L2_PIX_FMT_SRGGB10:
560 case V4L2_PIX_FMT_SBGGR12:
561 case V4L2_PIX_FMT_SGBRG12:
562 case V4L2_PIX_FMT_SGRBG12:
563 case V4L2_PIX_FMT_SRGGB12:
564 ret = 0;
565 bayer = true;
566 break;
567
568 case V4L2_PIX_FMT_YUV420:
569 case V4L2_PIX_FMT_YUV422P:
570 case V4L2_PIX_FMT_YUYV:
571 case V4L2_PIX_FMT_UYVY:
572 case V4L2_PIX_FMT_VYUY:
573 ret = 0;
574 yuv = true;
575 break;
576
577 case V4L2_PIX_FMT_RGB565:
578 case V4L2_PIX_FMT_ABGR32:
579 case V4L2_PIX_FMT_XBGR32:
580 case V4L2_PIX_FMT_ARGB444:
581 case V4L2_PIX_FMT_ARGB555:
582 ret = 0;
583 rgb = true;
584 break;
585 case V4L2_PIX_FMT_GREY:
586 case V4L2_PIX_FMT_Y10:
587 case V4L2_PIX_FMT_Y16:
588 ret = 0;
589 grey = true;
590 break;
591 default:
592 /* any other different formats are not supported */
593 ret = -EINVAL;
594 }
595 v4l2_dbg(1, debug, &isc->v4l2_dev,
596 "Format validation, requested rgb=%u, yuv=%u, grey=%u, bayer=%u\n",
597 rgb, yuv, grey, bayer);
598
599 /* we cannot output RAW if we do not receive RAW */
600 if ((bayer) && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code))
601 return -EINVAL;
602
603 /* we cannot output GREY if we do not receive RAW/GREY */
604 if (grey && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code) &&
605 !ISC_IS_FORMAT_GREY(isc->try_config.sd_format->mbus_code))
606 return -EINVAL;
607
608 return ret;
609 }
610
611 /*
612 * Configures the RLP and DMA modules, depending on the output format
613 * configured for the ISC.
614 * If direct_dump == true, just dump raw data 8/16 bits depending on format.
615 */
isc_try_configure_rlp_dma(struct isc_device * isc,bool direct_dump)616 static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump)
617 {
618 isc->try_config.rlp_cfg_mode = 0;
619
620 switch (isc->try_config.fourcc) {
621 case V4L2_PIX_FMT_SBGGR8:
622 case V4L2_PIX_FMT_SGBRG8:
623 case V4L2_PIX_FMT_SGRBG8:
624 case V4L2_PIX_FMT_SRGGB8:
625 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8;
626 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
627 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
628 isc->try_config.bpp = 8;
629 isc->try_config.bpp_v4l2 = 8;
630 break;
631 case V4L2_PIX_FMT_SBGGR10:
632 case V4L2_PIX_FMT_SGBRG10:
633 case V4L2_PIX_FMT_SGRBG10:
634 case V4L2_PIX_FMT_SRGGB10:
635 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT10;
636 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
637 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
638 isc->try_config.bpp = 16;
639 isc->try_config.bpp_v4l2 = 16;
640 break;
641 case V4L2_PIX_FMT_SBGGR12:
642 case V4L2_PIX_FMT_SGBRG12:
643 case V4L2_PIX_FMT_SGRBG12:
644 case V4L2_PIX_FMT_SRGGB12:
645 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT12;
646 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
647 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
648 isc->try_config.bpp = 16;
649 isc->try_config.bpp_v4l2 = 16;
650 break;
651 case V4L2_PIX_FMT_RGB565:
652 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_RGB565;
653 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
654 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
655 isc->try_config.bpp = 16;
656 isc->try_config.bpp_v4l2 = 16;
657 break;
658 case V4L2_PIX_FMT_ARGB444:
659 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB444;
660 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
661 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
662 isc->try_config.bpp = 16;
663 isc->try_config.bpp_v4l2 = 16;
664 break;
665 case V4L2_PIX_FMT_ARGB555:
666 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB555;
667 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
668 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
669 isc->try_config.bpp = 16;
670 isc->try_config.bpp_v4l2 = 16;
671 break;
672 case V4L2_PIX_FMT_ABGR32:
673 case V4L2_PIX_FMT_XBGR32:
674 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB32;
675 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
676 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
677 isc->try_config.bpp = 32;
678 isc->try_config.bpp_v4l2 = 32;
679 break;
680 case V4L2_PIX_FMT_YUV420:
681 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
682 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC420P;
683 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR;
684 isc->try_config.bpp = 12;
685 isc->try_config.bpp_v4l2 = 8; /* only first plane */
686 break;
687 case V4L2_PIX_FMT_YUV422P:
688 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
689 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC422P;
690 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR;
691 isc->try_config.bpp = 16;
692 isc->try_config.bpp_v4l2 = 8; /* only first plane */
693 break;
694 case V4L2_PIX_FMT_YUYV:
695 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_YUYV;
696 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
697 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
698 isc->try_config.bpp = 16;
699 isc->try_config.bpp_v4l2 = 16;
700 break;
701 case V4L2_PIX_FMT_UYVY:
702 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_UYVY;
703 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
704 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
705 isc->try_config.bpp = 16;
706 isc->try_config.bpp_v4l2 = 16;
707 break;
708 case V4L2_PIX_FMT_VYUY:
709 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_VYUY;
710 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
711 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
712 isc->try_config.bpp = 16;
713 isc->try_config.bpp_v4l2 = 16;
714 break;
715 case V4L2_PIX_FMT_GREY:
716 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY8;
717 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
718 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
719 isc->try_config.bpp = 8;
720 isc->try_config.bpp_v4l2 = 8;
721 break;
722 case V4L2_PIX_FMT_Y16:
723 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10 | ISC_RLP_CFG_LSH;
724 fallthrough;
725 case V4L2_PIX_FMT_Y10:
726 isc->try_config.rlp_cfg_mode |= ISC_RLP_CFG_MODE_DATY10;
727 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
728 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
729 isc->try_config.bpp = 16;
730 isc->try_config.bpp_v4l2 = 16;
731 break;
732 default:
733 return -EINVAL;
734 }
735
736 if (direct_dump) {
737 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8;
738 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
739 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
740 return 0;
741 }
742
743 return 0;
744 }
745
746 /*
747 * Configuring pipeline modules, depending on which format the ISC outputs
748 * and considering which format it has as input from the sensor.
749 */
isc_try_configure_pipeline(struct isc_device * isc)750 static int isc_try_configure_pipeline(struct isc_device *isc)
751 {
752 switch (isc->try_config.fourcc) {
753 case V4L2_PIX_FMT_RGB565:
754 case V4L2_PIX_FMT_ARGB555:
755 case V4L2_PIX_FMT_ARGB444:
756 case V4L2_PIX_FMT_ABGR32:
757 case V4L2_PIX_FMT_XBGR32:
758 /* if sensor format is RAW, we convert inside ISC */
759 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
760 isc->try_config.bits_pipeline = CFA_ENABLE |
761 WB_ENABLE | GAM_ENABLES | DPC_BLCENABLE |
762 CC_ENABLE;
763 } else {
764 isc->try_config.bits_pipeline = 0x0;
765 }
766 break;
767 case V4L2_PIX_FMT_YUV420:
768 /* if sensor format is RAW, we convert inside ISC */
769 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
770 isc->try_config.bits_pipeline = CFA_ENABLE |
771 CSC_ENABLE | GAM_ENABLES | WB_ENABLE |
772 SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE |
773 DPC_BLCENABLE;
774 } else {
775 isc->try_config.bits_pipeline = 0x0;
776 }
777 break;
778 case V4L2_PIX_FMT_YUV422P:
779 /* if sensor format is RAW, we convert inside ISC */
780 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
781 isc->try_config.bits_pipeline = CFA_ENABLE |
782 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
783 SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE;
784 } else {
785 isc->try_config.bits_pipeline = 0x0;
786 }
787 break;
788 case V4L2_PIX_FMT_YUYV:
789 case V4L2_PIX_FMT_UYVY:
790 case V4L2_PIX_FMT_VYUY:
791 /* if sensor format is RAW, we convert inside ISC */
792 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
793 isc->try_config.bits_pipeline = CFA_ENABLE |
794 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
795 SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE;
796 } else {
797 isc->try_config.bits_pipeline = 0x0;
798 }
799 break;
800 case V4L2_PIX_FMT_GREY:
801 case V4L2_PIX_FMT_Y16:
802 /* if sensor format is RAW, we convert inside ISC */
803 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
804 isc->try_config.bits_pipeline = CFA_ENABLE |
805 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
806 CBC_ENABLE | DPC_BLCENABLE;
807 } else {
808 isc->try_config.bits_pipeline = 0x0;
809 }
810 break;
811 default:
812 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code))
813 isc->try_config.bits_pipeline = WB_ENABLE | DPC_BLCENABLE;
814 else
815 isc->try_config.bits_pipeline = 0x0;
816 }
817
818 /* Tune the pipeline to product specific */
819 isc->adapt_pipeline(isc);
820
821 return 0;
822 }
823
isc_try_fse(struct isc_device * isc,struct v4l2_subdev_state * sd_state)824 static void isc_try_fse(struct isc_device *isc,
825 struct v4l2_subdev_state *sd_state)
826 {
827 int ret;
828 struct v4l2_subdev_frame_size_enum fse = {};
829
830 /*
831 * If we do not know yet which format the subdev is using, we cannot
832 * do anything.
833 */
834 if (!isc->try_config.sd_format)
835 return;
836
837 fse.code = isc->try_config.sd_format->mbus_code;
838 fse.which = V4L2_SUBDEV_FORMAT_TRY;
839
840 ret = v4l2_subdev_call(isc->current_subdev->sd, pad, enum_frame_size,
841 sd_state, &fse);
842 /*
843 * Attempt to obtain format size from subdev. If not available,
844 * just use the maximum ISC can receive.
845 */
846 if (ret) {
847 sd_state->pads->try_crop.width = isc->max_width;
848 sd_state->pads->try_crop.height = isc->max_height;
849 } else {
850 sd_state->pads->try_crop.width = fse.max_width;
851 sd_state->pads->try_crop.height = fse.max_height;
852 }
853 }
854
isc_try_fmt(struct isc_device * isc,struct v4l2_format * f,u32 * code)855 static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f,
856 u32 *code)
857 {
858 int i;
859 struct isc_format *sd_fmt = NULL, *direct_fmt = NULL;
860 struct v4l2_pix_format *pixfmt = &f->fmt.pix;
861 struct v4l2_subdev_pad_config pad_cfg = {};
862 struct v4l2_subdev_state pad_state = {
863 .pads = &pad_cfg
864 };
865 struct v4l2_subdev_format format = {
866 .which = V4L2_SUBDEV_FORMAT_TRY,
867 };
868 u32 mbus_code;
869 int ret;
870 bool rlp_dma_direct_dump = false;
871
872 if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
873 return -EINVAL;
874
875 /* Step 1: find a RAW format that is supported */
876 for (i = 0; i < isc->num_user_formats; i++) {
877 if (ISC_IS_FORMAT_RAW(isc->user_formats[i]->mbus_code)) {
878 sd_fmt = isc->user_formats[i];
879 break;
880 }
881 }
882 /* Step 2: We can continue with this RAW format, or we can look
883 * for better: maybe sensor supports directly what we need.
884 */
885 direct_fmt = find_format_by_fourcc(isc, pixfmt->pixelformat);
886
887 /* Step 3: We have both. We decide given the module parameter which
888 * one to use.
889 */
890 if (direct_fmt && sd_fmt && sensor_preferred)
891 sd_fmt = direct_fmt;
892
893 /* Step 4: we do not have RAW but we have a direct format. Use it. */
894 if (direct_fmt && !sd_fmt)
895 sd_fmt = direct_fmt;
896
897 /* Step 5: if we are using a direct format, we need to package
898 * everything as 8 bit data and just dump it
899 */
900 if (sd_fmt == direct_fmt)
901 rlp_dma_direct_dump = true;
902
903 /* Step 6: We have no format. This can happen if the userspace
904 * requests some weird/invalid format.
905 * In this case, default to whatever we have
906 */
907 if (!sd_fmt && !direct_fmt) {
908 sd_fmt = isc->user_formats[isc->num_user_formats - 1];
909 v4l2_dbg(1, debug, &isc->v4l2_dev,
910 "Sensor not supporting %.4s, using %.4s\n",
911 (char *)&pixfmt->pixelformat, (char *)&sd_fmt->fourcc);
912 }
913
914 if (!sd_fmt) {
915 ret = -EINVAL;
916 goto isc_try_fmt_err;
917 }
918
919 /* Step 7: Print out what we decided for debugging */
920 v4l2_dbg(1, debug, &isc->v4l2_dev,
921 "Preferring to have sensor using format %.4s\n",
922 (char *)&sd_fmt->fourcc);
923
924 /* Step 8: at this moment we decided which format the subdev will use */
925 isc->try_config.sd_format = sd_fmt;
926
927 /* Limit to Atmel ISC hardware capabilities */
928 if (pixfmt->width > isc->max_width)
929 pixfmt->width = isc->max_width;
930 if (pixfmt->height > isc->max_height)
931 pixfmt->height = isc->max_height;
932
933 /*
934 * The mbus format is the one the subdev outputs.
935 * The pixels will be transferred in this format Sensor -> ISC
936 */
937 mbus_code = sd_fmt->mbus_code;
938
939 /*
940 * Validate formats. If the required format is not OK, default to raw.
941 */
942
943 isc->try_config.fourcc = pixfmt->pixelformat;
944
945 if (isc_try_validate_formats(isc)) {
946 pixfmt->pixelformat = isc->try_config.fourcc = sd_fmt->fourcc;
947 /* Re-try to validate the new format */
948 ret = isc_try_validate_formats(isc);
949 if (ret)
950 goto isc_try_fmt_err;
951 }
952
953 ret = isc_try_configure_rlp_dma(isc, rlp_dma_direct_dump);
954 if (ret)
955 goto isc_try_fmt_err;
956
957 ret = isc_try_configure_pipeline(isc);
958 if (ret)
959 goto isc_try_fmt_err;
960
961 /* Obtain frame sizes if possible to have crop requirements ready */
962 isc_try_fse(isc, &pad_state);
963
964 v4l2_fill_mbus_format(&format.format, pixfmt, mbus_code);
965 ret = v4l2_subdev_call(isc->current_subdev->sd, pad, set_fmt,
966 &pad_state, &format);
967 if (ret < 0)
968 goto isc_try_fmt_subdev_err;
969
970 v4l2_fill_pix_format(pixfmt, &format.format);
971
972 /* Limit to Atmel ISC hardware capabilities */
973 if (pixfmt->width > isc->max_width)
974 pixfmt->width = isc->max_width;
975 if (pixfmt->height > isc->max_height)
976 pixfmt->height = isc->max_height;
977
978 pixfmt->field = V4L2_FIELD_NONE;
979 pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp_v4l2) >> 3;
980 pixfmt->sizeimage = ((pixfmt->width * isc->try_config.bpp) >> 3) *
981 pixfmt->height;
982
983 if (code)
984 *code = mbus_code;
985
986 return 0;
987
988 isc_try_fmt_err:
989 v4l2_err(&isc->v4l2_dev, "Could not find any possible format for a working pipeline\n");
990 isc_try_fmt_subdev_err:
991 memset(&isc->try_config, 0, sizeof(isc->try_config));
992
993 return ret;
994 }
995
isc_set_fmt(struct isc_device * isc,struct v4l2_format * f)996 static int isc_set_fmt(struct isc_device *isc, struct v4l2_format *f)
997 {
998 struct v4l2_subdev_format format = {
999 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1000 };
1001 u32 mbus_code = 0;
1002 int ret;
1003
1004 ret = isc_try_fmt(isc, f, &mbus_code);
1005 if (ret)
1006 return ret;
1007
1008 v4l2_fill_mbus_format(&format.format, &f->fmt.pix, mbus_code);
1009 ret = v4l2_subdev_call(isc->current_subdev->sd, pad,
1010 set_fmt, NULL, &format);
1011 if (ret < 0)
1012 return ret;
1013
1014 /* Limit to Atmel ISC hardware capabilities */
1015 if (f->fmt.pix.width > isc->max_width)
1016 f->fmt.pix.width = isc->max_width;
1017 if (f->fmt.pix.height > isc->max_height)
1018 f->fmt.pix.height = isc->max_height;
1019
1020 isc->fmt = *f;
1021
1022 if (isc->try_config.sd_format && isc->config.sd_format &&
1023 isc->try_config.sd_format != isc->config.sd_format) {
1024 isc->ctrls.hist_stat = HIST_INIT;
1025 isc_reset_awb_ctrls(isc);
1026 isc_update_v4l2_ctrls(isc);
1027 }
1028 /* make the try configuration active */
1029 isc->config = isc->try_config;
1030
1031 v4l2_dbg(1, debug, &isc->v4l2_dev, "New ISC configuration in place\n");
1032
1033 return 0;
1034 }
1035
isc_s_fmt_vid_cap(struct file * file,void * priv,struct v4l2_format * f)1036 static int isc_s_fmt_vid_cap(struct file *file, void *priv,
1037 struct v4l2_format *f)
1038 {
1039 struct isc_device *isc = video_drvdata(file);
1040
1041 if (vb2_is_busy(&isc->vb2_vidq))
1042 return -EBUSY;
1043
1044 return isc_set_fmt(isc, f);
1045 }
1046
isc_try_fmt_vid_cap(struct file * file,void * priv,struct v4l2_format * f)1047 static int isc_try_fmt_vid_cap(struct file *file, void *priv,
1048 struct v4l2_format *f)
1049 {
1050 struct isc_device *isc = video_drvdata(file);
1051
1052 return isc_try_fmt(isc, f, NULL);
1053 }
1054
isc_enum_input(struct file * file,void * priv,struct v4l2_input * inp)1055 static int isc_enum_input(struct file *file, void *priv,
1056 struct v4l2_input *inp)
1057 {
1058 if (inp->index != 0)
1059 return -EINVAL;
1060
1061 inp->type = V4L2_INPUT_TYPE_CAMERA;
1062 inp->std = 0;
1063 strscpy(inp->name, "Camera", sizeof(inp->name));
1064
1065 return 0;
1066 }
1067
isc_g_input(struct file * file,void * priv,unsigned int * i)1068 static int isc_g_input(struct file *file, void *priv, unsigned int *i)
1069 {
1070 *i = 0;
1071
1072 return 0;
1073 }
1074
isc_s_input(struct file * file,void * priv,unsigned int i)1075 static int isc_s_input(struct file *file, void *priv, unsigned int i)
1076 {
1077 if (i > 0)
1078 return -EINVAL;
1079
1080 return 0;
1081 }
1082
isc_g_parm(struct file * file,void * fh,struct v4l2_streamparm * a)1083 static int isc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1084 {
1085 struct isc_device *isc = video_drvdata(file);
1086
1087 return v4l2_g_parm_cap(video_devdata(file), isc->current_subdev->sd, a);
1088 }
1089
isc_s_parm(struct file * file,void * fh,struct v4l2_streamparm * a)1090 static int isc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1091 {
1092 struct isc_device *isc = video_drvdata(file);
1093
1094 return v4l2_s_parm_cap(video_devdata(file), isc->current_subdev->sd, a);
1095 }
1096
isc_enum_framesizes(struct file * file,void * fh,struct v4l2_frmsizeenum * fsize)1097 static int isc_enum_framesizes(struct file *file, void *fh,
1098 struct v4l2_frmsizeenum *fsize)
1099 {
1100 struct isc_device *isc = video_drvdata(file);
1101 int ret = -EINVAL;
1102 int i;
1103
1104 if (fsize->index)
1105 return -EINVAL;
1106
1107 for (i = 0; i < isc->num_user_formats; i++)
1108 if (isc->user_formats[i]->fourcc == fsize->pixel_format)
1109 ret = 0;
1110
1111 for (i = 0; i < isc->controller_formats_size; i++)
1112 if (isc->controller_formats[i].fourcc == fsize->pixel_format)
1113 ret = 0;
1114
1115 if (ret)
1116 return ret;
1117
1118 fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
1119
1120 fsize->stepwise.min_width = 16;
1121 fsize->stepwise.max_width = isc->max_width;
1122 fsize->stepwise.min_height = 16;
1123 fsize->stepwise.max_height = isc->max_height;
1124 fsize->stepwise.step_width = 1;
1125 fsize->stepwise.step_height = 1;
1126
1127 return 0;
1128 }
1129
1130 static const struct v4l2_ioctl_ops isc_ioctl_ops = {
1131 .vidioc_querycap = isc_querycap,
1132 .vidioc_enum_fmt_vid_cap = isc_enum_fmt_vid_cap,
1133 .vidioc_g_fmt_vid_cap = isc_g_fmt_vid_cap,
1134 .vidioc_s_fmt_vid_cap = isc_s_fmt_vid_cap,
1135 .vidioc_try_fmt_vid_cap = isc_try_fmt_vid_cap,
1136
1137 .vidioc_enum_input = isc_enum_input,
1138 .vidioc_g_input = isc_g_input,
1139 .vidioc_s_input = isc_s_input,
1140
1141 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1142 .vidioc_querybuf = vb2_ioctl_querybuf,
1143 .vidioc_qbuf = vb2_ioctl_qbuf,
1144 .vidioc_expbuf = vb2_ioctl_expbuf,
1145 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1146 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1147 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1148 .vidioc_streamon = vb2_ioctl_streamon,
1149 .vidioc_streamoff = vb2_ioctl_streamoff,
1150
1151 .vidioc_g_parm = isc_g_parm,
1152 .vidioc_s_parm = isc_s_parm,
1153 .vidioc_enum_framesizes = isc_enum_framesizes,
1154
1155 .vidioc_log_status = v4l2_ctrl_log_status,
1156 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1157 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1158 };
1159
isc_open(struct file * file)1160 static int isc_open(struct file *file)
1161 {
1162 struct isc_device *isc = video_drvdata(file);
1163 struct v4l2_subdev *sd = isc->current_subdev->sd;
1164 int ret;
1165
1166 if (mutex_lock_interruptible(&isc->lock))
1167 return -ERESTARTSYS;
1168
1169 ret = v4l2_fh_open(file);
1170 if (ret < 0)
1171 goto unlock;
1172
1173 if (!v4l2_fh_is_singular_file(file))
1174 goto unlock;
1175
1176 ret = v4l2_subdev_call(sd, core, s_power, 1);
1177 if (ret < 0 && ret != -ENOIOCTLCMD) {
1178 v4l2_fh_release(file);
1179 goto unlock;
1180 }
1181
1182 ret = isc_set_fmt(isc, &isc->fmt);
1183 if (ret) {
1184 v4l2_subdev_call(sd, core, s_power, 0);
1185 v4l2_fh_release(file);
1186 }
1187
1188 unlock:
1189 mutex_unlock(&isc->lock);
1190 return ret;
1191 }
1192
isc_release(struct file * file)1193 static int isc_release(struct file *file)
1194 {
1195 struct isc_device *isc = video_drvdata(file);
1196 struct v4l2_subdev *sd = isc->current_subdev->sd;
1197 bool fh_singular;
1198 int ret;
1199
1200 mutex_lock(&isc->lock);
1201
1202 fh_singular = v4l2_fh_is_singular_file(file);
1203
1204 ret = _vb2_fop_release(file, NULL);
1205
1206 if (fh_singular)
1207 v4l2_subdev_call(sd, core, s_power, 0);
1208
1209 mutex_unlock(&isc->lock);
1210
1211 return ret;
1212 }
1213
1214 static const struct v4l2_file_operations isc_fops = {
1215 .owner = THIS_MODULE,
1216 .open = isc_open,
1217 .release = isc_release,
1218 .unlocked_ioctl = video_ioctl2,
1219 .read = vb2_fop_read,
1220 .mmap = vb2_fop_mmap,
1221 .poll = vb2_fop_poll,
1222 };
1223
isc_interrupt(int irq,void * dev_id)1224 irqreturn_t isc_interrupt(int irq, void *dev_id)
1225 {
1226 struct isc_device *isc = (struct isc_device *)dev_id;
1227 struct regmap *regmap = isc->regmap;
1228 u32 isc_intsr, isc_intmask, pending;
1229 irqreturn_t ret = IRQ_NONE;
1230
1231 regmap_read(regmap, ISC_INTSR, &isc_intsr);
1232 regmap_read(regmap, ISC_INTMASK, &isc_intmask);
1233
1234 pending = isc_intsr & isc_intmask;
1235
1236 if (likely(pending & ISC_INT_DDONE)) {
1237 spin_lock(&isc->dma_queue_lock);
1238 if (isc->cur_frm) {
1239 struct vb2_v4l2_buffer *vbuf = &isc->cur_frm->vb;
1240 struct vb2_buffer *vb = &vbuf->vb2_buf;
1241
1242 vb->timestamp = ktime_get_ns();
1243 vbuf->sequence = isc->sequence++;
1244 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1245 isc->cur_frm = NULL;
1246 }
1247
1248 if (!list_empty(&isc->dma_queue) && !isc->stop) {
1249 isc->cur_frm = list_first_entry(&isc->dma_queue,
1250 struct isc_buffer, list);
1251 list_del(&isc->cur_frm->list);
1252
1253 isc_start_dma(isc);
1254 }
1255
1256 if (isc->stop)
1257 complete(&isc->comp);
1258
1259 ret = IRQ_HANDLED;
1260 spin_unlock(&isc->dma_queue_lock);
1261 }
1262
1263 if (pending & ISC_INT_HISDONE) {
1264 schedule_work(&isc->awb_work);
1265 ret = IRQ_HANDLED;
1266 }
1267
1268 return ret;
1269 }
1270 EXPORT_SYMBOL_GPL(isc_interrupt);
1271
isc_hist_count(struct isc_device * isc,u32 * min,u32 * max)1272 static void isc_hist_count(struct isc_device *isc, u32 *min, u32 *max)
1273 {
1274 struct regmap *regmap = isc->regmap;
1275 struct isc_ctrls *ctrls = &isc->ctrls;
1276 u32 *hist_count = &ctrls->hist_count[ctrls->hist_id];
1277 u32 *hist_entry = &ctrls->hist_entry[0];
1278 u32 i;
1279
1280 *min = 0;
1281 *max = HIST_ENTRIES;
1282
1283 regmap_bulk_read(regmap, ISC_HIS_ENTRY + isc->offsets.his_entry,
1284 hist_entry, HIST_ENTRIES);
1285
1286 *hist_count = 0;
1287 /*
1288 * we deliberately ignore the end of the histogram,
1289 * the most white pixels
1290 */
1291 for (i = 1; i < HIST_ENTRIES; i++) {
1292 if (*hist_entry && !*min)
1293 *min = i;
1294 if (*hist_entry)
1295 *max = i;
1296 *hist_count += i * (*hist_entry++);
1297 }
1298
1299 if (!*min)
1300 *min = 1;
1301
1302 v4l2_dbg(1, debug, &isc->v4l2_dev,
1303 "isc wb: hist_id %u, hist_count %u",
1304 ctrls->hist_id, *hist_count);
1305 }
1306
isc_wb_update(struct isc_ctrls * ctrls)1307 static void isc_wb_update(struct isc_ctrls *ctrls)
1308 {
1309 struct isc_device *isc = container_of(ctrls, struct isc_device, ctrls);
1310 u32 *hist_count = &ctrls->hist_count[0];
1311 u32 c, offset[4];
1312 u64 avg = 0;
1313 /* We compute two gains, stretch gain and grey world gain */
1314 u32 s_gain[4], gw_gain[4];
1315
1316 /*
1317 * According to Grey World, we need to set gains for R/B to normalize
1318 * them towards the green channel.
1319 * Thus we want to keep Green as fixed and adjust only Red/Blue
1320 * Compute the average of the both green channels first
1321 */
1322 avg = (u64)hist_count[ISC_HIS_CFG_MODE_GR] +
1323 (u64)hist_count[ISC_HIS_CFG_MODE_GB];
1324 avg >>= 1;
1325
1326 v4l2_dbg(1, debug, &isc->v4l2_dev,
1327 "isc wb: green components average %llu\n", avg);
1328
1329 /* Green histogram is null, nothing to do */
1330 if (!avg)
1331 return;
1332
1333 for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) {
1334 /*
1335 * the color offset is the minimum value of the histogram.
1336 * we stretch this color to the full range by substracting
1337 * this value from the color component.
1338 */
1339 offset[c] = ctrls->hist_minmax[c][HIST_MIN_INDEX];
1340 /*
1341 * The offset is always at least 1. If the offset is 1, we do
1342 * not need to adjust it, so our result must be zero.
1343 * the offset is computed in a histogram on 9 bits (0..512)
1344 * but the offset in register is based on
1345 * 12 bits pipeline (0..4096).
1346 * we need to shift with the 3 bits that the histogram is
1347 * ignoring
1348 */
1349 ctrls->offset[c] = (offset[c] - 1) << 3;
1350
1351 /*
1352 * the offset is then taken and converted to 2's complements,
1353 * and must be negative, as we subtract this value from the
1354 * color components
1355 */
1356 ctrls->offset[c] = -ctrls->offset[c];
1357
1358 /*
1359 * the stretch gain is the total number of histogram bins
1360 * divided by the actual range of color component (Max - Min)
1361 * If we compute gain like this, the actual color component
1362 * will be stretched to the full histogram.
1363 * We need to shift 9 bits for precision, we have 9 bits for
1364 * decimals
1365 */
1366 s_gain[c] = (HIST_ENTRIES << 9) /
1367 (ctrls->hist_minmax[c][HIST_MAX_INDEX] -
1368 ctrls->hist_minmax[c][HIST_MIN_INDEX] + 1);
1369
1370 /*
1371 * Now we have to compute the gain w.r.t. the average.
1372 * Add/lose gain to the component towards the average.
1373 * If it happens that the component is zero, use the
1374 * fixed point value : 1.0 gain.
1375 */
1376 if (hist_count[c])
1377 gw_gain[c] = div_u64(avg << 9, hist_count[c]);
1378 else
1379 gw_gain[c] = 1 << 9;
1380
1381 v4l2_dbg(1, debug, &isc->v4l2_dev,
1382 "isc wb: component %d, s_gain %u, gw_gain %u\n",
1383 c, s_gain[c], gw_gain[c]);
1384 /* multiply both gains and adjust for decimals */
1385 ctrls->gain[c] = s_gain[c] * gw_gain[c];
1386 ctrls->gain[c] >>= 9;
1387
1388 /* make sure we are not out of range */
1389 ctrls->gain[c] = clamp_val(ctrls->gain[c], 0, GENMASK(12, 0));
1390
1391 v4l2_dbg(1, debug, &isc->v4l2_dev,
1392 "isc wb: component %d, final gain %u\n",
1393 c, ctrls->gain[c]);
1394 }
1395 }
1396
isc_awb_work(struct work_struct * w)1397 static void isc_awb_work(struct work_struct *w)
1398 {
1399 struct isc_device *isc =
1400 container_of(w, struct isc_device, awb_work);
1401 struct regmap *regmap = isc->regmap;
1402 struct isc_ctrls *ctrls = &isc->ctrls;
1403 u32 hist_id = ctrls->hist_id;
1404 u32 baysel;
1405 unsigned long flags;
1406 u32 min, max;
1407 int ret;
1408
1409 if (ctrls->hist_stat != HIST_ENABLED)
1410 return;
1411
1412 isc_hist_count(isc, &min, &max);
1413
1414 v4l2_dbg(1, debug, &isc->v4l2_dev,
1415 "isc wb mode %d: hist min %u , max %u\n", hist_id, min, max);
1416
1417 ctrls->hist_minmax[hist_id][HIST_MIN_INDEX] = min;
1418 ctrls->hist_minmax[hist_id][HIST_MAX_INDEX] = max;
1419
1420 if (hist_id != ISC_HIS_CFG_MODE_B) {
1421 hist_id++;
1422 } else {
1423 isc_wb_update(ctrls);
1424 hist_id = ISC_HIS_CFG_MODE_GR;
1425 }
1426
1427 ctrls->hist_id = hist_id;
1428 baysel = isc->config.sd_format->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT;
1429
1430 ret = pm_runtime_resume_and_get(isc->dev);
1431 if (ret < 0)
1432 return;
1433
1434 /*
1435 * only update if we have all the required histograms and controls
1436 * if awb has been disabled, we need to reset registers as well.
1437 */
1438 if (hist_id == ISC_HIS_CFG_MODE_GR || ctrls->awb == ISC_WB_NONE) {
1439 /*
1440 * It may happen that DMA Done IRQ will trigger while we are
1441 * updating white balance registers here.
1442 * In that case, only parts of the controls have been updated.
1443 * We can avoid that by locking the section.
1444 */
1445 spin_lock_irqsave(&isc->awb_lock, flags);
1446 isc_update_awb_ctrls(isc);
1447 spin_unlock_irqrestore(&isc->awb_lock, flags);
1448
1449 /*
1450 * if we are doing just the one time white balance adjustment,
1451 * we are basically done.
1452 */
1453 if (ctrls->awb == ISC_WB_ONETIME) {
1454 v4l2_info(&isc->v4l2_dev,
1455 "Completed one time white-balance adjustment.\n");
1456 /* update the v4l2 controls values */
1457 isc_update_v4l2_ctrls(isc);
1458 ctrls->awb = ISC_WB_NONE;
1459 }
1460 }
1461 regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his,
1462 hist_id | baysel | ISC_HIS_CFG_RAR);
1463
1464 /*
1465 * We have to make sure the streaming has not stopped meanwhile.
1466 * ISC requires a frame to clock the internal profile update.
1467 * To avoid issues, lock the sequence with a mutex
1468 */
1469 mutex_lock(&isc->awb_mutex);
1470
1471 /* streaming is not active anymore */
1472 if (isc->stop) {
1473 mutex_unlock(&isc->awb_mutex);
1474 return;
1475 }
1476
1477 isc_update_profile(isc);
1478
1479 mutex_unlock(&isc->awb_mutex);
1480
1481 /* if awb has been disabled, we don't need to start another histogram */
1482 if (ctrls->awb)
1483 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ);
1484
1485 pm_runtime_put_sync(isc->dev);
1486 }
1487
isc_s_ctrl(struct v4l2_ctrl * ctrl)1488 static int isc_s_ctrl(struct v4l2_ctrl *ctrl)
1489 {
1490 struct isc_device *isc = container_of(ctrl->handler,
1491 struct isc_device, ctrls.handler);
1492 struct isc_ctrls *ctrls = &isc->ctrls;
1493
1494 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
1495 return 0;
1496
1497 switch (ctrl->id) {
1498 case V4L2_CID_BRIGHTNESS:
1499 ctrls->brightness = ctrl->val & ISC_CBC_BRIGHT_MASK;
1500 break;
1501 case V4L2_CID_CONTRAST:
1502 ctrls->contrast = ctrl->val & ISC_CBC_CONTRAST_MASK;
1503 break;
1504 case V4L2_CID_GAMMA:
1505 ctrls->gamma_index = ctrl->val;
1506 break;
1507 default:
1508 return -EINVAL;
1509 }
1510
1511 return 0;
1512 }
1513
1514 static const struct v4l2_ctrl_ops isc_ctrl_ops = {
1515 .s_ctrl = isc_s_ctrl,
1516 };
1517
isc_s_awb_ctrl(struct v4l2_ctrl * ctrl)1518 static int isc_s_awb_ctrl(struct v4l2_ctrl *ctrl)
1519 {
1520 struct isc_device *isc = container_of(ctrl->handler,
1521 struct isc_device, ctrls.handler);
1522 struct isc_ctrls *ctrls = &isc->ctrls;
1523
1524 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
1525 return 0;
1526
1527 switch (ctrl->id) {
1528 case V4L2_CID_AUTO_WHITE_BALANCE:
1529 if (ctrl->val == 1)
1530 ctrls->awb = ISC_WB_AUTO;
1531 else
1532 ctrls->awb = ISC_WB_NONE;
1533
1534 /* configure the controls with new values from v4l2 */
1535 if (ctrl->cluster[ISC_CTRL_R_GAIN]->is_new)
1536 ctrls->gain[ISC_HIS_CFG_MODE_R] = isc->r_gain_ctrl->val;
1537 if (ctrl->cluster[ISC_CTRL_B_GAIN]->is_new)
1538 ctrls->gain[ISC_HIS_CFG_MODE_B] = isc->b_gain_ctrl->val;
1539 if (ctrl->cluster[ISC_CTRL_GR_GAIN]->is_new)
1540 ctrls->gain[ISC_HIS_CFG_MODE_GR] = isc->gr_gain_ctrl->val;
1541 if (ctrl->cluster[ISC_CTRL_GB_GAIN]->is_new)
1542 ctrls->gain[ISC_HIS_CFG_MODE_GB] = isc->gb_gain_ctrl->val;
1543
1544 if (ctrl->cluster[ISC_CTRL_R_OFF]->is_new)
1545 ctrls->offset[ISC_HIS_CFG_MODE_R] = isc->r_off_ctrl->val;
1546 if (ctrl->cluster[ISC_CTRL_B_OFF]->is_new)
1547 ctrls->offset[ISC_HIS_CFG_MODE_B] = isc->b_off_ctrl->val;
1548 if (ctrl->cluster[ISC_CTRL_GR_OFF]->is_new)
1549 ctrls->offset[ISC_HIS_CFG_MODE_GR] = isc->gr_off_ctrl->val;
1550 if (ctrl->cluster[ISC_CTRL_GB_OFF]->is_new)
1551 ctrls->offset[ISC_HIS_CFG_MODE_GB] = isc->gb_off_ctrl->val;
1552
1553 isc_update_awb_ctrls(isc);
1554
1555 mutex_lock(&isc->awb_mutex);
1556 if (vb2_is_streaming(&isc->vb2_vidq)) {
1557 /*
1558 * If we are streaming, we can update profile to
1559 * have the new settings in place.
1560 */
1561 isc_update_profile(isc);
1562 } else {
1563 /*
1564 * The auto cluster will activate automatically this
1565 * control. This has to be deactivated when not
1566 * streaming.
1567 */
1568 v4l2_ctrl_activate(isc->do_wb_ctrl, false);
1569 }
1570 mutex_unlock(&isc->awb_mutex);
1571
1572 /* if we have autowhitebalance on, start histogram procedure */
1573 if (ctrls->awb == ISC_WB_AUTO &&
1574 vb2_is_streaming(&isc->vb2_vidq) &&
1575 ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
1576 isc_set_histogram(isc, true);
1577
1578 /*
1579 * for one time whitebalance adjustment, check the button,
1580 * if it's pressed, perform the one time operation.
1581 */
1582 if (ctrls->awb == ISC_WB_NONE &&
1583 ctrl->cluster[ISC_CTRL_DO_WB]->is_new &&
1584 !(ctrl->cluster[ISC_CTRL_DO_WB]->flags &
1585 V4L2_CTRL_FLAG_INACTIVE)) {
1586 ctrls->awb = ISC_WB_ONETIME;
1587 isc_set_histogram(isc, true);
1588 v4l2_dbg(1, debug, &isc->v4l2_dev,
1589 "One time white-balance started.\n");
1590 }
1591 return 0;
1592 }
1593 return 0;
1594 }
1595
isc_g_volatile_awb_ctrl(struct v4l2_ctrl * ctrl)1596 static int isc_g_volatile_awb_ctrl(struct v4l2_ctrl *ctrl)
1597 {
1598 struct isc_device *isc = container_of(ctrl->handler,
1599 struct isc_device, ctrls.handler);
1600 struct isc_ctrls *ctrls = &isc->ctrls;
1601
1602 switch (ctrl->id) {
1603 /* being a cluster, this id will be called for every control */
1604 case V4L2_CID_AUTO_WHITE_BALANCE:
1605 ctrl->cluster[ISC_CTRL_R_GAIN]->val =
1606 ctrls->gain[ISC_HIS_CFG_MODE_R];
1607 ctrl->cluster[ISC_CTRL_B_GAIN]->val =
1608 ctrls->gain[ISC_HIS_CFG_MODE_B];
1609 ctrl->cluster[ISC_CTRL_GR_GAIN]->val =
1610 ctrls->gain[ISC_HIS_CFG_MODE_GR];
1611 ctrl->cluster[ISC_CTRL_GB_GAIN]->val =
1612 ctrls->gain[ISC_HIS_CFG_MODE_GB];
1613
1614 ctrl->cluster[ISC_CTRL_R_OFF]->val =
1615 ctrls->offset[ISC_HIS_CFG_MODE_R];
1616 ctrl->cluster[ISC_CTRL_B_OFF]->val =
1617 ctrls->offset[ISC_HIS_CFG_MODE_B];
1618 ctrl->cluster[ISC_CTRL_GR_OFF]->val =
1619 ctrls->offset[ISC_HIS_CFG_MODE_GR];
1620 ctrl->cluster[ISC_CTRL_GB_OFF]->val =
1621 ctrls->offset[ISC_HIS_CFG_MODE_GB];
1622 break;
1623 }
1624 return 0;
1625 }
1626
1627 static const struct v4l2_ctrl_ops isc_awb_ops = {
1628 .s_ctrl = isc_s_awb_ctrl,
1629 .g_volatile_ctrl = isc_g_volatile_awb_ctrl,
1630 };
1631
1632 #define ISC_CTRL_OFF(_name, _id, _name_str) \
1633 static const struct v4l2_ctrl_config _name = { \
1634 .ops = &isc_awb_ops, \
1635 .id = _id, \
1636 .name = _name_str, \
1637 .type = V4L2_CTRL_TYPE_INTEGER, \
1638 .flags = V4L2_CTRL_FLAG_SLIDER, \
1639 .min = -4095, \
1640 .max = 4095, \
1641 .step = 1, \
1642 .def = 0, \
1643 }
1644
1645 ISC_CTRL_OFF(isc_r_off_ctrl, ISC_CID_R_OFFSET, "Red Component Offset");
1646 ISC_CTRL_OFF(isc_b_off_ctrl, ISC_CID_B_OFFSET, "Blue Component Offset");
1647 ISC_CTRL_OFF(isc_gr_off_ctrl, ISC_CID_GR_OFFSET, "Green Red Component Offset");
1648 ISC_CTRL_OFF(isc_gb_off_ctrl, ISC_CID_GB_OFFSET, "Green Blue Component Offset");
1649
1650 #define ISC_CTRL_GAIN(_name, _id, _name_str) \
1651 static const struct v4l2_ctrl_config _name = { \
1652 .ops = &isc_awb_ops, \
1653 .id = _id, \
1654 .name = _name_str, \
1655 .type = V4L2_CTRL_TYPE_INTEGER, \
1656 .flags = V4L2_CTRL_FLAG_SLIDER, \
1657 .min = 0, \
1658 .max = 8191, \
1659 .step = 1, \
1660 .def = 512, \
1661 }
1662
1663 ISC_CTRL_GAIN(isc_r_gain_ctrl, ISC_CID_R_GAIN, "Red Component Gain");
1664 ISC_CTRL_GAIN(isc_b_gain_ctrl, ISC_CID_B_GAIN, "Blue Component Gain");
1665 ISC_CTRL_GAIN(isc_gr_gain_ctrl, ISC_CID_GR_GAIN, "Green Red Component Gain");
1666 ISC_CTRL_GAIN(isc_gb_gain_ctrl, ISC_CID_GB_GAIN, "Green Blue Component Gain");
1667
isc_ctrl_init(struct isc_device * isc)1668 static int isc_ctrl_init(struct isc_device *isc)
1669 {
1670 const struct v4l2_ctrl_ops *ops = &isc_ctrl_ops;
1671 struct isc_ctrls *ctrls = &isc->ctrls;
1672 struct v4l2_ctrl_handler *hdl = &ctrls->handler;
1673 int ret;
1674
1675 ctrls->hist_stat = HIST_INIT;
1676 isc_reset_awb_ctrls(isc);
1677
1678 ret = v4l2_ctrl_handler_init(hdl, 13);
1679 if (ret < 0)
1680 return ret;
1681
1682 /* Initialize product specific controls. For example, contrast */
1683 isc->config_ctrls(isc, ops);
1684
1685 ctrls->brightness = 0;
1686
1687 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0);
1688 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1,
1689 isc->gamma_max);
1690 isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,
1691 V4L2_CID_AUTO_WHITE_BALANCE,
1692 0, 1, 1, 1);
1693
1694 /* do_white_balance is a button, so min,max,step,default are ignored */
1695 isc->do_wb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,
1696 V4L2_CID_DO_WHITE_BALANCE,
1697 0, 0, 0, 0);
1698
1699 if (!isc->do_wb_ctrl) {
1700 ret = hdl->error;
1701 v4l2_ctrl_handler_free(hdl);
1702 return ret;
1703 }
1704
1705 v4l2_ctrl_activate(isc->do_wb_ctrl, false);
1706
1707 isc->r_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_gain_ctrl, NULL);
1708 isc->b_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_gain_ctrl, NULL);
1709 isc->gr_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_gain_ctrl, NULL);
1710 isc->gb_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_gain_ctrl, NULL);
1711 isc->r_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_off_ctrl, NULL);
1712 isc->b_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_off_ctrl, NULL);
1713 isc->gr_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_off_ctrl, NULL);
1714 isc->gb_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_off_ctrl, NULL);
1715
1716 /*
1717 * The cluster is in auto mode with autowhitebalance enabled
1718 * and manual mode otherwise.
1719 */
1720 v4l2_ctrl_auto_cluster(10, &isc->awb_ctrl, 0, true);
1721
1722 v4l2_ctrl_handler_setup(hdl);
1723
1724 return 0;
1725 }
1726
isc_async_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_subdev * asd)1727 static int isc_async_bound(struct v4l2_async_notifier *notifier,
1728 struct v4l2_subdev *subdev,
1729 struct v4l2_async_subdev *asd)
1730 {
1731 struct isc_device *isc = container_of(notifier->v4l2_dev,
1732 struct isc_device, v4l2_dev);
1733 struct isc_subdev_entity *subdev_entity =
1734 container_of(notifier, struct isc_subdev_entity, notifier);
1735
1736 if (video_is_registered(&isc->video_dev)) {
1737 v4l2_err(&isc->v4l2_dev, "only supports one sub-device.\n");
1738 return -EBUSY;
1739 }
1740
1741 subdev_entity->sd = subdev;
1742
1743 return 0;
1744 }
1745
isc_async_unbind(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_subdev * asd)1746 static void isc_async_unbind(struct v4l2_async_notifier *notifier,
1747 struct v4l2_subdev *subdev,
1748 struct v4l2_async_subdev *asd)
1749 {
1750 struct isc_device *isc = container_of(notifier->v4l2_dev,
1751 struct isc_device, v4l2_dev);
1752 mutex_destroy(&isc->awb_mutex);
1753 cancel_work_sync(&isc->awb_work);
1754 video_unregister_device(&isc->video_dev);
1755 v4l2_ctrl_handler_free(&isc->ctrls.handler);
1756 }
1757
find_format_by_code(struct isc_device * isc,unsigned int code,int * index)1758 static struct isc_format *find_format_by_code(struct isc_device *isc,
1759 unsigned int code, int *index)
1760 {
1761 struct isc_format *fmt = &isc->formats_list[0];
1762 unsigned int i;
1763
1764 for (i = 0; i < isc->formats_list_size; i++) {
1765 if (fmt->mbus_code == code) {
1766 *index = i;
1767 return fmt;
1768 }
1769
1770 fmt++;
1771 }
1772
1773 return NULL;
1774 }
1775
isc_formats_init(struct isc_device * isc)1776 static int isc_formats_init(struct isc_device *isc)
1777 {
1778 struct isc_format *fmt;
1779 struct v4l2_subdev *subdev = isc->current_subdev->sd;
1780 unsigned int num_fmts, i, j;
1781 u32 list_size = isc->formats_list_size;
1782 struct v4l2_subdev_mbus_code_enum mbus_code = {
1783 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1784 };
1785
1786 num_fmts = 0;
1787 while (!v4l2_subdev_call(subdev, pad, enum_mbus_code,
1788 NULL, &mbus_code)) {
1789 mbus_code.index++;
1790
1791 fmt = find_format_by_code(isc, mbus_code.code, &i);
1792 if (!fmt) {
1793 v4l2_warn(&isc->v4l2_dev, "Mbus code %x not supported\n",
1794 mbus_code.code);
1795 continue;
1796 }
1797
1798 fmt->sd_support = true;
1799 num_fmts++;
1800 }
1801
1802 if (!num_fmts)
1803 return -ENXIO;
1804
1805 isc->num_user_formats = num_fmts;
1806 isc->user_formats = devm_kcalloc(isc->dev,
1807 num_fmts, sizeof(*isc->user_formats),
1808 GFP_KERNEL);
1809 if (!isc->user_formats)
1810 return -ENOMEM;
1811
1812 fmt = &isc->formats_list[0];
1813 for (i = 0, j = 0; i < list_size; i++) {
1814 if (fmt->sd_support)
1815 isc->user_formats[j++] = fmt;
1816 fmt++;
1817 }
1818
1819 return 0;
1820 }
1821
isc_set_default_fmt(struct isc_device * isc)1822 static int isc_set_default_fmt(struct isc_device *isc)
1823 {
1824 struct v4l2_format f = {
1825 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
1826 .fmt.pix = {
1827 .width = VGA_WIDTH,
1828 .height = VGA_HEIGHT,
1829 .field = V4L2_FIELD_NONE,
1830 .pixelformat = isc->user_formats[0]->fourcc,
1831 },
1832 };
1833 int ret;
1834
1835 ret = isc_try_fmt(isc, &f, NULL);
1836 if (ret)
1837 return ret;
1838
1839 isc->fmt = f;
1840 return 0;
1841 }
1842
isc_async_complete(struct v4l2_async_notifier * notifier)1843 static int isc_async_complete(struct v4l2_async_notifier *notifier)
1844 {
1845 struct isc_device *isc = container_of(notifier->v4l2_dev,
1846 struct isc_device, v4l2_dev);
1847 struct video_device *vdev = &isc->video_dev;
1848 struct vb2_queue *q = &isc->vb2_vidq;
1849 int ret = 0;
1850
1851 INIT_WORK(&isc->awb_work, isc_awb_work);
1852
1853 ret = v4l2_device_register_subdev_nodes(&isc->v4l2_dev);
1854 if (ret < 0) {
1855 v4l2_err(&isc->v4l2_dev, "Failed to register subdev nodes\n");
1856 return ret;
1857 }
1858
1859 isc->current_subdev = container_of(notifier,
1860 struct isc_subdev_entity, notifier);
1861 mutex_init(&isc->lock);
1862 mutex_init(&isc->awb_mutex);
1863
1864 init_completion(&isc->comp);
1865
1866 /* Initialize videobuf2 queue */
1867 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1868 q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
1869 q->drv_priv = isc;
1870 q->buf_struct_size = sizeof(struct isc_buffer);
1871 q->ops = &isc_vb2_ops;
1872 q->mem_ops = &vb2_dma_contig_memops;
1873 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1874 q->lock = &isc->lock;
1875 q->min_buffers_needed = 1;
1876 q->dev = isc->dev;
1877
1878 ret = vb2_queue_init(q);
1879 if (ret < 0) {
1880 v4l2_err(&isc->v4l2_dev,
1881 "vb2_queue_init() failed: %d\n", ret);
1882 goto isc_async_complete_err;
1883 }
1884
1885 /* Init video dma queues */
1886 INIT_LIST_HEAD(&isc->dma_queue);
1887 spin_lock_init(&isc->dma_queue_lock);
1888 spin_lock_init(&isc->awb_lock);
1889
1890 ret = isc_formats_init(isc);
1891 if (ret < 0) {
1892 v4l2_err(&isc->v4l2_dev,
1893 "Init format failed: %d\n", ret);
1894 goto isc_async_complete_err;
1895 }
1896
1897 ret = isc_set_default_fmt(isc);
1898 if (ret) {
1899 v4l2_err(&isc->v4l2_dev, "Could not set default format\n");
1900 goto isc_async_complete_err;
1901 }
1902
1903 ret = isc_ctrl_init(isc);
1904 if (ret) {
1905 v4l2_err(&isc->v4l2_dev, "Init isc ctrols failed: %d\n", ret);
1906 goto isc_async_complete_err;
1907 }
1908
1909 /* Register video device */
1910 strscpy(vdev->name, KBUILD_MODNAME, sizeof(vdev->name));
1911 vdev->release = video_device_release_empty;
1912 vdev->fops = &isc_fops;
1913 vdev->ioctl_ops = &isc_ioctl_ops;
1914 vdev->v4l2_dev = &isc->v4l2_dev;
1915 vdev->vfl_dir = VFL_DIR_RX;
1916 vdev->queue = q;
1917 vdev->lock = &isc->lock;
1918 vdev->ctrl_handler = &isc->ctrls.handler;
1919 vdev->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE;
1920 video_set_drvdata(vdev, isc);
1921
1922 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
1923 if (ret < 0) {
1924 v4l2_err(&isc->v4l2_dev,
1925 "video_register_device failed: %d\n", ret);
1926 goto isc_async_complete_err;
1927 }
1928
1929 return 0;
1930
1931 isc_async_complete_err:
1932 mutex_destroy(&isc->awb_mutex);
1933 mutex_destroy(&isc->lock);
1934 return ret;
1935 }
1936
1937 const struct v4l2_async_notifier_operations isc_async_ops = {
1938 .bound = isc_async_bound,
1939 .unbind = isc_async_unbind,
1940 .complete = isc_async_complete,
1941 };
1942 EXPORT_SYMBOL_GPL(isc_async_ops);
1943
isc_subdev_cleanup(struct isc_device * isc)1944 void isc_subdev_cleanup(struct isc_device *isc)
1945 {
1946 struct isc_subdev_entity *subdev_entity;
1947
1948 list_for_each_entry(subdev_entity, &isc->subdev_entities, list) {
1949 v4l2_async_nf_unregister(&subdev_entity->notifier);
1950 v4l2_async_nf_cleanup(&subdev_entity->notifier);
1951 }
1952
1953 INIT_LIST_HEAD(&isc->subdev_entities);
1954 }
1955 EXPORT_SYMBOL_GPL(isc_subdev_cleanup);
1956
isc_pipeline_init(struct isc_device * isc)1957 int isc_pipeline_init(struct isc_device *isc)
1958 {
1959 struct device *dev = isc->dev;
1960 struct regmap *regmap = isc->regmap;
1961 struct regmap_field *regs;
1962 unsigned int i;
1963
1964 /*
1965 * DPCEN-->GDCEN-->BLCEN-->WB-->CFA-->CC-->
1966 * GAM-->VHXS-->CSC-->CBC-->SUB422-->SUB420
1967 */
1968 const struct reg_field regfields[ISC_PIPE_LINE_NODE_NUM] = {
1969 REG_FIELD(ISC_DPC_CTRL, 0, 0),
1970 REG_FIELD(ISC_DPC_CTRL, 1, 1),
1971 REG_FIELD(ISC_DPC_CTRL, 2, 2),
1972 REG_FIELD(ISC_WB_CTRL, 0, 0),
1973 REG_FIELD(ISC_CFA_CTRL, 0, 0),
1974 REG_FIELD(ISC_CC_CTRL, 0, 0),
1975 REG_FIELD(ISC_GAM_CTRL, 0, 0),
1976 REG_FIELD(ISC_GAM_CTRL, 1, 1),
1977 REG_FIELD(ISC_GAM_CTRL, 2, 2),
1978 REG_FIELD(ISC_GAM_CTRL, 3, 3),
1979 REG_FIELD(ISC_VHXS_CTRL, 0, 0),
1980 REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0),
1981 REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0),
1982 REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0),
1983 REG_FIELD(ISC_SUB420_CTRL + isc->offsets.sub420, 0, 0),
1984 };
1985
1986 for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
1987 regs = devm_regmap_field_alloc(dev, regmap, regfields[i]);
1988 if (IS_ERR(regs))
1989 return PTR_ERR(regs);
1990
1991 isc->pipeline[i] = regs;
1992 }
1993
1994 return 0;
1995 }
1996 EXPORT_SYMBOL_GPL(isc_pipeline_init);
1997
1998 /* regmap configuration */
1999 #define ATMEL_ISC_REG_MAX 0xd5c
2000 const struct regmap_config isc_regmap_config = {
2001 .reg_bits = 32,
2002 .reg_stride = 4,
2003 .val_bits = 32,
2004 .max_register = ATMEL_ISC_REG_MAX,
2005 };
2006 EXPORT_SYMBOL_GPL(isc_regmap_config);
2007
2008 MODULE_AUTHOR("Songjun Wu");
2009 MODULE_AUTHOR("Eugen Hristev");
2010 MODULE_DESCRIPTION("Atmel ISC common code base");
2011 MODULE_LICENSE("GPL v2");
2012
