1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2005, 2006 IBM Corporation
4 * Copyright (C) 2014, 2015 Intel Corporation
5 *
6 * Authors:
7 * Leendert van Doorn <leendert@watson.ibm.com>
8 * Kylene Hall <kjhall@us.ibm.com>
9 *
10 * Maintained by: <tpmdd-devel@lists.sourceforge.net>
11 *
12 * Device driver for TCG/TCPA TPM (trusted platform module).
13 * Specifications at www.trustedcomputinggroup.org
14 *
15 * This device driver implements the TPM interface as defined in
16 * the TCG TPM Interface Spec version 1.2, revision 1.0.
17 */
18
19 #ifndef __TPM_TIS_CORE_H__
20 #define __TPM_TIS_CORE_H__
21
22 #include "tpm.h"
23
24 enum tis_access {
25 TPM_ACCESS_VALID = 0x80,
26 TPM_ACCESS_ACTIVE_LOCALITY = 0x20,
27 TPM_ACCESS_REQUEST_PENDING = 0x04,
28 TPM_ACCESS_REQUEST_USE = 0x02,
29 };
30
31 enum tis_status {
32 TPM_STS_VALID = 0x80,
33 TPM_STS_COMMAND_READY = 0x40,
34 TPM_STS_GO = 0x20,
35 TPM_STS_DATA_AVAIL = 0x10,
36 TPM_STS_DATA_EXPECT = 0x08,
37 TPM_STS_READ_ZERO = 0x23, /* bits that must be zero on read */
38 };
39
40 enum tis_int_flags {
41 TPM_GLOBAL_INT_ENABLE = 0x80000000,
42 TPM_INTF_BURST_COUNT_STATIC = 0x100,
43 TPM_INTF_CMD_READY_INT = 0x080,
44 TPM_INTF_INT_EDGE_FALLING = 0x040,
45 TPM_INTF_INT_EDGE_RISING = 0x020,
46 TPM_INTF_INT_LEVEL_LOW = 0x010,
47 TPM_INTF_INT_LEVEL_HIGH = 0x008,
48 TPM_INTF_LOCALITY_CHANGE_INT = 0x004,
49 TPM_INTF_STS_VALID_INT = 0x002,
50 TPM_INTF_DATA_AVAIL_INT = 0x001,
51 };
52
53 enum tis_defaults {
54 TIS_MEM_LEN = 0x5000,
55 TIS_SHORT_TIMEOUT = 750, /* ms */
56 TIS_LONG_TIMEOUT = 2000, /* 2 sec */
57 };
58
59 /* Some timeout values are needed before it is known whether the chip is
60 * TPM 1.0 or TPM 2.0.
61 */
62 #define TIS_TIMEOUT_A_MAX max_t(int, TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_A)
63 #define TIS_TIMEOUT_B_MAX max_t(int, TIS_LONG_TIMEOUT, TPM2_TIMEOUT_B)
64 #define TIS_TIMEOUT_C_MAX max_t(int, TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_C)
65 #define TIS_TIMEOUT_D_MAX max_t(int, TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_D)
66
67 #define TPM_ACCESS(l) (0x0000 | ((l) << 12))
68 #define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12))
69 #define TPM_INT_VECTOR(l) (0x000C | ((l) << 12))
70 #define TPM_INT_STATUS(l) (0x0010 | ((l) << 12))
71 #define TPM_INTF_CAPS(l) (0x0014 | ((l) << 12))
72 #define TPM_STS(l) (0x0018 | ((l) << 12))
73 #define TPM_STS3(l) (0x001b | ((l) << 12))
74 #define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12))
75
76 #define TPM_DID_VID(l) (0x0F00 | ((l) << 12))
77 #define TPM_RID(l) (0x0F04 | ((l) << 12))
78
79 #define LPC_CNTRL_OFFSET 0x84
80 #define LPC_CLKRUN_EN (1 << 2)
81 #define INTEL_LEGACY_BLK_BASE_ADDR 0xFED08000
82 #define ILB_REMAP_SIZE 0x100
83
84 enum tpm_tis_flags {
85 TPM_TIS_ITPM_WORKAROUND = BIT(0),
86 TPM_TIS_INVALID_STATUS = BIT(1),
87 };
88
89 struct tpm_tis_data {
90 u16 manufacturer_id;
91 int locality;
92 int irq;
93 bool irq_tested;
94 unsigned long flags;
95 void __iomem *ilb_base_addr;
96 u16 clkrun_enabled;
97 wait_queue_head_t int_queue;
98 wait_queue_head_t read_queue;
99 const struct tpm_tis_phy_ops *phy_ops;
100 unsigned short rng_quality;
101 };
102
103 struct tpm_tis_phy_ops {
104 int (*read_bytes)(struct tpm_tis_data *data, u32 addr, u16 len,
105 u8 *result);
106 int (*write_bytes)(struct tpm_tis_data *data, u32 addr, u16 len,
107 const u8 *value);
108 int (*read16)(struct tpm_tis_data *data, u32 addr, u16 *result);
109 int (*read32)(struct tpm_tis_data *data, u32 addr, u32 *result);
110 int (*write32)(struct tpm_tis_data *data, u32 addr, u32 src);
111 };
112
tpm_tis_read_bytes(struct tpm_tis_data * data,u32 addr,u16 len,u8 * result)113 static inline int tpm_tis_read_bytes(struct tpm_tis_data *data, u32 addr,
114 u16 len, u8 *result)
115 {
116 return data->phy_ops->read_bytes(data, addr, len, result);
117 }
118
tpm_tis_read8(struct tpm_tis_data * data,u32 addr,u8 * result)119 static inline int tpm_tis_read8(struct tpm_tis_data *data, u32 addr, u8 *result)
120 {
121 return data->phy_ops->read_bytes(data, addr, 1, result);
122 }
123
tpm_tis_read16(struct tpm_tis_data * data,u32 addr,u16 * result)124 static inline int tpm_tis_read16(struct tpm_tis_data *data, u32 addr,
125 u16 *result)
126 {
127 return data->phy_ops->read16(data, addr, result);
128 }
129
tpm_tis_read32(struct tpm_tis_data * data,u32 addr,u32 * result)130 static inline int tpm_tis_read32(struct tpm_tis_data *data, u32 addr,
131 u32 *result)
132 {
133 return data->phy_ops->read32(data, addr, result);
134 }
135
tpm_tis_write_bytes(struct tpm_tis_data * data,u32 addr,u16 len,const u8 * value)136 static inline int tpm_tis_write_bytes(struct tpm_tis_data *data, u32 addr,
137 u16 len, const u8 *value)
138 {
139 return data->phy_ops->write_bytes(data, addr, len, value);
140 }
141
tpm_tis_write8(struct tpm_tis_data * data,u32 addr,u8 value)142 static inline int tpm_tis_write8(struct tpm_tis_data *data, u32 addr, u8 value)
143 {
144 return data->phy_ops->write_bytes(data, addr, 1, &value);
145 }
146
tpm_tis_write32(struct tpm_tis_data * data,u32 addr,u32 value)147 static inline int tpm_tis_write32(struct tpm_tis_data *data, u32 addr,
148 u32 value)
149 {
150 return data->phy_ops->write32(data, addr, value);
151 }
152
is_bsw(void)153 static inline bool is_bsw(void)
154 {
155 #ifdef CONFIG_X86
156 return ((boot_cpu_data.x86_model == INTEL_FAM6_ATOM_AIRMONT) ? 1 : 0);
157 #else
158 return false;
159 #endif
160 }
161
162 void tpm_tis_remove(struct tpm_chip *chip);
163 int tpm_tis_core_init(struct device *dev, struct tpm_tis_data *priv, int irq,
164 const struct tpm_tis_phy_ops *phy_ops,
165 acpi_handle acpi_dev_handle);
166
167 #ifdef CONFIG_PM_SLEEP
168 int tpm_tis_resume(struct device *dev);
169 #endif
170
171 #endif
172
