1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2019 Intel Corporation
4 */
5
6 #include <linux/pci.h>
7 #include <linux/vgaarb.h>
8
9 #include <drm/i915_drm.h>
10 #include <video/vga.h>
11
12 #include "i915_drv.h"
13 #include "intel_de.h"
14 #include "intel_vga.h"
15
intel_vga_cntrl_reg(struct drm_i915_private * i915)16 static i915_reg_t intel_vga_cntrl_reg(struct drm_i915_private *i915)
17 {
18 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
19 return VLV_VGACNTRL;
20 else if (DISPLAY_VER(i915) >= 5)
21 return CPU_VGACNTRL;
22 else
23 return VGACNTRL;
24 }
25
26 /* Disable the VGA plane that we never use */
intel_vga_disable(struct drm_i915_private * dev_priv)27 void intel_vga_disable(struct drm_i915_private *dev_priv)
28 {
29 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
30 i915_reg_t vga_reg = intel_vga_cntrl_reg(dev_priv);
31 u8 sr1;
32
33 if (intel_de_read(dev_priv, vga_reg) & VGA_DISP_DISABLE)
34 return;
35
36 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
37 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
38 outb(0x01, VGA_SEQ_I);
39 sr1 = inb(VGA_SEQ_D);
40 outb(sr1 | VGA_SR01_SCREEN_OFF, VGA_SEQ_D);
41 vga_put(pdev, VGA_RSRC_LEGACY_IO);
42 udelay(300);
43
44 intel_de_write(dev_priv, vga_reg, VGA_DISP_DISABLE);
45 intel_de_posting_read(dev_priv, vga_reg);
46 }
47
intel_vga_redisable_power_on(struct drm_i915_private * dev_priv)48 void intel_vga_redisable_power_on(struct drm_i915_private *dev_priv)
49 {
50 i915_reg_t vga_reg = intel_vga_cntrl_reg(dev_priv);
51
52 if (!(intel_de_read(dev_priv, vga_reg) & VGA_DISP_DISABLE)) {
53 drm_dbg_kms(&dev_priv->drm,
54 "Something enabled VGA plane, disabling it\n");
55 intel_vga_disable(dev_priv);
56 }
57 }
58
intel_vga_redisable(struct drm_i915_private * i915)59 void intel_vga_redisable(struct drm_i915_private *i915)
60 {
61 intel_wakeref_t wakeref;
62
63 /*
64 * This function can be called both from intel_modeset_setup_hw_state or
65 * at a very early point in our resume sequence, where the power well
66 * structures are not yet restored. Since this function is at a very
67 * paranoid "someone might have enabled VGA while we were not looking"
68 * level, just check if the power well is enabled instead of trying to
69 * follow the "don't touch the power well if we don't need it" policy
70 * the rest of the driver uses.
71 */
72 wakeref = intel_display_power_get_if_enabled(i915, POWER_DOMAIN_VGA);
73 if (!wakeref)
74 return;
75
76 intel_vga_redisable_power_on(i915);
77
78 intel_display_power_put(i915, POWER_DOMAIN_VGA, wakeref);
79 }
80
intel_vga_reset_io_mem(struct drm_i915_private * i915)81 void intel_vga_reset_io_mem(struct drm_i915_private *i915)
82 {
83 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
84
85 /*
86 * After we re-enable the power well, if we touch VGA register 0x3d5
87 * we'll get unclaimed register interrupts. This stops after we write
88 * anything to the VGA MSR register. The vgacon module uses this
89 * register all the time, so if we unbind our driver and, as a
90 * consequence, bind vgacon, we'll get stuck in an infinite loop at
91 * console_unlock(). So make here we touch the VGA MSR register, making
92 * sure vgacon can keep working normally without triggering interrupts
93 * and error messages.
94 */
95 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
96 outb(inb(VGA_MIS_R), VGA_MIS_W);
97 vga_put(pdev, VGA_RSRC_LEGACY_IO);
98 }
99
100 static int
intel_vga_set_state(struct drm_i915_private * i915,bool enable_decode)101 intel_vga_set_state(struct drm_i915_private *i915, bool enable_decode)
102 {
103 unsigned int reg = DISPLAY_VER(i915) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
104 u16 gmch_ctrl;
105
106 if (pci_read_config_word(i915->bridge_dev, reg, &gmch_ctrl)) {
107 drm_err(&i915->drm, "failed to read control word\n");
108 return -EIO;
109 }
110
111 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !enable_decode)
112 return 0;
113
114 if (enable_decode)
115 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
116 else
117 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
118
119 if (pci_write_config_word(i915->bridge_dev, reg, gmch_ctrl)) {
120 drm_err(&i915->drm, "failed to write control word\n");
121 return -EIO;
122 }
123
124 return 0;
125 }
126
127 static unsigned int
intel_vga_set_decode(struct pci_dev * pdev,bool enable_decode)128 intel_vga_set_decode(struct pci_dev *pdev, bool enable_decode)
129 {
130 struct drm_i915_private *i915 = pdev_to_i915(pdev);
131
132 intel_vga_set_state(i915, enable_decode);
133
134 if (enable_decode)
135 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
136 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
137 else
138 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
139 }
140
intel_vga_register(struct drm_i915_private * i915)141 int intel_vga_register(struct drm_i915_private *i915)
142 {
143
144 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
145 int ret;
146
147 /*
148 * If we have > 1 VGA cards, then we need to arbitrate access to the
149 * common VGA resources.
150 *
151 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
152 * then we do not take part in VGA arbitration and the
153 * vga_client_register() fails with -ENODEV.
154 */
155 ret = vga_client_register(pdev, intel_vga_set_decode);
156 if (ret && ret != -ENODEV)
157 return ret;
158
159 return 0;
160 }
161
intel_vga_unregister(struct drm_i915_private * i915)162 void intel_vga_unregister(struct drm_i915_private *i915)
163 {
164 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
165
166 vga_client_unregister(pdev);
167 }
168
